1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/export.h> 9 #include <linux/clk-provider.h> 10 #include <linux/regmap.h> 11 #include <linux/delay.h> 12 13 #include "clk-alpha-pll.h" 14 #include "common.h" 15 16 #define PLL_MODE(p) ((p)->offset + 0x0) 17 # define PLL_OUTCTRL BIT(0) 18 # define PLL_BYPASSNL BIT(1) 19 # define PLL_RESET_N BIT(2) 20 # define PLL_OFFLINE_REQ BIT(7) 21 # define PLL_LOCK_COUNT_SHIFT 8 22 # define PLL_LOCK_COUNT_MASK 0x3f 23 # define PLL_BIAS_COUNT_SHIFT 14 24 # define PLL_BIAS_COUNT_MASK 0x3f 25 # define PLL_VOTE_FSM_ENA BIT(20) 26 # define PLL_FSM_ENA BIT(20) 27 # define PLL_VOTE_FSM_RESET BIT(21) 28 # define PLL_UPDATE BIT(22) 29 # define PLL_UPDATE_BYPASS BIT(23) 30 # define PLL_FSM_LEGACY_MODE BIT(24) 31 # define PLL_OFFLINE_ACK BIT(28) 32 # define ALPHA_PLL_ACK_LATCH BIT(29) 33 # define PLL_ACTIVE_FLAG BIT(30) 34 # define PLL_LOCK_DET BIT(31) 35 36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL]) 37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL]) 38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL]) 39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U]) 40 41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) 42 # define PLL_POST_DIV_SHIFT 8 43 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width ? (p)->width - 1 : 3, 0) 44 # define PLL_ALPHA_MSB BIT(15) 45 # define PLL_ALPHA_EN BIT(24) 46 # define PLL_ALPHA_MODE BIT(25) 47 # define PLL_VCO_SHIFT 20 48 # define PLL_VCO_MASK 0x3 49 50 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U]) 51 #define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1]) 52 53 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL]) 54 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U]) 55 #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1]) 56 #define PLL_CONFIG_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U2]) 57 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) 58 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) 59 #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1]) 60 #define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2]) 61 #define PLL_TEST_CTL_U3(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U3]) 62 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) 63 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE]) 64 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC]) 65 66 #define GET_PLL_TYPE(pll) (((pll)->regs - clk_alpha_pll_regs[0]) / PLL_OFF_MAX_REGS) 67 68 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 69 [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 70 [PLL_OFF_L_VAL] = 0x04, 71 [PLL_OFF_ALPHA_VAL] = 0x08, 72 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 73 [PLL_OFF_USER_CTL] = 0x10, 74 [PLL_OFF_USER_CTL_U] = 0x14, 75 [PLL_OFF_CONFIG_CTL] = 0x18, 76 [PLL_OFF_TEST_CTL] = 0x1c, 77 [PLL_OFF_TEST_CTL_U] = 0x20, 78 [PLL_OFF_STATUS] = 0x24, 79 }, 80 [CLK_ALPHA_PLL_TYPE_HUAYRA] = { 81 [PLL_OFF_L_VAL] = 0x04, 82 [PLL_OFF_ALPHA_VAL] = 0x08, 83 [PLL_OFF_USER_CTL] = 0x10, 84 [PLL_OFF_CONFIG_CTL] = 0x14, 85 [PLL_OFF_CONFIG_CTL_U] = 0x18, 86 [PLL_OFF_TEST_CTL] = 0x1c, 87 [PLL_OFF_TEST_CTL_U] = 0x20, 88 [PLL_OFF_STATUS] = 0x24, 89 }, 90 [CLK_ALPHA_PLL_TYPE_HUAYRA_APSS] = { 91 [PLL_OFF_L_VAL] = 0x08, 92 [PLL_OFF_ALPHA_VAL] = 0x10, 93 [PLL_OFF_USER_CTL] = 0x18, 94 [PLL_OFF_CONFIG_CTL] = 0x20, 95 [PLL_OFF_CONFIG_CTL_U] = 0x24, 96 [PLL_OFF_STATUS] = 0x28, 97 [PLL_OFF_TEST_CTL] = 0x30, 98 [PLL_OFF_TEST_CTL_U] = 0x34, 99 }, 100 [CLK_ALPHA_PLL_TYPE_HUAYRA_2290] = { 101 [PLL_OFF_L_VAL] = 0x04, 102 [PLL_OFF_ALPHA_VAL] = 0x08, 103 [PLL_OFF_USER_CTL] = 0x0c, 104 [PLL_OFF_CONFIG_CTL] = 0x10, 105 [PLL_OFF_CONFIG_CTL_U] = 0x14, 106 [PLL_OFF_CONFIG_CTL_U1] = 0x18, 107 [PLL_OFF_TEST_CTL] = 0x1c, 108 [PLL_OFF_TEST_CTL_U] = 0x20, 109 [PLL_OFF_TEST_CTL_U1] = 0x24, 110 [PLL_OFF_OPMODE] = 0x28, 111 [PLL_OFF_STATUS] = 0x38, 112 }, 113 [CLK_ALPHA_PLL_TYPE_BRAMMO] = { 114 [PLL_OFF_L_VAL] = 0x04, 115 [PLL_OFF_ALPHA_VAL] = 0x08, 116 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 117 [PLL_OFF_USER_CTL] = 0x10, 118 [PLL_OFF_CONFIG_CTL] = 0x18, 119 [PLL_OFF_TEST_CTL] = 0x1c, 120 [PLL_OFF_STATUS] = 0x24, 121 }, 122 [CLK_ALPHA_PLL_TYPE_FABIA] = { 123 [PLL_OFF_L_VAL] = 0x04, 124 [PLL_OFF_USER_CTL] = 0x0c, 125 [PLL_OFF_USER_CTL_U] = 0x10, 126 [PLL_OFF_CONFIG_CTL] = 0x14, 127 [PLL_OFF_CONFIG_CTL_U] = 0x18, 128 [PLL_OFF_TEST_CTL] = 0x1c, 129 [PLL_OFF_TEST_CTL_U] = 0x20, 130 [PLL_OFF_STATUS] = 0x24, 131 [PLL_OFF_OPMODE] = 0x2c, 132 [PLL_OFF_FRAC] = 0x38, 133 }, 134 [CLK_ALPHA_PLL_TYPE_TRION] = { 135 [PLL_OFF_L_VAL] = 0x04, 136 [PLL_OFF_CAL_L_VAL] = 0x08, 137 [PLL_OFF_USER_CTL] = 0x0c, 138 [PLL_OFF_USER_CTL_U] = 0x10, 139 [PLL_OFF_USER_CTL_U1] = 0x14, 140 [PLL_OFF_CONFIG_CTL] = 0x18, 141 [PLL_OFF_CONFIG_CTL_U] = 0x1c, 142 [PLL_OFF_CONFIG_CTL_U1] = 0x20, 143 [PLL_OFF_TEST_CTL] = 0x24, 144 [PLL_OFF_TEST_CTL_U] = 0x28, 145 [PLL_OFF_TEST_CTL_U1] = 0x2c, 146 [PLL_OFF_STATUS] = 0x30, 147 [PLL_OFF_OPMODE] = 0x38, 148 [PLL_OFF_ALPHA_VAL] = 0x40, 149 }, 150 [CLK_ALPHA_PLL_TYPE_AGERA] = { 151 [PLL_OFF_L_VAL] = 0x04, 152 [PLL_OFF_ALPHA_VAL] = 0x08, 153 [PLL_OFF_USER_CTL] = 0x0c, 154 [PLL_OFF_CONFIG_CTL] = 0x10, 155 [PLL_OFF_CONFIG_CTL_U] = 0x14, 156 [PLL_OFF_TEST_CTL] = 0x18, 157 [PLL_OFF_TEST_CTL_U] = 0x1c, 158 [PLL_OFF_STATUS] = 0x2c, 159 }, 160 [CLK_ALPHA_PLL_TYPE_ZONDA] = { 161 [PLL_OFF_L_VAL] = 0x04, 162 [PLL_OFF_ALPHA_VAL] = 0x08, 163 [PLL_OFF_USER_CTL] = 0x0c, 164 [PLL_OFF_CONFIG_CTL] = 0x10, 165 [PLL_OFF_CONFIG_CTL_U] = 0x14, 166 [PLL_OFF_CONFIG_CTL_U1] = 0x18, 167 [PLL_OFF_TEST_CTL] = 0x1c, 168 [PLL_OFF_TEST_CTL_U] = 0x20, 169 [PLL_OFF_TEST_CTL_U1] = 0x24, 170 [PLL_OFF_OPMODE] = 0x28, 171 [PLL_OFF_STATUS] = 0x38, 172 }, 173 [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = { 174 [PLL_OFF_OPMODE] = 0x04, 175 [PLL_OFF_STATUS] = 0x0c, 176 [PLL_OFF_L_VAL] = 0x10, 177 [PLL_OFF_ALPHA_VAL] = 0x14, 178 [PLL_OFF_USER_CTL] = 0x18, 179 [PLL_OFF_USER_CTL_U] = 0x1c, 180 [PLL_OFF_CONFIG_CTL] = 0x20, 181 [PLL_OFF_CONFIG_CTL_U] = 0x24, 182 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 183 [PLL_OFF_TEST_CTL] = 0x2c, 184 [PLL_OFF_TEST_CTL_U] = 0x30, 185 [PLL_OFF_TEST_CTL_U1] = 0x34, 186 }, 187 [CLK_ALPHA_PLL_TYPE_LUCID_OLE] = { 188 [PLL_OFF_OPMODE] = 0x04, 189 [PLL_OFF_STATE] = 0x08, 190 [PLL_OFF_STATUS] = 0x0c, 191 [PLL_OFF_L_VAL] = 0x10, 192 [PLL_OFF_ALPHA_VAL] = 0x14, 193 [PLL_OFF_USER_CTL] = 0x18, 194 [PLL_OFF_USER_CTL_U] = 0x1c, 195 [PLL_OFF_CONFIG_CTL] = 0x20, 196 [PLL_OFF_CONFIG_CTL_U] = 0x24, 197 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 198 [PLL_OFF_TEST_CTL] = 0x2c, 199 [PLL_OFF_TEST_CTL_U] = 0x30, 200 [PLL_OFF_TEST_CTL_U1] = 0x34, 201 [PLL_OFF_TEST_CTL_U2] = 0x38, 202 }, 203 [CLK_ALPHA_PLL_TYPE_PONGO_ELU] = { 204 [PLL_OFF_OPMODE] = 0x04, 205 [PLL_OFF_STATE] = 0x08, 206 [PLL_OFF_STATUS] = 0x0c, 207 [PLL_OFF_L_VAL] = 0x10, 208 [PLL_OFF_USER_CTL] = 0x14, 209 [PLL_OFF_USER_CTL_U] = 0x18, 210 [PLL_OFF_CONFIG_CTL] = 0x1c, 211 [PLL_OFF_CONFIG_CTL_U] = 0x20, 212 [PLL_OFF_CONFIG_CTL_U1] = 0x24, 213 [PLL_OFF_CONFIG_CTL_U2] = 0x28, 214 [PLL_OFF_TEST_CTL] = 0x2c, 215 [PLL_OFF_TEST_CTL_U] = 0x30, 216 [PLL_OFF_TEST_CTL_U1] = 0x34, 217 [PLL_OFF_TEST_CTL_U2] = 0x38, 218 [PLL_OFF_TEST_CTL_U3] = 0x3c, 219 }, 220 [CLK_ALPHA_PLL_TYPE_TAYCAN_ELU] = { 221 [PLL_OFF_OPMODE] = 0x04, 222 [PLL_OFF_STATE] = 0x08, 223 [PLL_OFF_STATUS] = 0x0c, 224 [PLL_OFF_L_VAL] = 0x10, 225 [PLL_OFF_ALPHA_VAL] = 0x14, 226 [PLL_OFF_USER_CTL] = 0x18, 227 [PLL_OFF_USER_CTL_U] = 0x1c, 228 [PLL_OFF_CONFIG_CTL] = 0x20, 229 [PLL_OFF_CONFIG_CTL_U] = 0x24, 230 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 231 [PLL_OFF_TEST_CTL] = 0x2c, 232 [PLL_OFF_TEST_CTL_U] = 0x30, 233 }, 234 [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = { 235 [PLL_OFF_OPMODE] = 0x04, 236 [PLL_OFF_STATUS] = 0x0c, 237 [PLL_OFF_L_VAL] = 0x10, 238 [PLL_OFF_USER_CTL] = 0x14, 239 [PLL_OFF_USER_CTL_U] = 0x18, 240 [PLL_OFF_CONFIG_CTL] = 0x1c, 241 [PLL_OFF_CONFIG_CTL_U] = 0x20, 242 [PLL_OFF_CONFIG_CTL_U1] = 0x24, 243 [PLL_OFF_TEST_CTL] = 0x28, 244 [PLL_OFF_TEST_CTL_U] = 0x2c, 245 }, 246 [CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = { 247 [PLL_OFF_L_VAL] = 0x04, 248 [PLL_OFF_ALPHA_VAL] = 0x08, 249 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 250 [PLL_OFF_TEST_CTL] = 0x10, 251 [PLL_OFF_TEST_CTL_U] = 0x14, 252 [PLL_OFF_USER_CTL] = 0x18, 253 [PLL_OFF_USER_CTL_U] = 0x1c, 254 [PLL_OFF_CONFIG_CTL] = 0x20, 255 [PLL_OFF_STATUS] = 0x24, 256 }, 257 [CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = { 258 [PLL_OFF_L_VAL] = 0x04, 259 [PLL_OFF_ALPHA_VAL] = 0x08, 260 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 261 [PLL_OFF_TEST_CTL] = 0x10, 262 [PLL_OFF_TEST_CTL_U] = 0x14, 263 [PLL_OFF_USER_CTL] = 0x18, 264 [PLL_OFF_CONFIG_CTL] = 0x1C, 265 [PLL_OFF_STATUS] = 0x20, 266 }, 267 [CLK_ALPHA_PLL_TYPE_STROMER] = { 268 [PLL_OFF_L_VAL] = 0x08, 269 [PLL_OFF_ALPHA_VAL] = 0x10, 270 [PLL_OFF_ALPHA_VAL_U] = 0x14, 271 [PLL_OFF_USER_CTL] = 0x18, 272 [PLL_OFF_USER_CTL_U] = 0x1c, 273 [PLL_OFF_CONFIG_CTL] = 0x20, 274 [PLL_OFF_STATUS] = 0x28, 275 [PLL_OFF_TEST_CTL] = 0x30, 276 [PLL_OFF_TEST_CTL_U] = 0x34, 277 }, 278 [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = { 279 [PLL_OFF_L_VAL] = 0x04, 280 [PLL_OFF_USER_CTL] = 0x08, 281 [PLL_OFF_USER_CTL_U] = 0x0c, 282 [PLL_OFF_CONFIG_CTL] = 0x10, 283 [PLL_OFF_TEST_CTL] = 0x14, 284 [PLL_OFF_TEST_CTL_U] = 0x18, 285 [PLL_OFF_STATUS] = 0x1c, 286 [PLL_OFF_ALPHA_VAL] = 0x24, 287 [PLL_OFF_ALPHA_VAL_U] = 0x28, 288 }, 289 [CLK_ALPHA_PLL_TYPE_ZONDA_OLE] = { 290 [PLL_OFF_L_VAL] = 0x04, 291 [PLL_OFF_ALPHA_VAL] = 0x08, 292 [PLL_OFF_USER_CTL] = 0x0c, 293 [PLL_OFF_USER_CTL_U] = 0x10, 294 [PLL_OFF_CONFIG_CTL] = 0x14, 295 [PLL_OFF_CONFIG_CTL_U] = 0x18, 296 [PLL_OFF_CONFIG_CTL_U1] = 0x1c, 297 [PLL_OFF_CONFIG_CTL_U2] = 0x20, 298 [PLL_OFF_TEST_CTL] = 0x24, 299 [PLL_OFF_TEST_CTL_U] = 0x28, 300 [PLL_OFF_TEST_CTL_U1] = 0x2c, 301 [PLL_OFF_OPMODE] = 0x30, 302 [PLL_OFF_STATUS] = 0x3c, 303 }, 304 [CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] = { 305 [PLL_OFF_L_VAL] = 0x04, 306 [PLL_OFF_ALPHA_VAL] = 0x08, 307 [PLL_OFF_TEST_CTL] = 0x0c, 308 [PLL_OFF_TEST_CTL_U] = 0x10, 309 [PLL_OFF_USER_CTL] = 0x14, 310 [PLL_OFF_CONFIG_CTL] = 0x18, 311 [PLL_OFF_CONFIG_CTL_U] = 0x1c, 312 [PLL_OFF_STATUS] = 0x20, 313 }, 314 315 }; 316 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 317 318 /* 319 * Even though 40 bits are present, use only 32 for ease of calculation. 320 */ 321 #define ALPHA_REG_BITWIDTH 40 322 #define ALPHA_REG_16BIT_WIDTH 16 323 #define ALPHA_BITWIDTH 32U 324 #define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH) 325 326 #define ALPHA_PLL_STATUS_REG_SHIFT 8 327 328 #define PLL_HUAYRA_M_WIDTH 8 329 #define PLL_HUAYRA_M_SHIFT 8 330 #define PLL_HUAYRA_M_MASK 0xff 331 #define PLL_HUAYRA_N_SHIFT 0 332 #define PLL_HUAYRA_N_MASK 0xff 333 #define PLL_HUAYRA_ALPHA_WIDTH 16 334 335 #define PLL_STANDBY 0x0 336 #define PLL_RUN 0x1 337 #define PLL_OUT_MASK 0x7 338 #define PLL_RATE_MARGIN 500 339 340 /* TRION PLL specific settings and offsets */ 341 #define TRION_PLL_CAL_VAL 0x44 342 #define TRION_PCAL_DONE BIT(26) 343 344 /* LUCID PLL specific settings and offsets */ 345 #define LUCID_PCAL_DONE BIT(27) 346 347 /* LUCID 5LPE PLL specific settings and offsets */ 348 #define LUCID_5LPE_PCAL_DONE BIT(11) 349 #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13) 350 #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14) 351 #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) 352 353 /* LUCID EVO PLL specific settings and offsets */ 354 #define LUCID_EVO_PCAL_NOT_DONE BIT(8) 355 #define LUCID_EVO_ENABLE_VOTE_RUN BIT(25) 356 #define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0) 357 #define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16 358 #define LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT 24 359 360 /* PONGO ELU PLL specific setting and offsets */ 361 #define PONGO_PLL_OUT_MASK GENMASK(1, 0) 362 #define PONGO_PLL_L_VAL_MASK GENMASK(11, 0) 363 #define PONGO_XO_PRESENT BIT(10) 364 #define PONGO_CLOCK_SELECT BIT(12) 365 366 /* ZONDA PLL specific */ 367 #define ZONDA_PLL_OUT_MASK 0xf 368 #define ZONDA_STAY_IN_CFA BIT(16) 369 #define ZONDA_PLL_FREQ_LOCK_DET BIT(29) 370 371 #define pll_alpha_width(p) \ 372 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ 373 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) 374 375 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4) 376 377 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ 378 struct clk_alpha_pll, clkr) 379 380 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \ 381 struct clk_alpha_pll_postdiv, clkr) 382 383 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, 384 const char *action) 385 { 386 u32 val; 387 int count; 388 int ret; 389 const char *name = clk_hw_get_name(&pll->clkr.hw); 390 391 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 392 if (ret) 393 return ret; 394 395 /* Pongo PLLs using a 32KHz reference can take upwards of 1500us to lock. */ 396 for (count = 1500; count > 0; count--) { 397 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 398 if (ret) 399 return ret; 400 if (inverse && !(val & mask)) 401 return 0; 402 else if ((val & mask) == mask) 403 return 0; 404 405 udelay(1); 406 } 407 408 WARN(1, "%s failed to %s!\n", name, action); 409 return -ETIMEDOUT; 410 } 411 412 #define wait_for_pll_enable_active(pll) \ 413 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable") 414 415 #define wait_for_pll_enable_lock(pll) \ 416 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable") 417 418 #define wait_for_zonda_pll_freq_lock(pll) \ 419 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable") 420 421 #define wait_for_pll_disable(pll) \ 422 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable") 423 424 #define wait_for_pll_offline(pll) \ 425 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline") 426 427 #define wait_for_pll_update(pll) \ 428 wait_for_pll(pll, PLL_UPDATE, 1, "update") 429 430 #define wait_for_pll_update_ack_set(pll) \ 431 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set") 432 433 #define wait_for_pll_update_ack_clear(pll) \ 434 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear") 435 436 static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg, 437 unsigned int val) 438 { 439 if (val) 440 regmap_write(regmap, reg, val); 441 } 442 443 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 444 const struct alpha_pll_config *config) 445 { 446 u32 val, mask; 447 448 regmap_write(regmap, PLL_L_VAL(pll), config->l); 449 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); 450 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 451 452 if (pll_has_64bit_config(pll)) 453 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), 454 config->config_ctl_hi_val); 455 456 if (pll_alpha_width(pll) > 32) 457 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); 458 459 val = config->main_output_mask; 460 val |= config->aux_output_mask; 461 val |= config->aux2_output_mask; 462 val |= config->early_output_mask; 463 val |= config->pre_div_val; 464 val |= config->post_div_val; 465 val |= config->vco_val; 466 val |= config->alpha_en_mask; 467 val |= config->alpha_mode_mask; 468 469 mask = config->main_output_mask; 470 mask |= config->aux_output_mask; 471 mask |= config->aux2_output_mask; 472 mask |= config->early_output_mask; 473 mask |= config->pre_div_mask; 474 mask |= config->post_div_mask; 475 mask |= config->vco_mask; 476 mask |= config->alpha_en_mask; 477 mask |= config->alpha_mode_mask; 478 479 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 480 481 if (config->test_ctl_mask) 482 regmap_update_bits(regmap, PLL_TEST_CTL(pll), 483 config->test_ctl_mask, 484 config->test_ctl_val); 485 else 486 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 487 config->test_ctl_val); 488 489 if (config->test_ctl_hi_mask) 490 regmap_update_bits(regmap, PLL_TEST_CTL_U(pll), 491 config->test_ctl_hi_mask, 492 config->test_ctl_hi_val); 493 else 494 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 495 config->test_ctl_hi_val); 496 497 if (pll->flags & SUPPORTS_FSM_MODE) 498 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); 499 } 500 EXPORT_SYMBOL_GPL(clk_alpha_pll_configure); 501 502 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) 503 { 504 int ret; 505 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 506 u32 val; 507 508 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 509 if (ret) 510 return ret; 511 512 val |= PLL_FSM_ENA; 513 514 if (pll->flags & SUPPORTS_OFFLINE_REQ) 515 val &= ~PLL_OFFLINE_REQ; 516 517 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); 518 if (ret) 519 return ret; 520 521 /* Make sure enable request goes through before waiting for update */ 522 mb(); 523 524 return wait_for_pll_enable_active(pll); 525 } 526 527 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw) 528 { 529 int ret; 530 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 531 u32 val; 532 533 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 534 if (ret) 535 return; 536 537 if (pll->flags & SUPPORTS_OFFLINE_REQ) { 538 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 539 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ); 540 if (ret) 541 return; 542 543 ret = wait_for_pll_offline(pll); 544 if (ret) 545 return; 546 } 547 548 /* Disable hwfsm */ 549 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 550 PLL_FSM_ENA, 0); 551 if (ret) 552 return; 553 554 wait_for_pll_disable(pll); 555 } 556 557 static int pll_is_enabled(struct clk_hw *hw, u32 mask) 558 { 559 int ret; 560 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 561 u32 val; 562 563 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 564 if (ret) 565 return ret; 566 567 return !!(val & mask); 568 } 569 570 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw) 571 { 572 return pll_is_enabled(hw, PLL_ACTIVE_FLAG); 573 } 574 575 static int clk_alpha_pll_is_enabled(struct clk_hw *hw) 576 { 577 return pll_is_enabled(hw, PLL_LOCK_DET); 578 } 579 580 static int clk_alpha_pll_enable(struct clk_hw *hw) 581 { 582 int ret; 583 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 584 u32 val, mask; 585 586 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; 587 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 588 if (ret) 589 return ret; 590 591 /* If in FSM mode, just vote for it */ 592 if (val & PLL_VOTE_FSM_ENA) { 593 ret = clk_enable_regmap(hw); 594 if (ret) 595 return ret; 596 return wait_for_pll_enable_active(pll); 597 } 598 599 /* Skip if already enabled */ 600 if ((val & mask) == mask) 601 return 0; 602 603 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 604 PLL_BYPASSNL, PLL_BYPASSNL); 605 if (ret) 606 return ret; 607 608 /* 609 * H/W requires a 5us delay between disabling the bypass and 610 * de-asserting the reset. 611 */ 612 mb(); 613 udelay(5); 614 615 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 616 PLL_RESET_N, PLL_RESET_N); 617 if (ret) 618 return ret; 619 620 ret = wait_for_pll_enable_lock(pll); 621 if (ret) 622 return ret; 623 624 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 625 PLL_OUTCTRL, PLL_OUTCTRL); 626 627 /* Ensure that the write above goes through before returning. */ 628 mb(); 629 return ret; 630 } 631 632 static void clk_alpha_pll_disable(struct clk_hw *hw) 633 { 634 int ret; 635 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 636 u32 val, mask; 637 638 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 639 if (ret) 640 return; 641 642 /* If in FSM mode, just unvote it */ 643 if (val & PLL_VOTE_FSM_ENA) { 644 clk_disable_regmap(hw); 645 return; 646 } 647 648 mask = PLL_OUTCTRL; 649 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 650 651 /* Delay of 2 output clock ticks required until output is disabled */ 652 mb(); 653 udelay(1); 654 655 mask = PLL_RESET_N | PLL_BYPASSNL; 656 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 657 } 658 659 static unsigned long 660 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width) 661 { 662 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width)); 663 } 664 665 static unsigned long 666 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a, 667 u32 alpha_width) 668 { 669 u64 remainder; 670 u64 quotient; 671 672 quotient = rate; 673 remainder = do_div(quotient, prate); 674 *l = quotient; 675 676 if (!remainder) { 677 *a = 0; 678 return rate; 679 } 680 681 /* Upper ALPHA_BITWIDTH bits of Alpha */ 682 quotient = remainder << ALPHA_SHIFT(alpha_width); 683 684 remainder = do_div(quotient, prate); 685 686 if (remainder) 687 quotient++; 688 689 *a = quotient; 690 return alpha_pll_calc_rate(prate, *l, *a, alpha_width); 691 } 692 693 static const struct pll_vco * 694 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) 695 { 696 const struct pll_vco *v = pll->vco_table; 697 const struct pll_vco *end = v + pll->num_vco; 698 699 for (; v < end; v++) 700 if (rate >= v->min_freq && rate <= v->max_freq) 701 return v; 702 703 return NULL; 704 } 705 706 static unsigned long 707 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 708 { 709 u32 l, low, high, ctl; 710 u64 a = 0, prate = parent_rate; 711 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 712 u32 alpha_width = pll_alpha_width(pll); 713 714 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) 715 return 0; 716 717 if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl)) 718 return 0; 719 720 if (ctl & PLL_ALPHA_EN) { 721 if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low)) 722 return 0; 723 if (alpha_width > 32) { 724 if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 725 &high)) 726 return 0; 727 a = (u64)high << 32 | low; 728 } else { 729 a = low & GENMASK(alpha_width - 1, 0); 730 } 731 732 if (alpha_width > ALPHA_BITWIDTH) 733 a >>= alpha_width - ALPHA_BITWIDTH; 734 } 735 736 return alpha_pll_calc_rate(prate, l, a, alpha_width); 737 } 738 739 740 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) 741 { 742 int ret; 743 u32 mode; 744 745 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); 746 747 /* Latch the input to the PLL */ 748 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 749 PLL_UPDATE); 750 751 /* Wait for 2 reference cycle before checking ACK bit */ 752 udelay(1); 753 754 /* 755 * PLL will latch the new L, Alpha and freq control word. 756 * PLL will respond by raising PLL_ACK_LATCH output when new programming 757 * has been latched in and PLL is being updated. When 758 * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared 759 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. 760 */ 761 if (mode & PLL_UPDATE_BYPASS) { 762 ret = wait_for_pll_update_ack_set(pll); 763 if (ret) 764 return ret; 765 766 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); 767 } else { 768 ret = wait_for_pll_update(pll); 769 if (ret) 770 return ret; 771 } 772 773 ret = wait_for_pll_update_ack_clear(pll); 774 if (ret) 775 return ret; 776 777 /* Wait for PLL output to stabilize */ 778 udelay(10); 779 780 return 0; 781 } 782 783 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, 784 int (*is_enabled)(struct clk_hw *)) 785 { 786 if (!is_enabled(&pll->clkr.hw) || 787 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) 788 return 0; 789 790 return __clk_alpha_pll_update_latch(pll); 791 } 792 793 static void clk_alpha_pll_update_configs(struct clk_alpha_pll *pll, const struct pll_vco *vco, 794 u32 l, u64 alpha, u32 alpha_width, bool alpha_en) 795 { 796 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 797 798 if (alpha_width > ALPHA_BITWIDTH) 799 alpha <<= alpha_width - ALPHA_BITWIDTH; 800 801 if (alpha_width > 32) 802 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), upper_32_bits(alpha)); 803 804 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), lower_32_bits(alpha)); 805 806 if (vco) { 807 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 808 PLL_VCO_MASK << PLL_VCO_SHIFT, 809 vco->val << PLL_VCO_SHIFT); 810 } 811 812 if (alpha_en) 813 regmap_set_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_ALPHA_EN); 814 } 815 816 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 817 unsigned long prate, 818 int (*is_enabled)(struct clk_hw *)) 819 { 820 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 821 const struct pll_vco *vco; 822 u32 l, alpha_width = pll_alpha_width(pll); 823 u64 a; 824 825 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 826 vco = alpha_pll_find_vco(pll, rate); 827 if (pll->vco_table && !vco) { 828 pr_err("%s: alpha pll not in a valid vco range\n", 829 clk_hw_get_name(hw)); 830 return -EINVAL; 831 } 832 833 clk_alpha_pll_update_configs(pll, vco, l, a, alpha_width, true); 834 835 return clk_alpha_pll_update_latch(pll, is_enabled); 836 } 837 838 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 839 unsigned long prate) 840 { 841 return __clk_alpha_pll_set_rate(hw, rate, prate, 842 clk_alpha_pll_is_enabled); 843 } 844 845 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate, 846 unsigned long prate) 847 { 848 return __clk_alpha_pll_set_rate(hw, rate, prate, 849 clk_alpha_pll_hwfsm_is_enabled); 850 } 851 852 static int clk_alpha_pll_determine_rate(struct clk_hw *hw, 853 struct clk_rate_request *req) 854 { 855 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 856 u32 l, alpha_width = pll_alpha_width(pll); 857 u64 a; 858 unsigned long min_freq, max_freq; 859 860 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, &l, 861 &a, alpha_width); 862 if (!pll->vco_table || alpha_pll_find_vco(pll, req->rate)) 863 return 0; 864 865 min_freq = pll->vco_table[0].min_freq; 866 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 867 868 req->rate = clamp(req->rate, min_freq, max_freq); 869 870 return 0; 871 } 872 873 void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 874 const struct alpha_pll_config *config) 875 { 876 u32 val; 877 878 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 879 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 880 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 881 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 882 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 883 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 884 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 885 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 886 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 887 888 /* Set PLL_BYPASSNL */ 889 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); 890 regmap_read(regmap, PLL_MODE(pll), &val); 891 892 /* Wait 5 us between setting BYPASS and deasserting reset */ 893 udelay(5); 894 895 /* Take PLL out from reset state */ 896 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 897 regmap_read(regmap, PLL_MODE(pll), &val); 898 899 /* Wait 50us for PLL_LOCK_DET bit to go high */ 900 usleep_range(50, 55); 901 902 /* Enable PLL output */ 903 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 904 } 905 EXPORT_SYMBOL_GPL(clk_huayra_2290_pll_configure); 906 907 static unsigned long 908 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a) 909 { 910 /* 911 * a contains 16 bit alpha_val in two’s complement number in the range 912 * of [-0.5, 0.5). 913 */ 914 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 915 l -= 1; 916 917 return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH); 918 } 919 920 static unsigned long 921 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate, 922 u32 *l, u32 *a) 923 { 924 u64 remainder; 925 u64 quotient; 926 927 quotient = rate; 928 remainder = do_div(quotient, prate); 929 *l = quotient; 930 931 if (!remainder) { 932 *a = 0; 933 return rate; 934 } 935 936 quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH; 937 remainder = do_div(quotient, prate); 938 939 if (remainder) 940 quotient++; 941 942 /* 943 * alpha_val should be in two’s complement number in the range 944 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value 945 * since alpha value will be subtracted in this case. 946 */ 947 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 948 *l += 1; 949 950 *a = quotient; 951 return alpha_huayra_pll_calc_rate(prate, *l, *a); 952 } 953 954 static unsigned long 955 alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 956 { 957 u64 rate = parent_rate, tmp; 958 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 959 u32 l, alpha = 0, ctl, alpha_m, alpha_n; 960 961 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) 962 return 0; 963 964 if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl)) 965 return 0; 966 967 if (ctl & PLL_ALPHA_EN) { 968 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); 969 /* 970 * Depending upon alpha_mode, it can be treated as M/N value or 971 * as a two’s complement number. When alpha_mode=1, 972 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N 973 * 974 * Fout=FIN*(L+(M/N)) 975 * 976 * M is a signed number (-128 to 127) and N is unsigned 977 * (0 to 255). M/N has to be within +/-0.5. 978 * 979 * When alpha_mode=0, it is a two’s complement number in the 980 * range [-0.5, 0.5). 981 * 982 * Fout=FIN*(L+(alpha_val)/2^16) 983 * 984 * where alpha_val is two’s complement number. 985 */ 986 if (!(ctl & PLL_ALPHA_MODE)) 987 return alpha_huayra_pll_calc_rate(rate, l, alpha); 988 989 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK; 990 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK; 991 992 rate *= l; 993 tmp = parent_rate; 994 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) { 995 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m; 996 tmp *= alpha_m; 997 do_div(tmp, alpha_n); 998 rate -= tmp; 999 } else { 1000 tmp *= alpha_m; 1001 do_div(tmp, alpha_n); 1002 rate += tmp; 1003 } 1004 1005 return rate; 1006 } 1007 1008 return alpha_huayra_pll_calc_rate(rate, l, alpha); 1009 } 1010 1011 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate, 1012 unsigned long prate) 1013 { 1014 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1015 u32 l, a, ctl, cur_alpha = 0; 1016 1017 rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a); 1018 1019 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 1020 1021 if (ctl & PLL_ALPHA_EN) 1022 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); 1023 1024 /* 1025 * Huayra PLL supports PLL dynamic programming. User can change L_VAL, 1026 * without having to go through the power on sequence. 1027 */ 1028 if (clk_alpha_pll_is_enabled(hw)) { 1029 if (cur_alpha != a) { 1030 pr_err("%s: clock needs to be gated\n", 1031 clk_hw_get_name(hw)); 1032 return -EBUSY; 1033 } 1034 1035 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1036 /* Ensure that the write above goes to detect L val change. */ 1037 mb(); 1038 return wait_for_pll_enable_lock(pll); 1039 } 1040 1041 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1042 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1043 1044 if (a == 0) 1045 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1046 PLL_ALPHA_EN, 0x0); 1047 else 1048 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1049 PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN); 1050 1051 return 0; 1052 } 1053 1054 static int alpha_pll_huayra_determine_rate(struct clk_hw *hw, 1055 struct clk_rate_request *req) 1056 { 1057 u32 l, a; 1058 1059 req->rate = alpha_huayra_pll_round_rate(req->rate, 1060 req->best_parent_rate, &l, &a); 1061 1062 return 0; 1063 } 1064 1065 static int trion_pll_is_enabled(struct clk_alpha_pll *pll, 1066 struct regmap *regmap) 1067 { 1068 u32 mode_val, opmode_val; 1069 int ret; 1070 1071 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); 1072 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 1073 if (ret) 1074 return 0; 1075 1076 return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL)); 1077 } 1078 1079 static int clk_trion_pll_is_enabled(struct clk_hw *hw) 1080 { 1081 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1082 1083 return trion_pll_is_enabled(pll, pll->clkr.regmap); 1084 } 1085 1086 static int clk_trion_pll_enable(struct clk_hw *hw) 1087 { 1088 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1089 struct regmap *regmap = pll->clkr.regmap; 1090 u32 val; 1091 int ret; 1092 1093 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1094 if (ret) 1095 return ret; 1096 1097 /* If in FSM mode, just vote for it */ 1098 if (val & PLL_VOTE_FSM_ENA) { 1099 ret = clk_enable_regmap(hw); 1100 if (ret) 1101 return ret; 1102 return wait_for_pll_enable_active(pll); 1103 } 1104 1105 /* Set operation mode to RUN */ 1106 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 1107 1108 ret = wait_for_pll_enable_lock(pll); 1109 if (ret) 1110 return ret; 1111 1112 /* Enable the PLL outputs */ 1113 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1114 PLL_OUT_MASK, PLL_OUT_MASK); 1115 if (ret) 1116 return ret; 1117 1118 /* Enable the global PLL outputs */ 1119 return regmap_update_bits(regmap, PLL_MODE(pll), 1120 PLL_OUTCTRL, PLL_OUTCTRL); 1121 } 1122 1123 static void clk_trion_pll_disable(struct clk_hw *hw) 1124 { 1125 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1126 struct regmap *regmap = pll->clkr.regmap; 1127 u32 val; 1128 int ret; 1129 1130 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1131 if (ret) 1132 return; 1133 1134 /* If in FSM mode, just unvote it */ 1135 if (val & PLL_VOTE_FSM_ENA) { 1136 clk_disable_regmap(hw); 1137 return; 1138 } 1139 1140 /* Disable the global PLL output */ 1141 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1142 if (ret) 1143 return; 1144 1145 /* Disable the PLL outputs */ 1146 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1147 PLL_OUT_MASK, 0); 1148 if (ret) 1149 return; 1150 1151 /* Place the PLL mode in STANDBY */ 1152 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1153 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1154 } 1155 1156 static unsigned long 1157 clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1158 { 1159 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1160 u32 l, frac, alpha_width = pll_alpha_width(pll); 1161 1162 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) 1163 return 0; 1164 1165 if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac)) 1166 return 0; 1167 1168 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 1169 } 1170 1171 const struct clk_ops clk_alpha_pll_fixed_ops = { 1172 .enable = clk_alpha_pll_enable, 1173 .disable = clk_alpha_pll_disable, 1174 .is_enabled = clk_alpha_pll_is_enabled, 1175 .recalc_rate = clk_alpha_pll_recalc_rate, 1176 }; 1177 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops); 1178 1179 const struct clk_ops clk_alpha_pll_ops = { 1180 .enable = clk_alpha_pll_enable, 1181 .disable = clk_alpha_pll_disable, 1182 .is_enabled = clk_alpha_pll_is_enabled, 1183 .recalc_rate = clk_alpha_pll_recalc_rate, 1184 .determine_rate = clk_alpha_pll_determine_rate, 1185 .set_rate = clk_alpha_pll_set_rate, 1186 }; 1187 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops); 1188 1189 const struct clk_ops clk_alpha_pll_huayra_ops = { 1190 .enable = clk_alpha_pll_enable, 1191 .disable = clk_alpha_pll_disable, 1192 .is_enabled = clk_alpha_pll_is_enabled, 1193 .recalc_rate = alpha_pll_huayra_recalc_rate, 1194 .determine_rate = alpha_pll_huayra_determine_rate, 1195 .set_rate = alpha_pll_huayra_set_rate, 1196 }; 1197 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops); 1198 1199 const struct clk_ops clk_alpha_pll_hwfsm_ops = { 1200 .enable = clk_alpha_pll_hwfsm_enable, 1201 .disable = clk_alpha_pll_hwfsm_disable, 1202 .is_enabled = clk_alpha_pll_hwfsm_is_enabled, 1203 .recalc_rate = clk_alpha_pll_recalc_rate, 1204 .determine_rate = clk_alpha_pll_determine_rate, 1205 .set_rate = clk_alpha_pll_hwfsm_set_rate, 1206 }; 1207 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); 1208 1209 const struct clk_ops clk_alpha_pll_fixed_trion_ops = { 1210 .enable = clk_trion_pll_enable, 1211 .disable = clk_trion_pll_disable, 1212 .is_enabled = clk_trion_pll_is_enabled, 1213 .recalc_rate = clk_trion_pll_recalc_rate, 1214 .determine_rate = clk_alpha_pll_determine_rate, 1215 }; 1216 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops); 1217 1218 static unsigned long 1219 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1220 { 1221 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1222 u32 ctl; 1223 1224 if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl)) 1225 return 0; 1226 1227 ctl >>= PLL_POST_DIV_SHIFT; 1228 ctl &= PLL_POST_DIV_MASK(pll); 1229 1230 return parent_rate >> fls(ctl); 1231 } 1232 1233 static const struct clk_div_table clk_alpha_div_table[] = { 1234 { 0x0, 1 }, 1235 { 0x1, 2 }, 1236 { 0x3, 4 }, 1237 { 0x7, 8 }, 1238 { 0xf, 16 }, 1239 { } 1240 }; 1241 1242 static const struct clk_div_table clk_alpha_2bit_div_table[] = { 1243 { 0x0, 1 }, 1244 { 0x1, 2 }, 1245 { 0x3, 4 }, 1246 { } 1247 }; 1248 1249 static int clk_alpha_pll_postdiv_determine_rate(struct clk_hw *hw, 1250 struct clk_rate_request *req) 1251 { 1252 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1253 const struct clk_div_table *table; 1254 1255 if (pll->width == 2) 1256 table = clk_alpha_2bit_div_table; 1257 else 1258 table = clk_alpha_div_table; 1259 1260 req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate, 1261 table, pll->width, 1262 CLK_DIVIDER_POWER_OF_TWO); 1263 1264 return 0; 1265 } 1266 1267 static int clk_alpha_pll_postdiv_ro_determine_rate(struct clk_hw *hw, 1268 struct clk_rate_request *req) 1269 { 1270 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1271 u32 ctl, div; 1272 1273 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 1274 1275 ctl >>= PLL_POST_DIV_SHIFT; 1276 ctl &= BIT(pll->width) - 1; 1277 div = 1 << fls(ctl); 1278 1279 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) 1280 req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), 1281 div * req->rate); 1282 1283 req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); 1284 1285 return 0; 1286 } 1287 1288 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1289 unsigned long parent_rate) 1290 { 1291 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1292 int div; 1293 1294 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ 1295 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1; 1296 1297 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1298 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 1299 div << PLL_POST_DIV_SHIFT); 1300 } 1301 1302 const struct clk_ops clk_alpha_pll_postdiv_ops = { 1303 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1304 .determine_rate = clk_alpha_pll_postdiv_determine_rate, 1305 .set_rate = clk_alpha_pll_postdiv_set_rate, 1306 }; 1307 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops); 1308 1309 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = { 1310 .determine_rate = clk_alpha_pll_postdiv_ro_determine_rate, 1311 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1312 }; 1313 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops); 1314 1315 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1316 const struct alpha_pll_config *config) 1317 { 1318 u32 val, mask; 1319 1320 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1321 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha); 1322 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1323 config->config_ctl_val); 1324 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1325 config->config_ctl_hi_val); 1326 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1327 config->user_ctl_val); 1328 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1329 config->user_ctl_hi_val); 1330 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1331 config->test_ctl_val); 1332 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1333 config->test_ctl_hi_val); 1334 1335 if (config->post_div_mask) { 1336 mask = config->post_div_mask; 1337 val = config->post_div_val; 1338 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 1339 } 1340 1341 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE) 1342 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE, 1343 PLL_FSM_LEGACY_MODE); 1344 1345 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1346 PLL_UPDATE_BYPASS); 1347 1348 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1349 } 1350 EXPORT_SYMBOL_GPL(clk_fabia_pll_configure); 1351 1352 static int alpha_pll_fabia_enable(struct clk_hw *hw) 1353 { 1354 int ret; 1355 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1356 u32 val, opmode_val; 1357 struct regmap *regmap = pll->clkr.regmap; 1358 1359 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1360 if (ret) 1361 return ret; 1362 1363 /* If in FSM mode, just vote for it */ 1364 if (val & PLL_VOTE_FSM_ENA) { 1365 ret = clk_enable_regmap(hw); 1366 if (ret) 1367 return ret; 1368 return wait_for_pll_enable_active(pll); 1369 } 1370 1371 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 1372 if (ret) 1373 return ret; 1374 1375 /* Skip If PLL is already running */ 1376 if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL)) 1377 return 0; 1378 1379 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1380 if (ret) 1381 return ret; 1382 1383 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1384 if (ret) 1385 return ret; 1386 1387 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 1388 PLL_RESET_N); 1389 if (ret) 1390 return ret; 1391 1392 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 1393 if (ret) 1394 return ret; 1395 1396 ret = wait_for_pll_enable_lock(pll); 1397 if (ret) 1398 return ret; 1399 1400 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1401 PLL_OUT_MASK, PLL_OUT_MASK); 1402 if (ret) 1403 return ret; 1404 1405 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 1406 PLL_OUTCTRL); 1407 } 1408 1409 static void alpha_pll_fabia_disable(struct clk_hw *hw) 1410 { 1411 int ret; 1412 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1413 u32 val; 1414 struct regmap *regmap = pll->clkr.regmap; 1415 1416 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1417 if (ret) 1418 return; 1419 1420 /* If in FSM mode, just unvote it */ 1421 if (val & PLL_FSM_ENA) { 1422 clk_disable_regmap(hw); 1423 return; 1424 } 1425 1426 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1427 if (ret) 1428 return; 1429 1430 /* Disable main outputs */ 1431 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 1432 if (ret) 1433 return; 1434 1435 /* Place the PLL in STANDBY */ 1436 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1437 } 1438 1439 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw, 1440 unsigned long parent_rate) 1441 { 1442 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1443 u32 l, frac, alpha_width = pll_alpha_width(pll); 1444 1445 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) 1446 return 0; 1447 1448 if (regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac)) 1449 return 0; 1450 1451 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 1452 } 1453 1454 /* 1455 * Due to limited number of bits for fractional rate programming, the 1456 * rounded up rate could be marginally higher than the requested rate. 1457 */ 1458 static int alpha_pll_check_rate_margin(struct clk_hw *hw, 1459 unsigned long rrate, unsigned long rate) 1460 { 1461 unsigned long rate_margin = rate + PLL_RATE_MARGIN; 1462 1463 if (rrate > rate_margin || rrate < rate) { 1464 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n", 1465 clk_hw_get_name(hw), rrate, rate, rate_margin); 1466 return -EINVAL; 1467 } 1468 1469 return 0; 1470 } 1471 1472 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate, 1473 unsigned long prate) 1474 { 1475 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1476 u32 l, alpha_width = pll_alpha_width(pll); 1477 unsigned long rrate; 1478 int ret; 1479 u64 a; 1480 1481 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1482 1483 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1484 if (ret < 0) 1485 return ret; 1486 1487 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1488 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); 1489 1490 return __clk_alpha_pll_update_latch(pll); 1491 } 1492 1493 static int alpha_pll_fabia_prepare(struct clk_hw *hw) 1494 { 1495 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1496 const struct pll_vco *vco; 1497 struct clk_hw *parent_hw; 1498 unsigned long cal_freq, rrate; 1499 u32 cal_l, val, alpha_width = pll_alpha_width(pll); 1500 const char *name = clk_hw_get_name(hw); 1501 u64 a; 1502 int ret; 1503 1504 /* Check if calibration needs to be done i.e. PLL is in reset */ 1505 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1506 if (ret) 1507 return ret; 1508 1509 /* Return early if calibration is not needed. */ 1510 if (val & PLL_RESET_N) 1511 return 0; 1512 1513 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); 1514 if (!vco) { 1515 pr_err("%s: alpha pll not in a valid vco range\n", name); 1516 return -EINVAL; 1517 } 1518 1519 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq + 1520 pll->vco_table[0].max_freq) * 54, 100); 1521 1522 parent_hw = clk_hw_get_parent(hw); 1523 if (!parent_hw) 1524 return -EINVAL; 1525 1526 rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw), 1527 &cal_l, &a, alpha_width); 1528 1529 ret = alpha_pll_check_rate_margin(hw, rrate, cal_freq); 1530 if (ret < 0) 1531 return ret; 1532 1533 /* Setup PLL for calibration frequency */ 1534 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l); 1535 1536 /* Bringup the PLL at calibration frequency */ 1537 ret = clk_alpha_pll_enable(hw); 1538 if (ret) { 1539 pr_err("%s: alpha pll calibration failed\n", name); 1540 return ret; 1541 } 1542 1543 clk_alpha_pll_disable(hw); 1544 1545 return 0; 1546 } 1547 1548 const struct clk_ops clk_alpha_pll_fabia_ops = { 1549 .prepare = alpha_pll_fabia_prepare, 1550 .enable = alpha_pll_fabia_enable, 1551 .disable = alpha_pll_fabia_disable, 1552 .is_enabled = clk_alpha_pll_is_enabled, 1553 .set_rate = alpha_pll_fabia_set_rate, 1554 .recalc_rate = alpha_pll_fabia_recalc_rate, 1555 .determine_rate = clk_alpha_pll_determine_rate, 1556 }; 1557 EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops); 1558 1559 const struct clk_ops clk_alpha_pll_fixed_fabia_ops = { 1560 .enable = alpha_pll_fabia_enable, 1561 .disable = alpha_pll_fabia_disable, 1562 .is_enabled = clk_alpha_pll_is_enabled, 1563 .recalc_rate = alpha_pll_fabia_recalc_rate, 1564 .determine_rate = clk_alpha_pll_determine_rate, 1565 }; 1566 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops); 1567 1568 static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw, 1569 unsigned long parent_rate) 1570 { 1571 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1572 u32 i, div = 1, val; 1573 int ret; 1574 1575 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1576 if (ret) 1577 return ret; 1578 1579 val >>= pll->post_div_shift; 1580 val &= BIT(pll->width) - 1; 1581 1582 for (i = 0; i < pll->num_post_div; i++) { 1583 if (pll->post_div_table[i].val == val) { 1584 div = pll->post_div_table[i].div; 1585 break; 1586 } 1587 } 1588 1589 return (parent_rate / div); 1590 } 1591 1592 static unsigned long 1593 clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1594 { 1595 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1596 struct regmap *regmap = pll->clkr.regmap; 1597 u32 i, div = 1, val; 1598 1599 if (regmap_read(regmap, PLL_USER_CTL(pll), &val)) 1600 return 0; 1601 1602 val >>= pll->post_div_shift; 1603 val &= PLL_POST_DIV_MASK(pll); 1604 1605 for (i = 0; i < pll->num_post_div; i++) { 1606 if (pll->post_div_table[i].val == val) { 1607 div = pll->post_div_table[i].div; 1608 break; 1609 } 1610 } 1611 1612 return (parent_rate / div); 1613 } 1614 1615 static int clk_trion_pll_postdiv_determine_rate(struct clk_hw *hw, 1616 struct clk_rate_request *req) 1617 { 1618 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1619 1620 req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate, 1621 pll->post_div_table, 1622 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1623 1624 return 0; 1625 }; 1626 1627 static int 1628 clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1629 unsigned long parent_rate) 1630 { 1631 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1632 struct regmap *regmap = pll->clkr.regmap; 1633 int i, val = 0, div; 1634 1635 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1636 for (i = 0; i < pll->num_post_div; i++) { 1637 if (pll->post_div_table[i].div == div) { 1638 val = pll->post_div_table[i].val; 1639 break; 1640 } 1641 } 1642 1643 return regmap_update_bits(regmap, PLL_USER_CTL(pll), 1644 PLL_POST_DIV_MASK(pll) << pll->post_div_shift, 1645 val << pll->post_div_shift); 1646 } 1647 1648 const struct clk_ops clk_alpha_pll_postdiv_trion_ops = { 1649 .recalc_rate = clk_trion_pll_postdiv_recalc_rate, 1650 .determine_rate = clk_trion_pll_postdiv_determine_rate, 1651 .set_rate = clk_trion_pll_postdiv_set_rate, 1652 }; 1653 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops); 1654 1655 static int clk_alpha_pll_postdiv_fabia_determine_rate(struct clk_hw *hw, 1656 struct clk_rate_request *req) 1657 { 1658 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1659 1660 req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate, 1661 pll->post_div_table, 1662 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1663 1664 return 0; 1665 } 1666 1667 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw, 1668 unsigned long rate, unsigned long parent_rate) 1669 { 1670 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1671 int i, val = 0, div, ret; 1672 1673 /* 1674 * If the PLL is in FSM mode, then treat set_rate callback as a 1675 * no-operation. 1676 */ 1677 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1678 if (ret) 1679 return ret; 1680 1681 if (val & PLL_VOTE_FSM_ENA) 1682 return 0; 1683 1684 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1685 for (i = 0; i < pll->num_post_div; i++) { 1686 if (pll->post_div_table[i].div == div) { 1687 val = pll->post_div_table[i].val; 1688 break; 1689 } 1690 } 1691 1692 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1693 (BIT(pll->width) - 1) << pll->post_div_shift, 1694 val << pll->post_div_shift); 1695 } 1696 1697 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = { 1698 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1699 .determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate, 1700 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1701 }; 1702 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops); 1703 1704 /** 1705 * clk_trion_pll_configure - configure the trion pll 1706 * 1707 * @pll: clk alpha pll 1708 * @regmap: register map 1709 * @config: configuration to apply for pll 1710 */ 1711 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1712 const struct alpha_pll_config *config) 1713 { 1714 /* 1715 * If the bootloader left the PLL enabled it's likely that there are 1716 * RCGs that will lock up if we disable the PLL below. 1717 */ 1718 if (trion_pll_is_enabled(pll, regmap)) { 1719 pr_debug("Trion PLL is already enabled, skipping configuration\n"); 1720 return; 1721 } 1722 1723 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1724 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); 1725 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1726 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1727 config->config_ctl_val); 1728 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1729 config->config_ctl_hi_val); 1730 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), 1731 config->config_ctl_hi1_val); 1732 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1733 config->user_ctl_val); 1734 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1735 config->user_ctl_hi_val); 1736 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), 1737 config->user_ctl_hi1_val); 1738 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1739 config->test_ctl_val); 1740 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1741 config->test_ctl_hi_val); 1742 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), 1743 config->test_ctl_hi1_val); 1744 1745 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1746 PLL_UPDATE_BYPASS); 1747 1748 /* Disable PLL output */ 1749 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1750 1751 /* Set operation mode to OFF */ 1752 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1753 1754 /* Place the PLL in STANDBY mode */ 1755 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1756 } 1757 EXPORT_SYMBOL_GPL(clk_trion_pll_configure); 1758 1759 /* 1760 * The TRION PLL requires a power-on self-calibration which happens when the 1761 * PLL comes out of reset. Calibrate in case it is not completed. 1762 */ 1763 static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done) 1764 { 1765 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1766 u32 val; 1767 int ret; 1768 1769 /* Return early if calibration is not needed. */ 1770 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); 1771 if (val & pcal_done) 1772 return 0; 1773 1774 /* On/off to calibrate */ 1775 ret = clk_trion_pll_enable(hw); 1776 if (!ret) 1777 clk_trion_pll_disable(hw); 1778 1779 return ret; 1780 } 1781 1782 static int alpha_pll_trion_prepare(struct clk_hw *hw) 1783 { 1784 return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE); 1785 } 1786 1787 static int alpha_pll_lucid_prepare(struct clk_hw *hw) 1788 { 1789 return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE); 1790 } 1791 1792 static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1793 unsigned long prate, u32 latch_bit, u32 latch_ack) 1794 { 1795 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1796 unsigned long rrate; 1797 u32 val, l, alpha_width = pll_alpha_width(pll); 1798 u64 a; 1799 int ret; 1800 1801 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1802 1803 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1804 if (ret < 0) 1805 return ret; 1806 1807 regmap_update_bits(pll->clkr.regmap, PLL_L_VAL(pll), LUCID_EVO_PLL_L_VAL_MASK, l); 1808 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1809 1810 /* Latch the PLL input */ 1811 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); 1812 if (ret) 1813 return ret; 1814 1815 /* Wait for 2 reference cycles before checking the ACK bit. */ 1816 udelay(1); 1817 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1818 if (!(val & latch_ack)) { 1819 pr_err("Lucid PLL latch failed. Output may be unstable!\n"); 1820 return -EINVAL; 1821 } 1822 1823 /* Return the latch input to 0 */ 1824 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); 1825 if (ret) 1826 return ret; 1827 1828 if (clk_hw_is_enabled(hw)) { 1829 ret = wait_for_pll_enable_lock(pll); 1830 if (ret) 1831 return ret; 1832 } 1833 1834 /* Wait for PLL output to stabilize */ 1835 udelay(100); 1836 return 0; 1837 } 1838 1839 static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1840 unsigned long prate) 1841 { 1842 return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH); 1843 } 1844 1845 const struct clk_ops clk_alpha_pll_trion_ops = { 1846 .prepare = alpha_pll_trion_prepare, 1847 .enable = clk_trion_pll_enable, 1848 .disable = clk_trion_pll_disable, 1849 .is_enabled = clk_trion_pll_is_enabled, 1850 .recalc_rate = clk_trion_pll_recalc_rate, 1851 .determine_rate = clk_alpha_pll_determine_rate, 1852 .set_rate = alpha_pll_trion_set_rate, 1853 }; 1854 EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops); 1855 1856 const struct clk_ops clk_alpha_pll_lucid_ops = { 1857 .prepare = alpha_pll_lucid_prepare, 1858 .enable = clk_trion_pll_enable, 1859 .disable = clk_trion_pll_disable, 1860 .is_enabled = clk_trion_pll_is_enabled, 1861 .recalc_rate = clk_trion_pll_recalc_rate, 1862 .determine_rate = clk_alpha_pll_determine_rate, 1863 .set_rate = alpha_pll_trion_set_rate, 1864 }; 1865 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops); 1866 1867 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { 1868 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1869 .determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate, 1870 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1871 }; 1872 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops); 1873 1874 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1875 const struct alpha_pll_config *config) 1876 { 1877 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1878 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1879 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1880 config->user_ctl_val); 1881 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1882 config->config_ctl_val); 1883 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1884 config->config_ctl_hi_val); 1885 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1886 config->test_ctl_val); 1887 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1888 config->test_ctl_hi_val); 1889 } 1890 EXPORT_SYMBOL_GPL(clk_agera_pll_configure); 1891 1892 static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate, 1893 unsigned long prate) 1894 { 1895 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1896 u32 l, alpha_width = pll_alpha_width(pll); 1897 int ret; 1898 unsigned long rrate; 1899 u64 a; 1900 1901 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1902 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1903 if (ret < 0) 1904 return ret; 1905 1906 /* change L_VAL without having to go through the power on sequence */ 1907 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1908 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1909 1910 if (clk_hw_is_enabled(hw)) 1911 return wait_for_pll_enable_lock(pll); 1912 1913 return 0; 1914 } 1915 1916 const struct clk_ops clk_alpha_pll_agera_ops = { 1917 .enable = clk_alpha_pll_enable, 1918 .disable = clk_alpha_pll_disable, 1919 .is_enabled = clk_alpha_pll_is_enabled, 1920 .recalc_rate = alpha_pll_fabia_recalc_rate, 1921 .determine_rate = clk_alpha_pll_determine_rate, 1922 .set_rate = clk_alpha_pll_agera_set_rate, 1923 }; 1924 EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops); 1925 1926 /** 1927 * clk_lucid_5lpe_pll_configure - configure the lucid 5lpe pll 1928 * 1929 * @pll: clk alpha pll 1930 * @regmap: register map 1931 * @config: configuration to apply for pll 1932 */ 1933 void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1934 const struct alpha_pll_config *config) 1935 { 1936 /* 1937 * If the bootloader left the PLL enabled it's likely that there are 1938 * RCGs that will lock up if we disable the PLL below. 1939 */ 1940 if (trion_pll_is_enabled(pll, regmap)) { 1941 pr_debug("Lucid 5LPE PLL is already enabled, skipping configuration\n"); 1942 return; 1943 } 1944 1945 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1946 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); 1947 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1948 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1949 config->config_ctl_val); 1950 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1951 config->config_ctl_hi_val); 1952 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), 1953 config->config_ctl_hi1_val); 1954 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1955 config->user_ctl_val); 1956 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1957 config->user_ctl_hi_val); 1958 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), 1959 config->user_ctl_hi1_val); 1960 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1961 config->test_ctl_val); 1962 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1963 config->test_ctl_hi_val); 1964 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), 1965 config->test_ctl_hi1_val); 1966 1967 /* Disable PLL output */ 1968 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1969 1970 /* Set operation mode to OFF */ 1971 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1972 1973 /* Place the PLL in STANDBY mode */ 1974 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1975 } 1976 EXPORT_SYMBOL_GPL(clk_lucid_5lpe_pll_configure); 1977 1978 static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw) 1979 { 1980 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1981 u32 val; 1982 int ret; 1983 1984 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1985 if (ret) 1986 return ret; 1987 1988 /* If in FSM mode, just vote for it */ 1989 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 1990 ret = clk_enable_regmap(hw); 1991 if (ret) 1992 return ret; 1993 return wait_for_pll_enable_lock(pll); 1994 } 1995 1996 /* Check if PLL is already enabled, return if enabled */ 1997 if (trion_pll_is_enabled(pll, pll->clkr.regmap)) 1998 return 0; 1999 2000 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2001 if (ret) 2002 return ret; 2003 2004 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); 2005 2006 ret = wait_for_pll_enable_lock(pll); 2007 if (ret) 2008 return ret; 2009 2010 /* Enable the PLL outputs */ 2011 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 2012 if (ret) 2013 return ret; 2014 2015 /* Enable the global PLL outputs */ 2016 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2017 } 2018 2019 static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw) 2020 { 2021 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2022 u32 val; 2023 int ret; 2024 2025 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 2026 if (ret) 2027 return; 2028 2029 /* If in FSM mode, just unvote it */ 2030 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 2031 clk_disable_regmap(hw); 2032 return; 2033 } 2034 2035 /* Disable the global PLL output */ 2036 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2037 if (ret) 2038 return; 2039 2040 /* Disable the PLL outputs */ 2041 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 2042 if (ret) 2043 return; 2044 2045 /* Place the PLL mode in STANDBY */ 2046 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY); 2047 } 2048 2049 /* 2050 * The Lucid 5LPE PLL requires a power-on self-calibration which happens 2051 * when the PLL comes out of reset. Calibrate in case it is not completed. 2052 */ 2053 static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw) 2054 { 2055 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2056 struct clk_hw *p; 2057 u32 val = 0; 2058 int ret; 2059 2060 /* Return early if calibration is not needed. */ 2061 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 2062 if (val & LUCID_5LPE_PCAL_DONE) 2063 return 0; 2064 2065 p = clk_hw_get_parent(hw); 2066 if (!p) 2067 return -EINVAL; 2068 2069 ret = alpha_pll_lucid_5lpe_enable(hw); 2070 if (ret) 2071 return ret; 2072 2073 alpha_pll_lucid_5lpe_disable(hw); 2074 2075 return 0; 2076 } 2077 2078 static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate, 2079 unsigned long prate) 2080 { 2081 return __alpha_pll_trion_set_rate(hw, rate, prate, 2082 LUCID_5LPE_PLL_LATCH_INPUT, 2083 LUCID_5LPE_ALPHA_PLL_ACK_LATCH); 2084 } 2085 2086 static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 2087 unsigned long parent_rate, 2088 unsigned long enable_vote_run) 2089 { 2090 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 2091 struct regmap *regmap = pll->clkr.regmap; 2092 int i, val, div, ret; 2093 u32 mask; 2094 2095 /* 2096 * If the PLL is in FSM mode, then treat set_rate callback as a 2097 * no-operation. 2098 */ 2099 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2100 if (ret) 2101 return ret; 2102 2103 if (val & enable_vote_run) 2104 return 0; 2105 2106 if (!pll->post_div_table) { 2107 pr_err("Missing the post_div_table for the %s PLL\n", 2108 clk_hw_get_name(&pll->clkr.hw)); 2109 return -EINVAL; 2110 } 2111 2112 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); 2113 for (i = 0; i < pll->num_post_div; i++) { 2114 if (pll->post_div_table[i].div == div) { 2115 val = pll->post_div_table[i].val; 2116 break; 2117 } 2118 } 2119 2120 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); 2121 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 2122 mask, val << pll->post_div_shift); 2123 } 2124 2125 static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 2126 unsigned long parent_rate) 2127 { 2128 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN); 2129 } 2130 2131 const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = { 2132 .prepare = alpha_pll_lucid_5lpe_prepare, 2133 .enable = alpha_pll_lucid_5lpe_enable, 2134 .disable = alpha_pll_lucid_5lpe_disable, 2135 .is_enabled = clk_trion_pll_is_enabled, 2136 .recalc_rate = clk_trion_pll_recalc_rate, 2137 .determine_rate = clk_alpha_pll_determine_rate, 2138 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2139 }; 2140 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops); 2141 2142 const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = { 2143 .enable = alpha_pll_lucid_5lpe_enable, 2144 .disable = alpha_pll_lucid_5lpe_disable, 2145 .is_enabled = clk_trion_pll_is_enabled, 2146 .recalc_rate = clk_trion_pll_recalc_rate, 2147 .determine_rate = clk_alpha_pll_determine_rate, 2148 }; 2149 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops); 2150 2151 const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = { 2152 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 2153 .determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate, 2154 .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate, 2155 }; 2156 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops); 2157 2158 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2159 const struct alpha_pll_config *config) 2160 { 2161 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2162 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2163 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2164 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2165 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2166 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2167 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2168 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); 2169 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2170 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2171 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2172 2173 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0); 2174 2175 /* Disable PLL output */ 2176 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2177 2178 /* Set operation mode to OFF */ 2179 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2180 2181 /* Place the PLL in STANDBY mode */ 2182 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2183 } 2184 EXPORT_SYMBOL_GPL(clk_zonda_pll_configure); 2185 2186 static int clk_zonda_pll_enable(struct clk_hw *hw) 2187 { 2188 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2189 struct regmap *regmap = pll->clkr.regmap; 2190 u32 val; 2191 int ret; 2192 2193 regmap_read(regmap, PLL_MODE(pll), &val); 2194 2195 /* If in FSM mode, just vote for it */ 2196 if (val & PLL_VOTE_FSM_ENA) { 2197 ret = clk_enable_regmap(hw); 2198 if (ret) 2199 return ret; 2200 return wait_for_pll_enable_active(pll); 2201 } 2202 2203 /* Get the PLL out of bypass mode */ 2204 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); 2205 2206 /* 2207 * H/W requires a 1us delay between disabling the bypass and 2208 * de-asserting the reset. 2209 */ 2210 udelay(1); 2211 2212 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2213 2214 /* Set operation mode to RUN */ 2215 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2216 2217 regmap_read(regmap, PLL_TEST_CTL(pll), &val); 2218 2219 /* If cfa mode then poll for freq lock */ 2220 if (val & ZONDA_STAY_IN_CFA) 2221 ret = wait_for_zonda_pll_freq_lock(pll); 2222 else 2223 ret = wait_for_pll_enable_lock(pll); 2224 if (ret) 2225 return ret; 2226 2227 /* Enable the PLL outputs */ 2228 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK); 2229 2230 /* Enable the global PLL outputs */ 2231 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2232 2233 return 0; 2234 } 2235 2236 static void clk_zonda_pll_disable(struct clk_hw *hw) 2237 { 2238 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2239 struct regmap *regmap = pll->clkr.regmap; 2240 u32 val; 2241 2242 regmap_read(regmap, PLL_MODE(pll), &val); 2243 2244 /* If in FSM mode, just unvote it */ 2245 if (val & PLL_VOTE_FSM_ENA) { 2246 clk_disable_regmap(hw); 2247 return; 2248 } 2249 2250 /* Disable the global PLL output */ 2251 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2252 2253 /* Disable the PLL outputs */ 2254 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0); 2255 2256 /* Put the PLL in bypass and reset */ 2257 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0); 2258 2259 /* Place the PLL mode in OFF state */ 2260 regmap_write(regmap, PLL_OPMODE(pll), 0x0); 2261 } 2262 2263 static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32 *l) 2264 { 2265 u64 remainder, quotient; 2266 2267 quotient = rate; 2268 remainder = do_div(quotient, prate); 2269 2270 *l = rate + (u32)(remainder * 2 >= prate); 2271 } 2272 2273 static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, 2274 unsigned long prate) 2275 { 2276 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2277 unsigned long rrate; 2278 u32 test_ctl_val; 2279 u32 l, alpha_width = pll_alpha_width(pll); 2280 u64 a; 2281 int ret; 2282 2283 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 2284 2285 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 2286 if (ret < 0) 2287 return ret; 2288 2289 if (a & PLL_ALPHA_MSB) 2290 zonda_pll_adjust_l_val(rate, prate, &l); 2291 2292 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2293 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2294 2295 if (!clk_hw_is_enabled(hw)) 2296 return 0; 2297 2298 /* Wait before polling for the frequency latch */ 2299 udelay(5); 2300 2301 /* Read stay in cfa mode */ 2302 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val); 2303 2304 /* If cfa mode then poll for freq lock */ 2305 if (test_ctl_val & ZONDA_STAY_IN_CFA) 2306 ret = wait_for_zonda_pll_freq_lock(pll); 2307 else 2308 ret = wait_for_pll_enable_lock(pll); 2309 if (ret) 2310 return ret; 2311 2312 /* Wait for PLL output to stabilize */ 2313 udelay(100); 2314 return 0; 2315 } 2316 2317 const struct clk_ops clk_alpha_pll_zonda_ops = { 2318 .enable = clk_zonda_pll_enable, 2319 .disable = clk_zonda_pll_disable, 2320 .is_enabled = clk_trion_pll_is_enabled, 2321 .recalc_rate = clk_trion_pll_recalc_rate, 2322 .determine_rate = clk_alpha_pll_determine_rate, 2323 .set_rate = clk_zonda_pll_set_rate, 2324 }; 2325 EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops); 2326 2327 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2328 const struct alpha_pll_config *config) 2329 { 2330 u32 lval = config->l; 2331 2332 /* 2333 * If the bootloader left the PLL enabled it's likely that there are 2334 * RCGs that will lock up if we disable the PLL below. 2335 */ 2336 if (trion_pll_is_enabled(pll, regmap)) { 2337 pr_debug("Lucid Evo PLL is already enabled, skipping configuration\n"); 2338 return; 2339 } 2340 2341 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT; 2342 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); 2343 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2344 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2345 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2346 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2347 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2348 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2349 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2350 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2351 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2352 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); 2353 2354 /* Disable PLL output */ 2355 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2356 2357 /* Set operation mode to STANDBY and de-assert the reset */ 2358 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2359 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2360 } 2361 EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure); 2362 2363 void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2364 const struct alpha_pll_config *config) 2365 { 2366 u32 lval = config->l; 2367 2368 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT; 2369 lval |= TRION_PLL_CAL_VAL << LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT; 2370 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); 2371 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2372 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2373 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2374 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2375 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2376 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2377 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2378 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2379 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2380 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); 2381 2382 /* Disable PLL output */ 2383 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2384 2385 /* Set operation mode to STANDBY and de-assert the reset */ 2386 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2387 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2388 } 2389 EXPORT_SYMBOL_GPL(clk_lucid_ole_pll_configure); 2390 2391 static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) 2392 { 2393 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2394 struct regmap *regmap = pll->clkr.regmap; 2395 u32 val; 2396 int ret; 2397 2398 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2399 if (ret) 2400 return ret; 2401 2402 /* If in FSM mode, just vote for it */ 2403 if (val & LUCID_EVO_ENABLE_VOTE_RUN) { 2404 ret = clk_enable_regmap(hw); 2405 if (ret) 2406 return ret; 2407 return wait_for_pll_enable_lock(pll); 2408 } 2409 2410 /* Check if PLL is already enabled */ 2411 if (trion_pll_is_enabled(pll, regmap)) 2412 return 0; 2413 2414 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2415 if (ret) 2416 return ret; 2417 2418 /* Set operation mode to RUN */ 2419 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2420 2421 ret = wait_for_pll_enable_lock(pll); 2422 if (ret) 2423 return ret; 2424 2425 /* Enable the PLL outputs */ 2426 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 2427 if (ret) 2428 return ret; 2429 2430 /* Enable the global PLL outputs */ 2431 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2432 if (ret) 2433 return ret; 2434 2435 /* Ensure that the write above goes through before returning. */ 2436 mb(); 2437 return ret; 2438 } 2439 2440 static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset) 2441 { 2442 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2443 struct regmap *regmap = pll->clkr.regmap; 2444 u32 val; 2445 int ret; 2446 2447 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2448 if (ret) 2449 return; 2450 2451 /* If in FSM mode, just unvote it */ 2452 if (val & LUCID_EVO_ENABLE_VOTE_RUN) { 2453 clk_disable_regmap(hw); 2454 return; 2455 } 2456 2457 /* Disable the global PLL output */ 2458 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2459 if (ret) 2460 return; 2461 2462 /* Disable the PLL outputs */ 2463 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 2464 if (ret) 2465 return; 2466 2467 /* Place the PLL mode in STANDBY */ 2468 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2469 2470 if (reset) 2471 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0); 2472 } 2473 2474 static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset) 2475 { 2476 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2477 struct clk_hw *p; 2478 u32 val = 0; 2479 int ret; 2480 2481 /* Return early if calibration is not needed. */ 2482 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 2483 if (!(val & LUCID_EVO_PCAL_NOT_DONE)) 2484 return 0; 2485 2486 p = clk_hw_get_parent(hw); 2487 if (!p) 2488 return -EINVAL; 2489 2490 ret = alpha_pll_lucid_evo_enable(hw); 2491 if (ret) 2492 return ret; 2493 2494 _alpha_pll_lucid_evo_disable(hw, reset); 2495 2496 return 0; 2497 } 2498 2499 static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) 2500 { 2501 _alpha_pll_lucid_evo_disable(hw, false); 2502 } 2503 2504 static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw) 2505 { 2506 return _alpha_pll_lucid_evo_prepare(hw, false); 2507 } 2508 2509 static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw) 2510 { 2511 _alpha_pll_lucid_evo_disable(hw, true); 2512 } 2513 2514 static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw) 2515 { 2516 return _alpha_pll_lucid_evo_prepare(hw, true); 2517 } 2518 2519 static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, 2520 unsigned long parent_rate) 2521 { 2522 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2523 struct regmap *regmap = pll->clkr.regmap; 2524 u32 l, frac; 2525 2526 if (regmap_read(regmap, PLL_L_VAL(pll), &l)) 2527 return 0; 2528 l &= LUCID_EVO_PLL_L_VAL_MASK; 2529 2530 if (regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac)) 2531 return 0; 2532 2533 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); 2534 } 2535 2536 static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 2537 unsigned long parent_rate) 2538 { 2539 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN); 2540 } 2541 2542 const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = { 2543 .enable = alpha_pll_lucid_evo_enable, 2544 .disable = alpha_pll_lucid_evo_disable, 2545 .is_enabled = clk_trion_pll_is_enabled, 2546 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2547 .determine_rate = clk_alpha_pll_determine_rate, 2548 }; 2549 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops); 2550 2551 const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = { 2552 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 2553 .determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate, 2554 .set_rate = clk_lucid_evo_pll_postdiv_set_rate, 2555 }; 2556 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops); 2557 2558 const struct clk_ops clk_alpha_pll_lucid_evo_ops = { 2559 .prepare = alpha_pll_lucid_evo_prepare, 2560 .enable = alpha_pll_lucid_evo_enable, 2561 .disable = alpha_pll_lucid_evo_disable, 2562 .is_enabled = clk_trion_pll_is_enabled, 2563 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2564 .determine_rate = clk_alpha_pll_determine_rate, 2565 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2566 }; 2567 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops); 2568 2569 const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = { 2570 .prepare = alpha_pll_reset_lucid_evo_prepare, 2571 .enable = alpha_pll_lucid_evo_enable, 2572 .disable = alpha_pll_reset_lucid_evo_disable, 2573 .is_enabled = clk_trion_pll_is_enabled, 2574 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2575 .determine_rate = clk_alpha_pll_determine_rate, 2576 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2577 }; 2578 EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops); 2579 2580 static int alpha_pll_pongo_elu_prepare(struct clk_hw *hw) 2581 { 2582 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2583 struct regmap *regmap = pll->clkr.regmap; 2584 int ret; 2585 2586 /* Enable PLL intially to one-time calibrate against XO. */ 2587 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2588 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2589 regmap_update_bits(regmap, PLL_MODE(pll), PONGO_XO_PRESENT, PONGO_XO_PRESENT); 2590 2591 /* Set regmap for wait_for_pll() */ 2592 pll->clkr.regmap = regmap; 2593 ret = wait_for_pll_enable_lock(pll); 2594 if (ret) { 2595 /* Reverse calibration - disable PLL output */ 2596 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2597 return ret; 2598 } 2599 2600 /* Disable PLL after one-time calibration. */ 2601 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2602 2603 /* Select internally generated clock. */ 2604 regmap_update_bits(regmap, PLL_MODE(pll), PONGO_CLOCK_SELECT, 2605 PONGO_CLOCK_SELECT); 2606 2607 return 0; 2608 } 2609 2610 static int alpha_pll_pongo_elu_enable(struct clk_hw *hw) 2611 { 2612 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2613 struct regmap *regmap = pll->clkr.regmap; 2614 int ret; 2615 2616 /* Check if PLL is already enabled */ 2617 if (trion_pll_is_enabled(pll, regmap)) 2618 return 0; 2619 2620 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2621 if (ret) 2622 return ret; 2623 2624 /* Set operation mode to RUN */ 2625 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2626 2627 ret = wait_for_pll_enable_lock(pll); 2628 if (ret) 2629 return ret; 2630 2631 /* Enable the global PLL outputs */ 2632 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2633 if (ret) 2634 return ret; 2635 2636 /* Ensure that the write above goes through before returning. */ 2637 mb(); 2638 2639 return ret; 2640 } 2641 2642 static void alpha_pll_pongo_elu_disable(struct clk_hw *hw) 2643 { 2644 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2645 struct regmap *regmap = pll->clkr.regmap; 2646 int ret; 2647 2648 /* Disable the global PLL output */ 2649 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2650 if (ret) 2651 return; 2652 2653 /* Place the PLL mode in STANDBY */ 2654 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2655 } 2656 2657 static unsigned long alpha_pll_pongo_elu_recalc_rate(struct clk_hw *hw, 2658 unsigned long parent_rate) 2659 { 2660 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2661 struct regmap *regmap = pll->clkr.regmap; 2662 u32 l; 2663 2664 if (regmap_read(regmap, PLL_L_VAL(pll), &l)) 2665 return 0; 2666 2667 l &= PONGO_PLL_L_VAL_MASK; 2668 2669 return alpha_pll_calc_rate(parent_rate, l, 0, pll_alpha_width(pll)); 2670 } 2671 2672 const struct clk_ops clk_alpha_pll_pongo_elu_ops = { 2673 .prepare = alpha_pll_pongo_elu_prepare, 2674 .enable = alpha_pll_pongo_elu_enable, 2675 .disable = alpha_pll_pongo_elu_disable, 2676 .recalc_rate = alpha_pll_pongo_elu_recalc_rate, 2677 }; 2678 EXPORT_SYMBOL_GPL(clk_alpha_pll_pongo_elu_ops); 2679 2680 void clk_pongo_elu_pll_configure(struct clk_alpha_pll *pll, 2681 struct regmap *regmap, 2682 const struct alpha_pll_config *config) 2683 { 2684 u32 val; 2685 2686 regmap_update_bits(regmap, PLL_USER_CTL(pll), PONGO_PLL_OUT_MASK, 2687 PONGO_PLL_OUT_MASK); 2688 2689 if (trion_pll_is_enabled(pll, regmap)) 2690 return; 2691 2692 if (regmap_read(regmap, PLL_L_VAL(pll), &val)) 2693 return; 2694 val &= PONGO_PLL_L_VAL_MASK; 2695 if (val) 2696 return; 2697 2698 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2699 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2700 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2701 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2702 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2703 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U2(pll), config->config_ctl_hi2_val); 2704 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 2705 config->user_ctl_val | PONGO_PLL_OUT_MASK); 2706 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2707 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2708 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2709 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2710 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); 2711 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U3(pll), config->test_ctl_hi3_val); 2712 2713 /* Disable PLL output */ 2714 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2715 } 2716 EXPORT_SYMBOL_GPL(clk_pongo_elu_pll_configure); 2717 2718 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2719 const struct alpha_pll_config *config) 2720 { 2721 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2722 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2723 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2724 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2725 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2726 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2727 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2728 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2729 2730 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2731 2732 regmap_update_bits(regmap, PLL_MODE(pll), 2733 PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL, 2734 PLL_RESET_N | PLL_BYPASSNL); 2735 } 2736 EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure); 2737 2738 static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw, 2739 unsigned long parent_rate) 2740 { 2741 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2742 u32 l; 2743 2744 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) 2745 return 0; 2746 2747 return parent_rate * l; 2748 } 2749 2750 static int clk_rivian_evo_pll_determine_rate(struct clk_hw *hw, 2751 struct clk_rate_request *req) 2752 { 2753 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2754 unsigned long min_freq, max_freq; 2755 u32 l; 2756 u64 a; 2757 2758 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, &l, 2759 &a, 0); 2760 if (!pll->vco_table || alpha_pll_find_vco(pll, req->rate)) 2761 return 0; 2762 2763 min_freq = pll->vco_table[0].min_freq; 2764 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 2765 2766 req->rate = clamp(req->rate, min_freq, max_freq); 2767 2768 return 0; 2769 } 2770 2771 const struct clk_ops clk_alpha_pll_rivian_evo_ops = { 2772 .enable = alpha_pll_lucid_5lpe_enable, 2773 .disable = alpha_pll_lucid_5lpe_disable, 2774 .is_enabled = clk_trion_pll_is_enabled, 2775 .recalc_rate = clk_rivian_evo_pll_recalc_rate, 2776 .determine_rate = clk_rivian_evo_pll_determine_rate, 2777 }; 2778 EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops); 2779 2780 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2781 const struct alpha_pll_config *config) 2782 { 2783 u32 val, val_u, mask, mask_u; 2784 2785 regmap_write(regmap, PLL_L_VAL(pll), config->l); 2786 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2787 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2788 2789 if (pll_has_64bit_config(pll)) 2790 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), 2791 config->config_ctl_hi_val); 2792 2793 if (pll_alpha_width(pll) > 32) 2794 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); 2795 2796 val = config->main_output_mask; 2797 val |= config->aux_output_mask; 2798 val |= config->aux2_output_mask; 2799 val |= config->early_output_mask; 2800 val |= config->pre_div_val; 2801 val |= config->post_div_val; 2802 val |= config->vco_val; 2803 val |= config->alpha_en_mask; 2804 val |= config->alpha_mode_mask; 2805 2806 mask = config->main_output_mask; 2807 mask |= config->aux_output_mask; 2808 mask |= config->aux2_output_mask; 2809 mask |= config->early_output_mask; 2810 mask |= config->pre_div_mask; 2811 mask |= config->post_div_mask; 2812 mask |= config->vco_mask; 2813 mask |= config->alpha_en_mask; 2814 mask |= config->alpha_mode_mask; 2815 2816 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 2817 2818 /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */ 2819 val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT; 2820 val_u |= config->lock_det; 2821 2822 mask_u = config->status_mask; 2823 mask_u |= config->lock_det; 2824 2825 regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u); 2826 regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2827 regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2828 2829 if (pll->flags & SUPPORTS_FSM_MODE) 2830 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); 2831 } 2832 EXPORT_SYMBOL_GPL(clk_stromer_pll_configure); 2833 2834 static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw, 2835 struct clk_rate_request *req) 2836 { 2837 u32 l; 2838 u64 a; 2839 2840 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, 2841 &l, &a, ALPHA_REG_BITWIDTH); 2842 2843 return 0; 2844 } 2845 2846 static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate, 2847 unsigned long prate) 2848 { 2849 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2850 int ret; 2851 u32 l; 2852 u64 a; 2853 2854 rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH); 2855 2856 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2857 2858 a <<= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH; 2859 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2860 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 2861 a >> ALPHA_BITWIDTH); 2862 2863 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 2864 PLL_ALPHA_EN, PLL_ALPHA_EN); 2865 2866 if (!clk_hw_is_enabled(hw)) 2867 return 0; 2868 2869 /* 2870 * Stromer PLL supports Dynamic programming. 2871 * It allows the PLL frequency to be changed on-the-fly without first 2872 * execution of a shutdown procedure followed by a bring up procedure. 2873 */ 2874 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 2875 PLL_UPDATE); 2876 2877 ret = wait_for_pll_update(pll); 2878 if (ret) 2879 return ret; 2880 2881 return wait_for_pll_enable_lock(pll); 2882 } 2883 2884 const struct clk_ops clk_alpha_pll_stromer_ops = { 2885 .enable = clk_alpha_pll_enable, 2886 .disable = clk_alpha_pll_disable, 2887 .is_enabled = clk_alpha_pll_is_enabled, 2888 .recalc_rate = clk_alpha_pll_recalc_rate, 2889 .determine_rate = clk_alpha_pll_stromer_determine_rate, 2890 .set_rate = clk_alpha_pll_stromer_set_rate, 2891 }; 2892 EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops); 2893 2894 static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw, 2895 unsigned long rate, 2896 unsigned long prate) 2897 { 2898 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2899 u32 l, alpha_width = pll_alpha_width(pll); 2900 int ret, pll_mode; 2901 u64 a; 2902 2903 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 2904 2905 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode); 2906 if (ret) 2907 return ret; 2908 2909 regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0); 2910 2911 /* Delay of 2 output clock ticks required until output is disabled */ 2912 udelay(1); 2913 2914 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2915 2916 if (alpha_width > ALPHA_BITWIDTH) 2917 a <<= alpha_width - ALPHA_BITWIDTH; 2918 2919 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2920 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 2921 a >> ALPHA_BITWIDTH); 2922 2923 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 2924 PLL_ALPHA_EN, PLL_ALPHA_EN); 2925 2926 regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL); 2927 2928 /* Wait five micro seconds or more */ 2929 udelay(5); 2930 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, 2931 PLL_RESET_N); 2932 2933 /* The lock time should be less than 50 micro seconds worst case */ 2934 usleep_range(50, 60); 2935 2936 ret = wait_for_pll_enable_lock(pll); 2937 if (ret) { 2938 pr_err("Wait for PLL enable lock failed [%s] %d\n", 2939 clk_hw_get_name(hw), ret); 2940 return ret; 2941 } 2942 2943 if (pll_mode & PLL_OUTCTRL) 2944 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 2945 PLL_OUTCTRL); 2946 2947 return 0; 2948 } 2949 2950 const struct clk_ops clk_alpha_pll_stromer_plus_ops = { 2951 .prepare = clk_alpha_pll_enable, 2952 .unprepare = clk_alpha_pll_disable, 2953 .is_enabled = clk_alpha_pll_is_enabled, 2954 .recalc_rate = clk_alpha_pll_recalc_rate, 2955 .determine_rate = clk_alpha_pll_stromer_determine_rate, 2956 .set_rate = clk_alpha_pll_stromer_plus_set_rate, 2957 }; 2958 EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops); 2959 2960 void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2961 const struct alpha_pll_config *config) 2962 { 2963 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2964 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2965 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2966 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2967 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2968 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2969 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2970 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); 2971 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2972 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2973 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2974 2975 /* Set operation mode to STANDBY */ 2976 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2977 } 2978 EXPORT_SYMBOL_GPL(clk_regera_pll_configure); 2979 2980 const struct clk_ops clk_alpha_pll_regera_ops = { 2981 .enable = clk_zonda_pll_enable, 2982 .disable = clk_zonda_pll_disable, 2983 .is_enabled = clk_alpha_pll_is_enabled, 2984 .recalc_rate = clk_trion_pll_recalc_rate, 2985 .determine_rate = clk_alpha_pll_determine_rate, 2986 .set_rate = clk_zonda_pll_set_rate, 2987 }; 2988 EXPORT_SYMBOL_GPL(clk_alpha_pll_regera_ops); 2989 2990 void qcom_clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap) 2991 { 2992 const struct clk_init_data *init = pll->clkr.hw.init; 2993 2994 switch (GET_PLL_TYPE(pll)) { 2995 case CLK_ALPHA_PLL_TYPE_LUCID_OLE: 2996 clk_lucid_ole_pll_configure(pll, regmap, pll->config); 2997 break; 2998 case CLK_ALPHA_PLL_TYPE_LUCID_EVO: 2999 clk_lucid_evo_pll_configure(pll, regmap, pll->config); 3000 break; 3001 case CLK_ALPHA_PLL_TYPE_TAYCAN_ELU: 3002 clk_taycan_elu_pll_configure(pll, regmap, pll->config); 3003 break; 3004 case CLK_ALPHA_PLL_TYPE_RIVIAN_EVO: 3005 clk_rivian_evo_pll_configure(pll, regmap, pll->config); 3006 break; 3007 case CLK_ALPHA_PLL_TYPE_TRION: 3008 clk_trion_pll_configure(pll, regmap, pll->config); 3009 break; 3010 case CLK_ALPHA_PLL_TYPE_HUAYRA_2290: 3011 clk_huayra_2290_pll_configure(pll, regmap, pll->config); 3012 break; 3013 case CLK_ALPHA_PLL_TYPE_FABIA: 3014 clk_fabia_pll_configure(pll, regmap, pll->config); 3015 break; 3016 case CLK_ALPHA_PLL_TYPE_AGERA: 3017 clk_agera_pll_configure(pll, regmap, pll->config); 3018 break; 3019 case CLK_ALPHA_PLL_TYPE_PONGO_ELU: 3020 clk_pongo_elu_pll_configure(pll, regmap, pll->config); 3021 break; 3022 case CLK_ALPHA_PLL_TYPE_ZONDA: 3023 case CLK_ALPHA_PLL_TYPE_ZONDA_OLE: 3024 clk_zonda_pll_configure(pll, regmap, pll->config); 3025 break; 3026 case CLK_ALPHA_PLL_TYPE_STROMER: 3027 case CLK_ALPHA_PLL_TYPE_STROMER_PLUS: 3028 clk_stromer_pll_configure(pll, regmap, pll->config); 3029 break; 3030 case CLK_ALPHA_PLL_TYPE_DEFAULT: 3031 case CLK_ALPHA_PLL_TYPE_DEFAULT_EVO: 3032 case CLK_ALPHA_PLL_TYPE_HUAYRA: 3033 case CLK_ALPHA_PLL_TYPE_HUAYRA_APSS: 3034 case CLK_ALPHA_PLL_TYPE_BRAMMO: 3035 case CLK_ALPHA_PLL_TYPE_BRAMMO_EVO: 3036 clk_alpha_pll_configure(pll, regmap, pll->config); 3037 break; 3038 default: 3039 WARN(1, "%s: invalid pll type\n", init->name); 3040 break; 3041 } 3042 } 3043 EXPORT_SYMBOL_GPL(qcom_clk_alpha_pll_configure); 3044 3045 static int clk_alpha_pll_slew_update(struct clk_alpha_pll *pll) 3046 { 3047 u32 val; 3048 int ret; 3049 3050 regmap_set_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE); 3051 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 3052 3053 ret = wait_for_pll_update(pll); 3054 if (ret) 3055 return ret; 3056 /* 3057 * Hardware programming mandates a wait of at least 570ns before polling the LOCK 3058 * detect bit. Have a delay of 1us just to be safe. 3059 */ 3060 udelay(1); 3061 3062 return wait_for_pll_enable_lock(pll); 3063 } 3064 3065 static int clk_alpha_pll_slew_set_rate(struct clk_hw *hw, unsigned long rate, 3066 unsigned long parent_rate) 3067 { 3068 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 3069 const struct pll_vco *curr_vco, *vco; 3070 unsigned long freq_hz; 3071 u64 a; 3072 u32 l; 3073 3074 freq_hz = alpha_pll_round_rate(rate, parent_rate, &l, &a, ALPHA_REG_BITWIDTH); 3075 if (freq_hz != rate) { 3076 pr_err("alpha_pll: Call clk_set_rate with rounded rates!\n"); 3077 return -EINVAL; 3078 } 3079 3080 curr_vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); 3081 if (!curr_vco) { 3082 pr_err("alpha pll: not in a valid vco range\n"); 3083 return -EINVAL; 3084 } 3085 3086 vco = alpha_pll_find_vco(pll, freq_hz); 3087 if (!vco) { 3088 pr_err("alpha pll: not in a valid vco range\n"); 3089 return -EINVAL; 3090 } 3091 3092 /* 3093 * Dynamic pll update will not support switching frequencies across 3094 * vco ranges. In those cases fall back to normal alpha set rate. 3095 */ 3096 if (curr_vco->val != vco->val) 3097 return clk_alpha_pll_set_rate(hw, rate, parent_rate); 3098 3099 clk_alpha_pll_update_configs(pll, NULL, l, a, ALPHA_REG_BITWIDTH, false); 3100 3101 /* Ensure that the write above goes before slewing the PLL */ 3102 mb(); 3103 3104 if (clk_hw_is_enabled(hw)) 3105 return clk_alpha_pll_slew_update(pll); 3106 3107 return 0; 3108 } 3109 3110 /* 3111 * Slewing plls should be bought up at frequency which is in the middle of the 3112 * desired VCO range. So after bringing up the pll at calibration freq, set it 3113 * back to desired frequency(that was set by previous clk_set_rate). 3114 */ 3115 static int clk_alpha_pll_calibrate(struct clk_hw *hw) 3116 { 3117 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 3118 struct clk_hw *parent; 3119 const struct pll_vco *vco; 3120 unsigned long calibration_freq, freq_hz; 3121 u64 a; 3122 u32 l; 3123 int rc; 3124 3125 parent = clk_hw_get_parent(hw); 3126 if (!parent) { 3127 pr_err("alpha pll: no valid parent found\n"); 3128 return -EINVAL; 3129 } 3130 3131 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); 3132 if (!vco) { 3133 pr_err("alpha pll: not in a valid vco range\n"); 3134 return -EINVAL; 3135 } 3136 3137 /* 3138 * As during slewing plls vco_sel won't be allowed to change, vco table 3139 * should have only one entry table, i.e. index = 0, find the 3140 * calibration frequency. 3141 */ 3142 calibration_freq = (pll->vco_table[0].min_freq + pll->vco_table[0].max_freq) / 2; 3143 3144 freq_hz = alpha_pll_round_rate(calibration_freq, clk_hw_get_rate(parent), 3145 &l, &a, ALPHA_REG_BITWIDTH); 3146 if (freq_hz != calibration_freq) { 3147 pr_err("alpha_pll: call clk_set_rate with rounded rates!\n"); 3148 return -EINVAL; 3149 } 3150 3151 clk_alpha_pll_update_configs(pll, vco, l, a, ALPHA_REG_BITWIDTH, false); 3152 3153 /* Bringup the pll at calibration frequency */ 3154 rc = clk_alpha_pll_enable(hw); 3155 if (rc) { 3156 pr_err("alpha pll calibration failed\n"); 3157 return rc; 3158 } 3159 3160 /* 3161 * PLL is already running at calibration frequency. 3162 * So slew pll to the previously set frequency. 3163 */ 3164 freq_hz = alpha_pll_round_rate(clk_hw_get_rate(hw), 3165 clk_hw_get_rate(parent), &l, &a, ALPHA_REG_BITWIDTH); 3166 3167 pr_debug("pll %s: setting back to required rate %lu, freq_hz %ld\n", 3168 clk_hw_get_name(hw), clk_hw_get_rate(hw), freq_hz); 3169 3170 clk_alpha_pll_update_configs(pll, NULL, l, a, ALPHA_REG_BITWIDTH, true); 3171 3172 return clk_alpha_pll_slew_update(pll); 3173 } 3174 3175 static int clk_alpha_pll_slew_enable(struct clk_hw *hw) 3176 { 3177 int rc; 3178 3179 rc = clk_alpha_pll_calibrate(hw); 3180 if (rc) 3181 return rc; 3182 3183 return clk_alpha_pll_enable(hw); 3184 } 3185 3186 const struct clk_ops clk_alpha_pll_slew_ops = { 3187 .enable = clk_alpha_pll_slew_enable, 3188 .disable = clk_alpha_pll_disable, 3189 .recalc_rate = clk_alpha_pll_recalc_rate, 3190 .determine_rate = clk_alpha_pll_determine_rate, 3191 .set_rate = clk_alpha_pll_slew_set_rate, 3192 }; 3193 EXPORT_SYMBOL(clk_alpha_pll_slew_ops); 3194