1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, 2023, Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/export.h> 9 #include <linux/clk-provider.h> 10 #include <linux/regmap.h> 11 #include <linux/delay.h> 12 13 #include "clk-alpha-pll.h" 14 #include "common.h" 15 16 #define PLL_MODE(p) ((p)->offset + 0x0) 17 # define PLL_OUTCTRL BIT(0) 18 # define PLL_BYPASSNL BIT(1) 19 # define PLL_RESET_N BIT(2) 20 # define PLL_OFFLINE_REQ BIT(7) 21 # define PLL_LOCK_COUNT_SHIFT 8 22 # define PLL_LOCK_COUNT_MASK 0x3f 23 # define PLL_BIAS_COUNT_SHIFT 14 24 # define PLL_BIAS_COUNT_MASK 0x3f 25 # define PLL_VOTE_FSM_ENA BIT(20) 26 # define PLL_FSM_ENA BIT(20) 27 # define PLL_VOTE_FSM_RESET BIT(21) 28 # define PLL_UPDATE BIT(22) 29 # define PLL_UPDATE_BYPASS BIT(23) 30 # define PLL_FSM_LEGACY_MODE BIT(24) 31 # define PLL_OFFLINE_ACK BIT(28) 32 # define ALPHA_PLL_ACK_LATCH BIT(29) 33 # define PLL_ACTIVE_FLAG BIT(30) 34 # define PLL_LOCK_DET BIT(31) 35 36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL]) 37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL]) 38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL]) 39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U]) 40 41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) 42 # define PLL_POST_DIV_SHIFT 8 43 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0) 44 # define PLL_ALPHA_EN BIT(24) 45 # define PLL_ALPHA_MODE BIT(25) 46 # define PLL_VCO_SHIFT 20 47 # define PLL_VCO_MASK 0x3 48 49 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U]) 50 #define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1]) 51 52 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL]) 53 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U]) 54 #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1]) 55 #define PLL_CONFIG_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U2]) 56 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) 57 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) 58 #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1]) 59 #define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2]) 60 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) 61 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE]) 62 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC]) 63 64 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 65 [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 66 [PLL_OFF_L_VAL] = 0x04, 67 [PLL_OFF_ALPHA_VAL] = 0x08, 68 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 69 [PLL_OFF_USER_CTL] = 0x10, 70 [PLL_OFF_USER_CTL_U] = 0x14, 71 [PLL_OFF_CONFIG_CTL] = 0x18, 72 [PLL_OFF_TEST_CTL] = 0x1c, 73 [PLL_OFF_TEST_CTL_U] = 0x20, 74 [PLL_OFF_STATUS] = 0x24, 75 }, 76 [CLK_ALPHA_PLL_TYPE_HUAYRA] = { 77 [PLL_OFF_L_VAL] = 0x04, 78 [PLL_OFF_ALPHA_VAL] = 0x08, 79 [PLL_OFF_USER_CTL] = 0x10, 80 [PLL_OFF_CONFIG_CTL] = 0x14, 81 [PLL_OFF_CONFIG_CTL_U] = 0x18, 82 [PLL_OFF_TEST_CTL] = 0x1c, 83 [PLL_OFF_TEST_CTL_U] = 0x20, 84 [PLL_OFF_STATUS] = 0x24, 85 }, 86 [CLK_ALPHA_PLL_TYPE_HUAYRA_APSS] = { 87 [PLL_OFF_L_VAL] = 0x08, 88 [PLL_OFF_ALPHA_VAL] = 0x10, 89 [PLL_OFF_USER_CTL] = 0x18, 90 [PLL_OFF_CONFIG_CTL] = 0x20, 91 [PLL_OFF_CONFIG_CTL_U] = 0x24, 92 [PLL_OFF_STATUS] = 0x28, 93 [PLL_OFF_TEST_CTL] = 0x30, 94 [PLL_OFF_TEST_CTL_U] = 0x34, 95 }, 96 [CLK_ALPHA_PLL_TYPE_HUAYRA_2290] = { 97 [PLL_OFF_L_VAL] = 0x04, 98 [PLL_OFF_ALPHA_VAL] = 0x08, 99 [PLL_OFF_USER_CTL] = 0x0c, 100 [PLL_OFF_CONFIG_CTL] = 0x10, 101 [PLL_OFF_CONFIG_CTL_U] = 0x14, 102 [PLL_OFF_CONFIG_CTL_U1] = 0x18, 103 [PLL_OFF_TEST_CTL] = 0x1c, 104 [PLL_OFF_TEST_CTL_U] = 0x20, 105 [PLL_OFF_TEST_CTL_U1] = 0x24, 106 [PLL_OFF_OPMODE] = 0x28, 107 [PLL_OFF_STATUS] = 0x38, 108 }, 109 [CLK_ALPHA_PLL_TYPE_BRAMMO] = { 110 [PLL_OFF_L_VAL] = 0x04, 111 [PLL_OFF_ALPHA_VAL] = 0x08, 112 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 113 [PLL_OFF_USER_CTL] = 0x10, 114 [PLL_OFF_CONFIG_CTL] = 0x18, 115 [PLL_OFF_TEST_CTL] = 0x1c, 116 [PLL_OFF_STATUS] = 0x24, 117 }, 118 [CLK_ALPHA_PLL_TYPE_FABIA] = { 119 [PLL_OFF_L_VAL] = 0x04, 120 [PLL_OFF_USER_CTL] = 0x0c, 121 [PLL_OFF_USER_CTL_U] = 0x10, 122 [PLL_OFF_CONFIG_CTL] = 0x14, 123 [PLL_OFF_CONFIG_CTL_U] = 0x18, 124 [PLL_OFF_TEST_CTL] = 0x1c, 125 [PLL_OFF_TEST_CTL_U] = 0x20, 126 [PLL_OFF_STATUS] = 0x24, 127 [PLL_OFF_OPMODE] = 0x2c, 128 [PLL_OFF_FRAC] = 0x38, 129 }, 130 [CLK_ALPHA_PLL_TYPE_TRION] = { 131 [PLL_OFF_L_VAL] = 0x04, 132 [PLL_OFF_CAL_L_VAL] = 0x08, 133 [PLL_OFF_USER_CTL] = 0x0c, 134 [PLL_OFF_USER_CTL_U] = 0x10, 135 [PLL_OFF_USER_CTL_U1] = 0x14, 136 [PLL_OFF_CONFIG_CTL] = 0x18, 137 [PLL_OFF_CONFIG_CTL_U] = 0x1c, 138 [PLL_OFF_CONFIG_CTL_U1] = 0x20, 139 [PLL_OFF_TEST_CTL] = 0x24, 140 [PLL_OFF_TEST_CTL_U] = 0x28, 141 [PLL_OFF_TEST_CTL_U1] = 0x2c, 142 [PLL_OFF_STATUS] = 0x30, 143 [PLL_OFF_OPMODE] = 0x38, 144 [PLL_OFF_ALPHA_VAL] = 0x40, 145 }, 146 [CLK_ALPHA_PLL_TYPE_AGERA] = { 147 [PLL_OFF_L_VAL] = 0x04, 148 [PLL_OFF_ALPHA_VAL] = 0x08, 149 [PLL_OFF_USER_CTL] = 0x0c, 150 [PLL_OFF_CONFIG_CTL] = 0x10, 151 [PLL_OFF_CONFIG_CTL_U] = 0x14, 152 [PLL_OFF_TEST_CTL] = 0x18, 153 [PLL_OFF_TEST_CTL_U] = 0x1c, 154 [PLL_OFF_STATUS] = 0x2c, 155 }, 156 [CLK_ALPHA_PLL_TYPE_ZONDA] = { 157 [PLL_OFF_L_VAL] = 0x04, 158 [PLL_OFF_ALPHA_VAL] = 0x08, 159 [PLL_OFF_USER_CTL] = 0x0c, 160 [PLL_OFF_CONFIG_CTL] = 0x10, 161 [PLL_OFF_CONFIG_CTL_U] = 0x14, 162 [PLL_OFF_CONFIG_CTL_U1] = 0x18, 163 [PLL_OFF_TEST_CTL] = 0x1c, 164 [PLL_OFF_TEST_CTL_U] = 0x20, 165 [PLL_OFF_TEST_CTL_U1] = 0x24, 166 [PLL_OFF_OPMODE] = 0x28, 167 [PLL_OFF_STATUS] = 0x38, 168 }, 169 [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = { 170 [PLL_OFF_OPMODE] = 0x04, 171 [PLL_OFF_STATUS] = 0x0c, 172 [PLL_OFF_L_VAL] = 0x10, 173 [PLL_OFF_ALPHA_VAL] = 0x14, 174 [PLL_OFF_USER_CTL] = 0x18, 175 [PLL_OFF_USER_CTL_U] = 0x1c, 176 [PLL_OFF_CONFIG_CTL] = 0x20, 177 [PLL_OFF_CONFIG_CTL_U] = 0x24, 178 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 179 [PLL_OFF_TEST_CTL] = 0x2c, 180 [PLL_OFF_TEST_CTL_U] = 0x30, 181 [PLL_OFF_TEST_CTL_U1] = 0x34, 182 }, 183 [CLK_ALPHA_PLL_TYPE_LUCID_OLE] = { 184 [PLL_OFF_OPMODE] = 0x04, 185 [PLL_OFF_STATE] = 0x08, 186 [PLL_OFF_STATUS] = 0x0c, 187 [PLL_OFF_L_VAL] = 0x10, 188 [PLL_OFF_ALPHA_VAL] = 0x14, 189 [PLL_OFF_USER_CTL] = 0x18, 190 [PLL_OFF_USER_CTL_U] = 0x1c, 191 [PLL_OFF_CONFIG_CTL] = 0x20, 192 [PLL_OFF_CONFIG_CTL_U] = 0x24, 193 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 194 [PLL_OFF_TEST_CTL] = 0x2c, 195 [PLL_OFF_TEST_CTL_U] = 0x30, 196 [PLL_OFF_TEST_CTL_U1] = 0x34, 197 [PLL_OFF_TEST_CTL_U2] = 0x38, 198 }, 199 [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = { 200 [PLL_OFF_OPMODE] = 0x04, 201 [PLL_OFF_STATUS] = 0x0c, 202 [PLL_OFF_L_VAL] = 0x10, 203 [PLL_OFF_USER_CTL] = 0x14, 204 [PLL_OFF_USER_CTL_U] = 0x18, 205 [PLL_OFF_CONFIG_CTL] = 0x1c, 206 [PLL_OFF_CONFIG_CTL_U] = 0x20, 207 [PLL_OFF_CONFIG_CTL_U1] = 0x24, 208 [PLL_OFF_TEST_CTL] = 0x28, 209 [PLL_OFF_TEST_CTL_U] = 0x2c, 210 }, 211 [CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = { 212 [PLL_OFF_L_VAL] = 0x04, 213 [PLL_OFF_ALPHA_VAL] = 0x08, 214 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 215 [PLL_OFF_TEST_CTL] = 0x10, 216 [PLL_OFF_TEST_CTL_U] = 0x14, 217 [PLL_OFF_USER_CTL] = 0x18, 218 [PLL_OFF_USER_CTL_U] = 0x1c, 219 [PLL_OFF_CONFIG_CTL] = 0x20, 220 [PLL_OFF_STATUS] = 0x24, 221 }, 222 [CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = { 223 [PLL_OFF_L_VAL] = 0x04, 224 [PLL_OFF_ALPHA_VAL] = 0x08, 225 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 226 [PLL_OFF_TEST_CTL] = 0x10, 227 [PLL_OFF_TEST_CTL_U] = 0x14, 228 [PLL_OFF_USER_CTL] = 0x18, 229 [PLL_OFF_CONFIG_CTL] = 0x1C, 230 [PLL_OFF_STATUS] = 0x20, 231 }, 232 [CLK_ALPHA_PLL_TYPE_STROMER] = { 233 [PLL_OFF_L_VAL] = 0x08, 234 [PLL_OFF_ALPHA_VAL] = 0x10, 235 [PLL_OFF_ALPHA_VAL_U] = 0x14, 236 [PLL_OFF_USER_CTL] = 0x18, 237 [PLL_OFF_USER_CTL_U] = 0x1c, 238 [PLL_OFF_CONFIG_CTL] = 0x20, 239 [PLL_OFF_STATUS] = 0x28, 240 [PLL_OFF_TEST_CTL] = 0x30, 241 [PLL_OFF_TEST_CTL_U] = 0x34, 242 }, 243 [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = { 244 [PLL_OFF_L_VAL] = 0x04, 245 [PLL_OFF_USER_CTL] = 0x08, 246 [PLL_OFF_USER_CTL_U] = 0x0c, 247 [PLL_OFF_CONFIG_CTL] = 0x10, 248 [PLL_OFF_TEST_CTL] = 0x14, 249 [PLL_OFF_TEST_CTL_U] = 0x18, 250 [PLL_OFF_STATUS] = 0x1c, 251 [PLL_OFF_ALPHA_VAL] = 0x24, 252 [PLL_OFF_ALPHA_VAL_U] = 0x28, 253 }, 254 [CLK_ALPHA_PLL_TYPE_ZONDA_OLE] = { 255 [PLL_OFF_L_VAL] = 0x04, 256 [PLL_OFF_ALPHA_VAL] = 0x08, 257 [PLL_OFF_USER_CTL] = 0x0c, 258 [PLL_OFF_USER_CTL_U] = 0x10, 259 [PLL_OFF_CONFIG_CTL] = 0x14, 260 [PLL_OFF_CONFIG_CTL_U] = 0x18, 261 [PLL_OFF_CONFIG_CTL_U1] = 0x1c, 262 [PLL_OFF_CONFIG_CTL_U2] = 0x20, 263 [PLL_OFF_TEST_CTL] = 0x24, 264 [PLL_OFF_TEST_CTL_U] = 0x28, 265 [PLL_OFF_TEST_CTL_U1] = 0x2c, 266 [PLL_OFF_OPMODE] = 0x30, 267 [PLL_OFF_STATUS] = 0x3c, 268 }, 269 }; 270 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 271 272 /* 273 * Even though 40 bits are present, use only 32 for ease of calculation. 274 */ 275 #define ALPHA_REG_BITWIDTH 40 276 #define ALPHA_REG_16BIT_WIDTH 16 277 #define ALPHA_BITWIDTH 32U 278 #define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH) 279 280 #define ALPHA_PLL_STATUS_REG_SHIFT 8 281 282 #define PLL_HUAYRA_M_WIDTH 8 283 #define PLL_HUAYRA_M_SHIFT 8 284 #define PLL_HUAYRA_M_MASK 0xff 285 #define PLL_HUAYRA_N_SHIFT 0 286 #define PLL_HUAYRA_N_MASK 0xff 287 #define PLL_HUAYRA_ALPHA_WIDTH 16 288 289 #define PLL_STANDBY 0x0 290 #define PLL_RUN 0x1 291 #define PLL_OUT_MASK 0x7 292 #define PLL_RATE_MARGIN 500 293 294 /* TRION PLL specific settings and offsets */ 295 #define TRION_PLL_CAL_VAL 0x44 296 #define TRION_PCAL_DONE BIT(26) 297 298 /* LUCID PLL specific settings and offsets */ 299 #define LUCID_PCAL_DONE BIT(27) 300 301 /* LUCID 5LPE PLL specific settings and offsets */ 302 #define LUCID_5LPE_PCAL_DONE BIT(11) 303 #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13) 304 #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14) 305 #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) 306 307 /* LUCID EVO PLL specific settings and offsets */ 308 #define LUCID_EVO_PCAL_NOT_DONE BIT(8) 309 #define LUCID_EVO_ENABLE_VOTE_RUN BIT(25) 310 #define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0) 311 #define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16 312 #define LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT 24 313 314 /* ZONDA PLL specific */ 315 #define ZONDA_PLL_OUT_MASK 0xf 316 #define ZONDA_STAY_IN_CFA BIT(16) 317 #define ZONDA_PLL_FREQ_LOCK_DET BIT(29) 318 319 #define pll_alpha_width(p) \ 320 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ 321 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) 322 323 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4) 324 325 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ 326 struct clk_alpha_pll, clkr) 327 328 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \ 329 struct clk_alpha_pll_postdiv, clkr) 330 331 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, 332 const char *action) 333 { 334 u32 val; 335 int count; 336 int ret; 337 const char *name = clk_hw_get_name(&pll->clkr.hw); 338 339 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 340 if (ret) 341 return ret; 342 343 for (count = 200; count > 0; count--) { 344 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 345 if (ret) 346 return ret; 347 if (inverse && !(val & mask)) 348 return 0; 349 else if ((val & mask) == mask) 350 return 0; 351 352 udelay(1); 353 } 354 355 WARN(1, "%s failed to %s!\n", name, action); 356 return -ETIMEDOUT; 357 } 358 359 #define wait_for_pll_enable_active(pll) \ 360 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable") 361 362 #define wait_for_pll_enable_lock(pll) \ 363 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable") 364 365 #define wait_for_zonda_pll_freq_lock(pll) \ 366 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable") 367 368 #define wait_for_pll_disable(pll) \ 369 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable") 370 371 #define wait_for_pll_offline(pll) \ 372 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline") 373 374 #define wait_for_pll_update(pll) \ 375 wait_for_pll(pll, PLL_UPDATE, 1, "update") 376 377 #define wait_for_pll_update_ack_set(pll) \ 378 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set") 379 380 #define wait_for_pll_update_ack_clear(pll) \ 381 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear") 382 383 static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg, 384 unsigned int val) 385 { 386 if (val) 387 regmap_write(regmap, reg, val); 388 } 389 390 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 391 const struct alpha_pll_config *config) 392 { 393 u32 val, mask; 394 395 regmap_write(regmap, PLL_L_VAL(pll), config->l); 396 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); 397 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 398 399 if (pll_has_64bit_config(pll)) 400 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), 401 config->config_ctl_hi_val); 402 403 if (pll_alpha_width(pll) > 32) 404 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); 405 406 val = config->main_output_mask; 407 val |= config->aux_output_mask; 408 val |= config->aux2_output_mask; 409 val |= config->early_output_mask; 410 val |= config->pre_div_val; 411 val |= config->post_div_val; 412 val |= config->vco_val; 413 val |= config->alpha_en_mask; 414 val |= config->alpha_mode_mask; 415 416 mask = config->main_output_mask; 417 mask |= config->aux_output_mask; 418 mask |= config->aux2_output_mask; 419 mask |= config->early_output_mask; 420 mask |= config->pre_div_mask; 421 mask |= config->post_div_mask; 422 mask |= config->vco_mask; 423 424 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 425 426 if (config->test_ctl_mask) 427 regmap_update_bits(regmap, PLL_TEST_CTL(pll), 428 config->test_ctl_mask, 429 config->test_ctl_val); 430 else 431 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 432 config->test_ctl_val); 433 434 if (config->test_ctl_hi_mask) 435 regmap_update_bits(regmap, PLL_TEST_CTL_U(pll), 436 config->test_ctl_hi_mask, 437 config->test_ctl_hi_val); 438 else 439 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 440 config->test_ctl_hi_val); 441 442 if (pll->flags & SUPPORTS_FSM_MODE) 443 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); 444 } 445 EXPORT_SYMBOL_GPL(clk_alpha_pll_configure); 446 447 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) 448 { 449 int ret; 450 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 451 u32 val; 452 453 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 454 if (ret) 455 return ret; 456 457 val |= PLL_FSM_ENA; 458 459 if (pll->flags & SUPPORTS_OFFLINE_REQ) 460 val &= ~PLL_OFFLINE_REQ; 461 462 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); 463 if (ret) 464 return ret; 465 466 /* Make sure enable request goes through before waiting for update */ 467 mb(); 468 469 return wait_for_pll_enable_active(pll); 470 } 471 472 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw) 473 { 474 int ret; 475 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 476 u32 val; 477 478 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 479 if (ret) 480 return; 481 482 if (pll->flags & SUPPORTS_OFFLINE_REQ) { 483 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 484 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ); 485 if (ret) 486 return; 487 488 ret = wait_for_pll_offline(pll); 489 if (ret) 490 return; 491 } 492 493 /* Disable hwfsm */ 494 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 495 PLL_FSM_ENA, 0); 496 if (ret) 497 return; 498 499 wait_for_pll_disable(pll); 500 } 501 502 static int pll_is_enabled(struct clk_hw *hw, u32 mask) 503 { 504 int ret; 505 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 506 u32 val; 507 508 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 509 if (ret) 510 return ret; 511 512 return !!(val & mask); 513 } 514 515 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw) 516 { 517 return pll_is_enabled(hw, PLL_ACTIVE_FLAG); 518 } 519 520 static int clk_alpha_pll_is_enabled(struct clk_hw *hw) 521 { 522 return pll_is_enabled(hw, PLL_LOCK_DET); 523 } 524 525 static int clk_alpha_pll_enable(struct clk_hw *hw) 526 { 527 int ret; 528 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 529 u32 val, mask; 530 531 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; 532 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 533 if (ret) 534 return ret; 535 536 /* If in FSM mode, just vote for it */ 537 if (val & PLL_VOTE_FSM_ENA) { 538 ret = clk_enable_regmap(hw); 539 if (ret) 540 return ret; 541 return wait_for_pll_enable_active(pll); 542 } 543 544 /* Skip if already enabled */ 545 if ((val & mask) == mask) 546 return 0; 547 548 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 549 PLL_BYPASSNL, PLL_BYPASSNL); 550 if (ret) 551 return ret; 552 553 /* 554 * H/W requires a 5us delay between disabling the bypass and 555 * de-asserting the reset. 556 */ 557 mb(); 558 udelay(5); 559 560 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 561 PLL_RESET_N, PLL_RESET_N); 562 if (ret) 563 return ret; 564 565 ret = wait_for_pll_enable_lock(pll); 566 if (ret) 567 return ret; 568 569 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 570 PLL_OUTCTRL, PLL_OUTCTRL); 571 572 /* Ensure that the write above goes through before returning. */ 573 mb(); 574 return ret; 575 } 576 577 static void clk_alpha_pll_disable(struct clk_hw *hw) 578 { 579 int ret; 580 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 581 u32 val, mask; 582 583 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 584 if (ret) 585 return; 586 587 /* If in FSM mode, just unvote it */ 588 if (val & PLL_VOTE_FSM_ENA) { 589 clk_disable_regmap(hw); 590 return; 591 } 592 593 mask = PLL_OUTCTRL; 594 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 595 596 /* Delay of 2 output clock ticks required until output is disabled */ 597 mb(); 598 udelay(1); 599 600 mask = PLL_RESET_N | PLL_BYPASSNL; 601 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 602 } 603 604 static unsigned long 605 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width) 606 { 607 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width)); 608 } 609 610 static unsigned long 611 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a, 612 u32 alpha_width) 613 { 614 u64 remainder; 615 u64 quotient; 616 617 quotient = rate; 618 remainder = do_div(quotient, prate); 619 *l = quotient; 620 621 if (!remainder) { 622 *a = 0; 623 return rate; 624 } 625 626 /* Upper ALPHA_BITWIDTH bits of Alpha */ 627 quotient = remainder << ALPHA_SHIFT(alpha_width); 628 629 remainder = do_div(quotient, prate); 630 631 if (remainder) 632 quotient++; 633 634 *a = quotient; 635 return alpha_pll_calc_rate(prate, *l, *a, alpha_width); 636 } 637 638 static const struct pll_vco * 639 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) 640 { 641 const struct pll_vco *v = pll->vco_table; 642 const struct pll_vco *end = v + pll->num_vco; 643 644 for (; v < end; v++) 645 if (rate >= v->min_freq && rate <= v->max_freq) 646 return v; 647 648 return NULL; 649 } 650 651 static unsigned long 652 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 653 { 654 u32 l, low, high, ctl; 655 u64 a = 0, prate = parent_rate; 656 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 657 u32 alpha_width = pll_alpha_width(pll); 658 659 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 660 661 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 662 if (ctl & PLL_ALPHA_EN) { 663 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); 664 if (alpha_width > 32) { 665 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 666 &high); 667 a = (u64)high << 32 | low; 668 } else { 669 a = low & GENMASK(alpha_width - 1, 0); 670 } 671 672 if (alpha_width > ALPHA_BITWIDTH) 673 a >>= alpha_width - ALPHA_BITWIDTH; 674 } 675 676 return alpha_pll_calc_rate(prate, l, a, alpha_width); 677 } 678 679 680 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) 681 { 682 int ret; 683 u32 mode; 684 685 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); 686 687 /* Latch the input to the PLL */ 688 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 689 PLL_UPDATE); 690 691 /* Wait for 2 reference cycle before checking ACK bit */ 692 udelay(1); 693 694 /* 695 * PLL will latch the new L, Alpha and freq control word. 696 * PLL will respond by raising PLL_ACK_LATCH output when new programming 697 * has been latched in and PLL is being updated. When 698 * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared 699 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. 700 */ 701 if (mode & PLL_UPDATE_BYPASS) { 702 ret = wait_for_pll_update_ack_set(pll); 703 if (ret) 704 return ret; 705 706 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); 707 } else { 708 ret = wait_for_pll_update(pll); 709 if (ret) 710 return ret; 711 } 712 713 ret = wait_for_pll_update_ack_clear(pll); 714 if (ret) 715 return ret; 716 717 /* Wait for PLL output to stabilize */ 718 udelay(10); 719 720 return 0; 721 } 722 723 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, 724 int (*is_enabled)(struct clk_hw *)) 725 { 726 if (!is_enabled(&pll->clkr.hw) || 727 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) 728 return 0; 729 730 return __clk_alpha_pll_update_latch(pll); 731 } 732 733 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 734 unsigned long prate, 735 int (*is_enabled)(struct clk_hw *)) 736 { 737 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 738 const struct pll_vco *vco; 739 u32 l, alpha_width = pll_alpha_width(pll); 740 u64 a; 741 742 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 743 vco = alpha_pll_find_vco(pll, rate); 744 if (pll->vco_table && !vco) { 745 pr_err("%s: alpha pll not in a valid vco range\n", 746 clk_hw_get_name(hw)); 747 return -EINVAL; 748 } 749 750 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 751 752 if (alpha_width > ALPHA_BITWIDTH) 753 a <<= alpha_width - ALPHA_BITWIDTH; 754 755 if (alpha_width > 32) 756 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); 757 758 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 759 760 if (vco) { 761 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 762 PLL_VCO_MASK << PLL_VCO_SHIFT, 763 vco->val << PLL_VCO_SHIFT); 764 } 765 766 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 767 PLL_ALPHA_EN, PLL_ALPHA_EN); 768 769 return clk_alpha_pll_update_latch(pll, is_enabled); 770 } 771 772 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 773 unsigned long prate) 774 { 775 return __clk_alpha_pll_set_rate(hw, rate, prate, 776 clk_alpha_pll_is_enabled); 777 } 778 779 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate, 780 unsigned long prate) 781 { 782 return __clk_alpha_pll_set_rate(hw, rate, prate, 783 clk_alpha_pll_hwfsm_is_enabled); 784 } 785 786 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, 787 unsigned long *prate) 788 { 789 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 790 u32 l, alpha_width = pll_alpha_width(pll); 791 u64 a; 792 unsigned long min_freq, max_freq; 793 794 rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width); 795 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) 796 return rate; 797 798 min_freq = pll->vco_table[0].min_freq; 799 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 800 801 return clamp(rate, min_freq, max_freq); 802 } 803 804 void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 805 const struct alpha_pll_config *config) 806 { 807 u32 val; 808 809 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 810 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 811 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 812 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 813 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 814 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 815 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 816 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 817 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 818 819 /* Set PLL_BYPASSNL */ 820 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); 821 regmap_read(regmap, PLL_MODE(pll), &val); 822 823 /* Wait 5 us between setting BYPASS and deasserting reset */ 824 udelay(5); 825 826 /* Take PLL out from reset state */ 827 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 828 regmap_read(regmap, PLL_MODE(pll), &val); 829 830 /* Wait 50us for PLL_LOCK_DET bit to go high */ 831 usleep_range(50, 55); 832 833 /* Enable PLL output */ 834 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 835 } 836 EXPORT_SYMBOL_GPL(clk_huayra_2290_pll_configure); 837 838 static unsigned long 839 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a) 840 { 841 /* 842 * a contains 16 bit alpha_val in two’s complement number in the range 843 * of [-0.5, 0.5). 844 */ 845 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 846 l -= 1; 847 848 return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH); 849 } 850 851 static unsigned long 852 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate, 853 u32 *l, u32 *a) 854 { 855 u64 remainder; 856 u64 quotient; 857 858 quotient = rate; 859 remainder = do_div(quotient, prate); 860 *l = quotient; 861 862 if (!remainder) { 863 *a = 0; 864 return rate; 865 } 866 867 quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH; 868 remainder = do_div(quotient, prate); 869 870 if (remainder) 871 quotient++; 872 873 /* 874 * alpha_val should be in two’s complement number in the range 875 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value 876 * since alpha value will be subtracted in this case. 877 */ 878 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 879 *l += 1; 880 881 *a = quotient; 882 return alpha_huayra_pll_calc_rate(prate, *l, *a); 883 } 884 885 static unsigned long 886 alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 887 { 888 u64 rate = parent_rate, tmp; 889 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 890 u32 l, alpha = 0, ctl, alpha_m, alpha_n; 891 892 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 893 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 894 895 if (ctl & PLL_ALPHA_EN) { 896 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); 897 /* 898 * Depending upon alpha_mode, it can be treated as M/N value or 899 * as a two’s complement number. When alpha_mode=1, 900 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N 901 * 902 * Fout=FIN*(L+(M/N)) 903 * 904 * M is a signed number (-128 to 127) and N is unsigned 905 * (0 to 255). M/N has to be within +/-0.5. 906 * 907 * When alpha_mode=0, it is a two’s complement number in the 908 * range [-0.5, 0.5). 909 * 910 * Fout=FIN*(L+(alpha_val)/2^16) 911 * 912 * where alpha_val is two’s complement number. 913 */ 914 if (!(ctl & PLL_ALPHA_MODE)) 915 return alpha_huayra_pll_calc_rate(rate, l, alpha); 916 917 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK; 918 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK; 919 920 rate *= l; 921 tmp = parent_rate; 922 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) { 923 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m; 924 tmp *= alpha_m; 925 do_div(tmp, alpha_n); 926 rate -= tmp; 927 } else { 928 tmp *= alpha_m; 929 do_div(tmp, alpha_n); 930 rate += tmp; 931 } 932 933 return rate; 934 } 935 936 return alpha_huayra_pll_calc_rate(rate, l, alpha); 937 } 938 939 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate, 940 unsigned long prate) 941 { 942 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 943 u32 l, a, ctl, cur_alpha = 0; 944 945 rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a); 946 947 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 948 949 if (ctl & PLL_ALPHA_EN) 950 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); 951 952 /* 953 * Huayra PLL supports PLL dynamic programming. User can change L_VAL, 954 * without having to go through the power on sequence. 955 */ 956 if (clk_alpha_pll_is_enabled(hw)) { 957 if (cur_alpha != a) { 958 pr_err("%s: clock needs to be gated\n", 959 clk_hw_get_name(hw)); 960 return -EBUSY; 961 } 962 963 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 964 /* Ensure that the write above goes to detect L val change. */ 965 mb(); 966 return wait_for_pll_enable_lock(pll); 967 } 968 969 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 970 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 971 972 if (a == 0) 973 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 974 PLL_ALPHA_EN, 0x0); 975 else 976 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 977 PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN); 978 979 return 0; 980 } 981 982 static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate, 983 unsigned long *prate) 984 { 985 u32 l, a; 986 987 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a); 988 } 989 990 static int trion_pll_is_enabled(struct clk_alpha_pll *pll, 991 struct regmap *regmap) 992 { 993 u32 mode_val, opmode_val; 994 int ret; 995 996 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); 997 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 998 if (ret) 999 return 0; 1000 1001 return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL)); 1002 } 1003 1004 static int clk_trion_pll_is_enabled(struct clk_hw *hw) 1005 { 1006 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1007 1008 return trion_pll_is_enabled(pll, pll->clkr.regmap); 1009 } 1010 1011 static int clk_trion_pll_enable(struct clk_hw *hw) 1012 { 1013 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1014 struct regmap *regmap = pll->clkr.regmap; 1015 u32 val; 1016 int ret; 1017 1018 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1019 if (ret) 1020 return ret; 1021 1022 /* If in FSM mode, just vote for it */ 1023 if (val & PLL_VOTE_FSM_ENA) { 1024 ret = clk_enable_regmap(hw); 1025 if (ret) 1026 return ret; 1027 return wait_for_pll_enable_active(pll); 1028 } 1029 1030 /* Set operation mode to RUN */ 1031 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 1032 1033 ret = wait_for_pll_enable_lock(pll); 1034 if (ret) 1035 return ret; 1036 1037 /* Enable the PLL outputs */ 1038 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1039 PLL_OUT_MASK, PLL_OUT_MASK); 1040 if (ret) 1041 return ret; 1042 1043 /* Enable the global PLL outputs */ 1044 return regmap_update_bits(regmap, PLL_MODE(pll), 1045 PLL_OUTCTRL, PLL_OUTCTRL); 1046 } 1047 1048 static void clk_trion_pll_disable(struct clk_hw *hw) 1049 { 1050 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1051 struct regmap *regmap = pll->clkr.regmap; 1052 u32 val; 1053 int ret; 1054 1055 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1056 if (ret) 1057 return; 1058 1059 /* If in FSM mode, just unvote it */ 1060 if (val & PLL_VOTE_FSM_ENA) { 1061 clk_disable_regmap(hw); 1062 return; 1063 } 1064 1065 /* Disable the global PLL output */ 1066 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1067 if (ret) 1068 return; 1069 1070 /* Disable the PLL outputs */ 1071 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1072 PLL_OUT_MASK, 0); 1073 if (ret) 1074 return; 1075 1076 /* Place the PLL mode in STANDBY */ 1077 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1078 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1079 } 1080 1081 static unsigned long 1082 clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1083 { 1084 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1085 u32 l, frac, alpha_width = pll_alpha_width(pll); 1086 1087 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 1088 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac); 1089 1090 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 1091 } 1092 1093 const struct clk_ops clk_alpha_pll_fixed_ops = { 1094 .enable = clk_alpha_pll_enable, 1095 .disable = clk_alpha_pll_disable, 1096 .is_enabled = clk_alpha_pll_is_enabled, 1097 .recalc_rate = clk_alpha_pll_recalc_rate, 1098 }; 1099 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops); 1100 1101 const struct clk_ops clk_alpha_pll_ops = { 1102 .enable = clk_alpha_pll_enable, 1103 .disable = clk_alpha_pll_disable, 1104 .is_enabled = clk_alpha_pll_is_enabled, 1105 .recalc_rate = clk_alpha_pll_recalc_rate, 1106 .round_rate = clk_alpha_pll_round_rate, 1107 .set_rate = clk_alpha_pll_set_rate, 1108 }; 1109 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops); 1110 1111 const struct clk_ops clk_alpha_pll_huayra_ops = { 1112 .enable = clk_alpha_pll_enable, 1113 .disable = clk_alpha_pll_disable, 1114 .is_enabled = clk_alpha_pll_is_enabled, 1115 .recalc_rate = alpha_pll_huayra_recalc_rate, 1116 .round_rate = alpha_pll_huayra_round_rate, 1117 .set_rate = alpha_pll_huayra_set_rate, 1118 }; 1119 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops); 1120 1121 const struct clk_ops clk_alpha_pll_hwfsm_ops = { 1122 .enable = clk_alpha_pll_hwfsm_enable, 1123 .disable = clk_alpha_pll_hwfsm_disable, 1124 .is_enabled = clk_alpha_pll_hwfsm_is_enabled, 1125 .recalc_rate = clk_alpha_pll_recalc_rate, 1126 .round_rate = clk_alpha_pll_round_rate, 1127 .set_rate = clk_alpha_pll_hwfsm_set_rate, 1128 }; 1129 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); 1130 1131 const struct clk_ops clk_alpha_pll_fixed_trion_ops = { 1132 .enable = clk_trion_pll_enable, 1133 .disable = clk_trion_pll_disable, 1134 .is_enabled = clk_trion_pll_is_enabled, 1135 .recalc_rate = clk_trion_pll_recalc_rate, 1136 .round_rate = clk_alpha_pll_round_rate, 1137 }; 1138 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops); 1139 1140 static unsigned long 1141 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1142 { 1143 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1144 u32 ctl; 1145 1146 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 1147 1148 ctl >>= PLL_POST_DIV_SHIFT; 1149 ctl &= PLL_POST_DIV_MASK(pll); 1150 1151 return parent_rate >> fls(ctl); 1152 } 1153 1154 static const struct clk_div_table clk_alpha_div_table[] = { 1155 { 0x0, 1 }, 1156 { 0x1, 2 }, 1157 { 0x3, 4 }, 1158 { 0x7, 8 }, 1159 { 0xf, 16 }, 1160 { } 1161 }; 1162 1163 static const struct clk_div_table clk_alpha_2bit_div_table[] = { 1164 { 0x0, 1 }, 1165 { 0x1, 2 }, 1166 { 0x3, 4 }, 1167 { } 1168 }; 1169 1170 static long 1171 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, 1172 unsigned long *prate) 1173 { 1174 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1175 const struct clk_div_table *table; 1176 1177 if (pll->width == 2) 1178 table = clk_alpha_2bit_div_table; 1179 else 1180 table = clk_alpha_div_table; 1181 1182 return divider_round_rate(hw, rate, prate, table, 1183 pll->width, CLK_DIVIDER_POWER_OF_TWO); 1184 } 1185 1186 static long 1187 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate, 1188 unsigned long *prate) 1189 { 1190 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1191 u32 ctl, div; 1192 1193 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 1194 1195 ctl >>= PLL_POST_DIV_SHIFT; 1196 ctl &= BIT(pll->width) - 1; 1197 div = 1 << fls(ctl); 1198 1199 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) 1200 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate); 1201 1202 return DIV_ROUND_UP_ULL((u64)*prate, div); 1203 } 1204 1205 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1206 unsigned long parent_rate) 1207 { 1208 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1209 int div; 1210 1211 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ 1212 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1; 1213 1214 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1215 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 1216 div << PLL_POST_DIV_SHIFT); 1217 } 1218 1219 const struct clk_ops clk_alpha_pll_postdiv_ops = { 1220 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1221 .round_rate = clk_alpha_pll_postdiv_round_rate, 1222 .set_rate = clk_alpha_pll_postdiv_set_rate, 1223 }; 1224 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops); 1225 1226 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = { 1227 .round_rate = clk_alpha_pll_postdiv_round_ro_rate, 1228 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1229 }; 1230 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops); 1231 1232 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1233 const struct alpha_pll_config *config) 1234 { 1235 u32 val, mask; 1236 1237 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1238 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha); 1239 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1240 config->config_ctl_val); 1241 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1242 config->config_ctl_hi_val); 1243 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1244 config->user_ctl_val); 1245 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1246 config->user_ctl_hi_val); 1247 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1248 config->test_ctl_val); 1249 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1250 config->test_ctl_hi_val); 1251 1252 if (config->post_div_mask) { 1253 mask = config->post_div_mask; 1254 val = config->post_div_val; 1255 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 1256 } 1257 1258 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE) 1259 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE, 1260 PLL_FSM_LEGACY_MODE); 1261 1262 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1263 PLL_UPDATE_BYPASS); 1264 1265 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1266 } 1267 EXPORT_SYMBOL_GPL(clk_fabia_pll_configure); 1268 1269 static int alpha_pll_fabia_enable(struct clk_hw *hw) 1270 { 1271 int ret; 1272 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1273 u32 val, opmode_val; 1274 struct regmap *regmap = pll->clkr.regmap; 1275 1276 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1277 if (ret) 1278 return ret; 1279 1280 /* If in FSM mode, just vote for it */ 1281 if (val & PLL_VOTE_FSM_ENA) { 1282 ret = clk_enable_regmap(hw); 1283 if (ret) 1284 return ret; 1285 return wait_for_pll_enable_active(pll); 1286 } 1287 1288 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 1289 if (ret) 1290 return ret; 1291 1292 /* Skip If PLL is already running */ 1293 if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL)) 1294 return 0; 1295 1296 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1297 if (ret) 1298 return ret; 1299 1300 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1301 if (ret) 1302 return ret; 1303 1304 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 1305 PLL_RESET_N); 1306 if (ret) 1307 return ret; 1308 1309 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 1310 if (ret) 1311 return ret; 1312 1313 ret = wait_for_pll_enable_lock(pll); 1314 if (ret) 1315 return ret; 1316 1317 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1318 PLL_OUT_MASK, PLL_OUT_MASK); 1319 if (ret) 1320 return ret; 1321 1322 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 1323 PLL_OUTCTRL); 1324 } 1325 1326 static void alpha_pll_fabia_disable(struct clk_hw *hw) 1327 { 1328 int ret; 1329 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1330 u32 val; 1331 struct regmap *regmap = pll->clkr.regmap; 1332 1333 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1334 if (ret) 1335 return; 1336 1337 /* If in FSM mode, just unvote it */ 1338 if (val & PLL_FSM_ENA) { 1339 clk_disable_regmap(hw); 1340 return; 1341 } 1342 1343 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1344 if (ret) 1345 return; 1346 1347 /* Disable main outputs */ 1348 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 1349 if (ret) 1350 return; 1351 1352 /* Place the PLL in STANDBY */ 1353 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1354 } 1355 1356 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw, 1357 unsigned long parent_rate) 1358 { 1359 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1360 u32 l, frac, alpha_width = pll_alpha_width(pll); 1361 1362 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 1363 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac); 1364 1365 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 1366 } 1367 1368 /* 1369 * Due to limited number of bits for fractional rate programming, the 1370 * rounded up rate could be marginally higher than the requested rate. 1371 */ 1372 static int alpha_pll_check_rate_margin(struct clk_hw *hw, 1373 unsigned long rrate, unsigned long rate) 1374 { 1375 unsigned long rate_margin = rate + PLL_RATE_MARGIN; 1376 1377 if (rrate > rate_margin || rrate < rate) { 1378 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n", 1379 clk_hw_get_name(hw), rrate, rate, rate_margin); 1380 return -EINVAL; 1381 } 1382 1383 return 0; 1384 } 1385 1386 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate, 1387 unsigned long prate) 1388 { 1389 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1390 u32 l, alpha_width = pll_alpha_width(pll); 1391 unsigned long rrate; 1392 int ret; 1393 u64 a; 1394 1395 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1396 1397 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1398 if (ret < 0) 1399 return ret; 1400 1401 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1402 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); 1403 1404 return __clk_alpha_pll_update_latch(pll); 1405 } 1406 1407 static int alpha_pll_fabia_prepare(struct clk_hw *hw) 1408 { 1409 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1410 const struct pll_vco *vco; 1411 struct clk_hw *parent_hw; 1412 unsigned long cal_freq, rrate; 1413 u32 cal_l, val, alpha_width = pll_alpha_width(pll); 1414 const char *name = clk_hw_get_name(hw); 1415 u64 a; 1416 int ret; 1417 1418 /* Check if calibration needs to be done i.e. PLL is in reset */ 1419 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1420 if (ret) 1421 return ret; 1422 1423 /* Return early if calibration is not needed. */ 1424 if (val & PLL_RESET_N) 1425 return 0; 1426 1427 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); 1428 if (!vco) { 1429 pr_err("%s: alpha pll not in a valid vco range\n", name); 1430 return -EINVAL; 1431 } 1432 1433 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq + 1434 pll->vco_table[0].max_freq) * 54, 100); 1435 1436 parent_hw = clk_hw_get_parent(hw); 1437 if (!parent_hw) 1438 return -EINVAL; 1439 1440 rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw), 1441 &cal_l, &a, alpha_width); 1442 1443 ret = alpha_pll_check_rate_margin(hw, rrate, cal_freq); 1444 if (ret < 0) 1445 return ret; 1446 1447 /* Setup PLL for calibration frequency */ 1448 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l); 1449 1450 /* Bringup the PLL at calibration frequency */ 1451 ret = clk_alpha_pll_enable(hw); 1452 if (ret) { 1453 pr_err("%s: alpha pll calibration failed\n", name); 1454 return ret; 1455 } 1456 1457 clk_alpha_pll_disable(hw); 1458 1459 return 0; 1460 } 1461 1462 const struct clk_ops clk_alpha_pll_fabia_ops = { 1463 .prepare = alpha_pll_fabia_prepare, 1464 .enable = alpha_pll_fabia_enable, 1465 .disable = alpha_pll_fabia_disable, 1466 .is_enabled = clk_alpha_pll_is_enabled, 1467 .set_rate = alpha_pll_fabia_set_rate, 1468 .recalc_rate = alpha_pll_fabia_recalc_rate, 1469 .round_rate = clk_alpha_pll_round_rate, 1470 }; 1471 EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops); 1472 1473 const struct clk_ops clk_alpha_pll_fixed_fabia_ops = { 1474 .enable = alpha_pll_fabia_enable, 1475 .disable = alpha_pll_fabia_disable, 1476 .is_enabled = clk_alpha_pll_is_enabled, 1477 .recalc_rate = alpha_pll_fabia_recalc_rate, 1478 .round_rate = clk_alpha_pll_round_rate, 1479 }; 1480 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops); 1481 1482 static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw, 1483 unsigned long parent_rate) 1484 { 1485 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1486 u32 i, div = 1, val; 1487 int ret; 1488 1489 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1490 if (ret) 1491 return ret; 1492 1493 val >>= pll->post_div_shift; 1494 val &= BIT(pll->width) - 1; 1495 1496 for (i = 0; i < pll->num_post_div; i++) { 1497 if (pll->post_div_table[i].val == val) { 1498 div = pll->post_div_table[i].div; 1499 break; 1500 } 1501 } 1502 1503 return (parent_rate / div); 1504 } 1505 1506 static unsigned long 1507 clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1508 { 1509 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1510 struct regmap *regmap = pll->clkr.regmap; 1511 u32 i, div = 1, val; 1512 1513 regmap_read(regmap, PLL_USER_CTL(pll), &val); 1514 1515 val >>= pll->post_div_shift; 1516 val &= PLL_POST_DIV_MASK(pll); 1517 1518 for (i = 0; i < pll->num_post_div; i++) { 1519 if (pll->post_div_table[i].val == val) { 1520 div = pll->post_div_table[i].div; 1521 break; 1522 } 1523 } 1524 1525 return (parent_rate / div); 1526 } 1527 1528 static long 1529 clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, 1530 unsigned long *prate) 1531 { 1532 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1533 1534 return divider_round_rate(hw, rate, prate, pll->post_div_table, 1535 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1536 }; 1537 1538 static int 1539 clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1540 unsigned long parent_rate) 1541 { 1542 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1543 struct regmap *regmap = pll->clkr.regmap; 1544 int i, val = 0, div; 1545 1546 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1547 for (i = 0; i < pll->num_post_div; i++) { 1548 if (pll->post_div_table[i].div == div) { 1549 val = pll->post_div_table[i].val; 1550 break; 1551 } 1552 } 1553 1554 return regmap_update_bits(regmap, PLL_USER_CTL(pll), 1555 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 1556 val << PLL_POST_DIV_SHIFT); 1557 } 1558 1559 const struct clk_ops clk_alpha_pll_postdiv_trion_ops = { 1560 .recalc_rate = clk_trion_pll_postdiv_recalc_rate, 1561 .round_rate = clk_trion_pll_postdiv_round_rate, 1562 .set_rate = clk_trion_pll_postdiv_set_rate, 1563 }; 1564 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops); 1565 1566 static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw, 1567 unsigned long rate, unsigned long *prate) 1568 { 1569 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1570 1571 return divider_round_rate(hw, rate, prate, pll->post_div_table, 1572 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1573 } 1574 1575 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw, 1576 unsigned long rate, unsigned long parent_rate) 1577 { 1578 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1579 int i, val = 0, div, ret; 1580 1581 /* 1582 * If the PLL is in FSM mode, then treat set_rate callback as a 1583 * no-operation. 1584 */ 1585 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1586 if (ret) 1587 return ret; 1588 1589 if (val & PLL_VOTE_FSM_ENA) 1590 return 0; 1591 1592 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1593 for (i = 0; i < pll->num_post_div; i++) { 1594 if (pll->post_div_table[i].div == div) { 1595 val = pll->post_div_table[i].val; 1596 break; 1597 } 1598 } 1599 1600 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1601 (BIT(pll->width) - 1) << pll->post_div_shift, 1602 val << pll->post_div_shift); 1603 } 1604 1605 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = { 1606 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1607 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1608 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1609 }; 1610 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops); 1611 1612 /** 1613 * clk_trion_pll_configure - configure the trion pll 1614 * 1615 * @pll: clk alpha pll 1616 * @regmap: register map 1617 * @config: configuration to apply for pll 1618 */ 1619 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1620 const struct alpha_pll_config *config) 1621 { 1622 /* 1623 * If the bootloader left the PLL enabled it's likely that there are 1624 * RCGs that will lock up if we disable the PLL below. 1625 */ 1626 if (trion_pll_is_enabled(pll, regmap)) { 1627 pr_debug("Trion PLL is already enabled, skipping configuration\n"); 1628 return; 1629 } 1630 1631 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1632 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); 1633 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1634 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1635 config->config_ctl_val); 1636 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1637 config->config_ctl_hi_val); 1638 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), 1639 config->config_ctl_hi1_val); 1640 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1641 config->user_ctl_val); 1642 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1643 config->user_ctl_hi_val); 1644 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), 1645 config->user_ctl_hi1_val); 1646 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1647 config->test_ctl_val); 1648 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1649 config->test_ctl_hi_val); 1650 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), 1651 config->test_ctl_hi1_val); 1652 1653 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1654 PLL_UPDATE_BYPASS); 1655 1656 /* Disable PLL output */ 1657 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1658 1659 /* Set operation mode to OFF */ 1660 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1661 1662 /* Place the PLL in STANDBY mode */ 1663 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1664 } 1665 EXPORT_SYMBOL_GPL(clk_trion_pll_configure); 1666 1667 /* 1668 * The TRION PLL requires a power-on self-calibration which happens when the 1669 * PLL comes out of reset. Calibrate in case it is not completed. 1670 */ 1671 static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done) 1672 { 1673 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1674 u32 val; 1675 int ret; 1676 1677 /* Return early if calibration is not needed. */ 1678 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); 1679 if (val & pcal_done) 1680 return 0; 1681 1682 /* On/off to calibrate */ 1683 ret = clk_trion_pll_enable(hw); 1684 if (!ret) 1685 clk_trion_pll_disable(hw); 1686 1687 return ret; 1688 } 1689 1690 static int alpha_pll_trion_prepare(struct clk_hw *hw) 1691 { 1692 return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE); 1693 } 1694 1695 static int alpha_pll_lucid_prepare(struct clk_hw *hw) 1696 { 1697 return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE); 1698 } 1699 1700 static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1701 unsigned long prate, u32 latch_bit, u32 latch_ack) 1702 { 1703 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1704 unsigned long rrate; 1705 u32 val, l, alpha_width = pll_alpha_width(pll); 1706 u64 a; 1707 int ret; 1708 1709 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1710 1711 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1712 if (ret < 0) 1713 return ret; 1714 1715 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1716 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1717 1718 /* Latch the PLL input */ 1719 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); 1720 if (ret) 1721 return ret; 1722 1723 /* Wait for 2 reference cycles before checking the ACK bit. */ 1724 udelay(1); 1725 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1726 if (!(val & latch_ack)) { 1727 pr_err("Lucid PLL latch failed. Output may be unstable!\n"); 1728 return -EINVAL; 1729 } 1730 1731 /* Return the latch input to 0 */ 1732 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); 1733 if (ret) 1734 return ret; 1735 1736 if (clk_hw_is_enabled(hw)) { 1737 ret = wait_for_pll_enable_lock(pll); 1738 if (ret) 1739 return ret; 1740 } 1741 1742 /* Wait for PLL output to stabilize */ 1743 udelay(100); 1744 return 0; 1745 } 1746 1747 static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1748 unsigned long prate) 1749 { 1750 return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH); 1751 } 1752 1753 const struct clk_ops clk_alpha_pll_trion_ops = { 1754 .prepare = alpha_pll_trion_prepare, 1755 .enable = clk_trion_pll_enable, 1756 .disable = clk_trion_pll_disable, 1757 .is_enabled = clk_trion_pll_is_enabled, 1758 .recalc_rate = clk_trion_pll_recalc_rate, 1759 .round_rate = clk_alpha_pll_round_rate, 1760 .set_rate = alpha_pll_trion_set_rate, 1761 }; 1762 EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops); 1763 1764 const struct clk_ops clk_alpha_pll_lucid_ops = { 1765 .prepare = alpha_pll_lucid_prepare, 1766 .enable = clk_trion_pll_enable, 1767 .disable = clk_trion_pll_disable, 1768 .is_enabled = clk_trion_pll_is_enabled, 1769 .recalc_rate = clk_trion_pll_recalc_rate, 1770 .round_rate = clk_alpha_pll_round_rate, 1771 .set_rate = alpha_pll_trion_set_rate, 1772 }; 1773 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops); 1774 1775 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { 1776 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1777 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1778 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1779 }; 1780 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops); 1781 1782 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1783 const struct alpha_pll_config *config) 1784 { 1785 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1786 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1787 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1788 config->user_ctl_val); 1789 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1790 config->config_ctl_val); 1791 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1792 config->config_ctl_hi_val); 1793 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1794 config->test_ctl_val); 1795 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1796 config->test_ctl_hi_val); 1797 } 1798 EXPORT_SYMBOL_GPL(clk_agera_pll_configure); 1799 1800 static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate, 1801 unsigned long prate) 1802 { 1803 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1804 u32 l, alpha_width = pll_alpha_width(pll); 1805 int ret; 1806 unsigned long rrate; 1807 u64 a; 1808 1809 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1810 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1811 if (ret < 0) 1812 return ret; 1813 1814 /* change L_VAL without having to go through the power on sequence */ 1815 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1816 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1817 1818 if (clk_hw_is_enabled(hw)) 1819 return wait_for_pll_enable_lock(pll); 1820 1821 return 0; 1822 } 1823 1824 const struct clk_ops clk_alpha_pll_agera_ops = { 1825 .enable = clk_alpha_pll_enable, 1826 .disable = clk_alpha_pll_disable, 1827 .is_enabled = clk_alpha_pll_is_enabled, 1828 .recalc_rate = alpha_pll_fabia_recalc_rate, 1829 .round_rate = clk_alpha_pll_round_rate, 1830 .set_rate = clk_alpha_pll_agera_set_rate, 1831 }; 1832 EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops); 1833 1834 static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw) 1835 { 1836 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1837 u32 val; 1838 int ret; 1839 1840 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1841 if (ret) 1842 return ret; 1843 1844 /* If in FSM mode, just vote for it */ 1845 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 1846 ret = clk_enable_regmap(hw); 1847 if (ret) 1848 return ret; 1849 return wait_for_pll_enable_lock(pll); 1850 } 1851 1852 /* Check if PLL is already enabled, return if enabled */ 1853 ret = trion_pll_is_enabled(pll, pll->clkr.regmap); 1854 if (ret < 0) 1855 return ret; 1856 1857 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1858 if (ret) 1859 return ret; 1860 1861 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); 1862 1863 ret = wait_for_pll_enable_lock(pll); 1864 if (ret) 1865 return ret; 1866 1867 /* Enable the PLL outputs */ 1868 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 1869 if (ret) 1870 return ret; 1871 1872 /* Enable the global PLL outputs */ 1873 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 1874 } 1875 1876 static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw) 1877 { 1878 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1879 u32 val; 1880 int ret; 1881 1882 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1883 if (ret) 1884 return; 1885 1886 /* If in FSM mode, just unvote it */ 1887 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 1888 clk_disable_regmap(hw); 1889 return; 1890 } 1891 1892 /* Disable the global PLL output */ 1893 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1894 if (ret) 1895 return; 1896 1897 /* Disable the PLL outputs */ 1898 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 1899 if (ret) 1900 return; 1901 1902 /* Place the PLL mode in STANDBY */ 1903 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY); 1904 } 1905 1906 /* 1907 * The Lucid 5LPE PLL requires a power-on self-calibration which happens 1908 * when the PLL comes out of reset. Calibrate in case it is not completed. 1909 */ 1910 static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw) 1911 { 1912 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1913 struct clk_hw *p; 1914 u32 val = 0; 1915 int ret; 1916 1917 /* Return early if calibration is not needed. */ 1918 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1919 if (val & LUCID_5LPE_PCAL_DONE) 1920 return 0; 1921 1922 p = clk_hw_get_parent(hw); 1923 if (!p) 1924 return -EINVAL; 1925 1926 ret = alpha_pll_lucid_5lpe_enable(hw); 1927 if (ret) 1928 return ret; 1929 1930 alpha_pll_lucid_5lpe_disable(hw); 1931 1932 return 0; 1933 } 1934 1935 static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate, 1936 unsigned long prate) 1937 { 1938 return __alpha_pll_trion_set_rate(hw, rate, prate, 1939 LUCID_5LPE_PLL_LATCH_INPUT, 1940 LUCID_5LPE_ALPHA_PLL_ACK_LATCH); 1941 } 1942 1943 static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1944 unsigned long parent_rate, 1945 unsigned long enable_vote_run) 1946 { 1947 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1948 struct regmap *regmap = pll->clkr.regmap; 1949 int i, val, div, ret; 1950 u32 mask; 1951 1952 /* 1953 * If the PLL is in FSM mode, then treat set_rate callback as a 1954 * no-operation. 1955 */ 1956 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 1957 if (ret) 1958 return ret; 1959 1960 if (val & enable_vote_run) 1961 return 0; 1962 1963 if (!pll->post_div_table) { 1964 pr_err("Missing the post_div_table for the %s PLL\n", 1965 clk_hw_get_name(&pll->clkr.hw)); 1966 return -EINVAL; 1967 } 1968 1969 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); 1970 for (i = 0; i < pll->num_post_div; i++) { 1971 if (pll->post_div_table[i].div == div) { 1972 val = pll->post_div_table[i].val; 1973 break; 1974 } 1975 } 1976 1977 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); 1978 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1979 mask, val << pll->post_div_shift); 1980 } 1981 1982 static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1983 unsigned long parent_rate) 1984 { 1985 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN); 1986 } 1987 1988 const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = { 1989 .prepare = alpha_pll_lucid_5lpe_prepare, 1990 .enable = alpha_pll_lucid_5lpe_enable, 1991 .disable = alpha_pll_lucid_5lpe_disable, 1992 .is_enabled = clk_trion_pll_is_enabled, 1993 .recalc_rate = clk_trion_pll_recalc_rate, 1994 .round_rate = clk_alpha_pll_round_rate, 1995 .set_rate = alpha_pll_lucid_5lpe_set_rate, 1996 }; 1997 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops); 1998 1999 const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = { 2000 .enable = alpha_pll_lucid_5lpe_enable, 2001 .disable = alpha_pll_lucid_5lpe_disable, 2002 .is_enabled = clk_trion_pll_is_enabled, 2003 .recalc_rate = clk_trion_pll_recalc_rate, 2004 .round_rate = clk_alpha_pll_round_rate, 2005 }; 2006 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops); 2007 2008 const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = { 2009 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 2010 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 2011 .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate, 2012 }; 2013 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops); 2014 2015 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2016 const struct alpha_pll_config *config) 2017 { 2018 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2019 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2020 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2021 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2022 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2023 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2024 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2025 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); 2026 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2027 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2028 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2029 2030 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0); 2031 2032 /* Disable PLL output */ 2033 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2034 2035 /* Set operation mode to OFF */ 2036 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2037 2038 /* Place the PLL in STANDBY mode */ 2039 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2040 } 2041 EXPORT_SYMBOL_GPL(clk_zonda_pll_configure); 2042 2043 static int clk_zonda_pll_enable(struct clk_hw *hw) 2044 { 2045 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2046 struct regmap *regmap = pll->clkr.regmap; 2047 u32 val; 2048 int ret; 2049 2050 regmap_read(regmap, PLL_MODE(pll), &val); 2051 2052 /* If in FSM mode, just vote for it */ 2053 if (val & PLL_VOTE_FSM_ENA) { 2054 ret = clk_enable_regmap(hw); 2055 if (ret) 2056 return ret; 2057 return wait_for_pll_enable_active(pll); 2058 } 2059 2060 /* Get the PLL out of bypass mode */ 2061 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); 2062 2063 /* 2064 * H/W requires a 1us delay between disabling the bypass and 2065 * de-asserting the reset. 2066 */ 2067 udelay(1); 2068 2069 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2070 2071 /* Set operation mode to RUN */ 2072 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2073 2074 regmap_read(regmap, PLL_TEST_CTL(pll), &val); 2075 2076 /* If cfa mode then poll for freq lock */ 2077 if (val & ZONDA_STAY_IN_CFA) 2078 ret = wait_for_zonda_pll_freq_lock(pll); 2079 else 2080 ret = wait_for_pll_enable_lock(pll); 2081 if (ret) 2082 return ret; 2083 2084 /* Enable the PLL outputs */ 2085 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK); 2086 2087 /* Enable the global PLL outputs */ 2088 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2089 2090 return 0; 2091 } 2092 2093 static void clk_zonda_pll_disable(struct clk_hw *hw) 2094 { 2095 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2096 struct regmap *regmap = pll->clkr.regmap; 2097 u32 val; 2098 2099 regmap_read(regmap, PLL_MODE(pll), &val); 2100 2101 /* If in FSM mode, just unvote it */ 2102 if (val & PLL_VOTE_FSM_ENA) { 2103 clk_disable_regmap(hw); 2104 return; 2105 } 2106 2107 /* Disable the global PLL output */ 2108 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2109 2110 /* Disable the PLL outputs */ 2111 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0); 2112 2113 /* Put the PLL in bypass and reset */ 2114 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0); 2115 2116 /* Place the PLL mode in OFF state */ 2117 regmap_write(regmap, PLL_OPMODE(pll), 0x0); 2118 } 2119 2120 static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, 2121 unsigned long prate) 2122 { 2123 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2124 unsigned long rrate; 2125 u32 test_ctl_val; 2126 u32 l, alpha_width = pll_alpha_width(pll); 2127 u64 a; 2128 int ret; 2129 2130 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 2131 2132 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 2133 if (ret < 0) 2134 return ret; 2135 2136 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2137 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2138 2139 /* Wait before polling for the frequency latch */ 2140 udelay(5); 2141 2142 /* Read stay in cfa mode */ 2143 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val); 2144 2145 /* If cfa mode then poll for freq lock */ 2146 if (test_ctl_val & ZONDA_STAY_IN_CFA) 2147 ret = wait_for_zonda_pll_freq_lock(pll); 2148 else 2149 ret = wait_for_pll_enable_lock(pll); 2150 if (ret) 2151 return ret; 2152 2153 /* Wait for PLL output to stabilize */ 2154 udelay(100); 2155 return 0; 2156 } 2157 2158 const struct clk_ops clk_alpha_pll_zonda_ops = { 2159 .enable = clk_zonda_pll_enable, 2160 .disable = clk_zonda_pll_disable, 2161 .is_enabled = clk_trion_pll_is_enabled, 2162 .recalc_rate = clk_trion_pll_recalc_rate, 2163 .round_rate = clk_alpha_pll_round_rate, 2164 .set_rate = clk_zonda_pll_set_rate, 2165 }; 2166 EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops); 2167 2168 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2169 const struct alpha_pll_config *config) 2170 { 2171 u32 lval = config->l; 2172 2173 /* 2174 * If the bootloader left the PLL enabled it's likely that there are 2175 * RCGs that will lock up if we disable the PLL below. 2176 */ 2177 if (trion_pll_is_enabled(pll, regmap)) { 2178 pr_debug("Lucid Evo PLL is already enabled, skipping configuration\n"); 2179 return; 2180 } 2181 2182 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT; 2183 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); 2184 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2185 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2186 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2187 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2188 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2189 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2190 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2191 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2192 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2193 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); 2194 2195 /* Disable PLL output */ 2196 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2197 2198 /* Set operation mode to STANDBY and de-assert the reset */ 2199 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2200 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2201 } 2202 EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure); 2203 2204 void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2205 const struct alpha_pll_config *config) 2206 { 2207 u32 lval = config->l; 2208 2209 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT; 2210 lval |= TRION_PLL_CAL_VAL << LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT; 2211 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); 2212 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2213 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2214 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2215 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2216 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2217 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2218 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2219 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2220 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2221 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); 2222 2223 /* Disable PLL output */ 2224 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2225 2226 /* Set operation mode to STANDBY and de-assert the reset */ 2227 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2228 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2229 } 2230 EXPORT_SYMBOL_GPL(clk_lucid_ole_pll_configure); 2231 2232 static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) 2233 { 2234 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2235 struct regmap *regmap = pll->clkr.regmap; 2236 u32 val; 2237 int ret; 2238 2239 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2240 if (ret) 2241 return ret; 2242 2243 /* If in FSM mode, just vote for it */ 2244 if (val & LUCID_EVO_ENABLE_VOTE_RUN) { 2245 ret = clk_enable_regmap(hw); 2246 if (ret) 2247 return ret; 2248 return wait_for_pll_enable_lock(pll); 2249 } 2250 2251 /* Check if PLL is already enabled */ 2252 ret = trion_pll_is_enabled(pll, regmap); 2253 if (ret < 0) { 2254 return ret; 2255 } else if (ret) { 2256 pr_warn("%s PLL is already enabled\n", clk_hw_get_name(&pll->clkr.hw)); 2257 return 0; 2258 } 2259 2260 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2261 if (ret) 2262 return ret; 2263 2264 /* Set operation mode to RUN */ 2265 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2266 2267 ret = wait_for_pll_enable_lock(pll); 2268 if (ret) 2269 return ret; 2270 2271 /* Enable the PLL outputs */ 2272 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 2273 if (ret) 2274 return ret; 2275 2276 /* Enable the global PLL outputs */ 2277 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2278 if (ret) 2279 return ret; 2280 2281 /* Ensure that the write above goes through before returning. */ 2282 mb(); 2283 return ret; 2284 } 2285 2286 static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset) 2287 { 2288 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2289 struct regmap *regmap = pll->clkr.regmap; 2290 u32 val; 2291 int ret; 2292 2293 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2294 if (ret) 2295 return; 2296 2297 /* If in FSM mode, just unvote it */ 2298 if (val & LUCID_EVO_ENABLE_VOTE_RUN) { 2299 clk_disable_regmap(hw); 2300 return; 2301 } 2302 2303 /* Disable the global PLL output */ 2304 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2305 if (ret) 2306 return; 2307 2308 /* Disable the PLL outputs */ 2309 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 2310 if (ret) 2311 return; 2312 2313 /* Place the PLL mode in STANDBY */ 2314 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2315 2316 if (reset) 2317 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0); 2318 } 2319 2320 static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset) 2321 { 2322 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2323 struct clk_hw *p; 2324 u32 val = 0; 2325 int ret; 2326 2327 /* Return early if calibration is not needed. */ 2328 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 2329 if (!(val & LUCID_EVO_PCAL_NOT_DONE)) 2330 return 0; 2331 2332 p = clk_hw_get_parent(hw); 2333 if (!p) 2334 return -EINVAL; 2335 2336 ret = alpha_pll_lucid_evo_enable(hw); 2337 if (ret) 2338 return ret; 2339 2340 _alpha_pll_lucid_evo_disable(hw, reset); 2341 2342 return 0; 2343 } 2344 2345 static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) 2346 { 2347 _alpha_pll_lucid_evo_disable(hw, false); 2348 } 2349 2350 static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw) 2351 { 2352 return _alpha_pll_lucid_evo_prepare(hw, false); 2353 } 2354 2355 static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw) 2356 { 2357 _alpha_pll_lucid_evo_disable(hw, true); 2358 } 2359 2360 static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw) 2361 { 2362 return _alpha_pll_lucid_evo_prepare(hw, true); 2363 } 2364 2365 static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, 2366 unsigned long parent_rate) 2367 { 2368 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2369 struct regmap *regmap = pll->clkr.regmap; 2370 u32 l, frac; 2371 2372 regmap_read(regmap, PLL_L_VAL(pll), &l); 2373 l &= LUCID_EVO_PLL_L_VAL_MASK; 2374 regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac); 2375 2376 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); 2377 } 2378 2379 static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 2380 unsigned long parent_rate) 2381 { 2382 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN); 2383 } 2384 2385 const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = { 2386 .enable = alpha_pll_lucid_evo_enable, 2387 .disable = alpha_pll_lucid_evo_disable, 2388 .is_enabled = clk_trion_pll_is_enabled, 2389 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2390 .round_rate = clk_alpha_pll_round_rate, 2391 }; 2392 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops); 2393 2394 const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = { 2395 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 2396 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 2397 .set_rate = clk_lucid_evo_pll_postdiv_set_rate, 2398 }; 2399 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops); 2400 2401 const struct clk_ops clk_alpha_pll_lucid_evo_ops = { 2402 .prepare = alpha_pll_lucid_evo_prepare, 2403 .enable = alpha_pll_lucid_evo_enable, 2404 .disable = alpha_pll_lucid_evo_disable, 2405 .is_enabled = clk_trion_pll_is_enabled, 2406 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2407 .round_rate = clk_alpha_pll_round_rate, 2408 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2409 }; 2410 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops); 2411 2412 const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = { 2413 .prepare = alpha_pll_reset_lucid_evo_prepare, 2414 .enable = alpha_pll_lucid_evo_enable, 2415 .disable = alpha_pll_reset_lucid_evo_disable, 2416 .is_enabled = clk_trion_pll_is_enabled, 2417 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2418 .round_rate = clk_alpha_pll_round_rate, 2419 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2420 }; 2421 EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops); 2422 2423 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2424 const struct alpha_pll_config *config) 2425 { 2426 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2427 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2428 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2429 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2430 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2431 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2432 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2433 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2434 2435 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2436 2437 regmap_update_bits(regmap, PLL_MODE(pll), 2438 PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL, 2439 PLL_RESET_N | PLL_BYPASSNL); 2440 } 2441 EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure); 2442 2443 static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw, 2444 unsigned long parent_rate) 2445 { 2446 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2447 u32 l; 2448 2449 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 2450 2451 return parent_rate * l; 2452 } 2453 2454 static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate, 2455 unsigned long *prate) 2456 { 2457 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2458 unsigned long min_freq, max_freq; 2459 u32 l; 2460 u64 a; 2461 2462 rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0); 2463 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) 2464 return rate; 2465 2466 min_freq = pll->vco_table[0].min_freq; 2467 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 2468 2469 return clamp(rate, min_freq, max_freq); 2470 } 2471 2472 const struct clk_ops clk_alpha_pll_rivian_evo_ops = { 2473 .enable = alpha_pll_lucid_5lpe_enable, 2474 .disable = alpha_pll_lucid_5lpe_disable, 2475 .is_enabled = clk_trion_pll_is_enabled, 2476 .recalc_rate = clk_rivian_evo_pll_recalc_rate, 2477 .round_rate = clk_rivian_evo_pll_round_rate, 2478 }; 2479 EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops); 2480 2481 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2482 const struct alpha_pll_config *config) 2483 { 2484 u32 val, val_u, mask, mask_u; 2485 2486 regmap_write(regmap, PLL_L_VAL(pll), config->l); 2487 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2488 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2489 2490 if (pll_has_64bit_config(pll)) 2491 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), 2492 config->config_ctl_hi_val); 2493 2494 if (pll_alpha_width(pll) > 32) 2495 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); 2496 2497 val = config->main_output_mask; 2498 val |= config->aux_output_mask; 2499 val |= config->aux2_output_mask; 2500 val |= config->early_output_mask; 2501 val |= config->pre_div_val; 2502 val |= config->post_div_val; 2503 val |= config->vco_val; 2504 val |= config->alpha_en_mask; 2505 val |= config->alpha_mode_mask; 2506 2507 mask = config->main_output_mask; 2508 mask |= config->aux_output_mask; 2509 mask |= config->aux2_output_mask; 2510 mask |= config->early_output_mask; 2511 mask |= config->pre_div_mask; 2512 mask |= config->post_div_mask; 2513 mask |= config->vco_mask; 2514 mask |= config->alpha_en_mask; 2515 mask |= config->alpha_mode_mask; 2516 2517 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 2518 2519 /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */ 2520 val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT; 2521 val_u |= config->lock_det; 2522 2523 mask_u = config->status_mask; 2524 mask_u |= config->lock_det; 2525 2526 regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u); 2527 regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2528 regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2529 2530 if (pll->flags & SUPPORTS_FSM_MODE) 2531 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); 2532 } 2533 EXPORT_SYMBOL_GPL(clk_stromer_pll_configure); 2534 2535 static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw, 2536 struct clk_rate_request *req) 2537 { 2538 u32 l; 2539 u64 a; 2540 2541 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, 2542 &l, &a, ALPHA_REG_BITWIDTH); 2543 2544 return 0; 2545 } 2546 2547 static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate, 2548 unsigned long prate) 2549 { 2550 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2551 int ret; 2552 u32 l; 2553 u64 a; 2554 2555 rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH); 2556 2557 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2558 2559 a <<= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH; 2560 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2561 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 2562 a >> ALPHA_BITWIDTH); 2563 2564 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 2565 PLL_ALPHA_EN, PLL_ALPHA_EN); 2566 2567 if (!clk_hw_is_enabled(hw)) 2568 return 0; 2569 2570 /* 2571 * Stromer PLL supports Dynamic programming. 2572 * It allows the PLL frequency to be changed on-the-fly without first 2573 * execution of a shutdown procedure followed by a bring up procedure. 2574 */ 2575 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 2576 PLL_UPDATE); 2577 2578 ret = wait_for_pll_update(pll); 2579 if (ret) 2580 return ret; 2581 2582 return wait_for_pll_enable_lock(pll); 2583 } 2584 2585 const struct clk_ops clk_alpha_pll_stromer_ops = { 2586 .enable = clk_alpha_pll_enable, 2587 .disable = clk_alpha_pll_disable, 2588 .is_enabled = clk_alpha_pll_is_enabled, 2589 .recalc_rate = clk_alpha_pll_recalc_rate, 2590 .determine_rate = clk_alpha_pll_stromer_determine_rate, 2591 .set_rate = clk_alpha_pll_stromer_set_rate, 2592 }; 2593 EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops); 2594 2595 static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw, 2596 unsigned long rate, 2597 unsigned long prate) 2598 { 2599 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2600 u32 l, alpha_width = pll_alpha_width(pll); 2601 int ret, pll_mode; 2602 u64 a; 2603 2604 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 2605 2606 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode); 2607 if (ret) 2608 return ret; 2609 2610 regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0); 2611 2612 /* Delay of 2 output clock ticks required until output is disabled */ 2613 udelay(1); 2614 2615 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2616 2617 if (alpha_width > ALPHA_BITWIDTH) 2618 a <<= alpha_width - ALPHA_BITWIDTH; 2619 2620 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2621 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 2622 a >> ALPHA_BITWIDTH); 2623 2624 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 2625 PLL_ALPHA_EN, PLL_ALPHA_EN); 2626 2627 regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL); 2628 2629 /* Wait five micro seconds or more */ 2630 udelay(5); 2631 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, 2632 PLL_RESET_N); 2633 2634 /* The lock time should be less than 50 micro seconds worst case */ 2635 usleep_range(50, 60); 2636 2637 ret = wait_for_pll_enable_lock(pll); 2638 if (ret) { 2639 pr_err("Wait for PLL enable lock failed [%s] %d\n", 2640 clk_hw_get_name(hw), ret); 2641 return ret; 2642 } 2643 2644 if (pll_mode & PLL_OUTCTRL) 2645 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 2646 PLL_OUTCTRL); 2647 2648 return 0; 2649 } 2650 2651 const struct clk_ops clk_alpha_pll_stromer_plus_ops = { 2652 .prepare = clk_alpha_pll_enable, 2653 .unprepare = clk_alpha_pll_disable, 2654 .is_enabled = clk_alpha_pll_is_enabled, 2655 .recalc_rate = clk_alpha_pll_recalc_rate, 2656 .determine_rate = clk_alpha_pll_stromer_determine_rate, 2657 .set_rate = clk_alpha_pll_stromer_plus_set_rate, 2658 }; 2659 EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops); 2660