1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, 2023, Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/export.h> 9 #include <linux/clk-provider.h> 10 #include <linux/regmap.h> 11 #include <linux/delay.h> 12 13 #include "clk-alpha-pll.h" 14 #include "common.h" 15 16 #define PLL_MODE(p) ((p)->offset + 0x0) 17 # define PLL_OUTCTRL BIT(0) 18 # define PLL_BYPASSNL BIT(1) 19 # define PLL_RESET_N BIT(2) 20 # define PLL_OFFLINE_REQ BIT(7) 21 # define PLL_LOCK_COUNT_SHIFT 8 22 # define PLL_LOCK_COUNT_MASK 0x3f 23 # define PLL_BIAS_COUNT_SHIFT 14 24 # define PLL_BIAS_COUNT_MASK 0x3f 25 # define PLL_VOTE_FSM_ENA BIT(20) 26 # define PLL_FSM_ENA BIT(20) 27 # define PLL_VOTE_FSM_RESET BIT(21) 28 # define PLL_UPDATE BIT(22) 29 # define PLL_UPDATE_BYPASS BIT(23) 30 # define PLL_FSM_LEGACY_MODE BIT(24) 31 # define PLL_OFFLINE_ACK BIT(28) 32 # define ALPHA_PLL_ACK_LATCH BIT(29) 33 # define PLL_ACTIVE_FLAG BIT(30) 34 # define PLL_LOCK_DET BIT(31) 35 36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL]) 37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL]) 38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL]) 39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U]) 40 41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) 42 # define PLL_POST_DIV_SHIFT 8 43 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0) 44 # define PLL_ALPHA_EN BIT(24) 45 # define PLL_ALPHA_MODE BIT(25) 46 # define PLL_VCO_SHIFT 20 47 # define PLL_VCO_MASK 0x3 48 49 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U]) 50 #define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1]) 51 52 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL]) 53 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U]) 54 #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1]) 55 #define PLL_CONFIG_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U2]) 56 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) 57 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) 58 #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1]) 59 #define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2]) 60 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) 61 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE]) 62 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC]) 63 64 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 65 [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 66 [PLL_OFF_L_VAL] = 0x04, 67 [PLL_OFF_ALPHA_VAL] = 0x08, 68 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 69 [PLL_OFF_USER_CTL] = 0x10, 70 [PLL_OFF_USER_CTL_U] = 0x14, 71 [PLL_OFF_CONFIG_CTL] = 0x18, 72 [PLL_OFF_TEST_CTL] = 0x1c, 73 [PLL_OFF_TEST_CTL_U] = 0x20, 74 [PLL_OFF_STATUS] = 0x24, 75 }, 76 [CLK_ALPHA_PLL_TYPE_HUAYRA] = { 77 [PLL_OFF_L_VAL] = 0x04, 78 [PLL_OFF_ALPHA_VAL] = 0x08, 79 [PLL_OFF_USER_CTL] = 0x10, 80 [PLL_OFF_CONFIG_CTL] = 0x14, 81 [PLL_OFF_CONFIG_CTL_U] = 0x18, 82 [PLL_OFF_TEST_CTL] = 0x1c, 83 [PLL_OFF_TEST_CTL_U] = 0x20, 84 [PLL_OFF_STATUS] = 0x24, 85 }, 86 [CLK_ALPHA_PLL_TYPE_HUAYRA_APSS] = { 87 [PLL_OFF_L_VAL] = 0x08, 88 [PLL_OFF_ALPHA_VAL] = 0x10, 89 [PLL_OFF_USER_CTL] = 0x18, 90 [PLL_OFF_CONFIG_CTL] = 0x20, 91 [PLL_OFF_CONFIG_CTL_U] = 0x24, 92 [PLL_OFF_STATUS] = 0x28, 93 [PLL_OFF_TEST_CTL] = 0x30, 94 [PLL_OFF_TEST_CTL_U] = 0x34, 95 }, 96 [CLK_ALPHA_PLL_TYPE_BRAMMO] = { 97 [PLL_OFF_L_VAL] = 0x04, 98 [PLL_OFF_ALPHA_VAL] = 0x08, 99 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 100 [PLL_OFF_USER_CTL] = 0x10, 101 [PLL_OFF_CONFIG_CTL] = 0x18, 102 [PLL_OFF_TEST_CTL] = 0x1c, 103 [PLL_OFF_STATUS] = 0x24, 104 }, 105 [CLK_ALPHA_PLL_TYPE_FABIA] = { 106 [PLL_OFF_L_VAL] = 0x04, 107 [PLL_OFF_USER_CTL] = 0x0c, 108 [PLL_OFF_USER_CTL_U] = 0x10, 109 [PLL_OFF_CONFIG_CTL] = 0x14, 110 [PLL_OFF_CONFIG_CTL_U] = 0x18, 111 [PLL_OFF_TEST_CTL] = 0x1c, 112 [PLL_OFF_TEST_CTL_U] = 0x20, 113 [PLL_OFF_STATUS] = 0x24, 114 [PLL_OFF_OPMODE] = 0x2c, 115 [PLL_OFF_FRAC] = 0x38, 116 }, 117 [CLK_ALPHA_PLL_TYPE_TRION] = { 118 [PLL_OFF_L_VAL] = 0x04, 119 [PLL_OFF_CAL_L_VAL] = 0x08, 120 [PLL_OFF_USER_CTL] = 0x0c, 121 [PLL_OFF_USER_CTL_U] = 0x10, 122 [PLL_OFF_USER_CTL_U1] = 0x14, 123 [PLL_OFF_CONFIG_CTL] = 0x18, 124 [PLL_OFF_CONFIG_CTL_U] = 0x1c, 125 [PLL_OFF_CONFIG_CTL_U1] = 0x20, 126 [PLL_OFF_TEST_CTL] = 0x24, 127 [PLL_OFF_TEST_CTL_U] = 0x28, 128 [PLL_OFF_TEST_CTL_U1] = 0x2c, 129 [PLL_OFF_STATUS] = 0x30, 130 [PLL_OFF_OPMODE] = 0x38, 131 [PLL_OFF_ALPHA_VAL] = 0x40, 132 }, 133 [CLK_ALPHA_PLL_TYPE_AGERA] = { 134 [PLL_OFF_L_VAL] = 0x04, 135 [PLL_OFF_ALPHA_VAL] = 0x08, 136 [PLL_OFF_USER_CTL] = 0x0c, 137 [PLL_OFF_CONFIG_CTL] = 0x10, 138 [PLL_OFF_CONFIG_CTL_U] = 0x14, 139 [PLL_OFF_TEST_CTL] = 0x18, 140 [PLL_OFF_TEST_CTL_U] = 0x1c, 141 [PLL_OFF_STATUS] = 0x2c, 142 }, 143 [CLK_ALPHA_PLL_TYPE_ZONDA] = { 144 [PLL_OFF_L_VAL] = 0x04, 145 [PLL_OFF_ALPHA_VAL] = 0x08, 146 [PLL_OFF_USER_CTL] = 0x0c, 147 [PLL_OFF_CONFIG_CTL] = 0x10, 148 [PLL_OFF_CONFIG_CTL_U] = 0x14, 149 [PLL_OFF_CONFIG_CTL_U1] = 0x18, 150 [PLL_OFF_TEST_CTL] = 0x1c, 151 [PLL_OFF_TEST_CTL_U] = 0x20, 152 [PLL_OFF_TEST_CTL_U1] = 0x24, 153 [PLL_OFF_OPMODE] = 0x28, 154 [PLL_OFF_STATUS] = 0x38, 155 }, 156 [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = { 157 [PLL_OFF_OPMODE] = 0x04, 158 [PLL_OFF_STATUS] = 0x0c, 159 [PLL_OFF_L_VAL] = 0x10, 160 [PLL_OFF_ALPHA_VAL] = 0x14, 161 [PLL_OFF_USER_CTL] = 0x18, 162 [PLL_OFF_USER_CTL_U] = 0x1c, 163 [PLL_OFF_CONFIG_CTL] = 0x20, 164 [PLL_OFF_CONFIG_CTL_U] = 0x24, 165 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 166 [PLL_OFF_TEST_CTL] = 0x2c, 167 [PLL_OFF_TEST_CTL_U] = 0x30, 168 [PLL_OFF_TEST_CTL_U1] = 0x34, 169 }, 170 [CLK_ALPHA_PLL_TYPE_LUCID_OLE] = { 171 [PLL_OFF_OPMODE] = 0x04, 172 [PLL_OFF_STATE] = 0x08, 173 [PLL_OFF_STATUS] = 0x0c, 174 [PLL_OFF_L_VAL] = 0x10, 175 [PLL_OFF_ALPHA_VAL] = 0x14, 176 [PLL_OFF_USER_CTL] = 0x18, 177 [PLL_OFF_USER_CTL_U] = 0x1c, 178 [PLL_OFF_CONFIG_CTL] = 0x20, 179 [PLL_OFF_CONFIG_CTL_U] = 0x24, 180 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 181 [PLL_OFF_TEST_CTL] = 0x2c, 182 [PLL_OFF_TEST_CTL_U] = 0x30, 183 [PLL_OFF_TEST_CTL_U1] = 0x34, 184 [PLL_OFF_TEST_CTL_U2] = 0x38, 185 }, 186 [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = { 187 [PLL_OFF_OPMODE] = 0x04, 188 [PLL_OFF_STATUS] = 0x0c, 189 [PLL_OFF_L_VAL] = 0x10, 190 [PLL_OFF_USER_CTL] = 0x14, 191 [PLL_OFF_USER_CTL_U] = 0x18, 192 [PLL_OFF_CONFIG_CTL] = 0x1c, 193 [PLL_OFF_CONFIG_CTL_U] = 0x20, 194 [PLL_OFF_CONFIG_CTL_U1] = 0x24, 195 [PLL_OFF_TEST_CTL] = 0x28, 196 [PLL_OFF_TEST_CTL_U] = 0x2c, 197 }, 198 [CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = { 199 [PLL_OFF_L_VAL] = 0x04, 200 [PLL_OFF_ALPHA_VAL] = 0x08, 201 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 202 [PLL_OFF_TEST_CTL] = 0x10, 203 [PLL_OFF_TEST_CTL_U] = 0x14, 204 [PLL_OFF_USER_CTL] = 0x18, 205 [PLL_OFF_USER_CTL_U] = 0x1c, 206 [PLL_OFF_CONFIG_CTL] = 0x20, 207 [PLL_OFF_STATUS] = 0x24, 208 }, 209 [CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = { 210 [PLL_OFF_L_VAL] = 0x04, 211 [PLL_OFF_ALPHA_VAL] = 0x08, 212 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 213 [PLL_OFF_TEST_CTL] = 0x10, 214 [PLL_OFF_TEST_CTL_U] = 0x14, 215 [PLL_OFF_USER_CTL] = 0x18, 216 [PLL_OFF_CONFIG_CTL] = 0x1C, 217 [PLL_OFF_STATUS] = 0x20, 218 }, 219 [CLK_ALPHA_PLL_TYPE_STROMER] = { 220 [PLL_OFF_L_VAL] = 0x08, 221 [PLL_OFF_ALPHA_VAL] = 0x10, 222 [PLL_OFF_ALPHA_VAL_U] = 0x14, 223 [PLL_OFF_USER_CTL] = 0x18, 224 [PLL_OFF_USER_CTL_U] = 0x1c, 225 [PLL_OFF_CONFIG_CTL] = 0x20, 226 [PLL_OFF_STATUS] = 0x28, 227 [PLL_OFF_TEST_CTL] = 0x30, 228 [PLL_OFF_TEST_CTL_U] = 0x34, 229 }, 230 [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = { 231 [PLL_OFF_L_VAL] = 0x04, 232 [PLL_OFF_USER_CTL] = 0x08, 233 [PLL_OFF_USER_CTL_U] = 0x0c, 234 [PLL_OFF_CONFIG_CTL] = 0x10, 235 [PLL_OFF_TEST_CTL] = 0x14, 236 [PLL_OFF_TEST_CTL_U] = 0x18, 237 [PLL_OFF_STATUS] = 0x1c, 238 [PLL_OFF_ALPHA_VAL] = 0x24, 239 [PLL_OFF_ALPHA_VAL_U] = 0x28, 240 }, 241 [CLK_ALPHA_PLL_TYPE_ZONDA_OLE] = { 242 [PLL_OFF_L_VAL] = 0x04, 243 [PLL_OFF_ALPHA_VAL] = 0x08, 244 [PLL_OFF_USER_CTL] = 0x0c, 245 [PLL_OFF_USER_CTL_U] = 0x10, 246 [PLL_OFF_CONFIG_CTL] = 0x14, 247 [PLL_OFF_CONFIG_CTL_U] = 0x18, 248 [PLL_OFF_CONFIG_CTL_U1] = 0x1c, 249 [PLL_OFF_CONFIG_CTL_U2] = 0x20, 250 [PLL_OFF_TEST_CTL] = 0x24, 251 [PLL_OFF_TEST_CTL_U] = 0x28, 252 [PLL_OFF_TEST_CTL_U1] = 0x2c, 253 [PLL_OFF_OPMODE] = 0x30, 254 [PLL_OFF_STATUS] = 0x3c, 255 }, 256 }; 257 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 258 259 /* 260 * Even though 40 bits are present, use only 32 for ease of calculation. 261 */ 262 #define ALPHA_REG_BITWIDTH 40 263 #define ALPHA_REG_16BIT_WIDTH 16 264 #define ALPHA_BITWIDTH 32U 265 #define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH) 266 267 #define ALPHA_PLL_STATUS_REG_SHIFT 8 268 269 #define PLL_HUAYRA_M_WIDTH 8 270 #define PLL_HUAYRA_M_SHIFT 8 271 #define PLL_HUAYRA_M_MASK 0xff 272 #define PLL_HUAYRA_N_SHIFT 0 273 #define PLL_HUAYRA_N_MASK 0xff 274 #define PLL_HUAYRA_ALPHA_WIDTH 16 275 276 #define PLL_STANDBY 0x0 277 #define PLL_RUN 0x1 278 #define PLL_OUT_MASK 0x7 279 #define PLL_RATE_MARGIN 500 280 281 /* TRION PLL specific settings and offsets */ 282 #define TRION_PLL_CAL_VAL 0x44 283 #define TRION_PCAL_DONE BIT(26) 284 285 /* LUCID PLL specific settings and offsets */ 286 #define LUCID_PCAL_DONE BIT(27) 287 288 /* LUCID 5LPE PLL specific settings and offsets */ 289 #define LUCID_5LPE_PCAL_DONE BIT(11) 290 #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13) 291 #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14) 292 #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) 293 294 /* LUCID EVO PLL specific settings and offsets */ 295 #define LUCID_EVO_PCAL_NOT_DONE BIT(8) 296 #define LUCID_EVO_ENABLE_VOTE_RUN BIT(25) 297 #define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0) 298 #define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16 299 #define LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT 24 300 301 /* ZONDA PLL specific */ 302 #define ZONDA_PLL_OUT_MASK 0xf 303 #define ZONDA_STAY_IN_CFA BIT(16) 304 #define ZONDA_PLL_FREQ_LOCK_DET BIT(29) 305 306 #define pll_alpha_width(p) \ 307 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ 308 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) 309 310 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4) 311 312 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ 313 struct clk_alpha_pll, clkr) 314 315 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \ 316 struct clk_alpha_pll_postdiv, clkr) 317 318 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, 319 const char *action) 320 { 321 u32 val; 322 int count; 323 int ret; 324 const char *name = clk_hw_get_name(&pll->clkr.hw); 325 326 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 327 if (ret) 328 return ret; 329 330 for (count = 200; count > 0; count--) { 331 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 332 if (ret) 333 return ret; 334 if (inverse && !(val & mask)) 335 return 0; 336 else if ((val & mask) == mask) 337 return 0; 338 339 udelay(1); 340 } 341 342 WARN(1, "%s failed to %s!\n", name, action); 343 return -ETIMEDOUT; 344 } 345 346 #define wait_for_pll_enable_active(pll) \ 347 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable") 348 349 #define wait_for_pll_enable_lock(pll) \ 350 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable") 351 352 #define wait_for_zonda_pll_freq_lock(pll) \ 353 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable") 354 355 #define wait_for_pll_disable(pll) \ 356 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable") 357 358 #define wait_for_pll_offline(pll) \ 359 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline") 360 361 #define wait_for_pll_update(pll) \ 362 wait_for_pll(pll, PLL_UPDATE, 1, "update") 363 364 #define wait_for_pll_update_ack_set(pll) \ 365 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set") 366 367 #define wait_for_pll_update_ack_clear(pll) \ 368 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear") 369 370 static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg, 371 unsigned int val) 372 { 373 if (val) 374 regmap_write(regmap, reg, val); 375 } 376 377 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 378 const struct alpha_pll_config *config) 379 { 380 u32 val, mask; 381 382 regmap_write(regmap, PLL_L_VAL(pll), config->l); 383 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); 384 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 385 386 if (pll_has_64bit_config(pll)) 387 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), 388 config->config_ctl_hi_val); 389 390 if (pll_alpha_width(pll) > 32) 391 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); 392 393 val = config->main_output_mask; 394 val |= config->aux_output_mask; 395 val |= config->aux2_output_mask; 396 val |= config->early_output_mask; 397 val |= config->pre_div_val; 398 val |= config->post_div_val; 399 val |= config->vco_val; 400 val |= config->alpha_en_mask; 401 val |= config->alpha_mode_mask; 402 403 mask = config->main_output_mask; 404 mask |= config->aux_output_mask; 405 mask |= config->aux2_output_mask; 406 mask |= config->early_output_mask; 407 mask |= config->pre_div_mask; 408 mask |= config->post_div_mask; 409 mask |= config->vco_mask; 410 411 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 412 413 if (config->test_ctl_mask) 414 regmap_update_bits(regmap, PLL_TEST_CTL(pll), 415 config->test_ctl_mask, 416 config->test_ctl_val); 417 else 418 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 419 config->test_ctl_val); 420 421 if (config->test_ctl_hi_mask) 422 regmap_update_bits(regmap, PLL_TEST_CTL_U(pll), 423 config->test_ctl_hi_mask, 424 config->test_ctl_hi_val); 425 else 426 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 427 config->test_ctl_hi_val); 428 429 if (pll->flags & SUPPORTS_FSM_MODE) 430 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); 431 } 432 EXPORT_SYMBOL_GPL(clk_alpha_pll_configure); 433 434 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) 435 { 436 int ret; 437 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 438 u32 val; 439 440 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 441 if (ret) 442 return ret; 443 444 val |= PLL_FSM_ENA; 445 446 if (pll->flags & SUPPORTS_OFFLINE_REQ) 447 val &= ~PLL_OFFLINE_REQ; 448 449 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); 450 if (ret) 451 return ret; 452 453 /* Make sure enable request goes through before waiting for update */ 454 mb(); 455 456 return wait_for_pll_enable_active(pll); 457 } 458 459 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw) 460 { 461 int ret; 462 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 463 u32 val; 464 465 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 466 if (ret) 467 return; 468 469 if (pll->flags & SUPPORTS_OFFLINE_REQ) { 470 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 471 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ); 472 if (ret) 473 return; 474 475 ret = wait_for_pll_offline(pll); 476 if (ret) 477 return; 478 } 479 480 /* Disable hwfsm */ 481 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 482 PLL_FSM_ENA, 0); 483 if (ret) 484 return; 485 486 wait_for_pll_disable(pll); 487 } 488 489 static int pll_is_enabled(struct clk_hw *hw, u32 mask) 490 { 491 int ret; 492 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 493 u32 val; 494 495 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 496 if (ret) 497 return ret; 498 499 return !!(val & mask); 500 } 501 502 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw) 503 { 504 return pll_is_enabled(hw, PLL_ACTIVE_FLAG); 505 } 506 507 static int clk_alpha_pll_is_enabled(struct clk_hw *hw) 508 { 509 return pll_is_enabled(hw, PLL_LOCK_DET); 510 } 511 512 static int clk_alpha_pll_enable(struct clk_hw *hw) 513 { 514 int ret; 515 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 516 u32 val, mask; 517 518 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; 519 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 520 if (ret) 521 return ret; 522 523 /* If in FSM mode, just vote for it */ 524 if (val & PLL_VOTE_FSM_ENA) { 525 ret = clk_enable_regmap(hw); 526 if (ret) 527 return ret; 528 return wait_for_pll_enable_active(pll); 529 } 530 531 /* Skip if already enabled */ 532 if ((val & mask) == mask) 533 return 0; 534 535 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 536 PLL_BYPASSNL, PLL_BYPASSNL); 537 if (ret) 538 return ret; 539 540 /* 541 * H/W requires a 5us delay between disabling the bypass and 542 * de-asserting the reset. 543 */ 544 mb(); 545 udelay(5); 546 547 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 548 PLL_RESET_N, PLL_RESET_N); 549 if (ret) 550 return ret; 551 552 ret = wait_for_pll_enable_lock(pll); 553 if (ret) 554 return ret; 555 556 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 557 PLL_OUTCTRL, PLL_OUTCTRL); 558 559 /* Ensure that the write above goes through before returning. */ 560 mb(); 561 return ret; 562 } 563 564 static void clk_alpha_pll_disable(struct clk_hw *hw) 565 { 566 int ret; 567 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 568 u32 val, mask; 569 570 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 571 if (ret) 572 return; 573 574 /* If in FSM mode, just unvote it */ 575 if (val & PLL_VOTE_FSM_ENA) { 576 clk_disable_regmap(hw); 577 return; 578 } 579 580 mask = PLL_OUTCTRL; 581 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 582 583 /* Delay of 2 output clock ticks required until output is disabled */ 584 mb(); 585 udelay(1); 586 587 mask = PLL_RESET_N | PLL_BYPASSNL; 588 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 589 } 590 591 static unsigned long 592 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width) 593 { 594 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width)); 595 } 596 597 static unsigned long 598 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a, 599 u32 alpha_width) 600 { 601 u64 remainder; 602 u64 quotient; 603 604 quotient = rate; 605 remainder = do_div(quotient, prate); 606 *l = quotient; 607 608 if (!remainder) { 609 *a = 0; 610 return rate; 611 } 612 613 /* Upper ALPHA_BITWIDTH bits of Alpha */ 614 quotient = remainder << ALPHA_SHIFT(alpha_width); 615 616 remainder = do_div(quotient, prate); 617 618 if (remainder) 619 quotient++; 620 621 *a = quotient; 622 return alpha_pll_calc_rate(prate, *l, *a, alpha_width); 623 } 624 625 static const struct pll_vco * 626 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) 627 { 628 const struct pll_vco *v = pll->vco_table; 629 const struct pll_vco *end = v + pll->num_vco; 630 631 for (; v < end; v++) 632 if (rate >= v->min_freq && rate <= v->max_freq) 633 return v; 634 635 return NULL; 636 } 637 638 static unsigned long 639 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 640 { 641 u32 l, low, high, ctl; 642 u64 a = 0, prate = parent_rate; 643 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 644 u32 alpha_width = pll_alpha_width(pll); 645 646 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 647 648 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 649 if (ctl & PLL_ALPHA_EN) { 650 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); 651 if (alpha_width > 32) { 652 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 653 &high); 654 a = (u64)high << 32 | low; 655 } else { 656 a = low & GENMASK(alpha_width - 1, 0); 657 } 658 659 if (alpha_width > ALPHA_BITWIDTH) 660 a >>= alpha_width - ALPHA_BITWIDTH; 661 } 662 663 return alpha_pll_calc_rate(prate, l, a, alpha_width); 664 } 665 666 667 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) 668 { 669 int ret; 670 u32 mode; 671 672 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); 673 674 /* Latch the input to the PLL */ 675 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 676 PLL_UPDATE); 677 678 /* Wait for 2 reference cycle before checking ACK bit */ 679 udelay(1); 680 681 /* 682 * PLL will latch the new L, Alpha and freq control word. 683 * PLL will respond by raising PLL_ACK_LATCH output when new programming 684 * has been latched in and PLL is being updated. When 685 * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared 686 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. 687 */ 688 if (mode & PLL_UPDATE_BYPASS) { 689 ret = wait_for_pll_update_ack_set(pll); 690 if (ret) 691 return ret; 692 693 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); 694 } else { 695 ret = wait_for_pll_update(pll); 696 if (ret) 697 return ret; 698 } 699 700 ret = wait_for_pll_update_ack_clear(pll); 701 if (ret) 702 return ret; 703 704 /* Wait for PLL output to stabilize */ 705 udelay(10); 706 707 return 0; 708 } 709 710 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, 711 int (*is_enabled)(struct clk_hw *)) 712 { 713 if (!is_enabled(&pll->clkr.hw) || 714 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) 715 return 0; 716 717 return __clk_alpha_pll_update_latch(pll); 718 } 719 720 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 721 unsigned long prate, 722 int (*is_enabled)(struct clk_hw *)) 723 { 724 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 725 const struct pll_vco *vco; 726 u32 l, alpha_width = pll_alpha_width(pll); 727 u64 a; 728 729 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 730 vco = alpha_pll_find_vco(pll, rate); 731 if (pll->vco_table && !vco) { 732 pr_err("%s: alpha pll not in a valid vco range\n", 733 clk_hw_get_name(hw)); 734 return -EINVAL; 735 } 736 737 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 738 739 if (alpha_width > ALPHA_BITWIDTH) 740 a <<= alpha_width - ALPHA_BITWIDTH; 741 742 if (alpha_width > 32) 743 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); 744 745 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 746 747 if (vco) { 748 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 749 PLL_VCO_MASK << PLL_VCO_SHIFT, 750 vco->val << PLL_VCO_SHIFT); 751 } 752 753 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 754 PLL_ALPHA_EN, PLL_ALPHA_EN); 755 756 return clk_alpha_pll_update_latch(pll, is_enabled); 757 } 758 759 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 760 unsigned long prate) 761 { 762 return __clk_alpha_pll_set_rate(hw, rate, prate, 763 clk_alpha_pll_is_enabled); 764 } 765 766 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate, 767 unsigned long prate) 768 { 769 return __clk_alpha_pll_set_rate(hw, rate, prate, 770 clk_alpha_pll_hwfsm_is_enabled); 771 } 772 773 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, 774 unsigned long *prate) 775 { 776 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 777 u32 l, alpha_width = pll_alpha_width(pll); 778 u64 a; 779 unsigned long min_freq, max_freq; 780 781 rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width); 782 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) 783 return rate; 784 785 min_freq = pll->vco_table[0].min_freq; 786 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 787 788 return clamp(rate, min_freq, max_freq); 789 } 790 791 static unsigned long 792 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a) 793 { 794 /* 795 * a contains 16 bit alpha_val in two’s complement number in the range 796 * of [-0.5, 0.5). 797 */ 798 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 799 l -= 1; 800 801 return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH); 802 } 803 804 static unsigned long 805 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate, 806 u32 *l, u32 *a) 807 { 808 u64 remainder; 809 u64 quotient; 810 811 quotient = rate; 812 remainder = do_div(quotient, prate); 813 *l = quotient; 814 815 if (!remainder) { 816 *a = 0; 817 return rate; 818 } 819 820 quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH; 821 remainder = do_div(quotient, prate); 822 823 if (remainder) 824 quotient++; 825 826 /* 827 * alpha_val should be in two’s complement number in the range 828 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value 829 * since alpha value will be subtracted in this case. 830 */ 831 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 832 *l += 1; 833 834 *a = quotient; 835 return alpha_huayra_pll_calc_rate(prate, *l, *a); 836 } 837 838 static unsigned long 839 alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 840 { 841 u64 rate = parent_rate, tmp; 842 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 843 u32 l, alpha = 0, ctl, alpha_m, alpha_n; 844 845 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 846 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 847 848 if (ctl & PLL_ALPHA_EN) { 849 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); 850 /* 851 * Depending upon alpha_mode, it can be treated as M/N value or 852 * as a two’s complement number. When alpha_mode=1, 853 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N 854 * 855 * Fout=FIN*(L+(M/N)) 856 * 857 * M is a signed number (-128 to 127) and N is unsigned 858 * (0 to 255). M/N has to be within +/-0.5. 859 * 860 * When alpha_mode=0, it is a two’s complement number in the 861 * range [-0.5, 0.5). 862 * 863 * Fout=FIN*(L+(alpha_val)/2^16) 864 * 865 * where alpha_val is two’s complement number. 866 */ 867 if (!(ctl & PLL_ALPHA_MODE)) 868 return alpha_huayra_pll_calc_rate(rate, l, alpha); 869 870 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK; 871 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK; 872 873 rate *= l; 874 tmp = parent_rate; 875 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) { 876 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m; 877 tmp *= alpha_m; 878 do_div(tmp, alpha_n); 879 rate -= tmp; 880 } else { 881 tmp *= alpha_m; 882 do_div(tmp, alpha_n); 883 rate += tmp; 884 } 885 886 return rate; 887 } 888 889 return alpha_huayra_pll_calc_rate(rate, l, alpha); 890 } 891 892 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate, 893 unsigned long prate) 894 { 895 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 896 u32 l, a, ctl, cur_alpha = 0; 897 898 rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a); 899 900 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 901 902 if (ctl & PLL_ALPHA_EN) 903 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); 904 905 /* 906 * Huayra PLL supports PLL dynamic programming. User can change L_VAL, 907 * without having to go through the power on sequence. 908 */ 909 if (clk_alpha_pll_is_enabled(hw)) { 910 if (cur_alpha != a) { 911 pr_err("%s: clock needs to be gated\n", 912 clk_hw_get_name(hw)); 913 return -EBUSY; 914 } 915 916 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 917 /* Ensure that the write above goes to detect L val change. */ 918 mb(); 919 return wait_for_pll_enable_lock(pll); 920 } 921 922 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 923 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 924 925 if (a == 0) 926 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 927 PLL_ALPHA_EN, 0x0); 928 else 929 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 930 PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN); 931 932 return 0; 933 } 934 935 static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate, 936 unsigned long *prate) 937 { 938 u32 l, a; 939 940 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a); 941 } 942 943 static int trion_pll_is_enabled(struct clk_alpha_pll *pll, 944 struct regmap *regmap) 945 { 946 u32 mode_val, opmode_val; 947 int ret; 948 949 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); 950 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 951 if (ret) 952 return 0; 953 954 return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL)); 955 } 956 957 static int clk_trion_pll_is_enabled(struct clk_hw *hw) 958 { 959 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 960 961 return trion_pll_is_enabled(pll, pll->clkr.regmap); 962 } 963 964 static int clk_trion_pll_enable(struct clk_hw *hw) 965 { 966 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 967 struct regmap *regmap = pll->clkr.regmap; 968 u32 val; 969 int ret; 970 971 ret = regmap_read(regmap, PLL_MODE(pll), &val); 972 if (ret) 973 return ret; 974 975 /* If in FSM mode, just vote for it */ 976 if (val & PLL_VOTE_FSM_ENA) { 977 ret = clk_enable_regmap(hw); 978 if (ret) 979 return ret; 980 return wait_for_pll_enable_active(pll); 981 } 982 983 /* Set operation mode to RUN */ 984 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 985 986 ret = wait_for_pll_enable_lock(pll); 987 if (ret) 988 return ret; 989 990 /* Enable the PLL outputs */ 991 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 992 PLL_OUT_MASK, PLL_OUT_MASK); 993 if (ret) 994 return ret; 995 996 /* Enable the global PLL outputs */ 997 return regmap_update_bits(regmap, PLL_MODE(pll), 998 PLL_OUTCTRL, PLL_OUTCTRL); 999 } 1000 1001 static void clk_trion_pll_disable(struct clk_hw *hw) 1002 { 1003 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1004 struct regmap *regmap = pll->clkr.regmap; 1005 u32 val; 1006 int ret; 1007 1008 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1009 if (ret) 1010 return; 1011 1012 /* If in FSM mode, just unvote it */ 1013 if (val & PLL_VOTE_FSM_ENA) { 1014 clk_disable_regmap(hw); 1015 return; 1016 } 1017 1018 /* Disable the global PLL output */ 1019 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1020 if (ret) 1021 return; 1022 1023 /* Disable the PLL outputs */ 1024 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1025 PLL_OUT_MASK, 0); 1026 if (ret) 1027 return; 1028 1029 /* Place the PLL mode in STANDBY */ 1030 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1031 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1032 } 1033 1034 static unsigned long 1035 clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1036 { 1037 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1038 u32 l, frac, alpha_width = pll_alpha_width(pll); 1039 1040 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 1041 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac); 1042 1043 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 1044 } 1045 1046 const struct clk_ops clk_alpha_pll_fixed_ops = { 1047 .enable = clk_alpha_pll_enable, 1048 .disable = clk_alpha_pll_disable, 1049 .is_enabled = clk_alpha_pll_is_enabled, 1050 .recalc_rate = clk_alpha_pll_recalc_rate, 1051 }; 1052 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops); 1053 1054 const struct clk_ops clk_alpha_pll_ops = { 1055 .enable = clk_alpha_pll_enable, 1056 .disable = clk_alpha_pll_disable, 1057 .is_enabled = clk_alpha_pll_is_enabled, 1058 .recalc_rate = clk_alpha_pll_recalc_rate, 1059 .round_rate = clk_alpha_pll_round_rate, 1060 .set_rate = clk_alpha_pll_set_rate, 1061 }; 1062 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops); 1063 1064 const struct clk_ops clk_alpha_pll_huayra_ops = { 1065 .enable = clk_alpha_pll_enable, 1066 .disable = clk_alpha_pll_disable, 1067 .is_enabled = clk_alpha_pll_is_enabled, 1068 .recalc_rate = alpha_pll_huayra_recalc_rate, 1069 .round_rate = alpha_pll_huayra_round_rate, 1070 .set_rate = alpha_pll_huayra_set_rate, 1071 }; 1072 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops); 1073 1074 const struct clk_ops clk_alpha_pll_hwfsm_ops = { 1075 .enable = clk_alpha_pll_hwfsm_enable, 1076 .disable = clk_alpha_pll_hwfsm_disable, 1077 .is_enabled = clk_alpha_pll_hwfsm_is_enabled, 1078 .recalc_rate = clk_alpha_pll_recalc_rate, 1079 .round_rate = clk_alpha_pll_round_rate, 1080 .set_rate = clk_alpha_pll_hwfsm_set_rate, 1081 }; 1082 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); 1083 1084 const struct clk_ops clk_alpha_pll_fixed_trion_ops = { 1085 .enable = clk_trion_pll_enable, 1086 .disable = clk_trion_pll_disable, 1087 .is_enabled = clk_trion_pll_is_enabled, 1088 .recalc_rate = clk_trion_pll_recalc_rate, 1089 .round_rate = clk_alpha_pll_round_rate, 1090 }; 1091 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops); 1092 1093 static unsigned long 1094 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1095 { 1096 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1097 u32 ctl; 1098 1099 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 1100 1101 ctl >>= PLL_POST_DIV_SHIFT; 1102 ctl &= PLL_POST_DIV_MASK(pll); 1103 1104 return parent_rate >> fls(ctl); 1105 } 1106 1107 static const struct clk_div_table clk_alpha_div_table[] = { 1108 { 0x0, 1 }, 1109 { 0x1, 2 }, 1110 { 0x3, 4 }, 1111 { 0x7, 8 }, 1112 { 0xf, 16 }, 1113 { } 1114 }; 1115 1116 static const struct clk_div_table clk_alpha_2bit_div_table[] = { 1117 { 0x0, 1 }, 1118 { 0x1, 2 }, 1119 { 0x3, 4 }, 1120 { } 1121 }; 1122 1123 static long 1124 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, 1125 unsigned long *prate) 1126 { 1127 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1128 const struct clk_div_table *table; 1129 1130 if (pll->width == 2) 1131 table = clk_alpha_2bit_div_table; 1132 else 1133 table = clk_alpha_div_table; 1134 1135 return divider_round_rate(hw, rate, prate, table, 1136 pll->width, CLK_DIVIDER_POWER_OF_TWO); 1137 } 1138 1139 static long 1140 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate, 1141 unsigned long *prate) 1142 { 1143 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1144 u32 ctl, div; 1145 1146 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 1147 1148 ctl >>= PLL_POST_DIV_SHIFT; 1149 ctl &= BIT(pll->width) - 1; 1150 div = 1 << fls(ctl); 1151 1152 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) 1153 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate); 1154 1155 return DIV_ROUND_UP_ULL((u64)*prate, div); 1156 } 1157 1158 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1159 unsigned long parent_rate) 1160 { 1161 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1162 int div; 1163 1164 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ 1165 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1; 1166 1167 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1168 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 1169 div << PLL_POST_DIV_SHIFT); 1170 } 1171 1172 const struct clk_ops clk_alpha_pll_postdiv_ops = { 1173 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1174 .round_rate = clk_alpha_pll_postdiv_round_rate, 1175 .set_rate = clk_alpha_pll_postdiv_set_rate, 1176 }; 1177 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops); 1178 1179 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = { 1180 .round_rate = clk_alpha_pll_postdiv_round_ro_rate, 1181 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1182 }; 1183 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops); 1184 1185 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1186 const struct alpha_pll_config *config) 1187 { 1188 u32 val, mask; 1189 1190 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1191 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha); 1192 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1193 config->config_ctl_val); 1194 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1195 config->config_ctl_hi_val); 1196 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1197 config->user_ctl_val); 1198 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1199 config->user_ctl_hi_val); 1200 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1201 config->test_ctl_val); 1202 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1203 config->test_ctl_hi_val); 1204 1205 if (config->post_div_mask) { 1206 mask = config->post_div_mask; 1207 val = config->post_div_val; 1208 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 1209 } 1210 1211 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE) 1212 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE, 1213 PLL_FSM_LEGACY_MODE); 1214 1215 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1216 PLL_UPDATE_BYPASS); 1217 1218 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1219 } 1220 EXPORT_SYMBOL_GPL(clk_fabia_pll_configure); 1221 1222 static int alpha_pll_fabia_enable(struct clk_hw *hw) 1223 { 1224 int ret; 1225 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1226 u32 val, opmode_val; 1227 struct regmap *regmap = pll->clkr.regmap; 1228 1229 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1230 if (ret) 1231 return ret; 1232 1233 /* If in FSM mode, just vote for it */ 1234 if (val & PLL_VOTE_FSM_ENA) { 1235 ret = clk_enable_regmap(hw); 1236 if (ret) 1237 return ret; 1238 return wait_for_pll_enable_active(pll); 1239 } 1240 1241 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 1242 if (ret) 1243 return ret; 1244 1245 /* Skip If PLL is already running */ 1246 if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL)) 1247 return 0; 1248 1249 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1250 if (ret) 1251 return ret; 1252 1253 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1254 if (ret) 1255 return ret; 1256 1257 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 1258 PLL_RESET_N); 1259 if (ret) 1260 return ret; 1261 1262 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 1263 if (ret) 1264 return ret; 1265 1266 ret = wait_for_pll_enable_lock(pll); 1267 if (ret) 1268 return ret; 1269 1270 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1271 PLL_OUT_MASK, PLL_OUT_MASK); 1272 if (ret) 1273 return ret; 1274 1275 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 1276 PLL_OUTCTRL); 1277 } 1278 1279 static void alpha_pll_fabia_disable(struct clk_hw *hw) 1280 { 1281 int ret; 1282 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1283 u32 val; 1284 struct regmap *regmap = pll->clkr.regmap; 1285 1286 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1287 if (ret) 1288 return; 1289 1290 /* If in FSM mode, just unvote it */ 1291 if (val & PLL_FSM_ENA) { 1292 clk_disable_regmap(hw); 1293 return; 1294 } 1295 1296 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1297 if (ret) 1298 return; 1299 1300 /* Disable main outputs */ 1301 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 1302 if (ret) 1303 return; 1304 1305 /* Place the PLL in STANDBY */ 1306 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1307 } 1308 1309 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw, 1310 unsigned long parent_rate) 1311 { 1312 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1313 u32 l, frac, alpha_width = pll_alpha_width(pll); 1314 1315 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 1316 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac); 1317 1318 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 1319 } 1320 1321 /* 1322 * Due to limited number of bits for fractional rate programming, the 1323 * rounded up rate could be marginally higher than the requested rate. 1324 */ 1325 static int alpha_pll_check_rate_margin(struct clk_hw *hw, 1326 unsigned long rrate, unsigned long rate) 1327 { 1328 unsigned long rate_margin = rate + PLL_RATE_MARGIN; 1329 1330 if (rrate > rate_margin || rrate < rate) { 1331 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n", 1332 clk_hw_get_name(hw), rrate, rate, rate_margin); 1333 return -EINVAL; 1334 } 1335 1336 return 0; 1337 } 1338 1339 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate, 1340 unsigned long prate) 1341 { 1342 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1343 u32 l, alpha_width = pll_alpha_width(pll); 1344 unsigned long rrate; 1345 int ret; 1346 u64 a; 1347 1348 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1349 1350 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1351 if (ret < 0) 1352 return ret; 1353 1354 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1355 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); 1356 1357 return __clk_alpha_pll_update_latch(pll); 1358 } 1359 1360 static int alpha_pll_fabia_prepare(struct clk_hw *hw) 1361 { 1362 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1363 const struct pll_vco *vco; 1364 struct clk_hw *parent_hw; 1365 unsigned long cal_freq, rrate; 1366 u32 cal_l, val, alpha_width = pll_alpha_width(pll); 1367 const char *name = clk_hw_get_name(hw); 1368 u64 a; 1369 int ret; 1370 1371 /* Check if calibration needs to be done i.e. PLL is in reset */ 1372 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1373 if (ret) 1374 return ret; 1375 1376 /* Return early if calibration is not needed. */ 1377 if (val & PLL_RESET_N) 1378 return 0; 1379 1380 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); 1381 if (!vco) { 1382 pr_err("%s: alpha pll not in a valid vco range\n", name); 1383 return -EINVAL; 1384 } 1385 1386 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq + 1387 pll->vco_table[0].max_freq) * 54, 100); 1388 1389 parent_hw = clk_hw_get_parent(hw); 1390 if (!parent_hw) 1391 return -EINVAL; 1392 1393 rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw), 1394 &cal_l, &a, alpha_width); 1395 1396 ret = alpha_pll_check_rate_margin(hw, rrate, cal_freq); 1397 if (ret < 0) 1398 return ret; 1399 1400 /* Setup PLL for calibration frequency */ 1401 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l); 1402 1403 /* Bringup the PLL at calibration frequency */ 1404 ret = clk_alpha_pll_enable(hw); 1405 if (ret) { 1406 pr_err("%s: alpha pll calibration failed\n", name); 1407 return ret; 1408 } 1409 1410 clk_alpha_pll_disable(hw); 1411 1412 return 0; 1413 } 1414 1415 const struct clk_ops clk_alpha_pll_fabia_ops = { 1416 .prepare = alpha_pll_fabia_prepare, 1417 .enable = alpha_pll_fabia_enable, 1418 .disable = alpha_pll_fabia_disable, 1419 .is_enabled = clk_alpha_pll_is_enabled, 1420 .set_rate = alpha_pll_fabia_set_rate, 1421 .recalc_rate = alpha_pll_fabia_recalc_rate, 1422 .round_rate = clk_alpha_pll_round_rate, 1423 }; 1424 EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops); 1425 1426 const struct clk_ops clk_alpha_pll_fixed_fabia_ops = { 1427 .enable = alpha_pll_fabia_enable, 1428 .disable = alpha_pll_fabia_disable, 1429 .is_enabled = clk_alpha_pll_is_enabled, 1430 .recalc_rate = alpha_pll_fabia_recalc_rate, 1431 .round_rate = clk_alpha_pll_round_rate, 1432 }; 1433 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops); 1434 1435 static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw, 1436 unsigned long parent_rate) 1437 { 1438 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1439 u32 i, div = 1, val; 1440 int ret; 1441 1442 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1443 if (ret) 1444 return ret; 1445 1446 val >>= pll->post_div_shift; 1447 val &= BIT(pll->width) - 1; 1448 1449 for (i = 0; i < pll->num_post_div; i++) { 1450 if (pll->post_div_table[i].val == val) { 1451 div = pll->post_div_table[i].div; 1452 break; 1453 } 1454 } 1455 1456 return (parent_rate / div); 1457 } 1458 1459 static unsigned long 1460 clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1461 { 1462 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1463 struct regmap *regmap = pll->clkr.regmap; 1464 u32 i, div = 1, val; 1465 1466 regmap_read(regmap, PLL_USER_CTL(pll), &val); 1467 1468 val >>= pll->post_div_shift; 1469 val &= PLL_POST_DIV_MASK(pll); 1470 1471 for (i = 0; i < pll->num_post_div; i++) { 1472 if (pll->post_div_table[i].val == val) { 1473 div = pll->post_div_table[i].div; 1474 break; 1475 } 1476 } 1477 1478 return (parent_rate / div); 1479 } 1480 1481 static long 1482 clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, 1483 unsigned long *prate) 1484 { 1485 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1486 1487 return divider_round_rate(hw, rate, prate, pll->post_div_table, 1488 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1489 }; 1490 1491 static int 1492 clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1493 unsigned long parent_rate) 1494 { 1495 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1496 struct regmap *regmap = pll->clkr.regmap; 1497 int i, val = 0, div; 1498 1499 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1500 for (i = 0; i < pll->num_post_div; i++) { 1501 if (pll->post_div_table[i].div == div) { 1502 val = pll->post_div_table[i].val; 1503 break; 1504 } 1505 } 1506 1507 return regmap_update_bits(regmap, PLL_USER_CTL(pll), 1508 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 1509 val << PLL_POST_DIV_SHIFT); 1510 } 1511 1512 const struct clk_ops clk_alpha_pll_postdiv_trion_ops = { 1513 .recalc_rate = clk_trion_pll_postdiv_recalc_rate, 1514 .round_rate = clk_trion_pll_postdiv_round_rate, 1515 .set_rate = clk_trion_pll_postdiv_set_rate, 1516 }; 1517 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops); 1518 1519 static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw, 1520 unsigned long rate, unsigned long *prate) 1521 { 1522 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1523 1524 return divider_round_rate(hw, rate, prate, pll->post_div_table, 1525 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1526 } 1527 1528 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw, 1529 unsigned long rate, unsigned long parent_rate) 1530 { 1531 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1532 int i, val = 0, div, ret; 1533 1534 /* 1535 * If the PLL is in FSM mode, then treat set_rate callback as a 1536 * no-operation. 1537 */ 1538 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1539 if (ret) 1540 return ret; 1541 1542 if (val & PLL_VOTE_FSM_ENA) 1543 return 0; 1544 1545 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1546 for (i = 0; i < pll->num_post_div; i++) { 1547 if (pll->post_div_table[i].div == div) { 1548 val = pll->post_div_table[i].val; 1549 break; 1550 } 1551 } 1552 1553 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1554 (BIT(pll->width) - 1) << pll->post_div_shift, 1555 val << pll->post_div_shift); 1556 } 1557 1558 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = { 1559 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1560 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1561 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1562 }; 1563 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops); 1564 1565 /** 1566 * clk_trion_pll_configure - configure the trion pll 1567 * 1568 * @pll: clk alpha pll 1569 * @regmap: register map 1570 * @config: configuration to apply for pll 1571 */ 1572 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1573 const struct alpha_pll_config *config) 1574 { 1575 /* 1576 * If the bootloader left the PLL enabled it's likely that there are 1577 * RCGs that will lock up if we disable the PLL below. 1578 */ 1579 if (trion_pll_is_enabled(pll, regmap)) { 1580 pr_debug("Trion PLL is already enabled, skipping configuration\n"); 1581 return; 1582 } 1583 1584 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1585 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); 1586 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1587 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1588 config->config_ctl_val); 1589 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1590 config->config_ctl_hi_val); 1591 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), 1592 config->config_ctl_hi1_val); 1593 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1594 config->user_ctl_val); 1595 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1596 config->user_ctl_hi_val); 1597 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), 1598 config->user_ctl_hi1_val); 1599 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1600 config->test_ctl_val); 1601 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1602 config->test_ctl_hi_val); 1603 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), 1604 config->test_ctl_hi1_val); 1605 1606 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1607 PLL_UPDATE_BYPASS); 1608 1609 /* Disable PLL output */ 1610 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1611 1612 /* Set operation mode to OFF */ 1613 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1614 1615 /* Place the PLL in STANDBY mode */ 1616 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1617 } 1618 EXPORT_SYMBOL_GPL(clk_trion_pll_configure); 1619 1620 /* 1621 * The TRION PLL requires a power-on self-calibration which happens when the 1622 * PLL comes out of reset. Calibrate in case it is not completed. 1623 */ 1624 static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done) 1625 { 1626 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1627 u32 val; 1628 int ret; 1629 1630 /* Return early if calibration is not needed. */ 1631 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); 1632 if (val & pcal_done) 1633 return 0; 1634 1635 /* On/off to calibrate */ 1636 ret = clk_trion_pll_enable(hw); 1637 if (!ret) 1638 clk_trion_pll_disable(hw); 1639 1640 return ret; 1641 } 1642 1643 static int alpha_pll_trion_prepare(struct clk_hw *hw) 1644 { 1645 return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE); 1646 } 1647 1648 static int alpha_pll_lucid_prepare(struct clk_hw *hw) 1649 { 1650 return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE); 1651 } 1652 1653 static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1654 unsigned long prate, u32 latch_bit, u32 latch_ack) 1655 { 1656 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1657 unsigned long rrate; 1658 u32 val, l, alpha_width = pll_alpha_width(pll); 1659 u64 a; 1660 int ret; 1661 1662 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1663 1664 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1665 if (ret < 0) 1666 return ret; 1667 1668 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1669 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1670 1671 /* Latch the PLL input */ 1672 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); 1673 if (ret) 1674 return ret; 1675 1676 /* Wait for 2 reference cycles before checking the ACK bit. */ 1677 udelay(1); 1678 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1679 if (!(val & latch_ack)) { 1680 pr_err("Lucid PLL latch failed. Output may be unstable!\n"); 1681 return -EINVAL; 1682 } 1683 1684 /* Return the latch input to 0 */ 1685 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); 1686 if (ret) 1687 return ret; 1688 1689 if (clk_hw_is_enabled(hw)) { 1690 ret = wait_for_pll_enable_lock(pll); 1691 if (ret) 1692 return ret; 1693 } 1694 1695 /* Wait for PLL output to stabilize */ 1696 udelay(100); 1697 return 0; 1698 } 1699 1700 static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1701 unsigned long prate) 1702 { 1703 return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH); 1704 } 1705 1706 const struct clk_ops clk_alpha_pll_trion_ops = { 1707 .prepare = alpha_pll_trion_prepare, 1708 .enable = clk_trion_pll_enable, 1709 .disable = clk_trion_pll_disable, 1710 .is_enabled = clk_trion_pll_is_enabled, 1711 .recalc_rate = clk_trion_pll_recalc_rate, 1712 .round_rate = clk_alpha_pll_round_rate, 1713 .set_rate = alpha_pll_trion_set_rate, 1714 }; 1715 EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops); 1716 1717 const struct clk_ops clk_alpha_pll_lucid_ops = { 1718 .prepare = alpha_pll_lucid_prepare, 1719 .enable = clk_trion_pll_enable, 1720 .disable = clk_trion_pll_disable, 1721 .is_enabled = clk_trion_pll_is_enabled, 1722 .recalc_rate = clk_trion_pll_recalc_rate, 1723 .round_rate = clk_alpha_pll_round_rate, 1724 .set_rate = alpha_pll_trion_set_rate, 1725 }; 1726 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops); 1727 1728 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { 1729 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1730 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1731 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1732 }; 1733 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops); 1734 1735 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1736 const struct alpha_pll_config *config) 1737 { 1738 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1739 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1740 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1741 config->user_ctl_val); 1742 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1743 config->config_ctl_val); 1744 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1745 config->config_ctl_hi_val); 1746 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1747 config->test_ctl_val); 1748 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1749 config->test_ctl_hi_val); 1750 } 1751 EXPORT_SYMBOL_GPL(clk_agera_pll_configure); 1752 1753 static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate, 1754 unsigned long prate) 1755 { 1756 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1757 u32 l, alpha_width = pll_alpha_width(pll); 1758 int ret; 1759 unsigned long rrate; 1760 u64 a; 1761 1762 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1763 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1764 if (ret < 0) 1765 return ret; 1766 1767 /* change L_VAL without having to go through the power on sequence */ 1768 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1769 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1770 1771 if (clk_hw_is_enabled(hw)) 1772 return wait_for_pll_enable_lock(pll); 1773 1774 return 0; 1775 } 1776 1777 const struct clk_ops clk_alpha_pll_agera_ops = { 1778 .enable = clk_alpha_pll_enable, 1779 .disable = clk_alpha_pll_disable, 1780 .is_enabled = clk_alpha_pll_is_enabled, 1781 .recalc_rate = alpha_pll_fabia_recalc_rate, 1782 .round_rate = clk_alpha_pll_round_rate, 1783 .set_rate = clk_alpha_pll_agera_set_rate, 1784 }; 1785 EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops); 1786 1787 static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw) 1788 { 1789 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1790 u32 val; 1791 int ret; 1792 1793 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1794 if (ret) 1795 return ret; 1796 1797 /* If in FSM mode, just vote for it */ 1798 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 1799 ret = clk_enable_regmap(hw); 1800 if (ret) 1801 return ret; 1802 return wait_for_pll_enable_lock(pll); 1803 } 1804 1805 /* Check if PLL is already enabled, return if enabled */ 1806 ret = trion_pll_is_enabled(pll, pll->clkr.regmap); 1807 if (ret < 0) 1808 return ret; 1809 1810 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1811 if (ret) 1812 return ret; 1813 1814 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); 1815 1816 ret = wait_for_pll_enable_lock(pll); 1817 if (ret) 1818 return ret; 1819 1820 /* Enable the PLL outputs */ 1821 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 1822 if (ret) 1823 return ret; 1824 1825 /* Enable the global PLL outputs */ 1826 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 1827 } 1828 1829 static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw) 1830 { 1831 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1832 u32 val; 1833 int ret; 1834 1835 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1836 if (ret) 1837 return; 1838 1839 /* If in FSM mode, just unvote it */ 1840 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 1841 clk_disable_regmap(hw); 1842 return; 1843 } 1844 1845 /* Disable the global PLL output */ 1846 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1847 if (ret) 1848 return; 1849 1850 /* Disable the PLL outputs */ 1851 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 1852 if (ret) 1853 return; 1854 1855 /* Place the PLL mode in STANDBY */ 1856 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY); 1857 } 1858 1859 /* 1860 * The Lucid 5LPE PLL requires a power-on self-calibration which happens 1861 * when the PLL comes out of reset. Calibrate in case it is not completed. 1862 */ 1863 static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw) 1864 { 1865 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1866 struct clk_hw *p; 1867 u32 val = 0; 1868 int ret; 1869 1870 /* Return early if calibration is not needed. */ 1871 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1872 if (val & LUCID_5LPE_PCAL_DONE) 1873 return 0; 1874 1875 p = clk_hw_get_parent(hw); 1876 if (!p) 1877 return -EINVAL; 1878 1879 ret = alpha_pll_lucid_5lpe_enable(hw); 1880 if (ret) 1881 return ret; 1882 1883 alpha_pll_lucid_5lpe_disable(hw); 1884 1885 return 0; 1886 } 1887 1888 static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate, 1889 unsigned long prate) 1890 { 1891 return __alpha_pll_trion_set_rate(hw, rate, prate, 1892 LUCID_5LPE_PLL_LATCH_INPUT, 1893 LUCID_5LPE_ALPHA_PLL_ACK_LATCH); 1894 } 1895 1896 static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1897 unsigned long parent_rate, 1898 unsigned long enable_vote_run) 1899 { 1900 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1901 struct regmap *regmap = pll->clkr.regmap; 1902 int i, val, div, ret; 1903 u32 mask; 1904 1905 /* 1906 * If the PLL is in FSM mode, then treat set_rate callback as a 1907 * no-operation. 1908 */ 1909 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 1910 if (ret) 1911 return ret; 1912 1913 if (val & enable_vote_run) 1914 return 0; 1915 1916 if (!pll->post_div_table) { 1917 pr_err("Missing the post_div_table for the %s PLL\n", 1918 clk_hw_get_name(&pll->clkr.hw)); 1919 return -EINVAL; 1920 } 1921 1922 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); 1923 for (i = 0; i < pll->num_post_div; i++) { 1924 if (pll->post_div_table[i].div == div) { 1925 val = pll->post_div_table[i].val; 1926 break; 1927 } 1928 } 1929 1930 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); 1931 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1932 mask, val << pll->post_div_shift); 1933 } 1934 1935 static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1936 unsigned long parent_rate) 1937 { 1938 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN); 1939 } 1940 1941 const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = { 1942 .prepare = alpha_pll_lucid_5lpe_prepare, 1943 .enable = alpha_pll_lucid_5lpe_enable, 1944 .disable = alpha_pll_lucid_5lpe_disable, 1945 .is_enabled = clk_trion_pll_is_enabled, 1946 .recalc_rate = clk_trion_pll_recalc_rate, 1947 .round_rate = clk_alpha_pll_round_rate, 1948 .set_rate = alpha_pll_lucid_5lpe_set_rate, 1949 }; 1950 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops); 1951 1952 const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = { 1953 .enable = alpha_pll_lucid_5lpe_enable, 1954 .disable = alpha_pll_lucid_5lpe_disable, 1955 .is_enabled = clk_trion_pll_is_enabled, 1956 .recalc_rate = clk_trion_pll_recalc_rate, 1957 .round_rate = clk_alpha_pll_round_rate, 1958 }; 1959 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops); 1960 1961 const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = { 1962 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1963 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1964 .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate, 1965 }; 1966 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops); 1967 1968 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1969 const struct alpha_pll_config *config) 1970 { 1971 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1972 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1973 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 1974 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 1975 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 1976 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 1977 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 1978 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); 1979 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 1980 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 1981 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 1982 1983 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0); 1984 1985 /* Disable PLL output */ 1986 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1987 1988 /* Set operation mode to OFF */ 1989 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1990 1991 /* Place the PLL in STANDBY mode */ 1992 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1993 } 1994 EXPORT_SYMBOL_GPL(clk_zonda_pll_configure); 1995 1996 static int clk_zonda_pll_enable(struct clk_hw *hw) 1997 { 1998 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1999 struct regmap *regmap = pll->clkr.regmap; 2000 u32 val; 2001 int ret; 2002 2003 regmap_read(regmap, PLL_MODE(pll), &val); 2004 2005 /* If in FSM mode, just vote for it */ 2006 if (val & PLL_VOTE_FSM_ENA) { 2007 ret = clk_enable_regmap(hw); 2008 if (ret) 2009 return ret; 2010 return wait_for_pll_enable_active(pll); 2011 } 2012 2013 /* Get the PLL out of bypass mode */ 2014 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); 2015 2016 /* 2017 * H/W requires a 1us delay between disabling the bypass and 2018 * de-asserting the reset. 2019 */ 2020 udelay(1); 2021 2022 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2023 2024 /* Set operation mode to RUN */ 2025 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2026 2027 regmap_read(regmap, PLL_TEST_CTL(pll), &val); 2028 2029 /* If cfa mode then poll for freq lock */ 2030 if (val & ZONDA_STAY_IN_CFA) 2031 ret = wait_for_zonda_pll_freq_lock(pll); 2032 else 2033 ret = wait_for_pll_enable_lock(pll); 2034 if (ret) 2035 return ret; 2036 2037 /* Enable the PLL outputs */ 2038 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK); 2039 2040 /* Enable the global PLL outputs */ 2041 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2042 2043 return 0; 2044 } 2045 2046 static void clk_zonda_pll_disable(struct clk_hw *hw) 2047 { 2048 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2049 struct regmap *regmap = pll->clkr.regmap; 2050 u32 val; 2051 2052 regmap_read(regmap, PLL_MODE(pll), &val); 2053 2054 /* If in FSM mode, just unvote it */ 2055 if (val & PLL_VOTE_FSM_ENA) { 2056 clk_disable_regmap(hw); 2057 return; 2058 } 2059 2060 /* Disable the global PLL output */ 2061 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2062 2063 /* Disable the PLL outputs */ 2064 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0); 2065 2066 /* Put the PLL in bypass and reset */ 2067 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0); 2068 2069 /* Place the PLL mode in OFF state */ 2070 regmap_write(regmap, PLL_OPMODE(pll), 0x0); 2071 } 2072 2073 static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, 2074 unsigned long prate) 2075 { 2076 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2077 unsigned long rrate; 2078 u32 test_ctl_val; 2079 u32 l, alpha_width = pll_alpha_width(pll); 2080 u64 a; 2081 int ret; 2082 2083 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 2084 2085 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 2086 if (ret < 0) 2087 return ret; 2088 2089 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2090 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2091 2092 /* Wait before polling for the frequency latch */ 2093 udelay(5); 2094 2095 /* Read stay in cfa mode */ 2096 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val); 2097 2098 /* If cfa mode then poll for freq lock */ 2099 if (test_ctl_val & ZONDA_STAY_IN_CFA) 2100 ret = wait_for_zonda_pll_freq_lock(pll); 2101 else 2102 ret = wait_for_pll_enable_lock(pll); 2103 if (ret) 2104 return ret; 2105 2106 /* Wait for PLL output to stabilize */ 2107 udelay(100); 2108 return 0; 2109 } 2110 2111 const struct clk_ops clk_alpha_pll_zonda_ops = { 2112 .enable = clk_zonda_pll_enable, 2113 .disable = clk_zonda_pll_disable, 2114 .is_enabled = clk_trion_pll_is_enabled, 2115 .recalc_rate = clk_trion_pll_recalc_rate, 2116 .round_rate = clk_alpha_pll_round_rate, 2117 .set_rate = clk_zonda_pll_set_rate, 2118 }; 2119 EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops); 2120 2121 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2122 const struct alpha_pll_config *config) 2123 { 2124 u32 lval = config->l; 2125 2126 /* 2127 * If the bootloader left the PLL enabled it's likely that there are 2128 * RCGs that will lock up if we disable the PLL below. 2129 */ 2130 if (trion_pll_is_enabled(pll, regmap)) { 2131 pr_debug("Lucid Evo PLL is already enabled, skipping configuration\n"); 2132 return; 2133 } 2134 2135 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT; 2136 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); 2137 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2138 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2139 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2140 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2141 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2142 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2143 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2144 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2145 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2146 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); 2147 2148 /* Disable PLL output */ 2149 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2150 2151 /* Set operation mode to STANDBY and de-assert the reset */ 2152 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2153 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2154 } 2155 EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure); 2156 2157 void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2158 const struct alpha_pll_config *config) 2159 { 2160 u32 lval = config->l; 2161 2162 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT; 2163 lval |= TRION_PLL_CAL_VAL << LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT; 2164 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); 2165 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2166 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2167 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2168 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2169 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2170 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2171 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2172 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2173 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2174 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); 2175 2176 /* Disable PLL output */ 2177 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2178 2179 /* Set operation mode to STANDBY and de-assert the reset */ 2180 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2181 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2182 } 2183 EXPORT_SYMBOL_GPL(clk_lucid_ole_pll_configure); 2184 2185 static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) 2186 { 2187 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2188 struct regmap *regmap = pll->clkr.regmap; 2189 u32 val; 2190 int ret; 2191 2192 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2193 if (ret) 2194 return ret; 2195 2196 /* If in FSM mode, just vote for it */ 2197 if (val & LUCID_EVO_ENABLE_VOTE_RUN) { 2198 ret = clk_enable_regmap(hw); 2199 if (ret) 2200 return ret; 2201 return wait_for_pll_enable_lock(pll); 2202 } 2203 2204 /* Check if PLL is already enabled */ 2205 ret = trion_pll_is_enabled(pll, regmap); 2206 if (ret < 0) { 2207 return ret; 2208 } else if (ret) { 2209 pr_warn("%s PLL is already enabled\n", clk_hw_get_name(&pll->clkr.hw)); 2210 return 0; 2211 } 2212 2213 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2214 if (ret) 2215 return ret; 2216 2217 /* Set operation mode to RUN */ 2218 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2219 2220 ret = wait_for_pll_enable_lock(pll); 2221 if (ret) 2222 return ret; 2223 2224 /* Enable the PLL outputs */ 2225 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 2226 if (ret) 2227 return ret; 2228 2229 /* Enable the global PLL outputs */ 2230 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2231 if (ret) 2232 return ret; 2233 2234 /* Ensure that the write above goes through before returning. */ 2235 mb(); 2236 return ret; 2237 } 2238 2239 static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset) 2240 { 2241 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2242 struct regmap *regmap = pll->clkr.regmap; 2243 u32 val; 2244 int ret; 2245 2246 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2247 if (ret) 2248 return; 2249 2250 /* If in FSM mode, just unvote it */ 2251 if (val & LUCID_EVO_ENABLE_VOTE_RUN) { 2252 clk_disable_regmap(hw); 2253 return; 2254 } 2255 2256 /* Disable the global PLL output */ 2257 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2258 if (ret) 2259 return; 2260 2261 /* Disable the PLL outputs */ 2262 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 2263 if (ret) 2264 return; 2265 2266 /* Place the PLL mode in STANDBY */ 2267 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2268 2269 if (reset) 2270 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0); 2271 } 2272 2273 static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset) 2274 { 2275 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2276 struct clk_hw *p; 2277 u32 val = 0; 2278 int ret; 2279 2280 /* Return early if calibration is not needed. */ 2281 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 2282 if (!(val & LUCID_EVO_PCAL_NOT_DONE)) 2283 return 0; 2284 2285 p = clk_hw_get_parent(hw); 2286 if (!p) 2287 return -EINVAL; 2288 2289 ret = alpha_pll_lucid_evo_enable(hw); 2290 if (ret) 2291 return ret; 2292 2293 _alpha_pll_lucid_evo_disable(hw, reset); 2294 2295 return 0; 2296 } 2297 2298 static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) 2299 { 2300 _alpha_pll_lucid_evo_disable(hw, false); 2301 } 2302 2303 static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw) 2304 { 2305 return _alpha_pll_lucid_evo_prepare(hw, false); 2306 } 2307 2308 static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw) 2309 { 2310 _alpha_pll_lucid_evo_disable(hw, true); 2311 } 2312 2313 static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw) 2314 { 2315 return _alpha_pll_lucid_evo_prepare(hw, true); 2316 } 2317 2318 static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, 2319 unsigned long parent_rate) 2320 { 2321 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2322 struct regmap *regmap = pll->clkr.regmap; 2323 u32 l, frac; 2324 2325 regmap_read(regmap, PLL_L_VAL(pll), &l); 2326 l &= LUCID_EVO_PLL_L_VAL_MASK; 2327 regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac); 2328 2329 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); 2330 } 2331 2332 static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 2333 unsigned long parent_rate) 2334 { 2335 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN); 2336 } 2337 2338 const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = { 2339 .enable = alpha_pll_lucid_evo_enable, 2340 .disable = alpha_pll_lucid_evo_disable, 2341 .is_enabled = clk_trion_pll_is_enabled, 2342 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2343 .round_rate = clk_alpha_pll_round_rate, 2344 }; 2345 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops); 2346 2347 const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = { 2348 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 2349 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 2350 .set_rate = clk_lucid_evo_pll_postdiv_set_rate, 2351 }; 2352 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops); 2353 2354 const struct clk_ops clk_alpha_pll_lucid_evo_ops = { 2355 .prepare = alpha_pll_lucid_evo_prepare, 2356 .enable = alpha_pll_lucid_evo_enable, 2357 .disable = alpha_pll_lucid_evo_disable, 2358 .is_enabled = clk_trion_pll_is_enabled, 2359 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2360 .round_rate = clk_alpha_pll_round_rate, 2361 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2362 }; 2363 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops); 2364 2365 const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = { 2366 .prepare = alpha_pll_reset_lucid_evo_prepare, 2367 .enable = alpha_pll_lucid_evo_enable, 2368 .disable = alpha_pll_reset_lucid_evo_disable, 2369 .is_enabled = clk_trion_pll_is_enabled, 2370 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2371 .round_rate = clk_alpha_pll_round_rate, 2372 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2373 }; 2374 EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops); 2375 2376 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2377 const struct alpha_pll_config *config) 2378 { 2379 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2380 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2381 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2382 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2383 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2384 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2385 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2386 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2387 2388 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2389 2390 regmap_update_bits(regmap, PLL_MODE(pll), 2391 PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL, 2392 PLL_RESET_N | PLL_BYPASSNL); 2393 } 2394 EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure); 2395 2396 static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw, 2397 unsigned long parent_rate) 2398 { 2399 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2400 u32 l; 2401 2402 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 2403 2404 return parent_rate * l; 2405 } 2406 2407 static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate, 2408 unsigned long *prate) 2409 { 2410 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2411 unsigned long min_freq, max_freq; 2412 u32 l; 2413 u64 a; 2414 2415 rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0); 2416 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) 2417 return rate; 2418 2419 min_freq = pll->vco_table[0].min_freq; 2420 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 2421 2422 return clamp(rate, min_freq, max_freq); 2423 } 2424 2425 const struct clk_ops clk_alpha_pll_rivian_evo_ops = { 2426 .enable = alpha_pll_lucid_5lpe_enable, 2427 .disable = alpha_pll_lucid_5lpe_disable, 2428 .is_enabled = clk_trion_pll_is_enabled, 2429 .recalc_rate = clk_rivian_evo_pll_recalc_rate, 2430 .round_rate = clk_rivian_evo_pll_round_rate, 2431 }; 2432 EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops); 2433 2434 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2435 const struct alpha_pll_config *config) 2436 { 2437 u32 val, val_u, mask, mask_u; 2438 2439 regmap_write(regmap, PLL_L_VAL(pll), config->l); 2440 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2441 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2442 2443 if (pll_has_64bit_config(pll)) 2444 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), 2445 config->config_ctl_hi_val); 2446 2447 if (pll_alpha_width(pll) > 32) 2448 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); 2449 2450 val = config->main_output_mask; 2451 val |= config->aux_output_mask; 2452 val |= config->aux2_output_mask; 2453 val |= config->early_output_mask; 2454 val |= config->pre_div_val; 2455 val |= config->post_div_val; 2456 val |= config->vco_val; 2457 val |= config->alpha_en_mask; 2458 val |= config->alpha_mode_mask; 2459 2460 mask = config->main_output_mask; 2461 mask |= config->aux_output_mask; 2462 mask |= config->aux2_output_mask; 2463 mask |= config->early_output_mask; 2464 mask |= config->pre_div_mask; 2465 mask |= config->post_div_mask; 2466 mask |= config->vco_mask; 2467 mask |= config->alpha_en_mask; 2468 mask |= config->alpha_mode_mask; 2469 2470 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 2471 2472 /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */ 2473 val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT; 2474 val_u |= config->lock_det; 2475 2476 mask_u = config->status_mask; 2477 mask_u |= config->lock_det; 2478 2479 regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u); 2480 regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2481 regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2482 2483 if (pll->flags & SUPPORTS_FSM_MODE) 2484 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); 2485 } 2486 EXPORT_SYMBOL_GPL(clk_stromer_pll_configure); 2487 2488 static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw, 2489 struct clk_rate_request *req) 2490 { 2491 u32 l; 2492 u64 a; 2493 2494 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, 2495 &l, &a, ALPHA_REG_BITWIDTH); 2496 2497 return 0; 2498 } 2499 2500 static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate, 2501 unsigned long prate) 2502 { 2503 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2504 int ret; 2505 u32 l; 2506 u64 a; 2507 2508 rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH); 2509 2510 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2511 2512 a <<= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH; 2513 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2514 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 2515 a >> ALPHA_BITWIDTH); 2516 2517 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 2518 PLL_ALPHA_EN, PLL_ALPHA_EN); 2519 2520 if (!clk_hw_is_enabled(hw)) 2521 return 0; 2522 2523 /* 2524 * Stromer PLL supports Dynamic programming. 2525 * It allows the PLL frequency to be changed on-the-fly without first 2526 * execution of a shutdown procedure followed by a bring up procedure. 2527 */ 2528 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 2529 PLL_UPDATE); 2530 2531 ret = wait_for_pll_update(pll); 2532 if (ret) 2533 return ret; 2534 2535 return wait_for_pll_enable_lock(pll); 2536 } 2537 2538 const struct clk_ops clk_alpha_pll_stromer_ops = { 2539 .enable = clk_alpha_pll_enable, 2540 .disable = clk_alpha_pll_disable, 2541 .is_enabled = clk_alpha_pll_is_enabled, 2542 .recalc_rate = clk_alpha_pll_recalc_rate, 2543 .determine_rate = clk_alpha_pll_stromer_determine_rate, 2544 .set_rate = clk_alpha_pll_stromer_set_rate, 2545 }; 2546 EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops); 2547 2548 static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw, 2549 unsigned long rate, 2550 unsigned long prate) 2551 { 2552 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2553 u32 l, alpha_width = pll_alpha_width(pll); 2554 int ret, pll_mode; 2555 u64 a; 2556 2557 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 2558 2559 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode); 2560 if (ret) 2561 return ret; 2562 2563 regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0); 2564 2565 /* Delay of 2 output clock ticks required until output is disabled */ 2566 udelay(1); 2567 2568 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2569 2570 if (alpha_width > ALPHA_BITWIDTH) 2571 a <<= alpha_width - ALPHA_BITWIDTH; 2572 2573 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2574 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 2575 a >> ALPHA_BITWIDTH); 2576 2577 regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL); 2578 2579 /* Wait five micro seconds or more */ 2580 udelay(5); 2581 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, 2582 PLL_RESET_N); 2583 2584 /* The lock time should be less than 50 micro seconds worst case */ 2585 usleep_range(50, 60); 2586 2587 ret = wait_for_pll_enable_lock(pll); 2588 if (ret) { 2589 pr_err("Wait for PLL enable lock failed [%s] %d\n", 2590 clk_hw_get_name(hw), ret); 2591 return ret; 2592 } 2593 2594 if (pll_mode & PLL_OUTCTRL) 2595 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 2596 PLL_OUTCTRL); 2597 2598 return 0; 2599 } 2600 2601 const struct clk_ops clk_alpha_pll_stromer_plus_ops = { 2602 .prepare = clk_alpha_pll_enable, 2603 .unprepare = clk_alpha_pll_disable, 2604 .is_enabled = clk_alpha_pll_is_enabled, 2605 .recalc_rate = clk_alpha_pll_recalc_rate, 2606 .determine_rate = clk_alpha_pll_stromer_determine_rate, 2607 .set_rate = clk_alpha_pll_stromer_plus_set_rate, 2608 }; 2609 EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops); 2610