1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/export.h> 9 #include <linux/clk-provider.h> 10 #include <linux/regmap.h> 11 #include <linux/delay.h> 12 13 #include "clk-alpha-pll.h" 14 #include "common.h" 15 16 #define PLL_MODE(p) ((p)->offset + 0x0) 17 # define PLL_OUTCTRL BIT(0) 18 # define PLL_BYPASSNL BIT(1) 19 # define PLL_RESET_N BIT(2) 20 # define PLL_OFFLINE_REQ BIT(7) 21 # define PLL_LOCK_COUNT_SHIFT 8 22 # define PLL_LOCK_COUNT_MASK 0x3f 23 # define PLL_BIAS_COUNT_SHIFT 14 24 # define PLL_BIAS_COUNT_MASK 0x3f 25 # define PLL_VOTE_FSM_ENA BIT(20) 26 # define PLL_FSM_ENA BIT(20) 27 # define PLL_VOTE_FSM_RESET BIT(21) 28 # define PLL_UPDATE BIT(22) 29 # define PLL_UPDATE_BYPASS BIT(23) 30 # define PLL_FSM_LEGACY_MODE BIT(24) 31 # define PLL_OFFLINE_ACK BIT(28) 32 # define ALPHA_PLL_ACK_LATCH BIT(29) 33 # define PLL_ACTIVE_FLAG BIT(30) 34 # define PLL_LOCK_DET BIT(31) 35 36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL]) 37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL]) 38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL]) 39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U]) 40 41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) 42 # define PLL_POST_DIV_SHIFT 8 43 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width ? (p)->width - 1 : 3, 0) 44 # define PLL_ALPHA_MSB BIT(15) 45 # define PLL_ALPHA_EN BIT(24) 46 # define PLL_ALPHA_MODE BIT(25) 47 # define PLL_VCO_SHIFT 20 48 # define PLL_VCO_MASK 0x3 49 50 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U]) 51 #define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1]) 52 53 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL]) 54 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U]) 55 #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1]) 56 #define PLL_CONFIG_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U2]) 57 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) 58 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) 59 #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1]) 60 #define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2]) 61 #define PLL_TEST_CTL_U3(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U3]) 62 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) 63 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE]) 64 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC]) 65 66 #define GET_PLL_TYPE(pll) (((pll)->regs - clk_alpha_pll_regs[0]) / PLL_OFF_MAX_REGS) 67 68 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 69 [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 70 [PLL_OFF_L_VAL] = 0x04, 71 [PLL_OFF_ALPHA_VAL] = 0x08, 72 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 73 [PLL_OFF_USER_CTL] = 0x10, 74 [PLL_OFF_USER_CTL_U] = 0x14, 75 [PLL_OFF_CONFIG_CTL] = 0x18, 76 [PLL_OFF_TEST_CTL] = 0x1c, 77 [PLL_OFF_TEST_CTL_U] = 0x20, 78 [PLL_OFF_STATUS] = 0x24, 79 }, 80 [CLK_ALPHA_PLL_TYPE_HUAYRA] = { 81 [PLL_OFF_L_VAL] = 0x04, 82 [PLL_OFF_ALPHA_VAL] = 0x08, 83 [PLL_OFF_USER_CTL] = 0x10, 84 [PLL_OFF_CONFIG_CTL] = 0x14, 85 [PLL_OFF_CONFIG_CTL_U] = 0x18, 86 [PLL_OFF_TEST_CTL] = 0x1c, 87 [PLL_OFF_TEST_CTL_U] = 0x20, 88 [PLL_OFF_STATUS] = 0x24, 89 }, 90 [CLK_ALPHA_PLL_TYPE_HUAYRA_APSS] = { 91 [PLL_OFF_L_VAL] = 0x08, 92 [PLL_OFF_ALPHA_VAL] = 0x10, 93 [PLL_OFF_USER_CTL] = 0x18, 94 [PLL_OFF_CONFIG_CTL] = 0x20, 95 [PLL_OFF_CONFIG_CTL_U] = 0x24, 96 [PLL_OFF_STATUS] = 0x28, 97 [PLL_OFF_TEST_CTL] = 0x30, 98 [PLL_OFF_TEST_CTL_U] = 0x34, 99 }, 100 [CLK_ALPHA_PLL_TYPE_HUAYRA_2290] = { 101 [PLL_OFF_L_VAL] = 0x04, 102 [PLL_OFF_ALPHA_VAL] = 0x08, 103 [PLL_OFF_USER_CTL] = 0x0c, 104 [PLL_OFF_CONFIG_CTL] = 0x10, 105 [PLL_OFF_CONFIG_CTL_U] = 0x14, 106 [PLL_OFF_CONFIG_CTL_U1] = 0x18, 107 [PLL_OFF_TEST_CTL] = 0x1c, 108 [PLL_OFF_TEST_CTL_U] = 0x20, 109 [PLL_OFF_TEST_CTL_U1] = 0x24, 110 [PLL_OFF_OPMODE] = 0x28, 111 [PLL_OFF_STATUS] = 0x38, 112 }, 113 [CLK_ALPHA_PLL_TYPE_BRAMMO] = { 114 [PLL_OFF_L_VAL] = 0x04, 115 [PLL_OFF_ALPHA_VAL] = 0x08, 116 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 117 [PLL_OFF_USER_CTL] = 0x10, 118 [PLL_OFF_CONFIG_CTL] = 0x18, 119 [PLL_OFF_TEST_CTL] = 0x1c, 120 [PLL_OFF_STATUS] = 0x24, 121 }, 122 [CLK_ALPHA_PLL_TYPE_FABIA] = { 123 [PLL_OFF_L_VAL] = 0x04, 124 [PLL_OFF_USER_CTL] = 0x0c, 125 [PLL_OFF_USER_CTL_U] = 0x10, 126 [PLL_OFF_CONFIG_CTL] = 0x14, 127 [PLL_OFF_CONFIG_CTL_U] = 0x18, 128 [PLL_OFF_TEST_CTL] = 0x1c, 129 [PLL_OFF_TEST_CTL_U] = 0x20, 130 [PLL_OFF_STATUS] = 0x24, 131 [PLL_OFF_OPMODE] = 0x2c, 132 [PLL_OFF_FRAC] = 0x38, 133 }, 134 [CLK_ALPHA_PLL_TYPE_TRION] = { 135 [PLL_OFF_L_VAL] = 0x04, 136 [PLL_OFF_CAL_L_VAL] = 0x08, 137 [PLL_OFF_USER_CTL] = 0x0c, 138 [PLL_OFF_USER_CTL_U] = 0x10, 139 [PLL_OFF_USER_CTL_U1] = 0x14, 140 [PLL_OFF_CONFIG_CTL] = 0x18, 141 [PLL_OFF_CONFIG_CTL_U] = 0x1c, 142 [PLL_OFF_CONFIG_CTL_U1] = 0x20, 143 [PLL_OFF_TEST_CTL] = 0x24, 144 [PLL_OFF_TEST_CTL_U] = 0x28, 145 [PLL_OFF_TEST_CTL_U1] = 0x2c, 146 [PLL_OFF_STATUS] = 0x30, 147 [PLL_OFF_OPMODE] = 0x38, 148 [PLL_OFF_ALPHA_VAL] = 0x40, 149 }, 150 [CLK_ALPHA_PLL_TYPE_AGERA] = { 151 [PLL_OFF_L_VAL] = 0x04, 152 [PLL_OFF_ALPHA_VAL] = 0x08, 153 [PLL_OFF_USER_CTL] = 0x0c, 154 [PLL_OFF_CONFIG_CTL] = 0x10, 155 [PLL_OFF_CONFIG_CTL_U] = 0x14, 156 [PLL_OFF_TEST_CTL] = 0x18, 157 [PLL_OFF_TEST_CTL_U] = 0x1c, 158 [PLL_OFF_STATUS] = 0x2c, 159 }, 160 [CLK_ALPHA_PLL_TYPE_ZONDA] = { 161 [PLL_OFF_L_VAL] = 0x04, 162 [PLL_OFF_ALPHA_VAL] = 0x08, 163 [PLL_OFF_USER_CTL] = 0x0c, 164 [PLL_OFF_CONFIG_CTL] = 0x10, 165 [PLL_OFF_CONFIG_CTL_U] = 0x14, 166 [PLL_OFF_CONFIG_CTL_U1] = 0x18, 167 [PLL_OFF_TEST_CTL] = 0x1c, 168 [PLL_OFF_TEST_CTL_U] = 0x20, 169 [PLL_OFF_TEST_CTL_U1] = 0x24, 170 [PLL_OFF_OPMODE] = 0x28, 171 [PLL_OFF_STATUS] = 0x38, 172 }, 173 [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = { 174 [PLL_OFF_OPMODE] = 0x04, 175 [PLL_OFF_STATUS] = 0x0c, 176 [PLL_OFF_L_VAL] = 0x10, 177 [PLL_OFF_ALPHA_VAL] = 0x14, 178 [PLL_OFF_USER_CTL] = 0x18, 179 [PLL_OFF_USER_CTL_U] = 0x1c, 180 [PLL_OFF_CONFIG_CTL] = 0x20, 181 [PLL_OFF_CONFIG_CTL_U] = 0x24, 182 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 183 [PLL_OFF_TEST_CTL] = 0x2c, 184 [PLL_OFF_TEST_CTL_U] = 0x30, 185 [PLL_OFF_TEST_CTL_U1] = 0x34, 186 }, 187 [CLK_ALPHA_PLL_TYPE_LUCID_OLE] = { 188 [PLL_OFF_OPMODE] = 0x04, 189 [PLL_OFF_STATE] = 0x08, 190 [PLL_OFF_STATUS] = 0x0c, 191 [PLL_OFF_L_VAL] = 0x10, 192 [PLL_OFF_ALPHA_VAL] = 0x14, 193 [PLL_OFF_USER_CTL] = 0x18, 194 [PLL_OFF_USER_CTL_U] = 0x1c, 195 [PLL_OFF_CONFIG_CTL] = 0x20, 196 [PLL_OFF_CONFIG_CTL_U] = 0x24, 197 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 198 [PLL_OFF_TEST_CTL] = 0x2c, 199 [PLL_OFF_TEST_CTL_U] = 0x30, 200 [PLL_OFF_TEST_CTL_U1] = 0x34, 201 [PLL_OFF_TEST_CTL_U2] = 0x38, 202 }, 203 [CLK_ALPHA_PLL_TYPE_PONGO_ELU] = { 204 [PLL_OFF_OPMODE] = 0x04, 205 [PLL_OFF_STATE] = 0x08, 206 [PLL_OFF_STATUS] = 0x0c, 207 [PLL_OFF_L_VAL] = 0x10, 208 [PLL_OFF_USER_CTL] = 0x14, 209 [PLL_OFF_USER_CTL_U] = 0x18, 210 [PLL_OFF_CONFIG_CTL] = 0x1c, 211 [PLL_OFF_CONFIG_CTL_U] = 0x20, 212 [PLL_OFF_CONFIG_CTL_U1] = 0x24, 213 [PLL_OFF_CONFIG_CTL_U2] = 0x28, 214 [PLL_OFF_TEST_CTL] = 0x2c, 215 [PLL_OFF_TEST_CTL_U] = 0x30, 216 [PLL_OFF_TEST_CTL_U1] = 0x34, 217 [PLL_OFF_TEST_CTL_U2] = 0x38, 218 [PLL_OFF_TEST_CTL_U3] = 0x3c, 219 }, 220 [CLK_ALPHA_PLL_TYPE_TAYCAN_ELU] = { 221 [PLL_OFF_OPMODE] = 0x04, 222 [PLL_OFF_STATE] = 0x08, 223 [PLL_OFF_STATUS] = 0x0c, 224 [PLL_OFF_L_VAL] = 0x10, 225 [PLL_OFF_ALPHA_VAL] = 0x14, 226 [PLL_OFF_USER_CTL] = 0x18, 227 [PLL_OFF_USER_CTL_U] = 0x1c, 228 [PLL_OFF_CONFIG_CTL] = 0x20, 229 [PLL_OFF_CONFIG_CTL_U] = 0x24, 230 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 231 [PLL_OFF_TEST_CTL] = 0x2c, 232 [PLL_OFF_TEST_CTL_U] = 0x30, 233 }, 234 [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = { 235 [PLL_OFF_OPMODE] = 0x04, 236 [PLL_OFF_STATUS] = 0x0c, 237 [PLL_OFF_L_VAL] = 0x10, 238 [PLL_OFF_USER_CTL] = 0x14, 239 [PLL_OFF_USER_CTL_U] = 0x18, 240 [PLL_OFF_CONFIG_CTL] = 0x1c, 241 [PLL_OFF_CONFIG_CTL_U] = 0x20, 242 [PLL_OFF_CONFIG_CTL_U1] = 0x24, 243 [PLL_OFF_TEST_CTL] = 0x28, 244 [PLL_OFF_TEST_CTL_U] = 0x2c, 245 }, 246 [CLK_ALPHA_PLL_TYPE_RIVIAN_ELU] = { 247 [PLL_OFF_OPMODE] = 0x04, 248 [PLL_OFF_STATUS] = 0x0c, 249 [PLL_OFF_L_VAL] = 0x10, 250 [PLL_OFF_USER_CTL] = 0x14, 251 [PLL_OFF_USER_CTL_U] = 0x18, 252 [PLL_OFF_CONFIG_CTL] = 0x1c, 253 [PLL_OFF_CONFIG_CTL_U] = 0x20, 254 [PLL_OFF_CONFIG_CTL_U1] = 0x24, 255 [PLL_OFF_CONFIG_CTL_U2] = 0x28, 256 [PLL_OFF_TEST_CTL] = 0x2c, 257 [PLL_OFF_TEST_CTL_U] = 0x30, 258 }, 259 [CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = { 260 [PLL_OFF_L_VAL] = 0x04, 261 [PLL_OFF_ALPHA_VAL] = 0x08, 262 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 263 [PLL_OFF_TEST_CTL] = 0x10, 264 [PLL_OFF_TEST_CTL_U] = 0x14, 265 [PLL_OFF_USER_CTL] = 0x18, 266 [PLL_OFF_USER_CTL_U] = 0x1c, 267 [PLL_OFF_CONFIG_CTL] = 0x20, 268 [PLL_OFF_STATUS] = 0x24, 269 }, 270 [CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = { 271 [PLL_OFF_L_VAL] = 0x04, 272 [PLL_OFF_ALPHA_VAL] = 0x08, 273 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 274 [PLL_OFF_TEST_CTL] = 0x10, 275 [PLL_OFF_TEST_CTL_U] = 0x14, 276 [PLL_OFF_USER_CTL] = 0x18, 277 [PLL_OFF_CONFIG_CTL] = 0x1C, 278 [PLL_OFF_STATUS] = 0x20, 279 }, 280 [CLK_ALPHA_PLL_TYPE_STROMER] = { 281 [PLL_OFF_L_VAL] = 0x08, 282 [PLL_OFF_ALPHA_VAL] = 0x10, 283 [PLL_OFF_ALPHA_VAL_U] = 0x14, 284 [PLL_OFF_USER_CTL] = 0x18, 285 [PLL_OFF_USER_CTL_U] = 0x1c, 286 [PLL_OFF_CONFIG_CTL] = 0x20, 287 [PLL_OFF_STATUS] = 0x28, 288 [PLL_OFF_TEST_CTL] = 0x30, 289 [PLL_OFF_TEST_CTL_U] = 0x34, 290 }, 291 [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = { 292 [PLL_OFF_L_VAL] = 0x04, 293 [PLL_OFF_USER_CTL] = 0x08, 294 [PLL_OFF_USER_CTL_U] = 0x0c, 295 [PLL_OFF_CONFIG_CTL] = 0x10, 296 [PLL_OFF_TEST_CTL] = 0x14, 297 [PLL_OFF_TEST_CTL_U] = 0x18, 298 [PLL_OFF_STATUS] = 0x1c, 299 [PLL_OFF_ALPHA_VAL] = 0x24, 300 [PLL_OFF_ALPHA_VAL_U] = 0x28, 301 }, 302 [CLK_ALPHA_PLL_TYPE_ZONDA_OLE] = { 303 [PLL_OFF_L_VAL] = 0x04, 304 [PLL_OFF_ALPHA_VAL] = 0x08, 305 [PLL_OFF_USER_CTL] = 0x0c, 306 [PLL_OFF_USER_CTL_U] = 0x10, 307 [PLL_OFF_CONFIG_CTL] = 0x14, 308 [PLL_OFF_CONFIG_CTL_U] = 0x18, 309 [PLL_OFF_CONFIG_CTL_U1] = 0x1c, 310 [PLL_OFF_CONFIG_CTL_U2] = 0x20, 311 [PLL_OFF_TEST_CTL] = 0x24, 312 [PLL_OFF_TEST_CTL_U] = 0x28, 313 [PLL_OFF_TEST_CTL_U1] = 0x2c, 314 [PLL_OFF_OPMODE] = 0x30, 315 [PLL_OFF_STATUS] = 0x3c, 316 }, 317 [CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] = { 318 [PLL_OFF_L_VAL] = 0x04, 319 [PLL_OFF_ALPHA_VAL] = 0x08, 320 [PLL_OFF_TEST_CTL] = 0x0c, 321 [PLL_OFF_TEST_CTL_U] = 0x10, 322 [PLL_OFF_USER_CTL] = 0x14, 323 [PLL_OFF_CONFIG_CTL] = 0x18, 324 [PLL_OFF_CONFIG_CTL_U] = 0x1c, 325 [PLL_OFF_STATUS] = 0x20, 326 }, 327 328 }; 329 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 330 331 /* 332 * Even though 40 bits are present, use only 32 for ease of calculation. 333 */ 334 #define ALPHA_REG_BITWIDTH 40 335 #define ALPHA_REG_16BIT_WIDTH 16 336 #define ALPHA_BITWIDTH 32U 337 #define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH) 338 339 #define ALPHA_PLL_STATUS_REG_SHIFT 8 340 341 #define PLL_HUAYRA_M_WIDTH 8 342 #define PLL_HUAYRA_M_SHIFT 8 343 #define PLL_HUAYRA_M_MASK 0xff 344 #define PLL_HUAYRA_N_SHIFT 0 345 #define PLL_HUAYRA_N_MASK 0xff 346 #define PLL_HUAYRA_ALPHA_WIDTH 16 347 348 #define PLL_STANDBY 0x0 349 #define PLL_RUN 0x1 350 #define PLL_OUT_MASK 0x7 351 #define PLL_RATE_MARGIN 500 352 353 /* TRION PLL specific settings and offsets */ 354 #define TRION_PLL_CAL_VAL 0x44 355 #define TRION_PCAL_DONE BIT(26) 356 357 /* LUCID PLL specific settings and offsets */ 358 #define LUCID_PCAL_DONE BIT(27) 359 360 /* LUCID 5LPE PLL specific settings and offsets */ 361 #define LUCID_5LPE_PCAL_DONE BIT(11) 362 #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13) 363 #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14) 364 #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) 365 366 /* LUCID EVO PLL specific settings and offsets */ 367 #define LUCID_EVO_PCAL_NOT_DONE BIT(8) 368 #define LUCID_EVO_ENABLE_VOTE_RUN BIT(25) 369 #define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0) 370 #define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16 371 #define LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT 24 372 373 /* PONGO ELU PLL specific setting and offsets */ 374 #define PONGO_PLL_OUT_MASK GENMASK(1, 0) 375 #define PONGO_PLL_L_VAL_MASK GENMASK(11, 0) 376 #define PONGO_XO_PRESENT BIT(10) 377 #define PONGO_CLOCK_SELECT BIT(12) 378 379 /* ZONDA PLL specific */ 380 #define ZONDA_PLL_OUT_MASK 0xf 381 #define ZONDA_STAY_IN_CFA BIT(16) 382 #define ZONDA_PLL_FREQ_LOCK_DET BIT(29) 383 384 #define pll_alpha_width(p) \ 385 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ 386 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) 387 388 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4) 389 390 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ 391 struct clk_alpha_pll, clkr) 392 393 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \ 394 struct clk_alpha_pll_postdiv, clkr) 395 396 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, 397 const char *action) 398 { 399 u32 val; 400 int count; 401 int ret; 402 const char *name = clk_hw_get_name(&pll->clkr.hw); 403 404 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 405 if (ret) 406 return ret; 407 408 /* Pongo PLLs using a 32KHz reference can take upwards of 1500us to lock. */ 409 for (count = 1500; count > 0; count--) { 410 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 411 if (ret) 412 return ret; 413 if (inverse && !(val & mask)) 414 return 0; 415 else if ((val & mask) == mask) 416 return 0; 417 418 udelay(1); 419 } 420 421 WARN(1, "%s failed to %s!\n", name, action); 422 return -ETIMEDOUT; 423 } 424 425 #define wait_for_pll_enable_active(pll) \ 426 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable") 427 428 #define wait_for_pll_enable_lock(pll) \ 429 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable") 430 431 #define wait_for_zonda_pll_freq_lock(pll) \ 432 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable") 433 434 #define wait_for_pll_disable(pll) \ 435 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable") 436 437 #define wait_for_pll_offline(pll) \ 438 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline") 439 440 #define wait_for_pll_update(pll) \ 441 wait_for_pll(pll, PLL_UPDATE, 1, "update") 442 443 #define wait_for_pll_update_ack_set(pll) \ 444 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set") 445 446 #define wait_for_pll_update_ack_clear(pll) \ 447 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear") 448 449 static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg, 450 unsigned int val) 451 { 452 if (val) 453 regmap_write(regmap, reg, val); 454 } 455 456 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 457 const struct alpha_pll_config *config) 458 { 459 u32 val, mask; 460 461 regmap_write(regmap, PLL_L_VAL(pll), config->l); 462 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); 463 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 464 465 if (pll_has_64bit_config(pll)) 466 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), 467 config->config_ctl_hi_val); 468 469 if (pll_alpha_width(pll) > 32) 470 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); 471 472 val = config->main_output_mask; 473 val |= config->aux_output_mask; 474 val |= config->aux2_output_mask; 475 val |= config->early_output_mask; 476 val |= config->pre_div_val; 477 val |= config->post_div_val; 478 val |= config->vco_val; 479 val |= config->alpha_en_mask; 480 val |= config->alpha_mode_mask; 481 482 mask = config->main_output_mask; 483 mask |= config->aux_output_mask; 484 mask |= config->aux2_output_mask; 485 mask |= config->early_output_mask; 486 mask |= config->pre_div_mask; 487 mask |= config->post_div_mask; 488 mask |= config->vco_mask; 489 mask |= config->alpha_en_mask; 490 mask |= config->alpha_mode_mask; 491 492 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 493 494 if (config->test_ctl_mask) 495 regmap_update_bits(regmap, PLL_TEST_CTL(pll), 496 config->test_ctl_mask, 497 config->test_ctl_val); 498 else 499 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 500 config->test_ctl_val); 501 502 if (config->test_ctl_hi_mask) 503 regmap_update_bits(regmap, PLL_TEST_CTL_U(pll), 504 config->test_ctl_hi_mask, 505 config->test_ctl_hi_val); 506 else 507 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 508 config->test_ctl_hi_val); 509 510 if (pll->flags & SUPPORTS_FSM_MODE) 511 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); 512 } 513 EXPORT_SYMBOL_GPL(clk_alpha_pll_configure); 514 515 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) 516 { 517 int ret; 518 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 519 u32 val; 520 521 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 522 if (ret) 523 return ret; 524 525 val |= PLL_FSM_ENA; 526 527 if (pll->flags & SUPPORTS_OFFLINE_REQ) 528 val &= ~PLL_OFFLINE_REQ; 529 530 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); 531 if (ret) 532 return ret; 533 534 /* Make sure enable request goes through before waiting for update */ 535 mb(); 536 537 return wait_for_pll_enable_active(pll); 538 } 539 540 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw) 541 { 542 int ret; 543 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 544 u32 val; 545 546 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 547 if (ret) 548 return; 549 550 if (pll->flags & SUPPORTS_OFFLINE_REQ) { 551 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 552 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ); 553 if (ret) 554 return; 555 556 ret = wait_for_pll_offline(pll); 557 if (ret) 558 return; 559 } 560 561 /* Disable hwfsm */ 562 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 563 PLL_FSM_ENA, 0); 564 if (ret) 565 return; 566 567 wait_for_pll_disable(pll); 568 } 569 570 static int pll_is_enabled(struct clk_hw *hw, u32 mask) 571 { 572 int ret; 573 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 574 u32 val; 575 576 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 577 if (ret) 578 return ret; 579 580 return !!(val & mask); 581 } 582 583 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw) 584 { 585 return pll_is_enabled(hw, PLL_ACTIVE_FLAG); 586 } 587 588 static int clk_alpha_pll_is_enabled(struct clk_hw *hw) 589 { 590 return pll_is_enabled(hw, PLL_LOCK_DET); 591 } 592 593 static int clk_alpha_pll_enable(struct clk_hw *hw) 594 { 595 int ret; 596 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 597 u32 val, mask; 598 599 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; 600 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 601 if (ret) 602 return ret; 603 604 /* If in FSM mode, just vote for it */ 605 if (val & PLL_VOTE_FSM_ENA) { 606 ret = clk_enable_regmap(hw); 607 if (ret) 608 return ret; 609 return wait_for_pll_enable_active(pll); 610 } 611 612 /* Skip if already enabled */ 613 if ((val & mask) == mask) 614 return 0; 615 616 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 617 PLL_BYPASSNL, PLL_BYPASSNL); 618 if (ret) 619 return ret; 620 621 /* 622 * H/W requires a 5us delay between disabling the bypass and 623 * de-asserting the reset. 624 */ 625 mb(); 626 udelay(5); 627 628 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 629 PLL_RESET_N, PLL_RESET_N); 630 if (ret) 631 return ret; 632 633 ret = wait_for_pll_enable_lock(pll); 634 if (ret) 635 return ret; 636 637 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 638 PLL_OUTCTRL, PLL_OUTCTRL); 639 640 /* Ensure that the write above goes through before returning. */ 641 mb(); 642 return ret; 643 } 644 645 static void clk_alpha_pll_disable(struct clk_hw *hw) 646 { 647 int ret; 648 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 649 u32 val, mask; 650 651 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 652 if (ret) 653 return; 654 655 /* If in FSM mode, just unvote it */ 656 if (val & PLL_VOTE_FSM_ENA) { 657 clk_disable_regmap(hw); 658 return; 659 } 660 661 mask = PLL_OUTCTRL; 662 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 663 664 /* Delay of 2 output clock ticks required until output is disabled */ 665 mb(); 666 udelay(1); 667 668 mask = PLL_RESET_N | PLL_BYPASSNL; 669 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 670 } 671 672 static unsigned long 673 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width) 674 { 675 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width)); 676 } 677 678 static unsigned long 679 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a, 680 u32 alpha_width) 681 { 682 u64 remainder; 683 u64 quotient; 684 685 quotient = rate; 686 remainder = do_div(quotient, prate); 687 *l = quotient; 688 689 if (!remainder) { 690 *a = 0; 691 return rate; 692 } 693 694 /* Upper ALPHA_BITWIDTH bits of Alpha */ 695 quotient = remainder << ALPHA_SHIFT(alpha_width); 696 697 remainder = do_div(quotient, prate); 698 699 if (remainder) 700 quotient++; 701 702 *a = quotient; 703 return alpha_pll_calc_rate(prate, *l, *a, alpha_width); 704 } 705 706 static const struct pll_vco * 707 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) 708 { 709 const struct pll_vco *v = pll->vco_table; 710 const struct pll_vco *end = v + pll->num_vco; 711 712 for (; v < end; v++) 713 if (rate >= v->min_freq && rate <= v->max_freq) 714 return v; 715 716 return NULL; 717 } 718 719 static unsigned long 720 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 721 { 722 u32 l, low, high, ctl; 723 u64 a = 0, prate = parent_rate; 724 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 725 u32 alpha_width = pll_alpha_width(pll); 726 727 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) 728 return 0; 729 730 if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl)) 731 return 0; 732 733 if (ctl & PLL_ALPHA_EN) { 734 if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low)) 735 return 0; 736 if (alpha_width > 32) { 737 if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 738 &high)) 739 return 0; 740 a = (u64)high << 32 | low; 741 } else { 742 a = low & GENMASK(alpha_width - 1, 0); 743 } 744 745 if (alpha_width > ALPHA_BITWIDTH) 746 a >>= alpha_width - ALPHA_BITWIDTH; 747 } 748 749 return alpha_pll_calc_rate(prate, l, a, alpha_width); 750 } 751 752 753 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) 754 { 755 int ret; 756 u32 mode; 757 758 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); 759 760 /* Latch the input to the PLL */ 761 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 762 PLL_UPDATE); 763 764 /* Wait for 2 reference cycle before checking ACK bit */ 765 udelay(1); 766 767 /* 768 * PLL will latch the new L, Alpha and freq control word. 769 * PLL will respond by raising PLL_ACK_LATCH output when new programming 770 * has been latched in and PLL is being updated. When 771 * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared 772 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. 773 */ 774 if (mode & PLL_UPDATE_BYPASS) { 775 ret = wait_for_pll_update_ack_set(pll); 776 if (ret) 777 return ret; 778 779 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); 780 } else { 781 ret = wait_for_pll_update(pll); 782 if (ret) 783 return ret; 784 } 785 786 ret = wait_for_pll_update_ack_clear(pll); 787 if (ret) 788 return ret; 789 790 /* Wait for PLL output to stabilize */ 791 udelay(10); 792 793 return 0; 794 } 795 796 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, 797 int (*is_enabled)(struct clk_hw *)) 798 { 799 if (!is_enabled(&pll->clkr.hw) || 800 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) 801 return 0; 802 803 return __clk_alpha_pll_update_latch(pll); 804 } 805 806 static void clk_alpha_pll_update_configs(struct clk_alpha_pll *pll, const struct pll_vco *vco, 807 u32 l, u64 alpha, u32 alpha_width, bool alpha_en) 808 { 809 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 810 811 if (alpha_width > ALPHA_BITWIDTH) 812 alpha <<= alpha_width - ALPHA_BITWIDTH; 813 814 if (alpha_width > 32) 815 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), upper_32_bits(alpha)); 816 817 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), lower_32_bits(alpha)); 818 819 if (vco) { 820 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 821 PLL_VCO_MASK << PLL_VCO_SHIFT, 822 vco->val << PLL_VCO_SHIFT); 823 } 824 825 if (alpha_en) 826 regmap_set_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_ALPHA_EN); 827 } 828 829 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 830 unsigned long prate, 831 int (*is_enabled)(struct clk_hw *)) 832 { 833 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 834 const struct pll_vco *vco; 835 u32 l, alpha_width = pll_alpha_width(pll); 836 u64 a; 837 838 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 839 vco = alpha_pll_find_vco(pll, rate); 840 if (pll->vco_table && !vco) { 841 pr_err("%s: alpha pll not in a valid vco range\n", 842 clk_hw_get_name(hw)); 843 return -EINVAL; 844 } 845 846 clk_alpha_pll_update_configs(pll, vco, l, a, alpha_width, true); 847 848 return clk_alpha_pll_update_latch(pll, is_enabled); 849 } 850 851 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 852 unsigned long prate) 853 { 854 return __clk_alpha_pll_set_rate(hw, rate, prate, 855 clk_alpha_pll_is_enabled); 856 } 857 858 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate, 859 unsigned long prate) 860 { 861 return __clk_alpha_pll_set_rate(hw, rate, prate, 862 clk_alpha_pll_hwfsm_is_enabled); 863 } 864 865 static int clk_alpha_pll_determine_rate(struct clk_hw *hw, 866 struct clk_rate_request *req) 867 { 868 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 869 u32 l, alpha_width = pll_alpha_width(pll); 870 u64 a; 871 unsigned long min_freq, max_freq; 872 873 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, &l, 874 &a, alpha_width); 875 if (!pll->vco_table || alpha_pll_find_vco(pll, req->rate)) 876 return 0; 877 878 min_freq = pll->vco_table[0].min_freq; 879 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 880 881 req->rate = clamp(req->rate, min_freq, max_freq); 882 883 return 0; 884 } 885 886 void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 887 const struct alpha_pll_config *config) 888 { 889 u32 val; 890 891 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 892 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 893 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 894 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 895 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 896 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 897 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 898 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 899 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 900 901 /* Set PLL_BYPASSNL */ 902 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); 903 regmap_read(regmap, PLL_MODE(pll), &val); 904 905 /* Wait 5 us between setting BYPASS and deasserting reset */ 906 udelay(5); 907 908 /* Take PLL out from reset state */ 909 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 910 regmap_read(regmap, PLL_MODE(pll), &val); 911 912 /* Wait 50us for PLL_LOCK_DET bit to go high */ 913 usleep_range(50, 55); 914 915 /* Enable PLL output */ 916 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 917 } 918 EXPORT_SYMBOL_GPL(clk_huayra_2290_pll_configure); 919 920 static unsigned long 921 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a) 922 { 923 /* 924 * a contains 16 bit alpha_val in two’s complement number in the range 925 * of [-0.5, 0.5). 926 */ 927 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 928 l -= 1; 929 930 return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH); 931 } 932 933 static unsigned long 934 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate, 935 u32 *l, u32 *a) 936 { 937 u64 remainder; 938 u64 quotient; 939 940 quotient = rate; 941 remainder = do_div(quotient, prate); 942 *l = quotient; 943 944 if (!remainder) { 945 *a = 0; 946 return rate; 947 } 948 949 quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH; 950 remainder = do_div(quotient, prate); 951 952 if (remainder) 953 quotient++; 954 955 /* 956 * alpha_val should be in two’s complement number in the range 957 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value 958 * since alpha value will be subtracted in this case. 959 */ 960 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 961 *l += 1; 962 963 *a = quotient; 964 return alpha_huayra_pll_calc_rate(prate, *l, *a); 965 } 966 967 static unsigned long 968 alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 969 { 970 u64 rate = parent_rate, tmp; 971 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 972 u32 l, alpha = 0, ctl, alpha_m, alpha_n; 973 974 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) 975 return 0; 976 977 if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl)) 978 return 0; 979 980 if (ctl & PLL_ALPHA_EN) { 981 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); 982 /* 983 * Depending upon alpha_mode, it can be treated as M/N value or 984 * as a two’s complement number. When alpha_mode=1, 985 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N 986 * 987 * Fout=FIN*(L+(M/N)) 988 * 989 * M is a signed number (-128 to 127) and N is unsigned 990 * (0 to 255). M/N has to be within +/-0.5. 991 * 992 * When alpha_mode=0, it is a two’s complement number in the 993 * range [-0.5, 0.5). 994 * 995 * Fout=FIN*(L+(alpha_val)/2^16) 996 * 997 * where alpha_val is two’s complement number. 998 */ 999 if (!(ctl & PLL_ALPHA_MODE)) 1000 return alpha_huayra_pll_calc_rate(rate, l, alpha); 1001 1002 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK; 1003 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK; 1004 1005 rate *= l; 1006 tmp = parent_rate; 1007 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) { 1008 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m; 1009 tmp *= alpha_m; 1010 do_div(tmp, alpha_n); 1011 rate -= tmp; 1012 } else { 1013 tmp *= alpha_m; 1014 do_div(tmp, alpha_n); 1015 rate += tmp; 1016 } 1017 1018 return rate; 1019 } 1020 1021 return alpha_huayra_pll_calc_rate(rate, l, alpha); 1022 } 1023 1024 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate, 1025 unsigned long prate) 1026 { 1027 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1028 u32 l, a, ctl, cur_alpha = 0; 1029 1030 rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a); 1031 1032 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 1033 1034 if (ctl & PLL_ALPHA_EN) 1035 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); 1036 1037 /* 1038 * Huayra PLL supports PLL dynamic programming. User can change L_VAL, 1039 * without having to go through the power on sequence. 1040 */ 1041 if (clk_alpha_pll_is_enabled(hw)) { 1042 if (cur_alpha != a) { 1043 pr_err("%s: clock needs to be gated\n", 1044 clk_hw_get_name(hw)); 1045 return -EBUSY; 1046 } 1047 1048 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1049 /* Ensure that the write above goes to detect L val change. */ 1050 mb(); 1051 return wait_for_pll_enable_lock(pll); 1052 } 1053 1054 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1055 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1056 1057 if (a == 0) 1058 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1059 PLL_ALPHA_EN, 0x0); 1060 else 1061 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1062 PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN); 1063 1064 return 0; 1065 } 1066 1067 static int alpha_pll_huayra_determine_rate(struct clk_hw *hw, 1068 struct clk_rate_request *req) 1069 { 1070 u32 l, a; 1071 1072 req->rate = alpha_huayra_pll_round_rate(req->rate, 1073 req->best_parent_rate, &l, &a); 1074 1075 return 0; 1076 } 1077 1078 static int trion_pll_is_enabled(struct clk_alpha_pll *pll, 1079 struct regmap *regmap) 1080 { 1081 u32 mode_val, opmode_val; 1082 int ret; 1083 1084 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); 1085 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 1086 if (ret) 1087 return 0; 1088 1089 return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL)); 1090 } 1091 1092 static int clk_trion_pll_is_enabled(struct clk_hw *hw) 1093 { 1094 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1095 1096 return trion_pll_is_enabled(pll, pll->clkr.regmap); 1097 } 1098 1099 static int clk_trion_pll_enable(struct clk_hw *hw) 1100 { 1101 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1102 struct regmap *regmap = pll->clkr.regmap; 1103 u32 val; 1104 int ret; 1105 1106 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1107 if (ret) 1108 return ret; 1109 1110 /* If in FSM mode, just vote for it */ 1111 if (val & PLL_VOTE_FSM_ENA) { 1112 ret = clk_enable_regmap(hw); 1113 if (ret) 1114 return ret; 1115 return wait_for_pll_enable_active(pll); 1116 } 1117 1118 /* Set operation mode to RUN */ 1119 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 1120 1121 ret = wait_for_pll_enable_lock(pll); 1122 if (ret) 1123 return ret; 1124 1125 /* Enable the PLL outputs */ 1126 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1127 PLL_OUT_MASK, PLL_OUT_MASK); 1128 if (ret) 1129 return ret; 1130 1131 /* Enable the global PLL outputs */ 1132 return regmap_update_bits(regmap, PLL_MODE(pll), 1133 PLL_OUTCTRL, PLL_OUTCTRL); 1134 } 1135 1136 static void clk_trion_pll_disable(struct clk_hw *hw) 1137 { 1138 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1139 struct regmap *regmap = pll->clkr.regmap; 1140 u32 val; 1141 int ret; 1142 1143 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1144 if (ret) 1145 return; 1146 1147 /* If in FSM mode, just unvote it */ 1148 if (val & PLL_VOTE_FSM_ENA) { 1149 clk_disable_regmap(hw); 1150 return; 1151 } 1152 1153 /* Disable the global PLL output */ 1154 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1155 if (ret) 1156 return; 1157 1158 /* Disable the PLL outputs */ 1159 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1160 PLL_OUT_MASK, 0); 1161 if (ret) 1162 return; 1163 1164 /* Place the PLL mode in STANDBY */ 1165 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1166 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1167 } 1168 1169 static unsigned long 1170 clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1171 { 1172 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1173 u32 l, frac, alpha_width = pll_alpha_width(pll); 1174 1175 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) 1176 return 0; 1177 1178 if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac)) 1179 return 0; 1180 1181 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 1182 } 1183 1184 const struct clk_ops clk_alpha_pll_fixed_ops = { 1185 .enable = clk_alpha_pll_enable, 1186 .disable = clk_alpha_pll_disable, 1187 .is_enabled = clk_alpha_pll_is_enabled, 1188 .recalc_rate = clk_alpha_pll_recalc_rate, 1189 }; 1190 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops); 1191 1192 const struct clk_ops clk_alpha_pll_ops = { 1193 .enable = clk_alpha_pll_enable, 1194 .disable = clk_alpha_pll_disable, 1195 .is_enabled = clk_alpha_pll_is_enabled, 1196 .recalc_rate = clk_alpha_pll_recalc_rate, 1197 .determine_rate = clk_alpha_pll_determine_rate, 1198 .set_rate = clk_alpha_pll_set_rate, 1199 }; 1200 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops); 1201 1202 const struct clk_ops clk_alpha_pll_huayra_ops = { 1203 .enable = clk_alpha_pll_enable, 1204 .disable = clk_alpha_pll_disable, 1205 .is_enabled = clk_alpha_pll_is_enabled, 1206 .recalc_rate = alpha_pll_huayra_recalc_rate, 1207 .determine_rate = alpha_pll_huayra_determine_rate, 1208 .set_rate = alpha_pll_huayra_set_rate, 1209 }; 1210 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops); 1211 1212 const struct clk_ops clk_alpha_pll_hwfsm_ops = { 1213 .enable = clk_alpha_pll_hwfsm_enable, 1214 .disable = clk_alpha_pll_hwfsm_disable, 1215 .is_enabled = clk_alpha_pll_hwfsm_is_enabled, 1216 .recalc_rate = clk_alpha_pll_recalc_rate, 1217 .determine_rate = clk_alpha_pll_determine_rate, 1218 .set_rate = clk_alpha_pll_hwfsm_set_rate, 1219 }; 1220 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); 1221 1222 const struct clk_ops clk_alpha_pll_fixed_trion_ops = { 1223 .enable = clk_trion_pll_enable, 1224 .disable = clk_trion_pll_disable, 1225 .is_enabled = clk_trion_pll_is_enabled, 1226 .recalc_rate = clk_trion_pll_recalc_rate, 1227 .determine_rate = clk_alpha_pll_determine_rate, 1228 }; 1229 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops); 1230 1231 static unsigned long 1232 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1233 { 1234 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1235 u32 ctl; 1236 1237 if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl)) 1238 return 0; 1239 1240 ctl >>= PLL_POST_DIV_SHIFT; 1241 ctl &= PLL_POST_DIV_MASK(pll); 1242 1243 return parent_rate >> fls(ctl); 1244 } 1245 1246 static const struct clk_div_table clk_alpha_div_table[] = { 1247 { 0x0, 1 }, 1248 { 0x1, 2 }, 1249 { 0x3, 4 }, 1250 { 0x7, 8 }, 1251 { 0xf, 16 }, 1252 { } 1253 }; 1254 1255 static const struct clk_div_table clk_alpha_2bit_div_table[] = { 1256 { 0x0, 1 }, 1257 { 0x1, 2 }, 1258 { 0x3, 4 }, 1259 { } 1260 }; 1261 1262 static int clk_alpha_pll_postdiv_determine_rate(struct clk_hw *hw, 1263 struct clk_rate_request *req) 1264 { 1265 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1266 const struct clk_div_table *table; 1267 1268 if (pll->width == 2) 1269 table = clk_alpha_2bit_div_table; 1270 else 1271 table = clk_alpha_div_table; 1272 1273 return divider_determine_rate(hw, req, table, pll->width, 1274 CLK_DIVIDER_POWER_OF_TWO); 1275 } 1276 1277 static int clk_alpha_pll_postdiv_ro_determine_rate(struct clk_hw *hw, 1278 struct clk_rate_request *req) 1279 { 1280 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1281 u32 ctl, div; 1282 1283 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 1284 1285 ctl >>= PLL_POST_DIV_SHIFT; 1286 ctl &= BIT(pll->width) - 1; 1287 div = 1 << fls(ctl); 1288 1289 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) 1290 req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), 1291 div * req->rate); 1292 1293 req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); 1294 1295 return 0; 1296 } 1297 1298 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1299 unsigned long parent_rate) 1300 { 1301 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1302 int div; 1303 1304 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ 1305 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1; 1306 1307 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1308 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 1309 div << PLL_POST_DIV_SHIFT); 1310 } 1311 1312 const struct clk_ops clk_alpha_pll_postdiv_ops = { 1313 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1314 .determine_rate = clk_alpha_pll_postdiv_determine_rate, 1315 .set_rate = clk_alpha_pll_postdiv_set_rate, 1316 }; 1317 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops); 1318 1319 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = { 1320 .determine_rate = clk_alpha_pll_postdiv_ro_determine_rate, 1321 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1322 }; 1323 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops); 1324 1325 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1326 const struct alpha_pll_config *config) 1327 { 1328 u32 val, mask; 1329 1330 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1331 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha); 1332 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1333 config->config_ctl_val); 1334 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1335 config->config_ctl_hi_val); 1336 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1337 config->user_ctl_val); 1338 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1339 config->user_ctl_hi_val); 1340 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1341 config->test_ctl_val); 1342 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1343 config->test_ctl_hi_val); 1344 1345 if (config->post_div_mask) { 1346 mask = config->post_div_mask; 1347 val = config->post_div_val; 1348 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 1349 } 1350 1351 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE) 1352 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE, 1353 PLL_FSM_LEGACY_MODE); 1354 1355 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1356 PLL_UPDATE_BYPASS); 1357 1358 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1359 } 1360 EXPORT_SYMBOL_GPL(clk_fabia_pll_configure); 1361 1362 static int alpha_pll_fabia_enable(struct clk_hw *hw) 1363 { 1364 int ret; 1365 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1366 u32 val, opmode_val; 1367 struct regmap *regmap = pll->clkr.regmap; 1368 1369 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1370 if (ret) 1371 return ret; 1372 1373 /* If in FSM mode, just vote for it */ 1374 if (val & PLL_VOTE_FSM_ENA) { 1375 ret = clk_enable_regmap(hw); 1376 if (ret) 1377 return ret; 1378 return wait_for_pll_enable_active(pll); 1379 } 1380 1381 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 1382 if (ret) 1383 return ret; 1384 1385 /* Skip If PLL is already running */ 1386 if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL)) 1387 return 0; 1388 1389 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1390 if (ret) 1391 return ret; 1392 1393 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1394 if (ret) 1395 return ret; 1396 1397 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 1398 PLL_RESET_N); 1399 if (ret) 1400 return ret; 1401 1402 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 1403 if (ret) 1404 return ret; 1405 1406 ret = wait_for_pll_enable_lock(pll); 1407 if (ret) 1408 return ret; 1409 1410 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1411 PLL_OUT_MASK, PLL_OUT_MASK); 1412 if (ret) 1413 return ret; 1414 1415 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 1416 PLL_OUTCTRL); 1417 } 1418 1419 static void alpha_pll_fabia_disable(struct clk_hw *hw) 1420 { 1421 int ret; 1422 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1423 u32 val; 1424 struct regmap *regmap = pll->clkr.regmap; 1425 1426 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1427 if (ret) 1428 return; 1429 1430 /* If in FSM mode, just unvote it */ 1431 if (val & PLL_FSM_ENA) { 1432 clk_disable_regmap(hw); 1433 return; 1434 } 1435 1436 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1437 if (ret) 1438 return; 1439 1440 /* Disable main outputs */ 1441 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 1442 if (ret) 1443 return; 1444 1445 /* Place the PLL in STANDBY */ 1446 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1447 } 1448 1449 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw, 1450 unsigned long parent_rate) 1451 { 1452 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1453 u32 l, frac, alpha_width = pll_alpha_width(pll); 1454 1455 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) 1456 return 0; 1457 1458 if (regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac)) 1459 return 0; 1460 1461 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 1462 } 1463 1464 /* 1465 * Due to limited number of bits for fractional rate programming, the 1466 * rounded up rate could be marginally higher than the requested rate. 1467 */ 1468 static int alpha_pll_check_rate_margin(struct clk_hw *hw, 1469 unsigned long rrate, unsigned long rate) 1470 { 1471 unsigned long rate_margin = rate + PLL_RATE_MARGIN; 1472 1473 if (rrate > rate_margin || rrate < rate) { 1474 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n", 1475 clk_hw_get_name(hw), rrate, rate, rate_margin); 1476 return -EINVAL; 1477 } 1478 1479 return 0; 1480 } 1481 1482 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate, 1483 unsigned long prate) 1484 { 1485 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1486 u32 l, alpha_width = pll_alpha_width(pll); 1487 unsigned long rrate; 1488 int ret; 1489 u64 a; 1490 1491 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1492 1493 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1494 if (ret < 0) 1495 return ret; 1496 1497 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1498 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); 1499 1500 return __clk_alpha_pll_update_latch(pll); 1501 } 1502 1503 static int alpha_pll_fabia_prepare(struct clk_hw *hw) 1504 { 1505 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1506 const struct pll_vco *vco; 1507 struct clk_hw *parent_hw; 1508 unsigned long cal_freq, rrate; 1509 u32 cal_l, val, alpha_width = pll_alpha_width(pll); 1510 const char *name = clk_hw_get_name(hw); 1511 u64 a; 1512 int ret; 1513 1514 /* Check if calibration needs to be done i.e. PLL is in reset */ 1515 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1516 if (ret) 1517 return ret; 1518 1519 /* Return early if calibration is not needed. */ 1520 if (val & PLL_RESET_N) 1521 return 0; 1522 1523 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); 1524 if (!vco) { 1525 pr_err("%s: alpha pll not in a valid vco range\n", name); 1526 return -EINVAL; 1527 } 1528 1529 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq + 1530 pll->vco_table[0].max_freq) * 54, 100); 1531 1532 parent_hw = clk_hw_get_parent(hw); 1533 if (!parent_hw) 1534 return -EINVAL; 1535 1536 rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw), 1537 &cal_l, &a, alpha_width); 1538 1539 ret = alpha_pll_check_rate_margin(hw, rrate, cal_freq); 1540 if (ret < 0) 1541 return ret; 1542 1543 /* Setup PLL for calibration frequency */ 1544 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l); 1545 1546 /* Bringup the PLL at calibration frequency */ 1547 ret = clk_alpha_pll_enable(hw); 1548 if (ret) { 1549 pr_err("%s: alpha pll calibration failed\n", name); 1550 return ret; 1551 } 1552 1553 clk_alpha_pll_disable(hw); 1554 1555 return 0; 1556 } 1557 1558 const struct clk_ops clk_alpha_pll_fabia_ops = { 1559 .prepare = alpha_pll_fabia_prepare, 1560 .enable = alpha_pll_fabia_enable, 1561 .disable = alpha_pll_fabia_disable, 1562 .is_enabled = clk_alpha_pll_is_enabled, 1563 .set_rate = alpha_pll_fabia_set_rate, 1564 .recalc_rate = alpha_pll_fabia_recalc_rate, 1565 .determine_rate = clk_alpha_pll_determine_rate, 1566 }; 1567 EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops); 1568 1569 const struct clk_ops clk_alpha_pll_fixed_fabia_ops = { 1570 .enable = alpha_pll_fabia_enable, 1571 .disable = alpha_pll_fabia_disable, 1572 .is_enabled = clk_alpha_pll_is_enabled, 1573 .recalc_rate = alpha_pll_fabia_recalc_rate, 1574 .determine_rate = clk_alpha_pll_determine_rate, 1575 }; 1576 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops); 1577 1578 static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw, 1579 unsigned long parent_rate) 1580 { 1581 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1582 u32 i, div = 1, val; 1583 int ret; 1584 1585 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1586 if (ret) 1587 return ret; 1588 1589 val >>= pll->post_div_shift; 1590 val &= BIT(pll->width) - 1; 1591 1592 for (i = 0; i < pll->num_post_div; i++) { 1593 if (pll->post_div_table[i].val == val) { 1594 div = pll->post_div_table[i].div; 1595 break; 1596 } 1597 } 1598 1599 return (parent_rate / div); 1600 } 1601 1602 static unsigned long 1603 clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1604 { 1605 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1606 struct regmap *regmap = pll->clkr.regmap; 1607 u32 i, div = 1, val; 1608 1609 if (regmap_read(regmap, PLL_USER_CTL(pll), &val)) 1610 return 0; 1611 1612 val >>= pll->post_div_shift; 1613 val &= PLL_POST_DIV_MASK(pll); 1614 1615 for (i = 0; i < pll->num_post_div; i++) { 1616 if (pll->post_div_table[i].val == val) { 1617 div = pll->post_div_table[i].div; 1618 break; 1619 } 1620 } 1621 1622 return (parent_rate / div); 1623 } 1624 1625 static int clk_trion_pll_postdiv_determine_rate(struct clk_hw *hw, 1626 struct clk_rate_request *req) 1627 { 1628 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1629 1630 return divider_determine_rate(hw, req, pll->post_div_table, pll->width, 1631 CLK_DIVIDER_ROUND_CLOSEST); 1632 }; 1633 1634 static int 1635 clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1636 unsigned long parent_rate) 1637 { 1638 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1639 struct regmap *regmap = pll->clkr.regmap; 1640 int i, val = 0, div; 1641 1642 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1643 for (i = 0; i < pll->num_post_div; i++) { 1644 if (pll->post_div_table[i].div == div) { 1645 val = pll->post_div_table[i].val; 1646 break; 1647 } 1648 } 1649 1650 return regmap_update_bits(regmap, PLL_USER_CTL(pll), 1651 PLL_POST_DIV_MASK(pll) << pll->post_div_shift, 1652 val << pll->post_div_shift); 1653 } 1654 1655 const struct clk_ops clk_alpha_pll_postdiv_trion_ops = { 1656 .recalc_rate = clk_trion_pll_postdiv_recalc_rate, 1657 .determine_rate = clk_trion_pll_postdiv_determine_rate, 1658 .set_rate = clk_trion_pll_postdiv_set_rate, 1659 }; 1660 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops); 1661 1662 static int clk_alpha_pll_postdiv_fabia_determine_rate(struct clk_hw *hw, 1663 struct clk_rate_request *req) 1664 { 1665 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1666 1667 return divider_determine_rate(hw, req, pll->post_div_table, pll->width, 1668 CLK_DIVIDER_ROUND_CLOSEST); 1669 } 1670 1671 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw, 1672 unsigned long rate, unsigned long parent_rate) 1673 { 1674 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1675 int i, val = 0, div, ret; 1676 1677 /* 1678 * If the PLL is in FSM mode, then treat set_rate callback as a 1679 * no-operation. 1680 */ 1681 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1682 if (ret) 1683 return ret; 1684 1685 if (val & PLL_VOTE_FSM_ENA) 1686 return 0; 1687 1688 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1689 for (i = 0; i < pll->num_post_div; i++) { 1690 if (pll->post_div_table[i].div == div) { 1691 val = pll->post_div_table[i].val; 1692 break; 1693 } 1694 } 1695 1696 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1697 (BIT(pll->width) - 1) << pll->post_div_shift, 1698 val << pll->post_div_shift); 1699 } 1700 1701 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = { 1702 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1703 .determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate, 1704 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1705 }; 1706 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops); 1707 1708 /** 1709 * clk_trion_pll_configure - configure the trion pll 1710 * 1711 * @pll: clk alpha pll 1712 * @regmap: register map 1713 * @config: configuration to apply for pll 1714 */ 1715 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1716 const struct alpha_pll_config *config) 1717 { 1718 /* 1719 * If the bootloader left the PLL enabled it's likely that there are 1720 * RCGs that will lock up if we disable the PLL below. 1721 */ 1722 if (trion_pll_is_enabled(pll, regmap)) { 1723 pr_debug("Trion PLL is already enabled, skipping configuration\n"); 1724 return; 1725 } 1726 1727 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1728 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); 1729 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1730 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1731 config->config_ctl_val); 1732 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1733 config->config_ctl_hi_val); 1734 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), 1735 config->config_ctl_hi1_val); 1736 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1737 config->user_ctl_val); 1738 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1739 config->user_ctl_hi_val); 1740 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), 1741 config->user_ctl_hi1_val); 1742 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1743 config->test_ctl_val); 1744 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1745 config->test_ctl_hi_val); 1746 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), 1747 config->test_ctl_hi1_val); 1748 1749 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1750 PLL_UPDATE_BYPASS); 1751 1752 /* Disable PLL output */ 1753 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1754 1755 /* Set operation mode to OFF */ 1756 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1757 1758 /* Place the PLL in STANDBY mode */ 1759 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1760 } 1761 EXPORT_SYMBOL_GPL(clk_trion_pll_configure); 1762 1763 /* 1764 * The TRION PLL requires a power-on self-calibration which happens when the 1765 * PLL comes out of reset. Calibrate in case it is not completed. 1766 */ 1767 static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done) 1768 { 1769 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1770 u32 val; 1771 int ret; 1772 1773 /* Return early if calibration is not needed. */ 1774 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); 1775 if (val & pcal_done) 1776 return 0; 1777 1778 /* On/off to calibrate */ 1779 ret = clk_trion_pll_enable(hw); 1780 if (!ret) 1781 clk_trion_pll_disable(hw); 1782 1783 return ret; 1784 } 1785 1786 static int alpha_pll_trion_prepare(struct clk_hw *hw) 1787 { 1788 return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE); 1789 } 1790 1791 static int alpha_pll_lucid_prepare(struct clk_hw *hw) 1792 { 1793 return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE); 1794 } 1795 1796 static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1797 unsigned long prate, u32 latch_bit, u32 latch_ack) 1798 { 1799 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1800 unsigned long rrate; 1801 u32 val, l, alpha_width = pll_alpha_width(pll); 1802 u64 a; 1803 int ret; 1804 1805 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1806 1807 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1808 if (ret < 0) 1809 return ret; 1810 1811 regmap_update_bits(pll->clkr.regmap, PLL_L_VAL(pll), LUCID_EVO_PLL_L_VAL_MASK, l); 1812 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1813 1814 /* Latch the PLL input */ 1815 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); 1816 if (ret) 1817 return ret; 1818 1819 /* Wait for 2 reference cycles before checking the ACK bit. */ 1820 udelay(1); 1821 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1822 if (!(val & latch_ack)) { 1823 pr_err("Lucid PLL latch failed. Output may be unstable!\n"); 1824 return -EINVAL; 1825 } 1826 1827 /* Return the latch input to 0 */ 1828 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); 1829 if (ret) 1830 return ret; 1831 1832 if (clk_hw_is_enabled(hw)) { 1833 ret = wait_for_pll_enable_lock(pll); 1834 if (ret) 1835 return ret; 1836 } 1837 1838 /* Wait for PLL output to stabilize */ 1839 udelay(100); 1840 return 0; 1841 } 1842 1843 static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1844 unsigned long prate) 1845 { 1846 return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH); 1847 } 1848 1849 const struct clk_ops clk_alpha_pll_trion_ops = { 1850 .prepare = alpha_pll_trion_prepare, 1851 .enable = clk_trion_pll_enable, 1852 .disable = clk_trion_pll_disable, 1853 .is_enabled = clk_trion_pll_is_enabled, 1854 .recalc_rate = clk_trion_pll_recalc_rate, 1855 .determine_rate = clk_alpha_pll_determine_rate, 1856 .set_rate = alpha_pll_trion_set_rate, 1857 }; 1858 EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops); 1859 1860 const struct clk_ops clk_alpha_pll_lucid_ops = { 1861 .prepare = alpha_pll_lucid_prepare, 1862 .enable = clk_trion_pll_enable, 1863 .disable = clk_trion_pll_disable, 1864 .is_enabled = clk_trion_pll_is_enabled, 1865 .recalc_rate = clk_trion_pll_recalc_rate, 1866 .determine_rate = clk_alpha_pll_determine_rate, 1867 .set_rate = alpha_pll_trion_set_rate, 1868 }; 1869 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops); 1870 1871 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { 1872 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1873 .determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate, 1874 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1875 }; 1876 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops); 1877 1878 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1879 const struct alpha_pll_config *config) 1880 { 1881 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1882 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1883 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1884 config->user_ctl_val); 1885 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1886 config->config_ctl_val); 1887 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1888 config->config_ctl_hi_val); 1889 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1890 config->test_ctl_val); 1891 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1892 config->test_ctl_hi_val); 1893 } 1894 EXPORT_SYMBOL_GPL(clk_agera_pll_configure); 1895 1896 static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate, 1897 unsigned long prate) 1898 { 1899 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1900 u32 l, alpha_width = pll_alpha_width(pll); 1901 int ret; 1902 unsigned long rrate; 1903 u64 a; 1904 1905 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1906 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1907 if (ret < 0) 1908 return ret; 1909 1910 /* change L_VAL without having to go through the power on sequence */ 1911 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1912 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1913 1914 if (clk_hw_is_enabled(hw)) 1915 return wait_for_pll_enable_lock(pll); 1916 1917 return 0; 1918 } 1919 1920 const struct clk_ops clk_alpha_pll_agera_ops = { 1921 .enable = clk_alpha_pll_enable, 1922 .disable = clk_alpha_pll_disable, 1923 .is_enabled = clk_alpha_pll_is_enabled, 1924 .recalc_rate = alpha_pll_fabia_recalc_rate, 1925 .determine_rate = clk_alpha_pll_determine_rate, 1926 .set_rate = clk_alpha_pll_agera_set_rate, 1927 }; 1928 EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops); 1929 1930 /** 1931 * clk_lucid_5lpe_pll_configure - configure the lucid 5lpe pll 1932 * 1933 * @pll: clk alpha pll 1934 * @regmap: register map 1935 * @config: configuration to apply for pll 1936 */ 1937 void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1938 const struct alpha_pll_config *config) 1939 { 1940 /* 1941 * If the bootloader left the PLL enabled it's likely that there are 1942 * RCGs that will lock up if we disable the PLL below. 1943 */ 1944 if (trion_pll_is_enabled(pll, regmap)) { 1945 pr_debug("Lucid 5LPE PLL is already enabled, skipping configuration\n"); 1946 return; 1947 } 1948 1949 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1950 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); 1951 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1952 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1953 config->config_ctl_val); 1954 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1955 config->config_ctl_hi_val); 1956 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), 1957 config->config_ctl_hi1_val); 1958 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1959 config->user_ctl_val); 1960 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1961 config->user_ctl_hi_val); 1962 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), 1963 config->user_ctl_hi1_val); 1964 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1965 config->test_ctl_val); 1966 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1967 config->test_ctl_hi_val); 1968 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), 1969 config->test_ctl_hi1_val); 1970 1971 /* Disable PLL output */ 1972 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1973 1974 /* Set operation mode to OFF */ 1975 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1976 1977 /* Place the PLL in STANDBY mode */ 1978 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1979 } 1980 EXPORT_SYMBOL_GPL(clk_lucid_5lpe_pll_configure); 1981 1982 static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw) 1983 { 1984 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1985 u32 val; 1986 int ret; 1987 1988 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1989 if (ret) 1990 return ret; 1991 1992 /* If in FSM mode, just vote for it */ 1993 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 1994 ret = clk_enable_regmap(hw); 1995 if (ret) 1996 return ret; 1997 return wait_for_pll_enable_lock(pll); 1998 } 1999 2000 /* Check if PLL is already enabled, return if enabled */ 2001 if (trion_pll_is_enabled(pll, pll->clkr.regmap)) 2002 return 0; 2003 2004 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2005 if (ret) 2006 return ret; 2007 2008 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); 2009 2010 ret = wait_for_pll_enable_lock(pll); 2011 if (ret) 2012 return ret; 2013 2014 /* Enable the PLL outputs */ 2015 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 2016 if (ret) 2017 return ret; 2018 2019 /* Enable the global PLL outputs */ 2020 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2021 } 2022 2023 static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw) 2024 { 2025 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2026 u32 val; 2027 int ret; 2028 2029 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 2030 if (ret) 2031 return; 2032 2033 /* If in FSM mode, just unvote it */ 2034 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 2035 clk_disable_regmap(hw); 2036 return; 2037 } 2038 2039 /* Disable the global PLL output */ 2040 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2041 if (ret) 2042 return; 2043 2044 /* Disable the PLL outputs */ 2045 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 2046 if (ret) 2047 return; 2048 2049 /* Place the PLL mode in STANDBY */ 2050 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY); 2051 } 2052 2053 /* 2054 * The Lucid 5LPE PLL requires a power-on self-calibration which happens 2055 * when the PLL comes out of reset. Calibrate in case it is not completed. 2056 */ 2057 static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw) 2058 { 2059 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2060 struct clk_hw *p; 2061 u32 val = 0; 2062 int ret; 2063 2064 /* Return early if calibration is not needed. */ 2065 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 2066 if (val & LUCID_5LPE_PCAL_DONE) 2067 return 0; 2068 2069 p = clk_hw_get_parent(hw); 2070 if (!p) 2071 return -EINVAL; 2072 2073 ret = alpha_pll_lucid_5lpe_enable(hw); 2074 if (ret) 2075 return ret; 2076 2077 alpha_pll_lucid_5lpe_disable(hw); 2078 2079 return 0; 2080 } 2081 2082 static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate, 2083 unsigned long prate) 2084 { 2085 return __alpha_pll_trion_set_rate(hw, rate, prate, 2086 LUCID_5LPE_PLL_LATCH_INPUT, 2087 LUCID_5LPE_ALPHA_PLL_ACK_LATCH); 2088 } 2089 2090 static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 2091 unsigned long parent_rate, 2092 unsigned long enable_vote_run) 2093 { 2094 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 2095 struct regmap *regmap = pll->clkr.regmap; 2096 int i, val, div, ret; 2097 u32 mask; 2098 2099 /* 2100 * If the PLL is in FSM mode, then treat set_rate callback as a 2101 * no-operation. 2102 */ 2103 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2104 if (ret) 2105 return ret; 2106 2107 if (val & enable_vote_run) 2108 return 0; 2109 2110 if (!pll->post_div_table) { 2111 pr_err("Missing the post_div_table for the %s PLL\n", 2112 clk_hw_get_name(&pll->clkr.hw)); 2113 return -EINVAL; 2114 } 2115 2116 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); 2117 for (i = 0; i < pll->num_post_div; i++) { 2118 if (pll->post_div_table[i].div == div) { 2119 val = pll->post_div_table[i].val; 2120 break; 2121 } 2122 } 2123 2124 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); 2125 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 2126 mask, val << pll->post_div_shift); 2127 } 2128 2129 static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 2130 unsigned long parent_rate) 2131 { 2132 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN); 2133 } 2134 2135 const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = { 2136 .prepare = alpha_pll_lucid_5lpe_prepare, 2137 .enable = alpha_pll_lucid_5lpe_enable, 2138 .disable = alpha_pll_lucid_5lpe_disable, 2139 .is_enabled = clk_trion_pll_is_enabled, 2140 .recalc_rate = clk_trion_pll_recalc_rate, 2141 .determine_rate = clk_alpha_pll_determine_rate, 2142 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2143 }; 2144 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops); 2145 2146 const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = { 2147 .enable = alpha_pll_lucid_5lpe_enable, 2148 .disable = alpha_pll_lucid_5lpe_disable, 2149 .is_enabled = clk_trion_pll_is_enabled, 2150 .recalc_rate = clk_trion_pll_recalc_rate, 2151 .determine_rate = clk_alpha_pll_determine_rate, 2152 }; 2153 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops); 2154 2155 const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = { 2156 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 2157 .determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate, 2158 .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate, 2159 }; 2160 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops); 2161 2162 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2163 const struct alpha_pll_config *config) 2164 { 2165 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2166 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2167 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2168 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2169 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2170 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2171 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2172 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); 2173 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2174 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2175 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2176 2177 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0); 2178 2179 /* Disable PLL output */ 2180 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2181 2182 /* Set operation mode to OFF */ 2183 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2184 2185 /* Place the PLL in STANDBY mode */ 2186 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2187 } 2188 EXPORT_SYMBOL_GPL(clk_zonda_pll_configure); 2189 2190 static int clk_zonda_pll_enable(struct clk_hw *hw) 2191 { 2192 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2193 struct regmap *regmap = pll->clkr.regmap; 2194 u32 val; 2195 int ret; 2196 2197 regmap_read(regmap, PLL_MODE(pll), &val); 2198 2199 /* If in FSM mode, just vote for it */ 2200 if (val & PLL_VOTE_FSM_ENA) { 2201 ret = clk_enable_regmap(hw); 2202 if (ret) 2203 return ret; 2204 return wait_for_pll_enable_active(pll); 2205 } 2206 2207 /* Get the PLL out of bypass mode */ 2208 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); 2209 2210 /* 2211 * H/W requires a 1us delay between disabling the bypass and 2212 * de-asserting the reset. 2213 */ 2214 udelay(1); 2215 2216 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2217 2218 /* Set operation mode to RUN */ 2219 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2220 2221 regmap_read(regmap, PLL_TEST_CTL(pll), &val); 2222 2223 /* If cfa mode then poll for freq lock */ 2224 if (val & ZONDA_STAY_IN_CFA) 2225 ret = wait_for_zonda_pll_freq_lock(pll); 2226 else 2227 ret = wait_for_pll_enable_lock(pll); 2228 if (ret) 2229 return ret; 2230 2231 /* Enable the PLL outputs */ 2232 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK); 2233 2234 /* Enable the global PLL outputs */ 2235 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2236 2237 return 0; 2238 } 2239 2240 static void clk_zonda_pll_disable(struct clk_hw *hw) 2241 { 2242 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2243 struct regmap *regmap = pll->clkr.regmap; 2244 u32 val; 2245 2246 regmap_read(regmap, PLL_MODE(pll), &val); 2247 2248 /* If in FSM mode, just unvote it */ 2249 if (val & PLL_VOTE_FSM_ENA) { 2250 clk_disable_regmap(hw); 2251 return; 2252 } 2253 2254 /* Disable the global PLL output */ 2255 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2256 2257 /* Disable the PLL outputs */ 2258 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0); 2259 2260 /* Put the PLL in bypass and reset */ 2261 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0); 2262 2263 /* Place the PLL mode in OFF state */ 2264 regmap_write(regmap, PLL_OPMODE(pll), 0x0); 2265 } 2266 2267 static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32 *l) 2268 { 2269 u64 remainder, quotient; 2270 2271 quotient = rate; 2272 remainder = do_div(quotient, prate); 2273 2274 *l = rate + (u32)(remainder * 2 >= prate); 2275 } 2276 2277 static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, 2278 unsigned long prate) 2279 { 2280 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2281 unsigned long rrate; 2282 u32 test_ctl_val; 2283 u32 l, alpha_width = pll_alpha_width(pll); 2284 u64 a; 2285 int ret; 2286 2287 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 2288 2289 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 2290 if (ret < 0) 2291 return ret; 2292 2293 if (a & PLL_ALPHA_MSB) 2294 zonda_pll_adjust_l_val(rate, prate, &l); 2295 2296 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2297 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2298 2299 if (!clk_hw_is_enabled(hw)) 2300 return 0; 2301 2302 /* Wait before polling for the frequency latch */ 2303 udelay(5); 2304 2305 /* Read stay in cfa mode */ 2306 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val); 2307 2308 /* If cfa mode then poll for freq lock */ 2309 if (test_ctl_val & ZONDA_STAY_IN_CFA) 2310 ret = wait_for_zonda_pll_freq_lock(pll); 2311 else 2312 ret = wait_for_pll_enable_lock(pll); 2313 if (ret) 2314 return ret; 2315 2316 /* Wait for PLL output to stabilize */ 2317 udelay(100); 2318 return 0; 2319 } 2320 2321 const struct clk_ops clk_alpha_pll_zonda_ops = { 2322 .enable = clk_zonda_pll_enable, 2323 .disable = clk_zonda_pll_disable, 2324 .is_enabled = clk_trion_pll_is_enabled, 2325 .recalc_rate = clk_trion_pll_recalc_rate, 2326 .determine_rate = clk_alpha_pll_determine_rate, 2327 .set_rate = clk_zonda_pll_set_rate, 2328 }; 2329 EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops); 2330 2331 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2332 const struct alpha_pll_config *config) 2333 { 2334 u32 lval = config->l; 2335 2336 /* 2337 * If the bootloader left the PLL enabled it's likely that there are 2338 * RCGs that will lock up if we disable the PLL below. 2339 */ 2340 if (trion_pll_is_enabled(pll, regmap)) { 2341 pr_debug("Lucid Evo PLL is already enabled, skipping configuration\n"); 2342 return; 2343 } 2344 2345 if (config->cal_l) 2346 lval |= config->cal_l << LUCID_EVO_PLL_CAL_L_VAL_SHIFT; 2347 else 2348 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT; 2349 2350 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); 2351 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2352 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2353 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2354 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2355 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2356 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2357 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2358 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2359 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2360 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); 2361 2362 /* Disable PLL output */ 2363 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2364 2365 /* Set operation mode to STANDBY and de-assert the reset */ 2366 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2367 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2368 } 2369 EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure); 2370 2371 void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2372 const struct alpha_pll_config *config) 2373 { 2374 u32 lval = config->l; 2375 2376 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT; 2377 lval |= TRION_PLL_CAL_VAL << LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT; 2378 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); 2379 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2380 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2381 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2382 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2383 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2384 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2385 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2386 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2387 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2388 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); 2389 2390 /* Disable PLL output */ 2391 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2392 2393 /* Set operation mode to STANDBY and de-assert the reset */ 2394 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2395 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2396 } 2397 EXPORT_SYMBOL_GPL(clk_lucid_ole_pll_configure); 2398 2399 static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) 2400 { 2401 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2402 struct regmap *regmap = pll->clkr.regmap; 2403 u32 val; 2404 int ret; 2405 2406 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2407 if (ret) 2408 return ret; 2409 2410 /* If in FSM mode, just vote for it */ 2411 if (val & LUCID_EVO_ENABLE_VOTE_RUN) { 2412 ret = clk_enable_regmap(hw); 2413 if (ret) 2414 return ret; 2415 return wait_for_pll_enable_lock(pll); 2416 } 2417 2418 /* Check if PLL is already enabled */ 2419 if (trion_pll_is_enabled(pll, regmap)) 2420 return 0; 2421 2422 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2423 if (ret) 2424 return ret; 2425 2426 /* Set operation mode to RUN */ 2427 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2428 2429 ret = wait_for_pll_enable_lock(pll); 2430 if (ret) 2431 return ret; 2432 2433 /* Enable the PLL outputs */ 2434 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 2435 if (ret) 2436 return ret; 2437 2438 /* Enable the global PLL outputs */ 2439 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2440 if (ret) 2441 return ret; 2442 2443 /* Ensure that the write above goes through before returning. */ 2444 mb(); 2445 return ret; 2446 } 2447 2448 static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset) 2449 { 2450 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2451 struct regmap *regmap = pll->clkr.regmap; 2452 u32 val; 2453 int ret; 2454 2455 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2456 if (ret) 2457 return; 2458 2459 /* If in FSM mode, just unvote it */ 2460 if (val & LUCID_EVO_ENABLE_VOTE_RUN) { 2461 clk_disable_regmap(hw); 2462 return; 2463 } 2464 2465 /* Disable the global PLL output */ 2466 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2467 if (ret) 2468 return; 2469 2470 /* Disable the PLL outputs */ 2471 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 2472 if (ret) 2473 return; 2474 2475 /* Place the PLL mode in STANDBY */ 2476 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2477 2478 if (reset) 2479 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0); 2480 } 2481 2482 static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset) 2483 { 2484 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2485 struct clk_hw *p; 2486 u32 val = 0; 2487 int ret; 2488 2489 /* Return early if calibration is not needed. */ 2490 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 2491 if (!(val & LUCID_EVO_PCAL_NOT_DONE)) 2492 return 0; 2493 2494 p = clk_hw_get_parent(hw); 2495 if (!p) 2496 return -EINVAL; 2497 2498 ret = alpha_pll_lucid_evo_enable(hw); 2499 if (ret) 2500 return ret; 2501 2502 _alpha_pll_lucid_evo_disable(hw, reset); 2503 2504 return 0; 2505 } 2506 2507 static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) 2508 { 2509 _alpha_pll_lucid_evo_disable(hw, false); 2510 } 2511 2512 static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw) 2513 { 2514 return _alpha_pll_lucid_evo_prepare(hw, false); 2515 } 2516 2517 static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw) 2518 { 2519 _alpha_pll_lucid_evo_disable(hw, true); 2520 } 2521 2522 static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw) 2523 { 2524 return _alpha_pll_lucid_evo_prepare(hw, true); 2525 } 2526 2527 static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, 2528 unsigned long parent_rate) 2529 { 2530 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2531 struct regmap *regmap = pll->clkr.regmap; 2532 u32 l, frac; 2533 2534 if (regmap_read(regmap, PLL_L_VAL(pll), &l)) 2535 return 0; 2536 l &= LUCID_EVO_PLL_L_VAL_MASK; 2537 2538 if (regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac)) 2539 return 0; 2540 2541 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); 2542 } 2543 2544 static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 2545 unsigned long parent_rate) 2546 { 2547 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN); 2548 } 2549 2550 const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = { 2551 .enable = alpha_pll_lucid_evo_enable, 2552 .disable = alpha_pll_lucid_evo_disable, 2553 .is_enabled = clk_trion_pll_is_enabled, 2554 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2555 .determine_rate = clk_alpha_pll_determine_rate, 2556 }; 2557 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops); 2558 2559 const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = { 2560 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 2561 .determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate, 2562 .set_rate = clk_lucid_evo_pll_postdiv_set_rate, 2563 }; 2564 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops); 2565 2566 const struct clk_ops clk_alpha_pll_lucid_evo_ops = { 2567 .prepare = alpha_pll_lucid_evo_prepare, 2568 .enable = alpha_pll_lucid_evo_enable, 2569 .disable = alpha_pll_lucid_evo_disable, 2570 .is_enabled = clk_trion_pll_is_enabled, 2571 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2572 .determine_rate = clk_alpha_pll_determine_rate, 2573 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2574 }; 2575 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops); 2576 2577 const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = { 2578 .prepare = alpha_pll_reset_lucid_evo_prepare, 2579 .enable = alpha_pll_lucid_evo_enable, 2580 .disable = alpha_pll_reset_lucid_evo_disable, 2581 .is_enabled = clk_trion_pll_is_enabled, 2582 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2583 .determine_rate = clk_alpha_pll_determine_rate, 2584 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2585 }; 2586 EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops); 2587 2588 static int alpha_pll_pongo_elu_prepare(struct clk_hw *hw) 2589 { 2590 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2591 struct regmap *regmap = pll->clkr.regmap; 2592 int ret; 2593 2594 /* Enable PLL intially to one-time calibrate against XO. */ 2595 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2596 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2597 regmap_update_bits(regmap, PLL_MODE(pll), PONGO_XO_PRESENT, PONGO_XO_PRESENT); 2598 2599 /* Set regmap for wait_for_pll() */ 2600 pll->clkr.regmap = regmap; 2601 ret = wait_for_pll_enable_lock(pll); 2602 if (ret) { 2603 /* Reverse calibration - disable PLL output */ 2604 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2605 return ret; 2606 } 2607 2608 /* Disable PLL after one-time calibration. */ 2609 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2610 2611 /* Select internally generated clock. */ 2612 regmap_update_bits(regmap, PLL_MODE(pll), PONGO_CLOCK_SELECT, 2613 PONGO_CLOCK_SELECT); 2614 2615 return 0; 2616 } 2617 2618 static int alpha_pll_pongo_elu_enable(struct clk_hw *hw) 2619 { 2620 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2621 struct regmap *regmap = pll->clkr.regmap; 2622 int ret; 2623 2624 /* Check if PLL is already enabled */ 2625 if (trion_pll_is_enabled(pll, regmap)) 2626 return 0; 2627 2628 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2629 if (ret) 2630 return ret; 2631 2632 /* Set operation mode to RUN */ 2633 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2634 2635 ret = wait_for_pll_enable_lock(pll); 2636 if (ret) 2637 return ret; 2638 2639 /* Enable the global PLL outputs */ 2640 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2641 if (ret) 2642 return ret; 2643 2644 /* Ensure that the write above goes through before returning. */ 2645 mb(); 2646 2647 return ret; 2648 } 2649 2650 static void alpha_pll_pongo_elu_disable(struct clk_hw *hw) 2651 { 2652 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2653 struct regmap *regmap = pll->clkr.regmap; 2654 int ret; 2655 2656 /* Disable the global PLL output */ 2657 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2658 if (ret) 2659 return; 2660 2661 /* Place the PLL mode in STANDBY */ 2662 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2663 } 2664 2665 static unsigned long alpha_pll_pongo_elu_recalc_rate(struct clk_hw *hw, 2666 unsigned long parent_rate) 2667 { 2668 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2669 struct regmap *regmap = pll->clkr.regmap; 2670 u32 l; 2671 2672 if (regmap_read(regmap, PLL_L_VAL(pll), &l)) 2673 return 0; 2674 2675 l &= PONGO_PLL_L_VAL_MASK; 2676 2677 return alpha_pll_calc_rate(parent_rate, l, 0, pll_alpha_width(pll)); 2678 } 2679 2680 const struct clk_ops clk_alpha_pll_pongo_elu_ops = { 2681 .prepare = alpha_pll_pongo_elu_prepare, 2682 .enable = alpha_pll_pongo_elu_enable, 2683 .disable = alpha_pll_pongo_elu_disable, 2684 .recalc_rate = alpha_pll_pongo_elu_recalc_rate, 2685 }; 2686 EXPORT_SYMBOL_GPL(clk_alpha_pll_pongo_elu_ops); 2687 2688 void clk_pongo_elu_pll_configure(struct clk_alpha_pll *pll, 2689 struct regmap *regmap, 2690 const struct alpha_pll_config *config) 2691 { 2692 u32 val; 2693 2694 regmap_update_bits(regmap, PLL_USER_CTL(pll), PONGO_PLL_OUT_MASK, 2695 PONGO_PLL_OUT_MASK); 2696 2697 if (trion_pll_is_enabled(pll, regmap)) 2698 return; 2699 2700 if (regmap_read(regmap, PLL_L_VAL(pll), &val)) 2701 return; 2702 val &= PONGO_PLL_L_VAL_MASK; 2703 if (val) 2704 return; 2705 2706 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2707 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2708 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2709 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2710 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2711 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U2(pll), config->config_ctl_hi2_val); 2712 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 2713 config->user_ctl_val | PONGO_PLL_OUT_MASK); 2714 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2715 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2716 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2717 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2718 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); 2719 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U3(pll), config->test_ctl_hi3_val); 2720 2721 /* Disable PLL output */ 2722 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2723 } 2724 EXPORT_SYMBOL_GPL(clk_pongo_elu_pll_configure); 2725 2726 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2727 const struct alpha_pll_config *config) 2728 { 2729 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2730 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2731 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2732 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2733 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2734 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2735 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2736 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2737 2738 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2739 2740 regmap_update_bits(regmap, PLL_MODE(pll), 2741 PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL, 2742 PLL_RESET_N | PLL_BYPASSNL); 2743 } 2744 EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure); 2745 2746 static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw, 2747 unsigned long parent_rate) 2748 { 2749 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2750 u32 l; 2751 2752 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) 2753 return 0; 2754 2755 return parent_rate * l; 2756 } 2757 2758 static int clk_rivian_evo_pll_determine_rate(struct clk_hw *hw, 2759 struct clk_rate_request *req) 2760 { 2761 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2762 unsigned long min_freq, max_freq; 2763 u32 l; 2764 u64 a; 2765 2766 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, &l, 2767 &a, 0); 2768 if (!pll->vco_table || alpha_pll_find_vco(pll, req->rate)) 2769 return 0; 2770 2771 min_freq = pll->vco_table[0].min_freq; 2772 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 2773 2774 req->rate = clamp(req->rate, min_freq, max_freq); 2775 2776 return 0; 2777 } 2778 2779 const struct clk_ops clk_alpha_pll_rivian_evo_ops = { 2780 .enable = alpha_pll_lucid_5lpe_enable, 2781 .disable = alpha_pll_lucid_5lpe_disable, 2782 .is_enabled = clk_trion_pll_is_enabled, 2783 .recalc_rate = clk_rivian_evo_pll_recalc_rate, 2784 .determine_rate = clk_rivian_evo_pll_determine_rate, 2785 }; 2786 EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops); 2787 2788 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2789 const struct alpha_pll_config *config) 2790 { 2791 u32 val, val_u, mask, mask_u; 2792 2793 regmap_write(regmap, PLL_L_VAL(pll), config->l); 2794 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2795 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2796 2797 if (pll_has_64bit_config(pll)) 2798 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), 2799 config->config_ctl_hi_val); 2800 2801 if (pll_alpha_width(pll) > 32) 2802 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); 2803 2804 val = config->main_output_mask; 2805 val |= config->aux_output_mask; 2806 val |= config->aux2_output_mask; 2807 val |= config->early_output_mask; 2808 val |= config->pre_div_val; 2809 val |= config->post_div_val; 2810 val |= config->vco_val; 2811 val |= config->alpha_en_mask; 2812 val |= config->alpha_mode_mask; 2813 2814 mask = config->main_output_mask; 2815 mask |= config->aux_output_mask; 2816 mask |= config->aux2_output_mask; 2817 mask |= config->early_output_mask; 2818 mask |= config->pre_div_mask; 2819 mask |= config->post_div_mask; 2820 mask |= config->vco_mask; 2821 mask |= config->alpha_en_mask; 2822 mask |= config->alpha_mode_mask; 2823 2824 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 2825 2826 /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */ 2827 val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT; 2828 val_u |= config->lock_det; 2829 2830 mask_u = config->status_mask; 2831 mask_u |= config->lock_det; 2832 2833 regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u); 2834 regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2835 regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2836 2837 if (pll->flags & SUPPORTS_FSM_MODE) 2838 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); 2839 } 2840 EXPORT_SYMBOL_GPL(clk_stromer_pll_configure); 2841 2842 static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw, 2843 struct clk_rate_request *req) 2844 { 2845 u32 l; 2846 u64 a; 2847 2848 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, 2849 &l, &a, ALPHA_REG_BITWIDTH); 2850 2851 return 0; 2852 } 2853 2854 static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate, 2855 unsigned long prate) 2856 { 2857 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2858 int ret; 2859 u32 l; 2860 u64 a; 2861 2862 rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH); 2863 2864 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2865 2866 a <<= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH; 2867 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2868 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 2869 a >> ALPHA_BITWIDTH); 2870 2871 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 2872 PLL_ALPHA_EN, PLL_ALPHA_EN); 2873 2874 if (!clk_hw_is_enabled(hw)) 2875 return 0; 2876 2877 /* 2878 * Stromer PLL supports Dynamic programming. 2879 * It allows the PLL frequency to be changed on-the-fly without first 2880 * execution of a shutdown procedure followed by a bring up procedure. 2881 */ 2882 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 2883 PLL_UPDATE); 2884 2885 ret = wait_for_pll_update(pll); 2886 if (ret) 2887 return ret; 2888 2889 return wait_for_pll_enable_lock(pll); 2890 } 2891 2892 const struct clk_ops clk_alpha_pll_stromer_ops = { 2893 .enable = clk_alpha_pll_enable, 2894 .disable = clk_alpha_pll_disable, 2895 .is_enabled = clk_alpha_pll_is_enabled, 2896 .recalc_rate = clk_alpha_pll_recalc_rate, 2897 .determine_rate = clk_alpha_pll_stromer_determine_rate, 2898 .set_rate = clk_alpha_pll_stromer_set_rate, 2899 }; 2900 EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops); 2901 2902 static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw, 2903 unsigned long rate, 2904 unsigned long prate) 2905 { 2906 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2907 u32 l, alpha_width = pll_alpha_width(pll); 2908 int ret, pll_mode; 2909 u64 a; 2910 2911 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 2912 2913 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode); 2914 if (ret) 2915 return ret; 2916 2917 regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0); 2918 2919 /* Delay of 2 output clock ticks required until output is disabled */ 2920 udelay(1); 2921 2922 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2923 2924 if (alpha_width > ALPHA_BITWIDTH) 2925 a <<= alpha_width - ALPHA_BITWIDTH; 2926 2927 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2928 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 2929 a >> ALPHA_BITWIDTH); 2930 2931 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 2932 PLL_ALPHA_EN, PLL_ALPHA_EN); 2933 2934 regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL); 2935 2936 /* Wait five micro seconds or more */ 2937 udelay(5); 2938 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, 2939 PLL_RESET_N); 2940 2941 /* The lock time should be less than 50 micro seconds worst case */ 2942 usleep_range(50, 60); 2943 2944 ret = wait_for_pll_enable_lock(pll); 2945 if (ret) { 2946 pr_err("Wait for PLL enable lock failed [%s] %d\n", 2947 clk_hw_get_name(hw), ret); 2948 return ret; 2949 } 2950 2951 if (pll_mode & PLL_OUTCTRL) 2952 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 2953 PLL_OUTCTRL); 2954 2955 return 0; 2956 } 2957 2958 const struct clk_ops clk_alpha_pll_stromer_plus_ops = { 2959 .prepare = clk_alpha_pll_enable, 2960 .unprepare = clk_alpha_pll_disable, 2961 .is_enabled = clk_alpha_pll_is_enabled, 2962 .recalc_rate = clk_alpha_pll_recalc_rate, 2963 .determine_rate = clk_alpha_pll_stromer_determine_rate, 2964 .set_rate = clk_alpha_pll_stromer_plus_set_rate, 2965 }; 2966 EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops); 2967 2968 void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2969 const struct alpha_pll_config *config) 2970 { 2971 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2972 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2973 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2974 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2975 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2976 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2977 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2978 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); 2979 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2980 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2981 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2982 2983 /* Set operation mode to STANDBY */ 2984 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2985 } 2986 EXPORT_SYMBOL_GPL(clk_regera_pll_configure); 2987 2988 const struct clk_ops clk_alpha_pll_regera_ops = { 2989 .enable = clk_zonda_pll_enable, 2990 .disable = clk_zonda_pll_disable, 2991 .is_enabled = clk_alpha_pll_is_enabled, 2992 .recalc_rate = clk_trion_pll_recalc_rate, 2993 .determine_rate = clk_alpha_pll_determine_rate, 2994 .set_rate = clk_zonda_pll_set_rate, 2995 }; 2996 EXPORT_SYMBOL_GPL(clk_alpha_pll_regera_ops); 2997 2998 void qcom_clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap) 2999 { 3000 const struct clk_init_data *init = pll->clkr.hw.init; 3001 3002 switch (GET_PLL_TYPE(pll)) { 3003 case CLK_ALPHA_PLL_TYPE_LUCID_OLE: 3004 clk_lucid_ole_pll_configure(pll, regmap, pll->config); 3005 break; 3006 case CLK_ALPHA_PLL_TYPE_LUCID_EVO: 3007 clk_lucid_evo_pll_configure(pll, regmap, pll->config); 3008 break; 3009 case CLK_ALPHA_PLL_TYPE_TAYCAN_ELU: 3010 clk_taycan_elu_pll_configure(pll, regmap, pll->config); 3011 break; 3012 case CLK_ALPHA_PLL_TYPE_RIVIAN_EVO: 3013 case CLK_ALPHA_PLL_TYPE_RIVIAN_ELU: 3014 clk_rivian_evo_pll_configure(pll, regmap, pll->config); 3015 break; 3016 case CLK_ALPHA_PLL_TYPE_TRION: 3017 clk_trion_pll_configure(pll, regmap, pll->config); 3018 break; 3019 case CLK_ALPHA_PLL_TYPE_HUAYRA_2290: 3020 clk_huayra_2290_pll_configure(pll, regmap, pll->config); 3021 break; 3022 case CLK_ALPHA_PLL_TYPE_FABIA: 3023 clk_fabia_pll_configure(pll, regmap, pll->config); 3024 break; 3025 case CLK_ALPHA_PLL_TYPE_AGERA: 3026 clk_agera_pll_configure(pll, regmap, pll->config); 3027 break; 3028 case CLK_ALPHA_PLL_TYPE_PONGO_ELU: 3029 clk_pongo_elu_pll_configure(pll, regmap, pll->config); 3030 break; 3031 case CLK_ALPHA_PLL_TYPE_ZONDA: 3032 case CLK_ALPHA_PLL_TYPE_ZONDA_OLE: 3033 clk_zonda_pll_configure(pll, regmap, pll->config); 3034 break; 3035 case CLK_ALPHA_PLL_TYPE_STROMER: 3036 case CLK_ALPHA_PLL_TYPE_STROMER_PLUS: 3037 clk_stromer_pll_configure(pll, regmap, pll->config); 3038 break; 3039 case CLK_ALPHA_PLL_TYPE_DEFAULT: 3040 case CLK_ALPHA_PLL_TYPE_DEFAULT_EVO: 3041 case CLK_ALPHA_PLL_TYPE_HUAYRA: 3042 case CLK_ALPHA_PLL_TYPE_HUAYRA_APSS: 3043 case CLK_ALPHA_PLL_TYPE_BRAMMO: 3044 case CLK_ALPHA_PLL_TYPE_BRAMMO_EVO: 3045 clk_alpha_pll_configure(pll, regmap, pll->config); 3046 break; 3047 default: 3048 WARN(1, "%s: invalid pll type\n", init->name); 3049 break; 3050 } 3051 } 3052 EXPORT_SYMBOL_GPL(qcom_clk_alpha_pll_configure); 3053 3054 static int clk_alpha_pll_slew_update(struct clk_alpha_pll *pll) 3055 { 3056 u32 val; 3057 int ret; 3058 3059 regmap_set_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE); 3060 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 3061 3062 ret = wait_for_pll_update(pll); 3063 if (ret) 3064 return ret; 3065 /* 3066 * Hardware programming mandates a wait of at least 570ns before polling the LOCK 3067 * detect bit. Have a delay of 1us just to be safe. 3068 */ 3069 udelay(1); 3070 3071 return wait_for_pll_enable_lock(pll); 3072 } 3073 3074 static int clk_alpha_pll_slew_set_rate(struct clk_hw *hw, unsigned long rate, 3075 unsigned long parent_rate) 3076 { 3077 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 3078 const struct pll_vco *curr_vco, *vco; 3079 unsigned long freq_hz; 3080 u64 a; 3081 u32 l; 3082 3083 freq_hz = alpha_pll_round_rate(rate, parent_rate, &l, &a, ALPHA_REG_BITWIDTH); 3084 if (freq_hz != rate) { 3085 pr_err("alpha_pll: Call clk_set_rate with rounded rates!\n"); 3086 return -EINVAL; 3087 } 3088 3089 curr_vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); 3090 if (!curr_vco) { 3091 pr_err("alpha pll: not in a valid vco range\n"); 3092 return -EINVAL; 3093 } 3094 3095 vco = alpha_pll_find_vco(pll, freq_hz); 3096 if (!vco) { 3097 pr_err("alpha pll: not in a valid vco range\n"); 3098 return -EINVAL; 3099 } 3100 3101 /* 3102 * Dynamic pll update will not support switching frequencies across 3103 * vco ranges. In those cases fall back to normal alpha set rate. 3104 */ 3105 if (curr_vco->val != vco->val) 3106 return clk_alpha_pll_set_rate(hw, rate, parent_rate); 3107 3108 clk_alpha_pll_update_configs(pll, NULL, l, a, ALPHA_REG_BITWIDTH, false); 3109 3110 /* Ensure that the write above goes before slewing the PLL */ 3111 mb(); 3112 3113 if (clk_hw_is_enabled(hw)) 3114 return clk_alpha_pll_slew_update(pll); 3115 3116 return 0; 3117 } 3118 3119 /* 3120 * Slewing plls should be bought up at frequency which is in the middle of the 3121 * desired VCO range. So after bringing up the pll at calibration freq, set it 3122 * back to desired frequency(that was set by previous clk_set_rate). 3123 */ 3124 static int clk_alpha_pll_calibrate(struct clk_hw *hw) 3125 { 3126 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 3127 struct clk_hw *parent; 3128 const struct pll_vco *vco; 3129 unsigned long calibration_freq, freq_hz; 3130 u64 a; 3131 u32 l; 3132 int rc; 3133 3134 parent = clk_hw_get_parent(hw); 3135 if (!parent) { 3136 pr_err("alpha pll: no valid parent found\n"); 3137 return -EINVAL; 3138 } 3139 3140 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); 3141 if (!vco) { 3142 pr_err("alpha pll: not in a valid vco range\n"); 3143 return -EINVAL; 3144 } 3145 3146 /* 3147 * As during slewing plls vco_sel won't be allowed to change, vco table 3148 * should have only one entry table, i.e. index = 0, find the 3149 * calibration frequency. 3150 */ 3151 calibration_freq = (pll->vco_table[0].min_freq + pll->vco_table[0].max_freq) / 2; 3152 3153 freq_hz = alpha_pll_round_rate(calibration_freq, clk_hw_get_rate(parent), 3154 &l, &a, ALPHA_REG_BITWIDTH); 3155 if (freq_hz != calibration_freq) { 3156 pr_err("alpha_pll: call clk_set_rate with rounded rates!\n"); 3157 return -EINVAL; 3158 } 3159 3160 clk_alpha_pll_update_configs(pll, vco, l, a, ALPHA_REG_BITWIDTH, false); 3161 3162 /* Bringup the pll at calibration frequency */ 3163 rc = clk_alpha_pll_enable(hw); 3164 if (rc) { 3165 pr_err("alpha pll calibration failed\n"); 3166 return rc; 3167 } 3168 3169 /* 3170 * PLL is already running at calibration frequency. 3171 * So slew pll to the previously set frequency. 3172 */ 3173 freq_hz = alpha_pll_round_rate(clk_hw_get_rate(hw), 3174 clk_hw_get_rate(parent), &l, &a, ALPHA_REG_BITWIDTH); 3175 3176 pr_debug("pll %s: setting back to required rate %lu, freq_hz %ld\n", 3177 clk_hw_get_name(hw), clk_hw_get_rate(hw), freq_hz); 3178 3179 clk_alpha_pll_update_configs(pll, NULL, l, a, ALPHA_REG_BITWIDTH, true); 3180 3181 return clk_alpha_pll_slew_update(pll); 3182 } 3183 3184 static int clk_alpha_pll_slew_enable(struct clk_hw *hw) 3185 { 3186 int rc; 3187 3188 rc = clk_alpha_pll_calibrate(hw); 3189 if (rc) 3190 return rc; 3191 3192 return clk_alpha_pll_enable(hw); 3193 } 3194 3195 const struct clk_ops clk_alpha_pll_slew_ops = { 3196 .enable = clk_alpha_pll_slew_enable, 3197 .disable = clk_alpha_pll_disable, 3198 .recalc_rate = clk_alpha_pll_recalc_rate, 3199 .determine_rate = clk_alpha_pll_determine_rate, 3200 .set_rate = clk_alpha_pll_slew_set_rate, 3201 }; 3202 EXPORT_SYMBOL(clk_alpha_pll_slew_ops); 3203