1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,x1e80100-camcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "common.h" 19 #include "gdsc.h" 20 #include "reset.h" 21 22 enum { 23 DT_IFACE, 24 DT_BI_TCXO, 25 DT_BI_TCXO_AO, 26 DT_SLEEP_CLK, 27 }; 28 29 enum { 30 P_BI_TCXO, 31 P_BI_TCXO_AO, 32 P_CAM_CC_PLL0_OUT_EVEN, 33 P_CAM_CC_PLL0_OUT_MAIN, 34 P_CAM_CC_PLL0_OUT_ODD, 35 P_CAM_CC_PLL1_OUT_EVEN, 36 P_CAM_CC_PLL2_OUT_EVEN, 37 P_CAM_CC_PLL2_OUT_MAIN, 38 P_CAM_CC_PLL3_OUT_EVEN, 39 P_CAM_CC_PLL4_OUT_EVEN, 40 P_CAM_CC_PLL6_OUT_EVEN, 41 P_CAM_CC_PLL8_OUT_EVEN, 42 P_SLEEP_CLK, 43 }; 44 45 static const struct pll_vco lucid_ole_vco[] = { 46 { 249600000, 2300000000, 0 }, 47 }; 48 49 static const struct pll_vco rivian_ole_vco[] = { 50 { 777000000, 1285000000, 0 }, 51 }; 52 53 static const struct alpha_pll_config cam_cc_pll0_config = { 54 .l = 0x3e, 55 .alpha = 0x8000, 56 .config_ctl_val = 0x20485699, 57 .config_ctl_hi_val = 0x00182261, 58 .config_ctl_hi1_val = 0x82aa299c, 59 .test_ctl_val = 0x00000000, 60 .test_ctl_hi_val = 0x00000003, 61 .test_ctl_hi1_val = 0x00009000, 62 .test_ctl_hi2_val = 0x00000034, 63 .user_ctl_val = 0x00008400, 64 .user_ctl_hi_val = 0x00000005, 65 }; 66 67 static struct clk_alpha_pll cam_cc_pll0 = { 68 .offset = 0x0, 69 .config = &cam_cc_pll0_config, 70 .vco_table = lucid_ole_vco, 71 .num_vco = ARRAY_SIZE(lucid_ole_vco), 72 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 73 .clkr = { 74 .hw.init = &(const struct clk_init_data) { 75 .name = "cam_cc_pll0", 76 .parent_data = &(const struct clk_parent_data) { 77 .index = DT_BI_TCXO, 78 }, 79 .num_parents = 1, 80 .ops = &clk_alpha_pll_lucid_evo_ops, 81 }, 82 }, 83 }; 84 85 static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { 86 { 0x1, 2 }, 87 { } 88 }; 89 90 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { 91 .offset = 0x0, 92 .post_div_shift = 10, 93 .post_div_table = post_div_table_cam_cc_pll0_out_even, 94 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), 95 .width = 4, 96 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 97 .clkr.hw.init = &(const struct clk_init_data) { 98 .name = "cam_cc_pll0_out_even", 99 .parent_hws = (const struct clk_hw*[]) { 100 &cam_cc_pll0.clkr.hw, 101 }, 102 .num_parents = 1, 103 .flags = CLK_SET_RATE_PARENT, 104 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 105 }, 106 }; 107 108 static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { 109 { 0x2, 3 }, 110 { } 111 }; 112 113 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { 114 .offset = 0x0, 115 .post_div_shift = 14, 116 .post_div_table = post_div_table_cam_cc_pll0_out_odd, 117 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), 118 .width = 4, 119 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 120 .clkr.hw.init = &(const struct clk_init_data) { 121 .name = "cam_cc_pll0_out_odd", 122 .parent_hws = (const struct clk_hw*[]) { 123 &cam_cc_pll0.clkr.hw, 124 }, 125 .num_parents = 1, 126 .flags = CLK_SET_RATE_PARENT, 127 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 128 }, 129 }; 130 131 static const struct alpha_pll_config cam_cc_pll1_config = { 132 .l = 0x1f, 133 .alpha = 0xaaaa, 134 .config_ctl_val = 0x20485699, 135 .config_ctl_hi_val = 0x00182261, 136 .config_ctl_hi1_val = 0x82aa299c, 137 .test_ctl_val = 0x00000000, 138 .test_ctl_hi_val = 0x00000003, 139 .test_ctl_hi1_val = 0x00009000, 140 .test_ctl_hi2_val = 0x00000034, 141 .user_ctl_val = 0x00000400, 142 .user_ctl_hi_val = 0x00000005, 143 }; 144 145 static struct clk_alpha_pll cam_cc_pll1 = { 146 .offset = 0x1000, 147 .config = &cam_cc_pll1_config, 148 .vco_table = lucid_ole_vco, 149 .num_vco = ARRAY_SIZE(lucid_ole_vco), 150 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 151 .clkr = { 152 .hw.init = &(const struct clk_init_data) { 153 .name = "cam_cc_pll1", 154 .parent_data = &(const struct clk_parent_data) { 155 .index = DT_BI_TCXO, 156 }, 157 .num_parents = 1, 158 .ops = &clk_alpha_pll_lucid_evo_ops, 159 }, 160 }, 161 }; 162 163 static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { 164 { 0x1, 2 }, 165 { } 166 }; 167 168 static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { 169 .offset = 0x1000, 170 .post_div_shift = 10, 171 .post_div_table = post_div_table_cam_cc_pll1_out_even, 172 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), 173 .width = 4, 174 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 175 .clkr.hw.init = &(const struct clk_init_data) { 176 .name = "cam_cc_pll1_out_even", 177 .parent_hws = (const struct clk_hw*[]) { 178 &cam_cc_pll1.clkr.hw, 179 }, 180 .num_parents = 1, 181 .flags = CLK_SET_RATE_PARENT, 182 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 183 }, 184 }; 185 186 static const struct alpha_pll_config cam_cc_pll2_config = { 187 .l = 0x32, 188 .alpha = 0x0, 189 .config_ctl_val = 0x10000030, 190 .config_ctl_hi_val = 0x80890263, 191 .config_ctl_hi1_val = 0x00000217, 192 .user_ctl_val = 0x00000001, 193 .user_ctl_hi_val = 0x00000000, 194 }; 195 196 static struct clk_alpha_pll cam_cc_pll2 = { 197 .offset = 0x2000, 198 .config = &cam_cc_pll2_config, 199 .vco_table = rivian_ole_vco, 200 .num_vco = ARRAY_SIZE(rivian_ole_vco), 201 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], 202 .clkr = { 203 .hw.init = &(const struct clk_init_data) { 204 .name = "cam_cc_pll2", 205 .parent_data = &(const struct clk_parent_data) { 206 .index = DT_BI_TCXO, 207 }, 208 .num_parents = 1, 209 .ops = &clk_alpha_pll_rivian_evo_ops, 210 }, 211 }, 212 }; 213 214 static const struct alpha_pll_config cam_cc_pll3_config = { 215 .l = 0x24, 216 .alpha = 0x0, 217 .config_ctl_val = 0x20485699, 218 .config_ctl_hi_val = 0x00182261, 219 .config_ctl_hi1_val = 0x82aa299c, 220 .test_ctl_val = 0x00000000, 221 .test_ctl_hi_val = 0x00000003, 222 .test_ctl_hi1_val = 0x00009000, 223 .test_ctl_hi2_val = 0x00000034, 224 .user_ctl_val = 0x00000400, 225 .user_ctl_hi_val = 0x00000005, 226 }; 227 228 static struct clk_alpha_pll cam_cc_pll3 = { 229 .offset = 0x3000, 230 .config = &cam_cc_pll3_config, 231 .vco_table = lucid_ole_vco, 232 .num_vco = ARRAY_SIZE(lucid_ole_vco), 233 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 234 .clkr = { 235 .hw.init = &(const struct clk_init_data) { 236 .name = "cam_cc_pll3", 237 .parent_data = &(const struct clk_parent_data) { 238 .index = DT_BI_TCXO, 239 }, 240 .num_parents = 1, 241 .ops = &clk_alpha_pll_lucid_evo_ops, 242 }, 243 }, 244 }; 245 246 static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { 247 { 0x1, 2 }, 248 { } 249 }; 250 251 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 252 .offset = 0x3000, 253 .post_div_shift = 10, 254 .post_div_table = post_div_table_cam_cc_pll3_out_even, 255 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), 256 .width = 4, 257 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 258 .clkr.hw.init = &(const struct clk_init_data) { 259 .name = "cam_cc_pll3_out_even", 260 .parent_hws = (const struct clk_hw*[]) { 261 &cam_cc_pll3.clkr.hw, 262 }, 263 .num_parents = 1, 264 .flags = CLK_SET_RATE_PARENT, 265 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 266 }, 267 }; 268 269 static const struct alpha_pll_config cam_cc_pll4_config = { 270 .l = 0x24, 271 .alpha = 0x0, 272 .config_ctl_val = 0x20485699, 273 .config_ctl_hi_val = 0x00182261, 274 .config_ctl_hi1_val = 0x82aa299c, 275 .test_ctl_val = 0x00000000, 276 .test_ctl_hi_val = 0x00000003, 277 .test_ctl_hi1_val = 0x00009000, 278 .test_ctl_hi2_val = 0x00000034, 279 .user_ctl_val = 0x00000400, 280 .user_ctl_hi_val = 0x00000005, 281 }; 282 283 static struct clk_alpha_pll cam_cc_pll4 = { 284 .offset = 0x4000, 285 .config = &cam_cc_pll4_config, 286 .vco_table = lucid_ole_vco, 287 .num_vco = ARRAY_SIZE(lucid_ole_vco), 288 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 289 .clkr = { 290 .hw.init = &(const struct clk_init_data) { 291 .name = "cam_cc_pll4", 292 .parent_data = &(const struct clk_parent_data) { 293 .index = DT_BI_TCXO, 294 }, 295 .num_parents = 1, 296 .ops = &clk_alpha_pll_lucid_evo_ops, 297 }, 298 }, 299 }; 300 301 static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { 302 { 0x1, 2 }, 303 { } 304 }; 305 306 static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { 307 .offset = 0x4000, 308 .post_div_shift = 10, 309 .post_div_table = post_div_table_cam_cc_pll4_out_even, 310 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), 311 .width = 4, 312 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 313 .clkr.hw.init = &(const struct clk_init_data) { 314 .name = "cam_cc_pll4_out_even", 315 .parent_hws = (const struct clk_hw*[]) { 316 &cam_cc_pll4.clkr.hw, 317 }, 318 .num_parents = 1, 319 .flags = CLK_SET_RATE_PARENT, 320 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 321 }, 322 }; 323 324 static const struct alpha_pll_config cam_cc_pll6_config = { 325 .l = 0x24, 326 .alpha = 0x0, 327 .config_ctl_val = 0x20485699, 328 .config_ctl_hi_val = 0x00182261, 329 .config_ctl_hi1_val = 0x82aa299c, 330 .test_ctl_val = 0x00000000, 331 .test_ctl_hi_val = 0x00000003, 332 .test_ctl_hi1_val = 0x00009000, 333 .test_ctl_hi2_val = 0x00000034, 334 .user_ctl_val = 0x00000400, 335 .user_ctl_hi_val = 0x00000005, 336 }; 337 338 static struct clk_alpha_pll cam_cc_pll6 = { 339 .offset = 0x6000, 340 .config = &cam_cc_pll6_config, 341 .vco_table = lucid_ole_vco, 342 .num_vco = ARRAY_SIZE(lucid_ole_vco), 343 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 344 .clkr = { 345 .hw.init = &(const struct clk_init_data) { 346 .name = "cam_cc_pll6", 347 .parent_data = &(const struct clk_parent_data) { 348 .index = DT_BI_TCXO, 349 }, 350 .num_parents = 1, 351 .ops = &clk_alpha_pll_lucid_evo_ops, 352 }, 353 }, 354 }; 355 356 static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { 357 { 0x1, 2 }, 358 { } 359 }; 360 361 static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { 362 .offset = 0x6000, 363 .post_div_shift = 10, 364 .post_div_table = post_div_table_cam_cc_pll6_out_even, 365 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), 366 .width = 4, 367 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 368 .clkr.hw.init = &(const struct clk_init_data) { 369 .name = "cam_cc_pll6_out_even", 370 .parent_hws = (const struct clk_hw*[]) { 371 &cam_cc_pll6.clkr.hw, 372 }, 373 .num_parents = 1, 374 .flags = CLK_SET_RATE_PARENT, 375 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 376 }, 377 }; 378 379 static const struct alpha_pll_config cam_cc_pll8_config = { 380 .l = 0x32, 381 .alpha = 0x0, 382 .config_ctl_val = 0x20485699, 383 .config_ctl_hi_val = 0x00182261, 384 .config_ctl_hi1_val = 0x82aa299c, 385 .test_ctl_val = 0x00000000, 386 .test_ctl_hi_val = 0x00000003, 387 .test_ctl_hi1_val = 0x00009000, 388 .test_ctl_hi2_val = 0x00000034, 389 .user_ctl_val = 0x00000400, 390 .user_ctl_hi_val = 0x00000005, 391 }; 392 393 static struct clk_alpha_pll cam_cc_pll8 = { 394 .offset = 0x8000, 395 .config = &cam_cc_pll8_config, 396 .vco_table = lucid_ole_vco, 397 .num_vco = ARRAY_SIZE(lucid_ole_vco), 398 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 399 .clkr = { 400 .hw.init = &(const struct clk_init_data) { 401 .name = "cam_cc_pll8", 402 .parent_data = &(const struct clk_parent_data) { 403 .index = DT_BI_TCXO, 404 }, 405 .num_parents = 1, 406 .ops = &clk_alpha_pll_lucid_evo_ops, 407 }, 408 }, 409 }; 410 411 static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = { 412 { 0x1, 2 }, 413 { } 414 }; 415 416 static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = { 417 .offset = 0x8000, 418 .post_div_shift = 10, 419 .post_div_table = post_div_table_cam_cc_pll8_out_even, 420 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll8_out_even), 421 .width = 4, 422 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 423 .clkr.hw.init = &(const struct clk_init_data) { 424 .name = "cam_cc_pll8_out_even", 425 .parent_hws = (const struct clk_hw*[]) { 426 &cam_cc_pll8.clkr.hw, 427 }, 428 .num_parents = 1, 429 .flags = CLK_SET_RATE_PARENT, 430 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 431 }, 432 }; 433 434 static const struct parent_map cam_cc_parent_map_0[] = { 435 { P_BI_TCXO, 0 }, 436 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 437 { P_CAM_CC_PLL0_OUT_EVEN, 2 }, 438 { P_CAM_CC_PLL0_OUT_ODD, 3 }, 439 { P_CAM_CC_PLL8_OUT_EVEN, 5 }, 440 }; 441 442 static const struct clk_parent_data cam_cc_parent_data_0[] = { 443 { .index = DT_BI_TCXO }, 444 { .hw = &cam_cc_pll0.clkr.hw }, 445 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 446 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 447 { .hw = &cam_cc_pll8_out_even.clkr.hw }, 448 }; 449 450 static const struct parent_map cam_cc_parent_map_1[] = { 451 { P_BI_TCXO, 0 }, 452 { P_CAM_CC_PLL2_OUT_EVEN, 3 }, 453 { P_CAM_CC_PLL2_OUT_MAIN, 5 }, 454 }; 455 456 static const struct clk_parent_data cam_cc_parent_data_1[] = { 457 { .index = DT_BI_TCXO }, 458 { .hw = &cam_cc_pll2.clkr.hw }, 459 { .hw = &cam_cc_pll2.clkr.hw }, 460 }; 461 462 static const struct parent_map cam_cc_parent_map_2[] = { 463 { P_BI_TCXO, 0 }, 464 { P_CAM_CC_PLL3_OUT_EVEN, 6 }, 465 }; 466 467 static const struct clk_parent_data cam_cc_parent_data_2[] = { 468 { .index = DT_BI_TCXO }, 469 { .hw = &cam_cc_pll3_out_even.clkr.hw }, 470 }; 471 472 static const struct parent_map cam_cc_parent_map_3[] = { 473 { P_BI_TCXO, 0 }, 474 { P_CAM_CC_PLL4_OUT_EVEN, 6 }, 475 }; 476 477 static const struct clk_parent_data cam_cc_parent_data_3[] = { 478 { .index = DT_BI_TCXO }, 479 { .hw = &cam_cc_pll4_out_even.clkr.hw }, 480 }; 481 482 static const struct parent_map cam_cc_parent_map_4[] = { 483 { P_BI_TCXO, 0 }, 484 { P_CAM_CC_PLL1_OUT_EVEN, 4 }, 485 }; 486 487 static const struct clk_parent_data cam_cc_parent_data_4[] = { 488 { .index = DT_BI_TCXO }, 489 { .hw = &cam_cc_pll1_out_even.clkr.hw }, 490 }; 491 492 static const struct parent_map cam_cc_parent_map_5[] = { 493 { P_BI_TCXO, 0 }, 494 { P_CAM_CC_PLL6_OUT_EVEN, 6 }, 495 }; 496 497 static const struct clk_parent_data cam_cc_parent_data_5[] = { 498 { .index = DT_BI_TCXO }, 499 { .hw = &cam_cc_pll6_out_even.clkr.hw }, 500 }; 501 502 static const struct parent_map cam_cc_parent_map_6[] = { 503 { P_SLEEP_CLK, 0 }, 504 }; 505 506 static const struct clk_parent_data cam_cc_parent_data_6_ao[] = { 507 { .index = DT_SLEEP_CLK }, 508 }; 509 510 static const struct parent_map cam_cc_parent_map_7[] = { 511 { P_BI_TCXO, 0 }, 512 }; 513 514 static const struct clk_parent_data cam_cc_parent_data_7_ao[] = { 515 { .index = DT_BI_TCXO_AO }, 516 }; 517 518 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { 519 F(19200000, P_BI_TCXO, 1, 0, 0), 520 F(160000000, P_CAM_CC_PLL0_OUT_ODD, 2.5, 0, 0), 521 F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), 522 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 523 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 524 { } 525 }; 526 527 static struct clk_rcg2 cam_cc_bps_clk_src = { 528 .cmd_rcgr = 0x10278, 529 .mnd_width = 0, 530 .hid_width = 5, 531 .parent_map = cam_cc_parent_map_0, 532 .freq_tbl = ftbl_cam_cc_bps_clk_src, 533 .clkr.hw.init = &(const struct clk_init_data) { 534 .name = "cam_cc_bps_clk_src", 535 .parent_data = cam_cc_parent_data_0, 536 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 537 .flags = CLK_SET_RATE_PARENT, 538 .ops = &clk_rcg2_shared_ops, 539 }, 540 }; 541 542 static const struct freq_tbl ftbl_cam_cc_camnoc_axi_rt_clk_src[] = { 543 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), 544 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 545 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 546 { } 547 }; 548 549 static struct clk_rcg2 cam_cc_camnoc_axi_rt_clk_src = { 550 .cmd_rcgr = 0x138f8, 551 .mnd_width = 0, 552 .hid_width = 5, 553 .parent_map = cam_cc_parent_map_0, 554 .freq_tbl = ftbl_cam_cc_camnoc_axi_rt_clk_src, 555 .clkr.hw.init = &(const struct clk_init_data) { 556 .name = "cam_cc_camnoc_axi_rt_clk_src", 557 .parent_data = cam_cc_parent_data_0, 558 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 559 .flags = CLK_SET_RATE_PARENT, 560 .ops = &clk_rcg2_shared_ops, 561 }, 562 }; 563 564 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { 565 F(19200000, P_BI_TCXO, 1, 0, 0), 566 F(30000000, P_CAM_CC_PLL8_OUT_EVEN, 16, 0, 0), 567 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 568 { } 569 }; 570 571 static struct clk_rcg2 cam_cc_cci_0_clk_src = { 572 .cmd_rcgr = 0x1365c, 573 .mnd_width = 8, 574 .hid_width = 5, 575 .parent_map = cam_cc_parent_map_0, 576 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 577 .clkr.hw.init = &(const struct clk_init_data) { 578 .name = "cam_cc_cci_0_clk_src", 579 .parent_data = cam_cc_parent_data_0, 580 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 581 .flags = CLK_SET_RATE_PARENT, 582 .ops = &clk_rcg2_ops, 583 }, 584 }; 585 586 static struct clk_rcg2 cam_cc_cci_1_clk_src = { 587 .cmd_rcgr = 0x1378c, 588 .mnd_width = 8, 589 .hid_width = 5, 590 .parent_map = cam_cc_parent_map_0, 591 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 592 .clkr.hw.init = &(const struct clk_init_data) { 593 .name = "cam_cc_cci_1_clk_src", 594 .parent_data = cam_cc_parent_data_0, 595 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 596 .flags = CLK_SET_RATE_PARENT, 597 .ops = &clk_rcg2_ops, 598 }, 599 }; 600 601 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 602 F(19200000, P_BI_TCXO, 1, 0, 0), 603 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), 604 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 605 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 606 { } 607 }; 608 609 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 610 .cmd_rcgr = 0x11164, 611 .mnd_width = 0, 612 .hid_width = 5, 613 .parent_map = cam_cc_parent_map_0, 614 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 615 .clkr.hw.init = &(const struct clk_init_data) { 616 .name = "cam_cc_cphy_rx_clk_src", 617 .parent_data = cam_cc_parent_data_0, 618 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 619 .flags = CLK_SET_RATE_PARENT, 620 .ops = &clk_rcg2_ops, 621 }, 622 }; 623 624 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 625 F(19200000, P_BI_TCXO, 1, 0, 0), 626 F(266666667, P_CAM_CC_PLL0_OUT_ODD, 1.5, 0, 0), 627 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 628 { } 629 }; 630 631 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 632 .cmd_rcgr = 0x150e0, 633 .mnd_width = 0, 634 .hid_width = 5, 635 .parent_map = cam_cc_parent_map_0, 636 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 637 .clkr.hw.init = &(const struct clk_init_data) { 638 .name = "cam_cc_csi0phytimer_clk_src", 639 .parent_data = cam_cc_parent_data_0, 640 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 641 .flags = CLK_SET_RATE_PARENT, 642 .ops = &clk_rcg2_ops, 643 }, 644 }; 645 646 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 647 .cmd_rcgr = 0x15104, 648 .mnd_width = 0, 649 .hid_width = 5, 650 .parent_map = cam_cc_parent_map_0, 651 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 652 .clkr.hw.init = &(const struct clk_init_data) { 653 .name = "cam_cc_csi1phytimer_clk_src", 654 .parent_data = cam_cc_parent_data_0, 655 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 656 .flags = CLK_SET_RATE_PARENT, 657 .ops = &clk_rcg2_ops, 658 }, 659 }; 660 661 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 662 .cmd_rcgr = 0x15124, 663 .mnd_width = 0, 664 .hid_width = 5, 665 .parent_map = cam_cc_parent_map_0, 666 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 667 .clkr.hw.init = &(const struct clk_init_data) { 668 .name = "cam_cc_csi2phytimer_clk_src", 669 .parent_data = cam_cc_parent_data_0, 670 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 671 .flags = CLK_SET_RATE_PARENT, 672 .ops = &clk_rcg2_ops, 673 }, 674 }; 675 676 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 677 .cmd_rcgr = 0x15258, 678 .mnd_width = 0, 679 .hid_width = 5, 680 .parent_map = cam_cc_parent_map_0, 681 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 682 .clkr.hw.init = &(const struct clk_init_data) { 683 .name = "cam_cc_csi3phytimer_clk_src", 684 .parent_data = cam_cc_parent_data_0, 685 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 686 .flags = CLK_SET_RATE_PARENT, 687 .ops = &clk_rcg2_ops, 688 }, 689 }; 690 691 static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { 692 .cmd_rcgr = 0x1538c, 693 .mnd_width = 0, 694 .hid_width = 5, 695 .parent_map = cam_cc_parent_map_0, 696 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 697 .clkr.hw.init = &(const struct clk_init_data) { 698 .name = "cam_cc_csi4phytimer_clk_src", 699 .parent_data = cam_cc_parent_data_0, 700 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 701 .flags = CLK_SET_RATE_PARENT, 702 .ops = &clk_rcg2_ops, 703 }, 704 }; 705 706 static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = { 707 .cmd_rcgr = 0x154c0, 708 .mnd_width = 0, 709 .hid_width = 5, 710 .parent_map = cam_cc_parent_map_0, 711 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 712 .clkr.hw.init = &(const struct clk_init_data) { 713 .name = "cam_cc_csi5phytimer_clk_src", 714 .parent_data = cam_cc_parent_data_0, 715 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 716 .flags = CLK_SET_RATE_PARENT, 717 .ops = &clk_rcg2_ops, 718 }, 719 }; 720 721 static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = { 722 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), 723 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 724 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 725 { } 726 }; 727 728 static struct clk_rcg2 cam_cc_csid_clk_src = { 729 .cmd_rcgr = 0x138d4, 730 .mnd_width = 0, 731 .hid_width = 5, 732 .parent_map = cam_cc_parent_map_0, 733 .freq_tbl = ftbl_cam_cc_csid_clk_src, 734 .clkr.hw.init = &(const struct clk_init_data) { 735 .name = "cam_cc_csid_clk_src", 736 .parent_data = cam_cc_parent_data_0, 737 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 738 .flags = CLK_SET_RATE_PARENT, 739 .ops = &clk_rcg2_shared_ops, 740 }, 741 }; 742 743 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 744 F(19200000, P_BI_TCXO, 1, 0, 0), 745 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 746 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 747 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 748 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), 749 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 750 { } 751 }; 752 753 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 754 .cmd_rcgr = 0x10018, 755 .mnd_width = 0, 756 .hid_width = 5, 757 .parent_map = cam_cc_parent_map_0, 758 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 759 .clkr.hw.init = &(const struct clk_init_data) { 760 .name = "cam_cc_fast_ahb_clk_src", 761 .parent_data = cam_cc_parent_data_0, 762 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 763 .flags = CLK_SET_RATE_PARENT, 764 .ops = &clk_rcg2_shared_ops, 765 }, 766 }; 767 768 static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 769 F(19200000, P_BI_TCXO, 1, 0, 0), 770 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 771 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 772 F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), 773 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 774 { } 775 }; 776 777 static struct clk_rcg2 cam_cc_icp_clk_src = { 778 .cmd_rcgr = 0x13520, 779 .mnd_width = 0, 780 .hid_width = 5, 781 .parent_map = cam_cc_parent_map_0, 782 .freq_tbl = ftbl_cam_cc_icp_clk_src, 783 .clkr.hw.init = &(const struct clk_init_data) { 784 .name = "cam_cc_icp_clk_src", 785 .parent_data = cam_cc_parent_data_0, 786 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 787 .flags = CLK_SET_RATE_PARENT, 788 .ops = &clk_rcg2_shared_ops, 789 }, 790 }; 791 792 static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { 793 F(19200000, P_BI_TCXO, 1, 0, 0), 794 F(345600000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 795 F(432000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 796 F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 797 F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 798 F(727000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 799 { } 800 }; 801 802 static struct clk_rcg2 cam_cc_ife_0_clk_src = { 803 .cmd_rcgr = 0x11018, 804 .mnd_width = 0, 805 .hid_width = 5, 806 .parent_map = cam_cc_parent_map_2, 807 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 808 .clkr.hw.init = &(const struct clk_init_data) { 809 .name = "cam_cc_ife_0_clk_src", 810 .parent_data = cam_cc_parent_data_2, 811 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 812 .flags = CLK_SET_RATE_PARENT, 813 .ops = &clk_rcg2_shared_ops, 814 }, 815 }; 816 817 static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = { 818 F(19200000, P_BI_TCXO, 1, 0, 0), 819 F(345600000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 820 F(432000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 821 F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 822 F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 823 F(727000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 824 { } 825 }; 826 827 static struct clk_rcg2 cam_cc_ife_1_clk_src = { 828 .cmd_rcgr = 0x12018, 829 .mnd_width = 0, 830 .hid_width = 5, 831 .parent_map = cam_cc_parent_map_3, 832 .freq_tbl = ftbl_cam_cc_ife_1_clk_src, 833 .clkr.hw.init = &(const struct clk_init_data) { 834 .name = "cam_cc_ife_1_clk_src", 835 .parent_data = cam_cc_parent_data_3, 836 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 837 .flags = CLK_SET_RATE_PARENT, 838 .ops = &clk_rcg2_shared_ops, 839 }, 840 }; 841 842 static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = { 843 F(266666667, P_CAM_CC_PLL0_OUT_ODD, 1.5, 0, 0), 844 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 845 F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), 846 { } 847 }; 848 849 static struct clk_rcg2 cam_cc_ife_lite_clk_src = { 850 .cmd_rcgr = 0x13000, 851 .mnd_width = 0, 852 .hid_width = 5, 853 .parent_map = cam_cc_parent_map_0, 854 .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, 855 .clkr.hw.init = &(const struct clk_init_data) { 856 .name = "cam_cc_ife_lite_clk_src", 857 .parent_data = cam_cc_parent_data_0, 858 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 859 .flags = CLK_SET_RATE_PARENT, 860 .ops = &clk_rcg2_shared_ops, 861 }, 862 }; 863 864 static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { 865 .cmd_rcgr = 0x1313c, 866 .mnd_width = 0, 867 .hid_width = 5, 868 .parent_map = cam_cc_parent_map_0, 869 .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, 870 .clkr.hw.init = &(const struct clk_init_data) { 871 .name = "cam_cc_ife_lite_csid_clk_src", 872 .parent_data = cam_cc_parent_data_0, 873 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 874 .flags = CLK_SET_RATE_PARENT, 875 .ops = &clk_rcg2_shared_ops, 876 }, 877 }; 878 879 static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = { 880 F(304000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 881 F(364000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 882 F(500000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 883 F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 884 F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 885 { } 886 }; 887 888 static struct clk_rcg2 cam_cc_ipe_nps_clk_src = { 889 .cmd_rcgr = 0x103cc, 890 .mnd_width = 0, 891 .hid_width = 5, 892 .parent_map = cam_cc_parent_map_4, 893 .freq_tbl = ftbl_cam_cc_ipe_nps_clk_src, 894 .clkr.hw.init = &(const struct clk_init_data) { 895 .name = "cam_cc_ipe_nps_clk_src", 896 .parent_data = cam_cc_parent_data_4, 897 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 898 .flags = CLK_SET_RATE_PARENT, 899 .ops = &clk_rcg2_shared_ops, 900 }, 901 }; 902 903 static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = { 904 F(19200000, P_BI_TCXO, 1, 0, 0), 905 F(160000000, P_CAM_CC_PLL0_OUT_ODD, 2.5, 0, 0), 906 F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), 907 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 908 F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), 909 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 910 { } 911 }; 912 913 static struct clk_rcg2 cam_cc_jpeg_clk_src = { 914 .cmd_rcgr = 0x133dc, 915 .mnd_width = 0, 916 .hid_width = 5, 917 .parent_map = cam_cc_parent_map_0, 918 .freq_tbl = ftbl_cam_cc_jpeg_clk_src, 919 .clkr.hw.init = &(const struct clk_init_data) { 920 .name = "cam_cc_jpeg_clk_src", 921 .parent_data = cam_cc_parent_data_0, 922 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 923 .flags = CLK_SET_RATE_PARENT, 924 .ops = &clk_rcg2_shared_ops, 925 }, 926 }; 927 928 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 929 F(19200000, P_BI_TCXO, 1, 0, 0), 930 F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4), 931 F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0), 932 { } 933 }; 934 935 static struct clk_rcg2 cam_cc_mclk0_clk_src = { 936 .cmd_rcgr = 0x15000, 937 .mnd_width = 8, 938 .hid_width = 5, 939 .parent_map = cam_cc_parent_map_1, 940 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 941 .clkr.hw.init = &(const struct clk_init_data) { 942 .name = "cam_cc_mclk0_clk_src", 943 .parent_data = cam_cc_parent_data_1, 944 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 945 .flags = CLK_SET_RATE_PARENT, 946 .ops = &clk_rcg2_ops, 947 }, 948 }; 949 950 static struct clk_rcg2 cam_cc_mclk1_clk_src = { 951 .cmd_rcgr = 0x1501c, 952 .mnd_width = 8, 953 .hid_width = 5, 954 .parent_map = cam_cc_parent_map_1, 955 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 956 .clkr.hw.init = &(const struct clk_init_data) { 957 .name = "cam_cc_mclk1_clk_src", 958 .parent_data = cam_cc_parent_data_1, 959 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 960 .flags = CLK_SET_RATE_PARENT, 961 .ops = &clk_rcg2_ops, 962 }, 963 }; 964 965 static struct clk_rcg2 cam_cc_mclk2_clk_src = { 966 .cmd_rcgr = 0x15038, 967 .mnd_width = 8, 968 .hid_width = 5, 969 .parent_map = cam_cc_parent_map_1, 970 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 971 .clkr.hw.init = &(const struct clk_init_data) { 972 .name = "cam_cc_mclk2_clk_src", 973 .parent_data = cam_cc_parent_data_1, 974 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 975 .flags = CLK_SET_RATE_PARENT, 976 .ops = &clk_rcg2_ops, 977 }, 978 }; 979 980 static struct clk_rcg2 cam_cc_mclk3_clk_src = { 981 .cmd_rcgr = 0x15054, 982 .mnd_width = 8, 983 .hid_width = 5, 984 .parent_map = cam_cc_parent_map_1, 985 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 986 .clkr.hw.init = &(const struct clk_init_data) { 987 .name = "cam_cc_mclk3_clk_src", 988 .parent_data = cam_cc_parent_data_1, 989 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 990 .flags = CLK_SET_RATE_PARENT, 991 .ops = &clk_rcg2_ops, 992 }, 993 }; 994 995 static struct clk_rcg2 cam_cc_mclk4_clk_src = { 996 .cmd_rcgr = 0x15070, 997 .mnd_width = 8, 998 .hid_width = 5, 999 .parent_map = cam_cc_parent_map_1, 1000 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1001 .clkr.hw.init = &(const struct clk_init_data) { 1002 .name = "cam_cc_mclk4_clk_src", 1003 .parent_data = cam_cc_parent_data_1, 1004 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1005 .flags = CLK_SET_RATE_PARENT, 1006 .ops = &clk_rcg2_ops, 1007 }, 1008 }; 1009 1010 static struct clk_rcg2 cam_cc_mclk5_clk_src = { 1011 .cmd_rcgr = 0x1508c, 1012 .mnd_width = 8, 1013 .hid_width = 5, 1014 .parent_map = cam_cc_parent_map_1, 1015 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1016 .clkr.hw.init = &(const struct clk_init_data) { 1017 .name = "cam_cc_mclk5_clk_src", 1018 .parent_data = cam_cc_parent_data_1, 1019 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1020 .flags = CLK_SET_RATE_PARENT, 1021 .ops = &clk_rcg2_ops, 1022 }, 1023 }; 1024 1025 static struct clk_rcg2 cam_cc_mclk6_clk_src = { 1026 .cmd_rcgr = 0x150a8, 1027 .mnd_width = 8, 1028 .hid_width = 5, 1029 .parent_map = cam_cc_parent_map_1, 1030 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1031 .clkr.hw.init = &(const struct clk_init_data) { 1032 .name = "cam_cc_mclk6_clk_src", 1033 .parent_data = cam_cc_parent_data_1, 1034 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1035 .flags = CLK_SET_RATE_PARENT, 1036 .ops = &clk_rcg2_ops, 1037 }, 1038 }; 1039 1040 static struct clk_rcg2 cam_cc_mclk7_clk_src = { 1041 .cmd_rcgr = 0x150c4, 1042 .mnd_width = 8, 1043 .hid_width = 5, 1044 .parent_map = cam_cc_parent_map_1, 1045 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1046 .clkr.hw.init = &(const struct clk_init_data) { 1047 .name = "cam_cc_mclk7_clk_src", 1048 .parent_data = cam_cc_parent_data_1, 1049 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1050 .flags = CLK_SET_RATE_PARENT, 1051 .ops = &clk_rcg2_ops, 1052 }, 1053 }; 1054 1055 static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = { 1056 F(345600000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1057 F(432000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1058 F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1059 F(675000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1060 F(727000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1061 { } 1062 }; 1063 1064 static struct clk_rcg2 cam_cc_sfe_0_clk_src = { 1065 .cmd_rcgr = 0x13294, 1066 .mnd_width = 0, 1067 .hid_width = 5, 1068 .parent_map = cam_cc_parent_map_5, 1069 .freq_tbl = ftbl_cam_cc_sfe_0_clk_src, 1070 .clkr.hw.init = &(const struct clk_init_data) { 1071 .name = "cam_cc_sfe_0_clk_src", 1072 .parent_data = cam_cc_parent_data_5, 1073 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 1074 .flags = CLK_SET_RATE_PARENT, 1075 .ops = &clk_rcg2_shared_ops, 1076 }, 1077 }; 1078 1079 static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { 1080 F(32000, P_SLEEP_CLK, 1, 0, 0), 1081 { } 1082 }; 1083 1084 static struct clk_rcg2 cam_cc_sleep_clk_src = { 1085 .cmd_rcgr = 0x13aa0, 1086 .mnd_width = 0, 1087 .hid_width = 5, 1088 .parent_map = cam_cc_parent_map_6, 1089 .freq_tbl = ftbl_cam_cc_sleep_clk_src, 1090 .clkr.hw.init = &(const struct clk_init_data) { 1091 .name = "cam_cc_sleep_clk_src", 1092 .parent_data = cam_cc_parent_data_6_ao, 1093 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6_ao), 1094 .flags = CLK_SET_RATE_PARENT, 1095 .ops = &clk_rcg2_ops, 1096 }, 1097 }; 1098 1099 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 1100 F(19200000, P_BI_TCXO, 1, 0, 0), 1101 F(64000000, P_CAM_CC_PLL8_OUT_EVEN, 7.5, 0, 0), 1102 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 1103 { } 1104 }; 1105 1106 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 1107 .cmd_rcgr = 0x10148, 1108 .mnd_width = 8, 1109 .hid_width = 5, 1110 .parent_map = cam_cc_parent_map_0, 1111 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 1112 .clkr.hw.init = &(const struct clk_init_data) { 1113 .name = "cam_cc_slow_ahb_clk_src", 1114 .parent_data = cam_cc_parent_data_0, 1115 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 1116 .flags = CLK_SET_RATE_PARENT, 1117 .ops = &clk_rcg2_shared_ops, 1118 }, 1119 }; 1120 1121 static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { 1122 F(19200000, P_BI_TCXO, 1, 0, 0), 1123 { } 1124 }; 1125 1126 static struct clk_rcg2 cam_cc_xo_clk_src = { 1127 .cmd_rcgr = 0x13a84, 1128 .mnd_width = 0, 1129 .hid_width = 5, 1130 .parent_map = cam_cc_parent_map_7, 1131 .freq_tbl = ftbl_cam_cc_xo_clk_src, 1132 .clkr.hw.init = &(const struct clk_init_data) { 1133 .name = "cam_cc_xo_clk_src", 1134 .parent_data = cam_cc_parent_data_7_ao, 1135 .num_parents = ARRAY_SIZE(cam_cc_parent_data_7_ao), 1136 .flags = CLK_SET_RATE_PARENT, 1137 .ops = &clk_rcg2_ops, 1138 }, 1139 }; 1140 1141 static struct clk_branch cam_cc_bps_ahb_clk = { 1142 .halt_reg = 0x10274, 1143 .halt_check = BRANCH_HALT, 1144 .clkr = { 1145 .enable_reg = 0x10274, 1146 .enable_mask = BIT(0), 1147 .hw.init = &(const struct clk_init_data) { 1148 .name = "cam_cc_bps_ahb_clk", 1149 .parent_hws = (const struct clk_hw*[]) { 1150 &cam_cc_slow_ahb_clk_src.clkr.hw, 1151 }, 1152 .num_parents = 1, 1153 .flags = CLK_SET_RATE_PARENT, 1154 .ops = &clk_branch2_ops, 1155 }, 1156 }, 1157 }; 1158 1159 static struct clk_branch cam_cc_bps_clk = { 1160 .halt_reg = 0x103a4, 1161 .halt_check = BRANCH_HALT, 1162 .clkr = { 1163 .enable_reg = 0x103a4, 1164 .enable_mask = BIT(0), 1165 .hw.init = &(const struct clk_init_data) { 1166 .name = "cam_cc_bps_clk", 1167 .parent_hws = (const struct clk_hw*[]) { 1168 &cam_cc_bps_clk_src.clkr.hw, 1169 }, 1170 .num_parents = 1, 1171 .flags = CLK_SET_RATE_PARENT, 1172 .ops = &clk_branch2_ops, 1173 }, 1174 }, 1175 }; 1176 1177 static struct clk_branch cam_cc_bps_fast_ahb_clk = { 1178 .halt_reg = 0x10144, 1179 .halt_check = BRANCH_HALT, 1180 .clkr = { 1181 .enable_reg = 0x10144, 1182 .enable_mask = BIT(0), 1183 .hw.init = &(const struct clk_init_data) { 1184 .name = "cam_cc_bps_fast_ahb_clk", 1185 .parent_hws = (const struct clk_hw*[]) { 1186 &cam_cc_fast_ahb_clk_src.clkr.hw, 1187 }, 1188 .num_parents = 1, 1189 .flags = CLK_SET_RATE_PARENT, 1190 .ops = &clk_branch2_ops, 1191 }, 1192 }, 1193 }; 1194 1195 static struct clk_branch cam_cc_camnoc_axi_nrt_clk = { 1196 .halt_reg = 0x13920, 1197 .halt_check = BRANCH_HALT, 1198 .clkr = { 1199 .enable_reg = 0x13920, 1200 .enable_mask = BIT(0), 1201 .hw.init = &(const struct clk_init_data) { 1202 .name = "cam_cc_camnoc_axi_nrt_clk", 1203 .parent_hws = (const struct clk_hw*[]) { 1204 &cam_cc_camnoc_axi_rt_clk_src.clkr.hw, 1205 }, 1206 .num_parents = 1, 1207 .flags = CLK_SET_RATE_PARENT, 1208 .ops = &clk_branch2_ops, 1209 }, 1210 }, 1211 }; 1212 1213 static struct clk_branch cam_cc_camnoc_axi_rt_clk = { 1214 .halt_reg = 0x13910, 1215 .halt_check = BRANCH_HALT, 1216 .clkr = { 1217 .enable_reg = 0x13910, 1218 .enable_mask = BIT(0), 1219 .hw.init = &(const struct clk_init_data) { 1220 .name = "cam_cc_camnoc_axi_rt_clk", 1221 .parent_hws = (const struct clk_hw*[]) { 1222 &cam_cc_camnoc_axi_rt_clk_src.clkr.hw, 1223 }, 1224 .num_parents = 1, 1225 .flags = CLK_SET_RATE_PARENT, 1226 .ops = &clk_branch2_ops, 1227 }, 1228 }, 1229 }; 1230 1231 static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { 1232 .halt_reg = 0x1392c, 1233 .halt_check = BRANCH_HALT, 1234 .clkr = { 1235 .enable_reg = 0x1392c, 1236 .enable_mask = BIT(0), 1237 .hw.init = &(const struct clk_init_data) { 1238 .name = "cam_cc_camnoc_dcd_xo_clk", 1239 .parent_hws = (const struct clk_hw*[]) { 1240 &cam_cc_xo_clk_src.clkr.hw, 1241 }, 1242 .num_parents = 1, 1243 .flags = CLK_SET_RATE_PARENT, 1244 .ops = &clk_branch2_ops, 1245 }, 1246 }, 1247 }; 1248 1249 static struct clk_branch cam_cc_camnoc_xo_clk = { 1250 .halt_reg = 0x13930, 1251 .halt_check = BRANCH_HALT, 1252 .clkr = { 1253 .enable_reg = 0x13930, 1254 .enable_mask = BIT(0), 1255 .hw.init = &(const struct clk_init_data) { 1256 .name = "cam_cc_camnoc_xo_clk", 1257 .parent_hws = (const struct clk_hw*[]) { 1258 &cam_cc_xo_clk_src.clkr.hw, 1259 }, 1260 .num_parents = 1, 1261 .flags = CLK_SET_RATE_PARENT, 1262 .ops = &clk_branch2_ops, 1263 }, 1264 }, 1265 }; 1266 1267 static struct clk_branch cam_cc_cci_0_clk = { 1268 .halt_reg = 0x13788, 1269 .halt_check = BRANCH_HALT, 1270 .clkr = { 1271 .enable_reg = 0x13788, 1272 .enable_mask = BIT(0), 1273 .hw.init = &(const struct clk_init_data) { 1274 .name = "cam_cc_cci_0_clk", 1275 .parent_hws = (const struct clk_hw*[]) { 1276 &cam_cc_cci_0_clk_src.clkr.hw, 1277 }, 1278 .num_parents = 1, 1279 .flags = CLK_SET_RATE_PARENT, 1280 .ops = &clk_branch2_ops, 1281 }, 1282 }, 1283 }; 1284 1285 static struct clk_branch cam_cc_cci_1_clk = { 1286 .halt_reg = 0x138b8, 1287 .halt_check = BRANCH_HALT, 1288 .clkr = { 1289 .enable_reg = 0x138b8, 1290 .enable_mask = BIT(0), 1291 .hw.init = &(const struct clk_init_data) { 1292 .name = "cam_cc_cci_1_clk", 1293 .parent_hws = (const struct clk_hw*[]) { 1294 &cam_cc_cci_1_clk_src.clkr.hw, 1295 }, 1296 .num_parents = 1, 1297 .flags = CLK_SET_RATE_PARENT, 1298 .ops = &clk_branch2_ops, 1299 }, 1300 }, 1301 }; 1302 1303 static struct clk_branch cam_cc_core_ahb_clk = { 1304 .halt_reg = 0x13a80, 1305 .halt_check = BRANCH_HALT_VOTED, 1306 .clkr = { 1307 .enable_reg = 0x13a80, 1308 .enable_mask = BIT(0), 1309 .hw.init = &(const struct clk_init_data) { 1310 .name = "cam_cc_core_ahb_clk", 1311 .parent_hws = (const struct clk_hw*[]) { 1312 &cam_cc_slow_ahb_clk_src.clkr.hw, 1313 }, 1314 .num_parents = 1, 1315 .flags = CLK_SET_RATE_PARENT, 1316 .ops = &clk_branch2_ops, 1317 }, 1318 }, 1319 }; 1320 1321 static struct clk_branch cam_cc_cpas_ahb_clk = { 1322 .halt_reg = 0x138bc, 1323 .halt_check = BRANCH_HALT, 1324 .clkr = { 1325 .enable_reg = 0x138bc, 1326 .enable_mask = BIT(0), 1327 .hw.init = &(const struct clk_init_data) { 1328 .name = "cam_cc_cpas_ahb_clk", 1329 .parent_hws = (const struct clk_hw*[]) { 1330 &cam_cc_slow_ahb_clk_src.clkr.hw, 1331 }, 1332 .num_parents = 1, 1333 .flags = CLK_SET_RATE_PARENT, 1334 .ops = &clk_branch2_ops, 1335 }, 1336 }, 1337 }; 1338 1339 static struct clk_branch cam_cc_cpas_bps_clk = { 1340 .halt_reg = 0x103b0, 1341 .halt_check = BRANCH_HALT, 1342 .clkr = { 1343 .enable_reg = 0x103b0, 1344 .enable_mask = BIT(0), 1345 .hw.init = &(const struct clk_init_data) { 1346 .name = "cam_cc_cpas_bps_clk", 1347 .parent_hws = (const struct clk_hw*[]) { 1348 &cam_cc_bps_clk_src.clkr.hw, 1349 }, 1350 .num_parents = 1, 1351 .flags = CLK_SET_RATE_PARENT, 1352 .ops = &clk_branch2_ops, 1353 }, 1354 }, 1355 }; 1356 1357 static struct clk_branch cam_cc_cpas_fast_ahb_clk = { 1358 .halt_reg = 0x138c8, 1359 .halt_check = BRANCH_HALT, 1360 .clkr = { 1361 .enable_reg = 0x138c8, 1362 .enable_mask = BIT(0), 1363 .hw.init = &(const struct clk_init_data) { 1364 .name = "cam_cc_cpas_fast_ahb_clk", 1365 .parent_hws = (const struct clk_hw*[]) { 1366 &cam_cc_fast_ahb_clk_src.clkr.hw, 1367 }, 1368 .num_parents = 1, 1369 .flags = CLK_SET_RATE_PARENT, 1370 .ops = &clk_branch2_ops, 1371 }, 1372 }, 1373 }; 1374 1375 static struct clk_branch cam_cc_cpas_ife_0_clk = { 1376 .halt_reg = 0x11150, 1377 .halt_check = BRANCH_HALT, 1378 .clkr = { 1379 .enable_reg = 0x11150, 1380 .enable_mask = BIT(0), 1381 .hw.init = &(const struct clk_init_data) { 1382 .name = "cam_cc_cpas_ife_0_clk", 1383 .parent_hws = (const struct clk_hw*[]) { 1384 &cam_cc_ife_0_clk_src.clkr.hw, 1385 }, 1386 .num_parents = 1, 1387 .flags = CLK_SET_RATE_PARENT, 1388 .ops = &clk_branch2_ops, 1389 }, 1390 }, 1391 }; 1392 1393 static struct clk_branch cam_cc_cpas_ife_1_clk = { 1394 .halt_reg = 0x1203c, 1395 .halt_check = BRANCH_HALT, 1396 .clkr = { 1397 .enable_reg = 0x1203c, 1398 .enable_mask = BIT(0), 1399 .hw.init = &(const struct clk_init_data) { 1400 .name = "cam_cc_cpas_ife_1_clk", 1401 .parent_hws = (const struct clk_hw*[]) { 1402 &cam_cc_ife_1_clk_src.clkr.hw, 1403 }, 1404 .num_parents = 1, 1405 .flags = CLK_SET_RATE_PARENT, 1406 .ops = &clk_branch2_ops, 1407 }, 1408 }, 1409 }; 1410 1411 static struct clk_branch cam_cc_cpas_ife_lite_clk = { 1412 .halt_reg = 0x13138, 1413 .halt_check = BRANCH_HALT, 1414 .clkr = { 1415 .enable_reg = 0x13138, 1416 .enable_mask = BIT(0), 1417 .hw.init = &(const struct clk_init_data) { 1418 .name = "cam_cc_cpas_ife_lite_clk", 1419 .parent_hws = (const struct clk_hw*[]) { 1420 &cam_cc_ife_lite_clk_src.clkr.hw, 1421 }, 1422 .num_parents = 1, 1423 .flags = CLK_SET_RATE_PARENT, 1424 .ops = &clk_branch2_ops, 1425 }, 1426 }, 1427 }; 1428 1429 static struct clk_branch cam_cc_cpas_ipe_nps_clk = { 1430 .halt_reg = 0x10504, 1431 .halt_check = BRANCH_HALT, 1432 .clkr = { 1433 .enable_reg = 0x10504, 1434 .enable_mask = BIT(0), 1435 .hw.init = &(const struct clk_init_data) { 1436 .name = "cam_cc_cpas_ipe_nps_clk", 1437 .parent_hws = (const struct clk_hw*[]) { 1438 &cam_cc_ipe_nps_clk_src.clkr.hw, 1439 }, 1440 .num_parents = 1, 1441 .flags = CLK_SET_RATE_PARENT, 1442 .ops = &clk_branch2_ops, 1443 }, 1444 }, 1445 }; 1446 1447 static struct clk_branch cam_cc_cpas_sfe_0_clk = { 1448 .halt_reg = 0x133cc, 1449 .halt_check = BRANCH_HALT, 1450 .clkr = { 1451 .enable_reg = 0x133cc, 1452 .enable_mask = BIT(0), 1453 .hw.init = &(const struct clk_init_data) { 1454 .name = "cam_cc_cpas_sfe_0_clk", 1455 .parent_hws = (const struct clk_hw*[]) { 1456 &cam_cc_sfe_0_clk_src.clkr.hw, 1457 }, 1458 .num_parents = 1, 1459 .flags = CLK_SET_RATE_PARENT, 1460 .ops = &clk_branch2_ops, 1461 }, 1462 }, 1463 }; 1464 1465 static struct clk_branch cam_cc_csi0phytimer_clk = { 1466 .halt_reg = 0x150f8, 1467 .halt_check = BRANCH_HALT, 1468 .clkr = { 1469 .enable_reg = 0x150f8, 1470 .enable_mask = BIT(0), 1471 .hw.init = &(const struct clk_init_data) { 1472 .name = "cam_cc_csi0phytimer_clk", 1473 .parent_hws = (const struct clk_hw*[]) { 1474 &cam_cc_csi0phytimer_clk_src.clkr.hw, 1475 }, 1476 .num_parents = 1, 1477 .flags = CLK_SET_RATE_PARENT, 1478 .ops = &clk_branch2_ops, 1479 }, 1480 }, 1481 }; 1482 1483 static struct clk_branch cam_cc_csi1phytimer_clk = { 1484 .halt_reg = 0x1511c, 1485 .halt_check = BRANCH_HALT, 1486 .clkr = { 1487 .enable_reg = 0x1511c, 1488 .enable_mask = BIT(0), 1489 .hw.init = &(const struct clk_init_data) { 1490 .name = "cam_cc_csi1phytimer_clk", 1491 .parent_hws = (const struct clk_hw*[]) { 1492 &cam_cc_csi1phytimer_clk_src.clkr.hw, 1493 }, 1494 .num_parents = 1, 1495 .flags = CLK_SET_RATE_PARENT, 1496 .ops = &clk_branch2_ops, 1497 }, 1498 }, 1499 }; 1500 1501 static struct clk_branch cam_cc_csi2phytimer_clk = { 1502 .halt_reg = 0x15250, 1503 .halt_check = BRANCH_HALT, 1504 .clkr = { 1505 .enable_reg = 0x15250, 1506 .enable_mask = BIT(0), 1507 .hw.init = &(const struct clk_init_data) { 1508 .name = "cam_cc_csi2phytimer_clk", 1509 .parent_hws = (const struct clk_hw*[]) { 1510 &cam_cc_csi2phytimer_clk_src.clkr.hw, 1511 }, 1512 .num_parents = 1, 1513 .flags = CLK_SET_RATE_PARENT, 1514 .ops = &clk_branch2_ops, 1515 }, 1516 }, 1517 }; 1518 1519 static struct clk_branch cam_cc_csi3phytimer_clk = { 1520 .halt_reg = 0x15384, 1521 .halt_check = BRANCH_HALT, 1522 .clkr = { 1523 .enable_reg = 0x15384, 1524 .enable_mask = BIT(0), 1525 .hw.init = &(const struct clk_init_data) { 1526 .name = "cam_cc_csi3phytimer_clk", 1527 .parent_hws = (const struct clk_hw*[]) { 1528 &cam_cc_csi3phytimer_clk_src.clkr.hw, 1529 }, 1530 .num_parents = 1, 1531 .flags = CLK_SET_RATE_PARENT, 1532 .ops = &clk_branch2_ops, 1533 }, 1534 }, 1535 }; 1536 1537 static struct clk_branch cam_cc_csi4phytimer_clk = { 1538 .halt_reg = 0x154b8, 1539 .halt_check = BRANCH_HALT, 1540 .clkr = { 1541 .enable_reg = 0x154b8, 1542 .enable_mask = BIT(0), 1543 .hw.init = &(const struct clk_init_data) { 1544 .name = "cam_cc_csi4phytimer_clk", 1545 .parent_hws = (const struct clk_hw*[]) { 1546 &cam_cc_csi4phytimer_clk_src.clkr.hw, 1547 }, 1548 .num_parents = 1, 1549 .flags = CLK_SET_RATE_PARENT, 1550 .ops = &clk_branch2_ops, 1551 }, 1552 }, 1553 }; 1554 1555 static struct clk_branch cam_cc_csi5phytimer_clk = { 1556 .halt_reg = 0x155ec, 1557 .halt_check = BRANCH_HALT, 1558 .clkr = { 1559 .enable_reg = 0x155ec, 1560 .enable_mask = BIT(0), 1561 .hw.init = &(const struct clk_init_data) { 1562 .name = "cam_cc_csi5phytimer_clk", 1563 .parent_hws = (const struct clk_hw*[]) { 1564 &cam_cc_csi5phytimer_clk_src.clkr.hw, 1565 }, 1566 .num_parents = 1, 1567 .flags = CLK_SET_RATE_PARENT, 1568 .ops = &clk_branch2_ops, 1569 }, 1570 }, 1571 }; 1572 1573 static struct clk_branch cam_cc_csid_clk = { 1574 .halt_reg = 0x138ec, 1575 .halt_check = BRANCH_HALT, 1576 .clkr = { 1577 .enable_reg = 0x138ec, 1578 .enable_mask = BIT(0), 1579 .hw.init = &(const struct clk_init_data) { 1580 .name = "cam_cc_csid_clk", 1581 .parent_hws = (const struct clk_hw*[]) { 1582 &cam_cc_csid_clk_src.clkr.hw, 1583 }, 1584 .num_parents = 1, 1585 .flags = CLK_SET_RATE_PARENT, 1586 .ops = &clk_branch2_ops, 1587 }, 1588 }, 1589 }; 1590 1591 static struct clk_branch cam_cc_csid_csiphy_rx_clk = { 1592 .halt_reg = 0x15100, 1593 .halt_check = BRANCH_HALT, 1594 .clkr = { 1595 .enable_reg = 0x15100, 1596 .enable_mask = BIT(0), 1597 .hw.init = &(const struct clk_init_data) { 1598 .name = "cam_cc_csid_csiphy_rx_clk", 1599 .parent_hws = (const struct clk_hw*[]) { 1600 &cam_cc_cphy_rx_clk_src.clkr.hw, 1601 }, 1602 .num_parents = 1, 1603 .flags = CLK_SET_RATE_PARENT, 1604 .ops = &clk_branch2_ops, 1605 }, 1606 }, 1607 }; 1608 1609 static struct clk_branch cam_cc_csiphy0_clk = { 1610 .halt_reg = 0x150fc, 1611 .halt_check = BRANCH_HALT, 1612 .clkr = { 1613 .enable_reg = 0x150fc, 1614 .enable_mask = BIT(0), 1615 .hw.init = &(const struct clk_init_data) { 1616 .name = "cam_cc_csiphy0_clk", 1617 .parent_hws = (const struct clk_hw*[]) { 1618 &cam_cc_cphy_rx_clk_src.clkr.hw, 1619 }, 1620 .num_parents = 1, 1621 .flags = CLK_SET_RATE_PARENT, 1622 .ops = &clk_branch2_ops, 1623 }, 1624 }, 1625 }; 1626 1627 static struct clk_branch cam_cc_csiphy1_clk = { 1628 .halt_reg = 0x15120, 1629 .halt_check = BRANCH_HALT, 1630 .clkr = { 1631 .enable_reg = 0x15120, 1632 .enable_mask = BIT(0), 1633 .hw.init = &(const struct clk_init_data) { 1634 .name = "cam_cc_csiphy1_clk", 1635 .parent_hws = (const struct clk_hw*[]) { 1636 &cam_cc_cphy_rx_clk_src.clkr.hw, 1637 }, 1638 .num_parents = 1, 1639 .flags = CLK_SET_RATE_PARENT, 1640 .ops = &clk_branch2_ops, 1641 }, 1642 }, 1643 }; 1644 1645 static struct clk_branch cam_cc_csiphy2_clk = { 1646 .halt_reg = 0x15254, 1647 .halt_check = BRANCH_HALT, 1648 .clkr = { 1649 .enable_reg = 0x15254, 1650 .enable_mask = BIT(0), 1651 .hw.init = &(const struct clk_init_data) { 1652 .name = "cam_cc_csiphy2_clk", 1653 .parent_hws = (const struct clk_hw*[]) { 1654 &cam_cc_cphy_rx_clk_src.clkr.hw, 1655 }, 1656 .num_parents = 1, 1657 .flags = CLK_SET_RATE_PARENT, 1658 .ops = &clk_branch2_ops, 1659 }, 1660 }, 1661 }; 1662 1663 static struct clk_branch cam_cc_csiphy3_clk = { 1664 .halt_reg = 0x15388, 1665 .halt_check = BRANCH_HALT, 1666 .clkr = { 1667 .enable_reg = 0x15388, 1668 .enable_mask = BIT(0), 1669 .hw.init = &(const struct clk_init_data) { 1670 .name = "cam_cc_csiphy3_clk", 1671 .parent_hws = (const struct clk_hw*[]) { 1672 &cam_cc_cphy_rx_clk_src.clkr.hw, 1673 }, 1674 .num_parents = 1, 1675 .flags = CLK_SET_RATE_PARENT, 1676 .ops = &clk_branch2_ops, 1677 }, 1678 }, 1679 }; 1680 1681 static struct clk_branch cam_cc_csiphy4_clk = { 1682 .halt_reg = 0x154bc, 1683 .halt_check = BRANCH_HALT, 1684 .clkr = { 1685 .enable_reg = 0x154bc, 1686 .enable_mask = BIT(0), 1687 .hw.init = &(const struct clk_init_data) { 1688 .name = "cam_cc_csiphy4_clk", 1689 .parent_hws = (const struct clk_hw*[]) { 1690 &cam_cc_cphy_rx_clk_src.clkr.hw, 1691 }, 1692 .num_parents = 1, 1693 .flags = CLK_SET_RATE_PARENT, 1694 .ops = &clk_branch2_ops, 1695 }, 1696 }, 1697 }; 1698 1699 static struct clk_branch cam_cc_csiphy5_clk = { 1700 .halt_reg = 0x155f0, 1701 .halt_check = BRANCH_HALT, 1702 .clkr = { 1703 .enable_reg = 0x155f0, 1704 .enable_mask = BIT(0), 1705 .hw.init = &(const struct clk_init_data) { 1706 .name = "cam_cc_csiphy5_clk", 1707 .parent_hws = (const struct clk_hw*[]) { 1708 &cam_cc_cphy_rx_clk_src.clkr.hw, 1709 }, 1710 .num_parents = 1, 1711 .flags = CLK_SET_RATE_PARENT, 1712 .ops = &clk_branch2_ops, 1713 }, 1714 }, 1715 }; 1716 1717 static struct clk_branch cam_cc_icp_ahb_clk = { 1718 .halt_reg = 0x13658, 1719 .halt_check = BRANCH_HALT, 1720 .clkr = { 1721 .enable_reg = 0x13658, 1722 .enable_mask = BIT(0), 1723 .hw.init = &(const struct clk_init_data) { 1724 .name = "cam_cc_icp_ahb_clk", 1725 .parent_hws = (const struct clk_hw*[]) { 1726 &cam_cc_slow_ahb_clk_src.clkr.hw, 1727 }, 1728 .num_parents = 1, 1729 .flags = CLK_SET_RATE_PARENT, 1730 .ops = &clk_branch2_ops, 1731 }, 1732 }, 1733 }; 1734 1735 static struct clk_branch cam_cc_icp_clk = { 1736 .halt_reg = 0x1364c, 1737 .halt_check = BRANCH_HALT, 1738 .clkr = { 1739 .enable_reg = 0x1364c, 1740 .enable_mask = BIT(0), 1741 .hw.init = &(const struct clk_init_data) { 1742 .name = "cam_cc_icp_clk", 1743 .parent_hws = (const struct clk_hw*[]) { 1744 &cam_cc_icp_clk_src.clkr.hw, 1745 }, 1746 .num_parents = 1, 1747 .flags = CLK_SET_RATE_PARENT, 1748 .ops = &clk_branch2_ops, 1749 }, 1750 }, 1751 }; 1752 1753 static struct clk_branch cam_cc_ife_0_clk = { 1754 .halt_reg = 0x11144, 1755 .halt_check = BRANCH_HALT, 1756 .clkr = { 1757 .enable_reg = 0x11144, 1758 .enable_mask = BIT(0), 1759 .hw.init = &(const struct clk_init_data) { 1760 .name = "cam_cc_ife_0_clk", 1761 .parent_hws = (const struct clk_hw*[]) { 1762 &cam_cc_ife_0_clk_src.clkr.hw, 1763 }, 1764 .num_parents = 1, 1765 .flags = CLK_SET_RATE_PARENT, 1766 .ops = &clk_branch2_ops, 1767 }, 1768 }, 1769 }; 1770 1771 static struct clk_branch cam_cc_ife_0_dsp_clk = { 1772 .halt_reg = 0x11154, 1773 .halt_check = BRANCH_HALT, 1774 .clkr = { 1775 .enable_reg = 0x11154, 1776 .enable_mask = BIT(0), 1777 .hw.init = &(const struct clk_init_data) { 1778 .name = "cam_cc_ife_0_dsp_clk", 1779 .parent_hws = (const struct clk_hw*[]) { 1780 &cam_cc_ife_0_clk_src.clkr.hw, 1781 }, 1782 .num_parents = 1, 1783 .flags = CLK_SET_RATE_PARENT, 1784 .ops = &clk_branch2_ops, 1785 }, 1786 }, 1787 }; 1788 1789 static struct clk_branch cam_cc_ife_0_fast_ahb_clk = { 1790 .halt_reg = 0x11160, 1791 .halt_check = BRANCH_HALT, 1792 .clkr = { 1793 .enable_reg = 0x11160, 1794 .enable_mask = BIT(0), 1795 .hw.init = &(const struct clk_init_data) { 1796 .name = "cam_cc_ife_0_fast_ahb_clk", 1797 .parent_hws = (const struct clk_hw*[]) { 1798 &cam_cc_fast_ahb_clk_src.clkr.hw, 1799 }, 1800 .num_parents = 1, 1801 .flags = CLK_SET_RATE_PARENT, 1802 .ops = &clk_branch2_ops, 1803 }, 1804 }, 1805 }; 1806 1807 static struct clk_branch cam_cc_ife_1_clk = { 1808 .halt_reg = 0x12030, 1809 .halt_check = BRANCH_HALT, 1810 .clkr = { 1811 .enable_reg = 0x12030, 1812 .enable_mask = BIT(0), 1813 .hw.init = &(const struct clk_init_data) { 1814 .name = "cam_cc_ife_1_clk", 1815 .parent_hws = (const struct clk_hw*[]) { 1816 &cam_cc_ife_1_clk_src.clkr.hw, 1817 }, 1818 .num_parents = 1, 1819 .flags = CLK_SET_RATE_PARENT, 1820 .ops = &clk_branch2_ops, 1821 }, 1822 }, 1823 }; 1824 1825 static struct clk_branch cam_cc_ife_1_dsp_clk = { 1826 .halt_reg = 0x12040, 1827 .halt_check = BRANCH_HALT, 1828 .clkr = { 1829 .enable_reg = 0x12040, 1830 .enable_mask = BIT(0), 1831 .hw.init = &(const struct clk_init_data) { 1832 .name = "cam_cc_ife_1_dsp_clk", 1833 .parent_hws = (const struct clk_hw*[]) { 1834 &cam_cc_ife_1_clk_src.clkr.hw, 1835 }, 1836 .num_parents = 1, 1837 .flags = CLK_SET_RATE_PARENT, 1838 .ops = &clk_branch2_ops, 1839 }, 1840 }, 1841 }; 1842 1843 static struct clk_branch cam_cc_ife_1_fast_ahb_clk = { 1844 .halt_reg = 0x1204c, 1845 .halt_check = BRANCH_HALT, 1846 .clkr = { 1847 .enable_reg = 0x1204c, 1848 .enable_mask = BIT(0), 1849 .hw.init = &(const struct clk_init_data) { 1850 .name = "cam_cc_ife_1_fast_ahb_clk", 1851 .parent_hws = (const struct clk_hw*[]) { 1852 &cam_cc_fast_ahb_clk_src.clkr.hw, 1853 }, 1854 .num_parents = 1, 1855 .flags = CLK_SET_RATE_PARENT, 1856 .ops = &clk_branch2_ops, 1857 }, 1858 }, 1859 }; 1860 1861 static struct clk_branch cam_cc_ife_lite_ahb_clk = { 1862 .halt_reg = 0x13278, 1863 .halt_check = BRANCH_HALT, 1864 .clkr = { 1865 .enable_reg = 0x13278, 1866 .enable_mask = BIT(0), 1867 .hw.init = &(const struct clk_init_data) { 1868 .name = "cam_cc_ife_lite_ahb_clk", 1869 .parent_hws = (const struct clk_hw*[]) { 1870 &cam_cc_slow_ahb_clk_src.clkr.hw, 1871 }, 1872 .num_parents = 1, 1873 .flags = CLK_SET_RATE_PARENT, 1874 .ops = &clk_branch2_ops, 1875 }, 1876 }, 1877 }; 1878 1879 static struct clk_branch cam_cc_ife_lite_clk = { 1880 .halt_reg = 0x1312c, 1881 .halt_check = BRANCH_HALT, 1882 .clkr = { 1883 .enable_reg = 0x1312c, 1884 .enable_mask = BIT(0), 1885 .hw.init = &(const struct clk_init_data) { 1886 .name = "cam_cc_ife_lite_clk", 1887 .parent_hws = (const struct clk_hw*[]) { 1888 &cam_cc_ife_lite_clk_src.clkr.hw, 1889 }, 1890 .num_parents = 1, 1891 .flags = CLK_SET_RATE_PARENT, 1892 .ops = &clk_branch2_ops, 1893 }, 1894 }, 1895 }; 1896 1897 static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { 1898 .halt_reg = 0x13274, 1899 .halt_check = BRANCH_HALT, 1900 .clkr = { 1901 .enable_reg = 0x13274, 1902 .enable_mask = BIT(0), 1903 .hw.init = &(const struct clk_init_data) { 1904 .name = "cam_cc_ife_lite_cphy_rx_clk", 1905 .parent_hws = (const struct clk_hw*[]) { 1906 &cam_cc_cphy_rx_clk_src.clkr.hw, 1907 }, 1908 .num_parents = 1, 1909 .flags = CLK_SET_RATE_PARENT, 1910 .ops = &clk_branch2_ops, 1911 }, 1912 }, 1913 }; 1914 1915 static struct clk_branch cam_cc_ife_lite_csid_clk = { 1916 .halt_reg = 0x13268, 1917 .halt_check = BRANCH_HALT, 1918 .clkr = { 1919 .enable_reg = 0x13268, 1920 .enable_mask = BIT(0), 1921 .hw.init = &(const struct clk_init_data) { 1922 .name = "cam_cc_ife_lite_csid_clk", 1923 .parent_hws = (const struct clk_hw*[]) { 1924 &cam_cc_ife_lite_csid_clk_src.clkr.hw, 1925 }, 1926 .num_parents = 1, 1927 .flags = CLK_SET_RATE_PARENT, 1928 .ops = &clk_branch2_ops, 1929 }, 1930 }, 1931 }; 1932 1933 static struct clk_branch cam_cc_ipe_nps_ahb_clk = { 1934 .halt_reg = 0x1051c, 1935 .halt_check = BRANCH_HALT, 1936 .clkr = { 1937 .enable_reg = 0x1051c, 1938 .enable_mask = BIT(0), 1939 .hw.init = &(const struct clk_init_data) { 1940 .name = "cam_cc_ipe_nps_ahb_clk", 1941 .parent_hws = (const struct clk_hw*[]) { 1942 &cam_cc_slow_ahb_clk_src.clkr.hw, 1943 }, 1944 .num_parents = 1, 1945 .flags = CLK_SET_RATE_PARENT, 1946 .ops = &clk_branch2_ops, 1947 }, 1948 }, 1949 }; 1950 1951 static struct clk_branch cam_cc_ipe_nps_clk = { 1952 .halt_reg = 0x104f8, 1953 .halt_check = BRANCH_HALT, 1954 .clkr = { 1955 .enable_reg = 0x104f8, 1956 .enable_mask = BIT(0), 1957 .hw.init = &(const struct clk_init_data) { 1958 .name = "cam_cc_ipe_nps_clk", 1959 .parent_hws = (const struct clk_hw*[]) { 1960 &cam_cc_ipe_nps_clk_src.clkr.hw, 1961 }, 1962 .num_parents = 1, 1963 .flags = CLK_SET_RATE_PARENT, 1964 .ops = &clk_branch2_ops, 1965 }, 1966 }, 1967 }; 1968 1969 static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = { 1970 .halt_reg = 0x10520, 1971 .halt_check = BRANCH_HALT, 1972 .clkr = { 1973 .enable_reg = 0x10520, 1974 .enable_mask = BIT(0), 1975 .hw.init = &(const struct clk_init_data) { 1976 .name = "cam_cc_ipe_nps_fast_ahb_clk", 1977 .parent_hws = (const struct clk_hw*[]) { 1978 &cam_cc_fast_ahb_clk_src.clkr.hw, 1979 }, 1980 .num_parents = 1, 1981 .flags = CLK_SET_RATE_PARENT, 1982 .ops = &clk_branch2_ops, 1983 }, 1984 }, 1985 }; 1986 1987 static struct clk_branch cam_cc_ipe_pps_clk = { 1988 .halt_reg = 0x10508, 1989 .halt_check = BRANCH_HALT, 1990 .clkr = { 1991 .enable_reg = 0x10508, 1992 .enable_mask = BIT(0), 1993 .hw.init = &(const struct clk_init_data) { 1994 .name = "cam_cc_ipe_pps_clk", 1995 .parent_hws = (const struct clk_hw*[]) { 1996 &cam_cc_ipe_nps_clk_src.clkr.hw, 1997 }, 1998 .num_parents = 1, 1999 .flags = CLK_SET_RATE_PARENT, 2000 .ops = &clk_branch2_ops, 2001 }, 2002 }, 2003 }; 2004 2005 static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = { 2006 .halt_reg = 0x10524, 2007 .halt_check = BRANCH_HALT, 2008 .clkr = { 2009 .enable_reg = 0x10524, 2010 .enable_mask = BIT(0), 2011 .hw.init = &(const struct clk_init_data) { 2012 .name = "cam_cc_ipe_pps_fast_ahb_clk", 2013 .parent_hws = (const struct clk_hw*[]) { 2014 &cam_cc_fast_ahb_clk_src.clkr.hw, 2015 }, 2016 .num_parents = 1, 2017 .flags = CLK_SET_RATE_PARENT, 2018 .ops = &clk_branch2_ops, 2019 }, 2020 }, 2021 }; 2022 2023 static struct clk_branch cam_cc_jpeg_clk = { 2024 .halt_reg = 0x13508, 2025 .halt_check = BRANCH_HALT, 2026 .clkr = { 2027 .enable_reg = 0x13508, 2028 .enable_mask = BIT(0), 2029 .hw.init = &(const struct clk_init_data) { 2030 .name = "cam_cc_jpeg_clk", 2031 .parent_hws = (const struct clk_hw*[]) { 2032 &cam_cc_jpeg_clk_src.clkr.hw, 2033 }, 2034 .num_parents = 1, 2035 .flags = CLK_SET_RATE_PARENT, 2036 .ops = &clk_branch2_ops, 2037 }, 2038 }, 2039 }; 2040 2041 static struct clk_branch cam_cc_mclk0_clk = { 2042 .halt_reg = 0x15018, 2043 .halt_check = BRANCH_HALT, 2044 .clkr = { 2045 .enable_reg = 0x15018, 2046 .enable_mask = BIT(0), 2047 .hw.init = &(const struct clk_init_data) { 2048 .name = "cam_cc_mclk0_clk", 2049 .parent_hws = (const struct clk_hw*[]) { 2050 &cam_cc_mclk0_clk_src.clkr.hw, 2051 }, 2052 .num_parents = 1, 2053 .flags = CLK_SET_RATE_PARENT, 2054 .ops = &clk_branch2_ops, 2055 }, 2056 }, 2057 }; 2058 2059 static struct clk_branch cam_cc_mclk1_clk = { 2060 .halt_reg = 0x15034, 2061 .halt_check = BRANCH_HALT, 2062 .clkr = { 2063 .enable_reg = 0x15034, 2064 .enable_mask = BIT(0), 2065 .hw.init = &(const struct clk_init_data) { 2066 .name = "cam_cc_mclk1_clk", 2067 .parent_hws = (const struct clk_hw*[]) { 2068 &cam_cc_mclk1_clk_src.clkr.hw, 2069 }, 2070 .num_parents = 1, 2071 .flags = CLK_SET_RATE_PARENT, 2072 .ops = &clk_branch2_ops, 2073 }, 2074 }, 2075 }; 2076 2077 static struct clk_branch cam_cc_mclk2_clk = { 2078 .halt_reg = 0x15050, 2079 .halt_check = BRANCH_HALT, 2080 .clkr = { 2081 .enable_reg = 0x15050, 2082 .enable_mask = BIT(0), 2083 .hw.init = &(const struct clk_init_data) { 2084 .name = "cam_cc_mclk2_clk", 2085 .parent_hws = (const struct clk_hw*[]) { 2086 &cam_cc_mclk2_clk_src.clkr.hw, 2087 }, 2088 .num_parents = 1, 2089 .flags = CLK_SET_RATE_PARENT, 2090 .ops = &clk_branch2_ops, 2091 }, 2092 }, 2093 }; 2094 2095 static struct clk_branch cam_cc_mclk3_clk = { 2096 .halt_reg = 0x1506c, 2097 .halt_check = BRANCH_HALT, 2098 .clkr = { 2099 .enable_reg = 0x1506c, 2100 .enable_mask = BIT(0), 2101 .hw.init = &(const struct clk_init_data) { 2102 .name = "cam_cc_mclk3_clk", 2103 .parent_hws = (const struct clk_hw*[]) { 2104 &cam_cc_mclk3_clk_src.clkr.hw, 2105 }, 2106 .num_parents = 1, 2107 .flags = CLK_SET_RATE_PARENT, 2108 .ops = &clk_branch2_ops, 2109 }, 2110 }, 2111 }; 2112 2113 static struct clk_branch cam_cc_mclk4_clk = { 2114 .halt_reg = 0x15088, 2115 .halt_check = BRANCH_HALT, 2116 .clkr = { 2117 .enable_reg = 0x15088, 2118 .enable_mask = BIT(0), 2119 .hw.init = &(const struct clk_init_data) { 2120 .name = "cam_cc_mclk4_clk", 2121 .parent_hws = (const struct clk_hw*[]) { 2122 &cam_cc_mclk4_clk_src.clkr.hw, 2123 }, 2124 .num_parents = 1, 2125 .flags = CLK_SET_RATE_PARENT, 2126 .ops = &clk_branch2_ops, 2127 }, 2128 }, 2129 }; 2130 2131 static struct clk_branch cam_cc_mclk5_clk = { 2132 .halt_reg = 0x150a4, 2133 .halt_check = BRANCH_HALT, 2134 .clkr = { 2135 .enable_reg = 0x150a4, 2136 .enable_mask = BIT(0), 2137 .hw.init = &(const struct clk_init_data) { 2138 .name = "cam_cc_mclk5_clk", 2139 .parent_hws = (const struct clk_hw*[]) { 2140 &cam_cc_mclk5_clk_src.clkr.hw, 2141 }, 2142 .num_parents = 1, 2143 .flags = CLK_SET_RATE_PARENT, 2144 .ops = &clk_branch2_ops, 2145 }, 2146 }, 2147 }; 2148 2149 static struct clk_branch cam_cc_mclk6_clk = { 2150 .halt_reg = 0x150c0, 2151 .halt_check = BRANCH_HALT, 2152 .clkr = { 2153 .enable_reg = 0x150c0, 2154 .enable_mask = BIT(0), 2155 .hw.init = &(const struct clk_init_data) { 2156 .name = "cam_cc_mclk6_clk", 2157 .parent_hws = (const struct clk_hw*[]) { 2158 &cam_cc_mclk6_clk_src.clkr.hw, 2159 }, 2160 .num_parents = 1, 2161 .flags = CLK_SET_RATE_PARENT, 2162 .ops = &clk_branch2_ops, 2163 }, 2164 }, 2165 }; 2166 2167 static struct clk_branch cam_cc_mclk7_clk = { 2168 .halt_reg = 0x150dc, 2169 .halt_check = BRANCH_HALT, 2170 .clkr = { 2171 .enable_reg = 0x150dc, 2172 .enable_mask = BIT(0), 2173 .hw.init = &(const struct clk_init_data) { 2174 .name = "cam_cc_mclk7_clk", 2175 .parent_hws = (const struct clk_hw*[]) { 2176 &cam_cc_mclk7_clk_src.clkr.hw, 2177 }, 2178 .num_parents = 1, 2179 .flags = CLK_SET_RATE_PARENT, 2180 .ops = &clk_branch2_ops, 2181 }, 2182 }, 2183 }; 2184 2185 static struct clk_branch cam_cc_sfe_0_clk = { 2186 .halt_reg = 0x133c0, 2187 .halt_check = BRANCH_HALT, 2188 .clkr = { 2189 .enable_reg = 0x133c0, 2190 .enable_mask = BIT(0), 2191 .hw.init = &(const struct clk_init_data) { 2192 .name = "cam_cc_sfe_0_clk", 2193 .parent_hws = (const struct clk_hw*[]) { 2194 &cam_cc_sfe_0_clk_src.clkr.hw, 2195 }, 2196 .num_parents = 1, 2197 .flags = CLK_SET_RATE_PARENT, 2198 .ops = &clk_branch2_ops, 2199 }, 2200 }, 2201 }; 2202 2203 static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = { 2204 .halt_reg = 0x133d8, 2205 .halt_check = BRANCH_HALT, 2206 .clkr = { 2207 .enable_reg = 0x133d8, 2208 .enable_mask = BIT(0), 2209 .hw.init = &(const struct clk_init_data) { 2210 .name = "cam_cc_sfe_0_fast_ahb_clk", 2211 .parent_hws = (const struct clk_hw*[]) { 2212 &cam_cc_fast_ahb_clk_src.clkr.hw, 2213 }, 2214 .num_parents = 1, 2215 .flags = CLK_SET_RATE_PARENT, 2216 .ops = &clk_branch2_ops, 2217 }, 2218 }, 2219 }; 2220 2221 static struct gdsc cam_cc_titan_top_gdsc; 2222 2223 static struct gdsc cam_cc_bps_gdsc = { 2224 .gdscr = 0x10004, 2225 .en_rest_wait_val = 0x2, 2226 .en_few_wait_val = 0x2, 2227 .clk_dis_wait_val = 0xf, 2228 .pd = { 2229 .name = "cam_cc_bps_gdsc", 2230 }, 2231 .pwrsts = PWRSTS_OFF_ON, 2232 .parent = &cam_cc_titan_top_gdsc.pd, 2233 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2234 }; 2235 2236 static struct gdsc cam_cc_ife_0_gdsc = { 2237 .gdscr = 0x11004, 2238 .en_rest_wait_val = 0x2, 2239 .en_few_wait_val = 0x2, 2240 .clk_dis_wait_val = 0xf, 2241 .pd = { 2242 .name = "cam_cc_ife_0_gdsc", 2243 }, 2244 .pwrsts = PWRSTS_OFF_ON, 2245 .parent = &cam_cc_titan_top_gdsc.pd, 2246 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2247 }; 2248 2249 static struct gdsc cam_cc_ife_1_gdsc = { 2250 .gdscr = 0x12004, 2251 .en_rest_wait_val = 0x2, 2252 .en_few_wait_val = 0x2, 2253 .clk_dis_wait_val = 0xf, 2254 .pd = { 2255 .name = "cam_cc_ife_1_gdsc", 2256 }, 2257 .pwrsts = PWRSTS_OFF_ON, 2258 .parent = &cam_cc_titan_top_gdsc.pd, 2259 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2260 }; 2261 2262 static struct gdsc cam_cc_ipe_0_gdsc = { 2263 .gdscr = 0x103b8, 2264 .en_rest_wait_val = 0x2, 2265 .en_few_wait_val = 0x2, 2266 .clk_dis_wait_val = 0xf, 2267 .pd = { 2268 .name = "cam_cc_ipe_0_gdsc", 2269 }, 2270 .pwrsts = PWRSTS_OFF_ON, 2271 .parent = &cam_cc_titan_top_gdsc.pd, 2272 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2273 }; 2274 2275 static struct gdsc cam_cc_sfe_0_gdsc = { 2276 .gdscr = 0x13280, 2277 .en_rest_wait_val = 0x2, 2278 .en_few_wait_val = 0x2, 2279 .clk_dis_wait_val = 0xf, 2280 .pd = { 2281 .name = "cam_cc_sfe_0_gdsc", 2282 }, 2283 .pwrsts = PWRSTS_OFF_ON, 2284 .parent = &cam_cc_titan_top_gdsc.pd, 2285 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2286 }; 2287 2288 static struct gdsc cam_cc_titan_top_gdsc = { 2289 .gdscr = 0x13a6c, 2290 .en_rest_wait_val = 0x2, 2291 .en_few_wait_val = 0x2, 2292 .clk_dis_wait_val = 0xf, 2293 .pd = { 2294 .name = "cam_cc_titan_top_gdsc", 2295 }, 2296 .pwrsts = PWRSTS_OFF_ON, 2297 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2298 }; 2299 2300 static struct clk_regmap *cam_cc_x1e80100_clocks[] = { 2301 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, 2302 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, 2303 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, 2304 [CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr, 2305 [CAM_CC_CAMNOC_AXI_NRT_CLK] = &cam_cc_camnoc_axi_nrt_clk.clkr, 2306 [CAM_CC_CAMNOC_AXI_RT_CLK] = &cam_cc_camnoc_axi_rt_clk.clkr, 2307 [CAM_CC_CAMNOC_AXI_RT_CLK_SRC] = &cam_cc_camnoc_axi_rt_clk_src.clkr, 2308 [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, 2309 [CAM_CC_CAMNOC_XO_CLK] = &cam_cc_camnoc_xo_clk.clkr, 2310 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, 2311 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, 2312 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, 2313 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, 2314 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 2315 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 2316 [CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr, 2317 [CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr, 2318 [CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr, 2319 [CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr, 2320 [CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr, 2321 [CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr, 2322 [CAM_CC_CPAS_SFE_0_CLK] = &cam_cc_cpas_sfe_0_clk.clkr, 2323 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 2324 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 2325 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 2326 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 2327 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 2328 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 2329 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 2330 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 2331 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 2332 [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr, 2333 [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr, 2334 [CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr, 2335 [CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr, 2336 [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr, 2337 [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr, 2338 [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr, 2339 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 2340 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 2341 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 2342 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 2343 [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, 2344 [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr, 2345 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 2346 [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr, 2347 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 2348 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 2349 [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, 2350 [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, 2351 [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, 2352 [CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr, 2353 [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, 2354 [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, 2355 [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, 2356 [CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr, 2357 [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr, 2358 [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, 2359 [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, 2360 [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, 2361 [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, 2362 [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, 2363 [CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr, 2364 [CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr, 2365 [CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr, 2366 [CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr, 2367 [CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr, 2368 [CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr, 2369 [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, 2370 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, 2371 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 2372 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 2373 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 2374 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 2375 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 2376 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 2377 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 2378 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 2379 [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, 2380 [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, 2381 [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr, 2382 [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr, 2383 [CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr, 2384 [CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr, 2385 [CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr, 2386 [CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr, 2387 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 2388 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, 2389 [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, 2390 [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 2391 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, 2392 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 2393 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 2394 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, 2395 [CAM_CC_PLL4] = &cam_cc_pll4.clkr, 2396 [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, 2397 [CAM_CC_PLL6] = &cam_cc_pll6.clkr, 2398 [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, 2399 [CAM_CC_PLL8] = &cam_cc_pll8.clkr, 2400 [CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr, 2401 [CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr, 2402 [CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr, 2403 [CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr, 2404 [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, 2405 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 2406 [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, 2407 }; 2408 2409 static struct gdsc *cam_cc_x1e80100_gdscs[] = { 2410 [CAM_CC_BPS_GDSC] = &cam_cc_bps_gdsc, 2411 [CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc, 2412 [CAM_CC_IFE_1_GDSC] = &cam_cc_ife_1_gdsc, 2413 [CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc, 2414 [CAM_CC_SFE_0_GDSC] = &cam_cc_sfe_0_gdsc, 2415 [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc, 2416 }; 2417 2418 static const struct qcom_reset_map cam_cc_x1e80100_resets[] = { 2419 [CAM_CC_BPS_BCR] = { 0x10000 }, 2420 [CAM_CC_ICP_BCR] = { 0x1351c }, 2421 [CAM_CC_IFE_0_BCR] = { 0x11000 }, 2422 [CAM_CC_IFE_1_BCR] = { 0x12000 }, 2423 [CAM_CC_IPE_0_BCR] = { 0x103b4 }, 2424 [CAM_CC_SFE_0_BCR] = { 0x1327c }, 2425 }; 2426 2427 static struct clk_alpha_pll *cam_cc_x1e80100_plls[] = { 2428 &cam_cc_pll0, 2429 &cam_cc_pll1, 2430 &cam_cc_pll2, 2431 &cam_cc_pll3, 2432 &cam_cc_pll4, 2433 &cam_cc_pll6, 2434 &cam_cc_pll8, 2435 }; 2436 2437 static u32 cam_cc_x1e80100_critical_cbcrs[] = { 2438 0x13a9c, /* CAM_CC_GDSC_CLK */ 2439 0x13ab8, /* CAM_CC_SLEEP_CLK */ 2440 }; 2441 2442 static const struct regmap_config cam_cc_x1e80100_regmap_config = { 2443 .reg_bits = 32, 2444 .reg_stride = 4, 2445 .val_bits = 32, 2446 .max_register = 0x1603c, 2447 .fast_io = true, 2448 }; 2449 2450 static struct qcom_cc_driver_data cam_cc_x1e80100_driver_data = { 2451 .alpha_plls = cam_cc_x1e80100_plls, 2452 .num_alpha_plls = ARRAY_SIZE(cam_cc_x1e80100_plls), 2453 .clk_cbcrs = cam_cc_x1e80100_critical_cbcrs, 2454 .num_clk_cbcrs = ARRAY_SIZE(cam_cc_x1e80100_critical_cbcrs), 2455 }; 2456 2457 static const struct qcom_cc_desc cam_cc_x1e80100_desc = { 2458 .config = &cam_cc_x1e80100_regmap_config, 2459 .clks = cam_cc_x1e80100_clocks, 2460 .num_clks = ARRAY_SIZE(cam_cc_x1e80100_clocks), 2461 .resets = cam_cc_x1e80100_resets, 2462 .num_resets = ARRAY_SIZE(cam_cc_x1e80100_resets), 2463 .gdscs = cam_cc_x1e80100_gdscs, 2464 .num_gdscs = ARRAY_SIZE(cam_cc_x1e80100_gdscs), 2465 .use_rpm = true, 2466 .driver_data = &cam_cc_x1e80100_driver_data, 2467 }; 2468 2469 static const struct of_device_id cam_cc_x1e80100_match_table[] = { 2470 { .compatible = "qcom,x1e80100-camcc" }, 2471 { } 2472 }; 2473 MODULE_DEVICE_TABLE(of, cam_cc_x1e80100_match_table); 2474 2475 static int cam_cc_x1e80100_probe(struct platform_device *pdev) 2476 { 2477 return qcom_cc_probe(pdev, &cam_cc_x1e80100_desc); 2478 } 2479 2480 static struct platform_driver cam_cc_x1e80100_driver = { 2481 .probe = cam_cc_x1e80100_probe, 2482 .driver = { 2483 .name = "camcc-x1e80100", 2484 .of_match_table = cam_cc_x1e80100_match_table, 2485 }, 2486 }; 2487 2488 module_platform_driver(cam_cc_x1e80100_driver); 2489 2490 MODULE_DESCRIPTION("QTI Camera Clock Controller X1E80100 Driver"); 2491 MODULE_LICENSE("GPL"); 2492