1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,x1e80100-camcc.h> 12 13 #include "clk-alpha-pll.h" 14 #include "clk-branch.h" 15 #include "clk-rcg.h" 16 #include "clk-regmap.h" 17 #include "common.h" 18 #include "gdsc.h" 19 #include "reset.h" 20 21 enum { 22 DT_IFACE, 23 DT_BI_TCXO, 24 DT_BI_TCXO_AO, 25 DT_SLEEP_CLK, 26 }; 27 28 enum { 29 P_BI_TCXO, 30 P_BI_TCXO_AO, 31 P_CAM_CC_PLL0_OUT_EVEN, 32 P_CAM_CC_PLL0_OUT_MAIN, 33 P_CAM_CC_PLL0_OUT_ODD, 34 P_CAM_CC_PLL1_OUT_EVEN, 35 P_CAM_CC_PLL2_OUT_EVEN, 36 P_CAM_CC_PLL2_OUT_MAIN, 37 P_CAM_CC_PLL3_OUT_EVEN, 38 P_CAM_CC_PLL4_OUT_EVEN, 39 P_CAM_CC_PLL6_OUT_EVEN, 40 P_CAM_CC_PLL8_OUT_EVEN, 41 P_SLEEP_CLK, 42 }; 43 44 static const struct pll_vco lucid_ole_vco[] = { 45 { 249600000, 2300000000, 0 }, 46 }; 47 48 static const struct pll_vco rivian_ole_vco[] = { 49 { 777000000, 1285000000, 0 }, 50 }; 51 52 static const struct alpha_pll_config cam_cc_pll0_config = { 53 .l = 0x3e, 54 .alpha = 0x8000, 55 .config_ctl_val = 0x20485699, 56 .config_ctl_hi_val = 0x00182261, 57 .config_ctl_hi1_val = 0x82aa299c, 58 .test_ctl_val = 0x00000000, 59 .test_ctl_hi_val = 0x00000003, 60 .test_ctl_hi1_val = 0x00009000, 61 .test_ctl_hi2_val = 0x00000034, 62 .user_ctl_val = 0x00008400, 63 .user_ctl_hi_val = 0x00000005, 64 }; 65 66 static struct clk_alpha_pll cam_cc_pll0 = { 67 .offset = 0x0, 68 .config = &cam_cc_pll0_config, 69 .vco_table = lucid_ole_vco, 70 .num_vco = ARRAY_SIZE(lucid_ole_vco), 71 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 72 .clkr = { 73 .hw.init = &(const struct clk_init_data) { 74 .name = "cam_cc_pll0", 75 .parent_data = &(const struct clk_parent_data) { 76 .index = DT_BI_TCXO, 77 }, 78 .num_parents = 1, 79 .ops = &clk_alpha_pll_lucid_evo_ops, 80 }, 81 }, 82 }; 83 84 static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { 85 { 0x1, 2 }, 86 { } 87 }; 88 89 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { 90 .offset = 0x0, 91 .post_div_shift = 10, 92 .post_div_table = post_div_table_cam_cc_pll0_out_even, 93 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), 94 .width = 4, 95 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 96 .clkr.hw.init = &(const struct clk_init_data) { 97 .name = "cam_cc_pll0_out_even", 98 .parent_hws = (const struct clk_hw*[]) { 99 &cam_cc_pll0.clkr.hw, 100 }, 101 .num_parents = 1, 102 .flags = CLK_SET_RATE_PARENT, 103 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 104 }, 105 }; 106 107 static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { 108 { 0x2, 3 }, 109 { } 110 }; 111 112 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { 113 .offset = 0x0, 114 .post_div_shift = 14, 115 .post_div_table = post_div_table_cam_cc_pll0_out_odd, 116 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), 117 .width = 4, 118 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 119 .clkr.hw.init = &(const struct clk_init_data) { 120 .name = "cam_cc_pll0_out_odd", 121 .parent_hws = (const struct clk_hw*[]) { 122 &cam_cc_pll0.clkr.hw, 123 }, 124 .num_parents = 1, 125 .flags = CLK_SET_RATE_PARENT, 126 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 127 }, 128 }; 129 130 static const struct alpha_pll_config cam_cc_pll1_config = { 131 .l = 0x1f, 132 .alpha = 0xaaaa, 133 .config_ctl_val = 0x20485699, 134 .config_ctl_hi_val = 0x00182261, 135 .config_ctl_hi1_val = 0x82aa299c, 136 .test_ctl_val = 0x00000000, 137 .test_ctl_hi_val = 0x00000003, 138 .test_ctl_hi1_val = 0x00009000, 139 .test_ctl_hi2_val = 0x00000034, 140 .user_ctl_val = 0x00000400, 141 .user_ctl_hi_val = 0x00000005, 142 }; 143 144 static struct clk_alpha_pll cam_cc_pll1 = { 145 .offset = 0x1000, 146 .config = &cam_cc_pll1_config, 147 .vco_table = lucid_ole_vco, 148 .num_vco = ARRAY_SIZE(lucid_ole_vco), 149 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 150 .clkr = { 151 .hw.init = &(const struct clk_init_data) { 152 .name = "cam_cc_pll1", 153 .parent_data = &(const struct clk_parent_data) { 154 .index = DT_BI_TCXO, 155 }, 156 .num_parents = 1, 157 .ops = &clk_alpha_pll_lucid_evo_ops, 158 }, 159 }, 160 }; 161 162 static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { 163 { 0x1, 2 }, 164 { } 165 }; 166 167 static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { 168 .offset = 0x1000, 169 .post_div_shift = 10, 170 .post_div_table = post_div_table_cam_cc_pll1_out_even, 171 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), 172 .width = 4, 173 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 174 .clkr.hw.init = &(const struct clk_init_data) { 175 .name = "cam_cc_pll1_out_even", 176 .parent_hws = (const struct clk_hw*[]) { 177 &cam_cc_pll1.clkr.hw, 178 }, 179 .num_parents = 1, 180 .flags = CLK_SET_RATE_PARENT, 181 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 182 }, 183 }; 184 185 static const struct alpha_pll_config cam_cc_pll2_config = { 186 .l = 0x32, 187 .alpha = 0x0, 188 .config_ctl_val = 0x10000030, 189 .config_ctl_hi_val = 0x80890263, 190 .config_ctl_hi1_val = 0x00000217, 191 .user_ctl_val = 0x00000001, 192 .user_ctl_hi_val = 0x00000000, 193 }; 194 195 static struct clk_alpha_pll cam_cc_pll2 = { 196 .offset = 0x2000, 197 .config = &cam_cc_pll2_config, 198 .vco_table = rivian_ole_vco, 199 .num_vco = ARRAY_SIZE(rivian_ole_vco), 200 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], 201 .clkr = { 202 .hw.init = &(const struct clk_init_data) { 203 .name = "cam_cc_pll2", 204 .parent_data = &(const struct clk_parent_data) { 205 .index = DT_BI_TCXO, 206 }, 207 .num_parents = 1, 208 .ops = &clk_alpha_pll_rivian_evo_ops, 209 }, 210 }, 211 }; 212 213 static const struct alpha_pll_config cam_cc_pll3_config = { 214 .l = 0x24, 215 .alpha = 0x0, 216 .config_ctl_val = 0x20485699, 217 .config_ctl_hi_val = 0x00182261, 218 .config_ctl_hi1_val = 0x82aa299c, 219 .test_ctl_val = 0x00000000, 220 .test_ctl_hi_val = 0x00000003, 221 .test_ctl_hi1_val = 0x00009000, 222 .test_ctl_hi2_val = 0x00000034, 223 .user_ctl_val = 0x00000400, 224 .user_ctl_hi_val = 0x00000005, 225 }; 226 227 static struct clk_alpha_pll cam_cc_pll3 = { 228 .offset = 0x3000, 229 .config = &cam_cc_pll3_config, 230 .vco_table = lucid_ole_vco, 231 .num_vco = ARRAY_SIZE(lucid_ole_vco), 232 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 233 .clkr = { 234 .hw.init = &(const struct clk_init_data) { 235 .name = "cam_cc_pll3", 236 .parent_data = &(const struct clk_parent_data) { 237 .index = DT_BI_TCXO, 238 }, 239 .num_parents = 1, 240 .ops = &clk_alpha_pll_lucid_evo_ops, 241 }, 242 }, 243 }; 244 245 static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { 246 { 0x1, 2 }, 247 { } 248 }; 249 250 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 251 .offset = 0x3000, 252 .post_div_shift = 10, 253 .post_div_table = post_div_table_cam_cc_pll3_out_even, 254 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), 255 .width = 4, 256 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 257 .clkr.hw.init = &(const struct clk_init_data) { 258 .name = "cam_cc_pll3_out_even", 259 .parent_hws = (const struct clk_hw*[]) { 260 &cam_cc_pll3.clkr.hw, 261 }, 262 .num_parents = 1, 263 .flags = CLK_SET_RATE_PARENT, 264 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 265 }, 266 }; 267 268 static const struct alpha_pll_config cam_cc_pll4_config = { 269 .l = 0x24, 270 .alpha = 0x0, 271 .config_ctl_val = 0x20485699, 272 .config_ctl_hi_val = 0x00182261, 273 .config_ctl_hi1_val = 0x82aa299c, 274 .test_ctl_val = 0x00000000, 275 .test_ctl_hi_val = 0x00000003, 276 .test_ctl_hi1_val = 0x00009000, 277 .test_ctl_hi2_val = 0x00000034, 278 .user_ctl_val = 0x00000400, 279 .user_ctl_hi_val = 0x00000005, 280 }; 281 282 static struct clk_alpha_pll cam_cc_pll4 = { 283 .offset = 0x4000, 284 .config = &cam_cc_pll4_config, 285 .vco_table = lucid_ole_vco, 286 .num_vco = ARRAY_SIZE(lucid_ole_vco), 287 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 288 .clkr = { 289 .hw.init = &(const struct clk_init_data) { 290 .name = "cam_cc_pll4", 291 .parent_data = &(const struct clk_parent_data) { 292 .index = DT_BI_TCXO, 293 }, 294 .num_parents = 1, 295 .ops = &clk_alpha_pll_lucid_evo_ops, 296 }, 297 }, 298 }; 299 300 static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { 301 { 0x1, 2 }, 302 { } 303 }; 304 305 static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { 306 .offset = 0x4000, 307 .post_div_shift = 10, 308 .post_div_table = post_div_table_cam_cc_pll4_out_even, 309 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), 310 .width = 4, 311 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 312 .clkr.hw.init = &(const struct clk_init_data) { 313 .name = "cam_cc_pll4_out_even", 314 .parent_hws = (const struct clk_hw*[]) { 315 &cam_cc_pll4.clkr.hw, 316 }, 317 .num_parents = 1, 318 .flags = CLK_SET_RATE_PARENT, 319 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 320 }, 321 }; 322 323 static const struct alpha_pll_config cam_cc_pll6_config = { 324 .l = 0x24, 325 .alpha = 0x0, 326 .config_ctl_val = 0x20485699, 327 .config_ctl_hi_val = 0x00182261, 328 .config_ctl_hi1_val = 0x82aa299c, 329 .test_ctl_val = 0x00000000, 330 .test_ctl_hi_val = 0x00000003, 331 .test_ctl_hi1_val = 0x00009000, 332 .test_ctl_hi2_val = 0x00000034, 333 .user_ctl_val = 0x00000400, 334 .user_ctl_hi_val = 0x00000005, 335 }; 336 337 static struct clk_alpha_pll cam_cc_pll6 = { 338 .offset = 0x6000, 339 .config = &cam_cc_pll6_config, 340 .vco_table = lucid_ole_vco, 341 .num_vco = ARRAY_SIZE(lucid_ole_vco), 342 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 343 .clkr = { 344 .hw.init = &(const struct clk_init_data) { 345 .name = "cam_cc_pll6", 346 .parent_data = &(const struct clk_parent_data) { 347 .index = DT_BI_TCXO, 348 }, 349 .num_parents = 1, 350 .ops = &clk_alpha_pll_lucid_evo_ops, 351 }, 352 }, 353 }; 354 355 static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { 356 { 0x1, 2 }, 357 { } 358 }; 359 360 static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { 361 .offset = 0x6000, 362 .post_div_shift = 10, 363 .post_div_table = post_div_table_cam_cc_pll6_out_even, 364 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), 365 .width = 4, 366 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 367 .clkr.hw.init = &(const struct clk_init_data) { 368 .name = "cam_cc_pll6_out_even", 369 .parent_hws = (const struct clk_hw*[]) { 370 &cam_cc_pll6.clkr.hw, 371 }, 372 .num_parents = 1, 373 .flags = CLK_SET_RATE_PARENT, 374 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 375 }, 376 }; 377 378 static const struct alpha_pll_config cam_cc_pll8_config = { 379 .l = 0x32, 380 .alpha = 0x0, 381 .config_ctl_val = 0x20485699, 382 .config_ctl_hi_val = 0x00182261, 383 .config_ctl_hi1_val = 0x82aa299c, 384 .test_ctl_val = 0x00000000, 385 .test_ctl_hi_val = 0x00000003, 386 .test_ctl_hi1_val = 0x00009000, 387 .test_ctl_hi2_val = 0x00000034, 388 .user_ctl_val = 0x00000400, 389 .user_ctl_hi_val = 0x00000005, 390 }; 391 392 static struct clk_alpha_pll cam_cc_pll8 = { 393 .offset = 0x8000, 394 .config = &cam_cc_pll8_config, 395 .vco_table = lucid_ole_vco, 396 .num_vco = ARRAY_SIZE(lucid_ole_vco), 397 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 398 .clkr = { 399 .hw.init = &(const struct clk_init_data) { 400 .name = "cam_cc_pll8", 401 .parent_data = &(const struct clk_parent_data) { 402 .index = DT_BI_TCXO, 403 }, 404 .num_parents = 1, 405 .ops = &clk_alpha_pll_lucid_evo_ops, 406 }, 407 }, 408 }; 409 410 static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = { 411 { 0x1, 2 }, 412 { } 413 }; 414 415 static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = { 416 .offset = 0x8000, 417 .post_div_shift = 10, 418 .post_div_table = post_div_table_cam_cc_pll8_out_even, 419 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll8_out_even), 420 .width = 4, 421 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 422 .clkr.hw.init = &(const struct clk_init_data) { 423 .name = "cam_cc_pll8_out_even", 424 .parent_hws = (const struct clk_hw*[]) { 425 &cam_cc_pll8.clkr.hw, 426 }, 427 .num_parents = 1, 428 .flags = CLK_SET_RATE_PARENT, 429 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 430 }, 431 }; 432 433 static const struct parent_map cam_cc_parent_map_0[] = { 434 { P_BI_TCXO, 0 }, 435 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 436 { P_CAM_CC_PLL0_OUT_EVEN, 2 }, 437 { P_CAM_CC_PLL0_OUT_ODD, 3 }, 438 { P_CAM_CC_PLL8_OUT_EVEN, 5 }, 439 }; 440 441 static const struct clk_parent_data cam_cc_parent_data_0[] = { 442 { .index = DT_BI_TCXO }, 443 { .hw = &cam_cc_pll0.clkr.hw }, 444 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 445 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 446 { .hw = &cam_cc_pll8_out_even.clkr.hw }, 447 }; 448 449 static const struct parent_map cam_cc_parent_map_1[] = { 450 { P_BI_TCXO, 0 }, 451 { P_CAM_CC_PLL2_OUT_EVEN, 3 }, 452 { P_CAM_CC_PLL2_OUT_MAIN, 5 }, 453 }; 454 455 static const struct clk_parent_data cam_cc_parent_data_1[] = { 456 { .index = DT_BI_TCXO }, 457 { .hw = &cam_cc_pll2.clkr.hw }, 458 { .hw = &cam_cc_pll2.clkr.hw }, 459 }; 460 461 static const struct parent_map cam_cc_parent_map_2[] = { 462 { P_BI_TCXO, 0 }, 463 { P_CAM_CC_PLL3_OUT_EVEN, 6 }, 464 }; 465 466 static const struct clk_parent_data cam_cc_parent_data_2[] = { 467 { .index = DT_BI_TCXO }, 468 { .hw = &cam_cc_pll3_out_even.clkr.hw }, 469 }; 470 471 static const struct parent_map cam_cc_parent_map_3[] = { 472 { P_BI_TCXO, 0 }, 473 { P_CAM_CC_PLL4_OUT_EVEN, 6 }, 474 }; 475 476 static const struct clk_parent_data cam_cc_parent_data_3[] = { 477 { .index = DT_BI_TCXO }, 478 { .hw = &cam_cc_pll4_out_even.clkr.hw }, 479 }; 480 481 static const struct parent_map cam_cc_parent_map_4[] = { 482 { P_BI_TCXO, 0 }, 483 { P_CAM_CC_PLL1_OUT_EVEN, 4 }, 484 }; 485 486 static const struct clk_parent_data cam_cc_parent_data_4[] = { 487 { .index = DT_BI_TCXO }, 488 { .hw = &cam_cc_pll1_out_even.clkr.hw }, 489 }; 490 491 static const struct parent_map cam_cc_parent_map_5[] = { 492 { P_BI_TCXO, 0 }, 493 { P_CAM_CC_PLL6_OUT_EVEN, 6 }, 494 }; 495 496 static const struct clk_parent_data cam_cc_parent_data_5[] = { 497 { .index = DT_BI_TCXO }, 498 { .hw = &cam_cc_pll6_out_even.clkr.hw }, 499 }; 500 501 static const struct parent_map cam_cc_parent_map_6[] = { 502 { P_SLEEP_CLK, 0 }, 503 }; 504 505 static const struct clk_parent_data cam_cc_parent_data_6_ao[] = { 506 { .index = DT_SLEEP_CLK }, 507 }; 508 509 static const struct parent_map cam_cc_parent_map_7[] = { 510 { P_BI_TCXO, 0 }, 511 }; 512 513 static const struct clk_parent_data cam_cc_parent_data_7_ao[] = { 514 { .index = DT_BI_TCXO_AO }, 515 }; 516 517 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { 518 F(19200000, P_BI_TCXO, 1, 0, 0), 519 F(160000000, P_CAM_CC_PLL0_OUT_ODD, 2.5, 0, 0), 520 F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), 521 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 522 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 523 { } 524 }; 525 526 static struct clk_rcg2 cam_cc_bps_clk_src = { 527 .cmd_rcgr = 0x10278, 528 .mnd_width = 0, 529 .hid_width = 5, 530 .parent_map = cam_cc_parent_map_0, 531 .freq_tbl = ftbl_cam_cc_bps_clk_src, 532 .clkr.hw.init = &(const struct clk_init_data) { 533 .name = "cam_cc_bps_clk_src", 534 .parent_data = cam_cc_parent_data_0, 535 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 536 .flags = CLK_SET_RATE_PARENT, 537 .ops = &clk_rcg2_shared_ops, 538 }, 539 }; 540 541 static const struct freq_tbl ftbl_cam_cc_camnoc_axi_rt_clk_src[] = { 542 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), 543 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 544 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 545 { } 546 }; 547 548 static struct clk_rcg2 cam_cc_camnoc_axi_rt_clk_src = { 549 .cmd_rcgr = 0x138f8, 550 .mnd_width = 0, 551 .hid_width = 5, 552 .parent_map = cam_cc_parent_map_0, 553 .freq_tbl = ftbl_cam_cc_camnoc_axi_rt_clk_src, 554 .clkr.hw.init = &(const struct clk_init_data) { 555 .name = "cam_cc_camnoc_axi_rt_clk_src", 556 .parent_data = cam_cc_parent_data_0, 557 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 558 .flags = CLK_SET_RATE_PARENT, 559 .ops = &clk_rcg2_shared_ops, 560 }, 561 }; 562 563 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { 564 F(19200000, P_BI_TCXO, 1, 0, 0), 565 F(30000000, P_CAM_CC_PLL8_OUT_EVEN, 16, 0, 0), 566 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 567 { } 568 }; 569 570 static struct clk_rcg2 cam_cc_cci_0_clk_src = { 571 .cmd_rcgr = 0x1365c, 572 .mnd_width = 8, 573 .hid_width = 5, 574 .parent_map = cam_cc_parent_map_0, 575 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 576 .clkr.hw.init = &(const struct clk_init_data) { 577 .name = "cam_cc_cci_0_clk_src", 578 .parent_data = cam_cc_parent_data_0, 579 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 580 .flags = CLK_SET_RATE_PARENT, 581 .ops = &clk_rcg2_ops, 582 }, 583 }; 584 585 static struct clk_rcg2 cam_cc_cci_1_clk_src = { 586 .cmd_rcgr = 0x1378c, 587 .mnd_width = 8, 588 .hid_width = 5, 589 .parent_map = cam_cc_parent_map_0, 590 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 591 .clkr.hw.init = &(const struct clk_init_data) { 592 .name = "cam_cc_cci_1_clk_src", 593 .parent_data = cam_cc_parent_data_0, 594 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 595 .flags = CLK_SET_RATE_PARENT, 596 .ops = &clk_rcg2_ops, 597 }, 598 }; 599 600 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 601 F(19200000, P_BI_TCXO, 1, 0, 0), 602 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), 603 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 604 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 605 { } 606 }; 607 608 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 609 .cmd_rcgr = 0x11164, 610 .mnd_width = 0, 611 .hid_width = 5, 612 .parent_map = cam_cc_parent_map_0, 613 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 614 .clkr.hw.init = &(const struct clk_init_data) { 615 .name = "cam_cc_cphy_rx_clk_src", 616 .parent_data = cam_cc_parent_data_0, 617 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 618 .flags = CLK_SET_RATE_PARENT, 619 .ops = &clk_rcg2_ops, 620 }, 621 }; 622 623 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 624 F(19200000, P_BI_TCXO, 1, 0, 0), 625 F(266666667, P_CAM_CC_PLL0_OUT_ODD, 1.5, 0, 0), 626 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 627 { } 628 }; 629 630 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 631 .cmd_rcgr = 0x150e0, 632 .mnd_width = 0, 633 .hid_width = 5, 634 .parent_map = cam_cc_parent_map_0, 635 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 636 .clkr.hw.init = &(const struct clk_init_data) { 637 .name = "cam_cc_csi0phytimer_clk_src", 638 .parent_data = cam_cc_parent_data_0, 639 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 640 .flags = CLK_SET_RATE_PARENT, 641 .ops = &clk_rcg2_ops, 642 }, 643 }; 644 645 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 646 .cmd_rcgr = 0x15104, 647 .mnd_width = 0, 648 .hid_width = 5, 649 .parent_map = cam_cc_parent_map_0, 650 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 651 .clkr.hw.init = &(const struct clk_init_data) { 652 .name = "cam_cc_csi1phytimer_clk_src", 653 .parent_data = cam_cc_parent_data_0, 654 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 655 .flags = CLK_SET_RATE_PARENT, 656 .ops = &clk_rcg2_ops, 657 }, 658 }; 659 660 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 661 .cmd_rcgr = 0x15124, 662 .mnd_width = 0, 663 .hid_width = 5, 664 .parent_map = cam_cc_parent_map_0, 665 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 666 .clkr.hw.init = &(const struct clk_init_data) { 667 .name = "cam_cc_csi2phytimer_clk_src", 668 .parent_data = cam_cc_parent_data_0, 669 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 670 .flags = CLK_SET_RATE_PARENT, 671 .ops = &clk_rcg2_ops, 672 }, 673 }; 674 675 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 676 .cmd_rcgr = 0x15258, 677 .mnd_width = 0, 678 .hid_width = 5, 679 .parent_map = cam_cc_parent_map_0, 680 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 681 .clkr.hw.init = &(const struct clk_init_data) { 682 .name = "cam_cc_csi3phytimer_clk_src", 683 .parent_data = cam_cc_parent_data_0, 684 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 685 .flags = CLK_SET_RATE_PARENT, 686 .ops = &clk_rcg2_ops, 687 }, 688 }; 689 690 static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { 691 .cmd_rcgr = 0x1538c, 692 .mnd_width = 0, 693 .hid_width = 5, 694 .parent_map = cam_cc_parent_map_0, 695 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 696 .clkr.hw.init = &(const struct clk_init_data) { 697 .name = "cam_cc_csi4phytimer_clk_src", 698 .parent_data = cam_cc_parent_data_0, 699 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 700 .flags = CLK_SET_RATE_PARENT, 701 .ops = &clk_rcg2_ops, 702 }, 703 }; 704 705 static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = { 706 .cmd_rcgr = 0x154c0, 707 .mnd_width = 0, 708 .hid_width = 5, 709 .parent_map = cam_cc_parent_map_0, 710 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 711 .clkr.hw.init = &(const struct clk_init_data) { 712 .name = "cam_cc_csi5phytimer_clk_src", 713 .parent_data = cam_cc_parent_data_0, 714 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 715 .flags = CLK_SET_RATE_PARENT, 716 .ops = &clk_rcg2_ops, 717 }, 718 }; 719 720 static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = { 721 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), 722 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 723 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 724 { } 725 }; 726 727 static struct clk_rcg2 cam_cc_csid_clk_src = { 728 .cmd_rcgr = 0x138d4, 729 .mnd_width = 0, 730 .hid_width = 5, 731 .parent_map = cam_cc_parent_map_0, 732 .freq_tbl = ftbl_cam_cc_csid_clk_src, 733 .clkr.hw.init = &(const struct clk_init_data) { 734 .name = "cam_cc_csid_clk_src", 735 .parent_data = cam_cc_parent_data_0, 736 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 737 .flags = CLK_SET_RATE_PARENT, 738 .ops = &clk_rcg2_shared_ops, 739 }, 740 }; 741 742 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 743 F(19200000, P_BI_TCXO, 1, 0, 0), 744 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 745 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 746 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 747 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), 748 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 749 { } 750 }; 751 752 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 753 .cmd_rcgr = 0x10018, 754 .mnd_width = 0, 755 .hid_width = 5, 756 .parent_map = cam_cc_parent_map_0, 757 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 758 .clkr.hw.init = &(const struct clk_init_data) { 759 .name = "cam_cc_fast_ahb_clk_src", 760 .parent_data = cam_cc_parent_data_0, 761 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 762 .flags = CLK_SET_RATE_PARENT, 763 .ops = &clk_rcg2_shared_ops, 764 }, 765 }; 766 767 static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 768 F(19200000, P_BI_TCXO, 1, 0, 0), 769 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 770 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 771 F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), 772 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 773 { } 774 }; 775 776 static struct clk_rcg2 cam_cc_icp_clk_src = { 777 .cmd_rcgr = 0x13520, 778 .mnd_width = 0, 779 .hid_width = 5, 780 .parent_map = cam_cc_parent_map_0, 781 .freq_tbl = ftbl_cam_cc_icp_clk_src, 782 .clkr.hw.init = &(const struct clk_init_data) { 783 .name = "cam_cc_icp_clk_src", 784 .parent_data = cam_cc_parent_data_0, 785 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 786 .flags = CLK_SET_RATE_PARENT, 787 .ops = &clk_rcg2_shared_ops, 788 }, 789 }; 790 791 static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { 792 F(19200000, P_BI_TCXO, 1, 0, 0), 793 F(345600000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 794 F(432000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 795 F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 796 F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 797 F(727000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 798 { } 799 }; 800 801 static struct clk_rcg2 cam_cc_ife_0_clk_src = { 802 .cmd_rcgr = 0x11018, 803 .mnd_width = 0, 804 .hid_width = 5, 805 .parent_map = cam_cc_parent_map_2, 806 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 807 .clkr.hw.init = &(const struct clk_init_data) { 808 .name = "cam_cc_ife_0_clk_src", 809 .parent_data = cam_cc_parent_data_2, 810 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 811 .flags = CLK_SET_RATE_PARENT, 812 .ops = &clk_rcg2_shared_ops, 813 }, 814 }; 815 816 static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = { 817 F(19200000, P_BI_TCXO, 1, 0, 0), 818 F(345600000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 819 F(432000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 820 F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 821 F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 822 F(727000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 823 { } 824 }; 825 826 static struct clk_rcg2 cam_cc_ife_1_clk_src = { 827 .cmd_rcgr = 0x12018, 828 .mnd_width = 0, 829 .hid_width = 5, 830 .parent_map = cam_cc_parent_map_3, 831 .freq_tbl = ftbl_cam_cc_ife_1_clk_src, 832 .clkr.hw.init = &(const struct clk_init_data) { 833 .name = "cam_cc_ife_1_clk_src", 834 .parent_data = cam_cc_parent_data_3, 835 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 836 .flags = CLK_SET_RATE_PARENT, 837 .ops = &clk_rcg2_shared_ops, 838 }, 839 }; 840 841 static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = { 842 F(266666667, P_CAM_CC_PLL0_OUT_ODD, 1.5, 0, 0), 843 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 844 F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), 845 { } 846 }; 847 848 static struct clk_rcg2 cam_cc_ife_lite_clk_src = { 849 .cmd_rcgr = 0x13000, 850 .mnd_width = 0, 851 .hid_width = 5, 852 .parent_map = cam_cc_parent_map_0, 853 .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, 854 .clkr.hw.init = &(const struct clk_init_data) { 855 .name = "cam_cc_ife_lite_clk_src", 856 .parent_data = cam_cc_parent_data_0, 857 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 858 .flags = CLK_SET_RATE_PARENT, 859 .ops = &clk_rcg2_shared_ops, 860 }, 861 }; 862 863 static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { 864 .cmd_rcgr = 0x1313c, 865 .mnd_width = 0, 866 .hid_width = 5, 867 .parent_map = cam_cc_parent_map_0, 868 .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, 869 .clkr.hw.init = &(const struct clk_init_data) { 870 .name = "cam_cc_ife_lite_csid_clk_src", 871 .parent_data = cam_cc_parent_data_0, 872 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 873 .flags = CLK_SET_RATE_PARENT, 874 .ops = &clk_rcg2_shared_ops, 875 }, 876 }; 877 878 static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = { 879 F(304000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 880 F(364000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 881 F(500000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 882 F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 883 F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 884 { } 885 }; 886 887 static struct clk_rcg2 cam_cc_ipe_nps_clk_src = { 888 .cmd_rcgr = 0x103cc, 889 .mnd_width = 0, 890 .hid_width = 5, 891 .parent_map = cam_cc_parent_map_4, 892 .freq_tbl = ftbl_cam_cc_ipe_nps_clk_src, 893 .clkr.hw.init = &(const struct clk_init_data) { 894 .name = "cam_cc_ipe_nps_clk_src", 895 .parent_data = cam_cc_parent_data_4, 896 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 897 .flags = CLK_SET_RATE_PARENT, 898 .ops = &clk_rcg2_shared_ops, 899 }, 900 }; 901 902 static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = { 903 F(19200000, P_BI_TCXO, 1, 0, 0), 904 F(160000000, P_CAM_CC_PLL0_OUT_ODD, 2.5, 0, 0), 905 F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), 906 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 907 F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), 908 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 909 { } 910 }; 911 912 static struct clk_rcg2 cam_cc_jpeg_clk_src = { 913 .cmd_rcgr = 0x133dc, 914 .mnd_width = 0, 915 .hid_width = 5, 916 .parent_map = cam_cc_parent_map_0, 917 .freq_tbl = ftbl_cam_cc_jpeg_clk_src, 918 .clkr.hw.init = &(const struct clk_init_data) { 919 .name = "cam_cc_jpeg_clk_src", 920 .parent_data = cam_cc_parent_data_0, 921 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 922 .flags = CLK_SET_RATE_PARENT, 923 .ops = &clk_rcg2_shared_ops, 924 }, 925 }; 926 927 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 928 F(19200000, P_BI_TCXO, 1, 0, 0), 929 F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4), 930 F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0), 931 { } 932 }; 933 934 static struct clk_rcg2 cam_cc_mclk0_clk_src = { 935 .cmd_rcgr = 0x15000, 936 .mnd_width = 8, 937 .hid_width = 5, 938 .parent_map = cam_cc_parent_map_1, 939 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 940 .clkr.hw.init = &(const struct clk_init_data) { 941 .name = "cam_cc_mclk0_clk_src", 942 .parent_data = cam_cc_parent_data_1, 943 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 944 .flags = CLK_SET_RATE_PARENT, 945 .ops = &clk_rcg2_ops, 946 }, 947 }; 948 949 static struct clk_rcg2 cam_cc_mclk1_clk_src = { 950 .cmd_rcgr = 0x1501c, 951 .mnd_width = 8, 952 .hid_width = 5, 953 .parent_map = cam_cc_parent_map_1, 954 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 955 .clkr.hw.init = &(const struct clk_init_data) { 956 .name = "cam_cc_mclk1_clk_src", 957 .parent_data = cam_cc_parent_data_1, 958 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 959 .flags = CLK_SET_RATE_PARENT, 960 .ops = &clk_rcg2_ops, 961 }, 962 }; 963 964 static struct clk_rcg2 cam_cc_mclk2_clk_src = { 965 .cmd_rcgr = 0x15038, 966 .mnd_width = 8, 967 .hid_width = 5, 968 .parent_map = cam_cc_parent_map_1, 969 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 970 .clkr.hw.init = &(const struct clk_init_data) { 971 .name = "cam_cc_mclk2_clk_src", 972 .parent_data = cam_cc_parent_data_1, 973 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 974 .flags = CLK_SET_RATE_PARENT, 975 .ops = &clk_rcg2_ops, 976 }, 977 }; 978 979 static struct clk_rcg2 cam_cc_mclk3_clk_src = { 980 .cmd_rcgr = 0x15054, 981 .mnd_width = 8, 982 .hid_width = 5, 983 .parent_map = cam_cc_parent_map_1, 984 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 985 .clkr.hw.init = &(const struct clk_init_data) { 986 .name = "cam_cc_mclk3_clk_src", 987 .parent_data = cam_cc_parent_data_1, 988 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 989 .flags = CLK_SET_RATE_PARENT, 990 .ops = &clk_rcg2_ops, 991 }, 992 }; 993 994 static struct clk_rcg2 cam_cc_mclk4_clk_src = { 995 .cmd_rcgr = 0x15070, 996 .mnd_width = 8, 997 .hid_width = 5, 998 .parent_map = cam_cc_parent_map_1, 999 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1000 .clkr.hw.init = &(const struct clk_init_data) { 1001 .name = "cam_cc_mclk4_clk_src", 1002 .parent_data = cam_cc_parent_data_1, 1003 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1004 .flags = CLK_SET_RATE_PARENT, 1005 .ops = &clk_rcg2_ops, 1006 }, 1007 }; 1008 1009 static struct clk_rcg2 cam_cc_mclk5_clk_src = { 1010 .cmd_rcgr = 0x1508c, 1011 .mnd_width = 8, 1012 .hid_width = 5, 1013 .parent_map = cam_cc_parent_map_1, 1014 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1015 .clkr.hw.init = &(const struct clk_init_data) { 1016 .name = "cam_cc_mclk5_clk_src", 1017 .parent_data = cam_cc_parent_data_1, 1018 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1019 .flags = CLK_SET_RATE_PARENT, 1020 .ops = &clk_rcg2_ops, 1021 }, 1022 }; 1023 1024 static struct clk_rcg2 cam_cc_mclk6_clk_src = { 1025 .cmd_rcgr = 0x150a8, 1026 .mnd_width = 8, 1027 .hid_width = 5, 1028 .parent_map = cam_cc_parent_map_1, 1029 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1030 .clkr.hw.init = &(const struct clk_init_data) { 1031 .name = "cam_cc_mclk6_clk_src", 1032 .parent_data = cam_cc_parent_data_1, 1033 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1034 .flags = CLK_SET_RATE_PARENT, 1035 .ops = &clk_rcg2_ops, 1036 }, 1037 }; 1038 1039 static struct clk_rcg2 cam_cc_mclk7_clk_src = { 1040 .cmd_rcgr = 0x150c4, 1041 .mnd_width = 8, 1042 .hid_width = 5, 1043 .parent_map = cam_cc_parent_map_1, 1044 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1045 .clkr.hw.init = &(const struct clk_init_data) { 1046 .name = "cam_cc_mclk7_clk_src", 1047 .parent_data = cam_cc_parent_data_1, 1048 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1049 .flags = CLK_SET_RATE_PARENT, 1050 .ops = &clk_rcg2_ops, 1051 }, 1052 }; 1053 1054 static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = { 1055 F(19200000, P_BI_TCXO, 1, 0, 0), 1056 F(60000000, P_CAM_CC_PLL8_OUT_EVEN, 8, 0, 0), 1057 F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0), 1058 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), 1059 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), 1060 { } 1061 }; 1062 1063 static struct clk_rcg2 cam_cc_qdss_debug_clk_src = { 1064 .cmd_rcgr = 0x13938, 1065 .mnd_width = 0, 1066 .hid_width = 5, 1067 .parent_map = cam_cc_parent_map_0, 1068 .freq_tbl = ftbl_cam_cc_qdss_debug_clk_src, 1069 .hw_clk_ctrl = true, 1070 .clkr.hw.init = &(const struct clk_init_data) { 1071 .name = "cam_cc_qdss_debug_clk_src", 1072 .parent_data = cam_cc_parent_data_0, 1073 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 1074 .flags = CLK_SET_RATE_PARENT, 1075 .ops = &clk_rcg2_shared_ops, 1076 }, 1077 }; 1078 1079 static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = { 1080 F(345600000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1081 F(432000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1082 F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1083 F(675000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1084 F(727000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1085 { } 1086 }; 1087 1088 static struct clk_rcg2 cam_cc_sfe_0_clk_src = { 1089 .cmd_rcgr = 0x13294, 1090 .mnd_width = 0, 1091 .hid_width = 5, 1092 .parent_map = cam_cc_parent_map_5, 1093 .freq_tbl = ftbl_cam_cc_sfe_0_clk_src, 1094 .clkr.hw.init = &(const struct clk_init_data) { 1095 .name = "cam_cc_sfe_0_clk_src", 1096 .parent_data = cam_cc_parent_data_5, 1097 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 1098 .flags = CLK_SET_RATE_PARENT, 1099 .ops = &clk_rcg2_shared_ops, 1100 }, 1101 }; 1102 1103 static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { 1104 F(32000, P_SLEEP_CLK, 1, 0, 0), 1105 { } 1106 }; 1107 1108 static struct clk_rcg2 cam_cc_sleep_clk_src = { 1109 .cmd_rcgr = 0x13aa0, 1110 .mnd_width = 0, 1111 .hid_width = 5, 1112 .parent_map = cam_cc_parent_map_6, 1113 .freq_tbl = ftbl_cam_cc_sleep_clk_src, 1114 .clkr.hw.init = &(const struct clk_init_data) { 1115 .name = "cam_cc_sleep_clk_src", 1116 .parent_data = cam_cc_parent_data_6_ao, 1117 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6_ao), 1118 .flags = CLK_SET_RATE_PARENT, 1119 .ops = &clk_rcg2_ops, 1120 }, 1121 }; 1122 1123 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 1124 F(19200000, P_BI_TCXO, 1, 0, 0), 1125 F(64000000, P_CAM_CC_PLL8_OUT_EVEN, 7.5, 0, 0), 1126 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 1127 { } 1128 }; 1129 1130 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 1131 .cmd_rcgr = 0x10148, 1132 .mnd_width = 8, 1133 .hid_width = 5, 1134 .parent_map = cam_cc_parent_map_0, 1135 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 1136 .clkr.hw.init = &(const struct clk_init_data) { 1137 .name = "cam_cc_slow_ahb_clk_src", 1138 .parent_data = cam_cc_parent_data_0, 1139 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 1140 .flags = CLK_SET_RATE_PARENT, 1141 .ops = &clk_rcg2_shared_ops, 1142 }, 1143 }; 1144 1145 static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { 1146 F(19200000, P_BI_TCXO, 1, 0, 0), 1147 { } 1148 }; 1149 1150 static struct clk_rcg2 cam_cc_xo_clk_src = { 1151 .cmd_rcgr = 0x13a84, 1152 .mnd_width = 0, 1153 .hid_width = 5, 1154 .parent_map = cam_cc_parent_map_7, 1155 .freq_tbl = ftbl_cam_cc_xo_clk_src, 1156 .clkr.hw.init = &(const struct clk_init_data) { 1157 .name = "cam_cc_xo_clk_src", 1158 .parent_data = cam_cc_parent_data_7_ao, 1159 .num_parents = ARRAY_SIZE(cam_cc_parent_data_7_ao), 1160 .flags = CLK_SET_RATE_PARENT, 1161 .ops = &clk_rcg2_ops, 1162 }, 1163 }; 1164 1165 static struct clk_branch cam_cc_bps_ahb_clk = { 1166 .halt_reg = 0x10274, 1167 .halt_check = BRANCH_HALT, 1168 .clkr = { 1169 .enable_reg = 0x10274, 1170 .enable_mask = BIT(0), 1171 .hw.init = &(const struct clk_init_data) { 1172 .name = "cam_cc_bps_ahb_clk", 1173 .parent_hws = (const struct clk_hw*[]) { 1174 &cam_cc_slow_ahb_clk_src.clkr.hw, 1175 }, 1176 .num_parents = 1, 1177 .flags = CLK_SET_RATE_PARENT, 1178 .ops = &clk_branch2_ops, 1179 }, 1180 }, 1181 }; 1182 1183 static struct clk_branch cam_cc_bps_clk = { 1184 .halt_reg = 0x103a4, 1185 .halt_check = BRANCH_HALT, 1186 .clkr = { 1187 .enable_reg = 0x103a4, 1188 .enable_mask = BIT(0), 1189 .hw.init = &(const struct clk_init_data) { 1190 .name = "cam_cc_bps_clk", 1191 .parent_hws = (const struct clk_hw*[]) { 1192 &cam_cc_bps_clk_src.clkr.hw, 1193 }, 1194 .num_parents = 1, 1195 .flags = CLK_SET_RATE_PARENT, 1196 .ops = &clk_branch2_ops, 1197 }, 1198 }, 1199 }; 1200 1201 static struct clk_branch cam_cc_bps_fast_ahb_clk = { 1202 .halt_reg = 0x10144, 1203 .halt_check = BRANCH_HALT, 1204 .clkr = { 1205 .enable_reg = 0x10144, 1206 .enable_mask = BIT(0), 1207 .hw.init = &(const struct clk_init_data) { 1208 .name = "cam_cc_bps_fast_ahb_clk", 1209 .parent_hws = (const struct clk_hw*[]) { 1210 &cam_cc_fast_ahb_clk_src.clkr.hw, 1211 }, 1212 .num_parents = 1, 1213 .flags = CLK_SET_RATE_PARENT, 1214 .ops = &clk_branch2_ops, 1215 }, 1216 }, 1217 }; 1218 1219 static struct clk_branch cam_cc_camnoc_axi_nrt_clk = { 1220 .halt_reg = 0x13920, 1221 .halt_check = BRANCH_HALT, 1222 .clkr = { 1223 .enable_reg = 0x13920, 1224 .enable_mask = BIT(0), 1225 .hw.init = &(const struct clk_init_data) { 1226 .name = "cam_cc_camnoc_axi_nrt_clk", 1227 .parent_hws = (const struct clk_hw*[]) { 1228 &cam_cc_camnoc_axi_rt_clk_src.clkr.hw, 1229 }, 1230 .num_parents = 1, 1231 .flags = CLK_SET_RATE_PARENT, 1232 .ops = &clk_branch2_ops, 1233 }, 1234 }, 1235 }; 1236 1237 static struct clk_branch cam_cc_camnoc_axi_rt_clk = { 1238 .halt_reg = 0x13910, 1239 .halt_check = BRANCH_HALT, 1240 .clkr = { 1241 .enable_reg = 0x13910, 1242 .enable_mask = BIT(0), 1243 .hw.init = &(const struct clk_init_data) { 1244 .name = "cam_cc_camnoc_axi_rt_clk", 1245 .parent_hws = (const struct clk_hw*[]) { 1246 &cam_cc_camnoc_axi_rt_clk_src.clkr.hw, 1247 }, 1248 .num_parents = 1, 1249 .flags = CLK_SET_RATE_PARENT, 1250 .ops = &clk_branch2_ops, 1251 }, 1252 }, 1253 }; 1254 1255 static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { 1256 .halt_reg = 0x1392c, 1257 .halt_check = BRANCH_HALT, 1258 .clkr = { 1259 .enable_reg = 0x1392c, 1260 .enable_mask = BIT(0), 1261 .hw.init = &(const struct clk_init_data) { 1262 .name = "cam_cc_camnoc_dcd_xo_clk", 1263 .parent_hws = (const struct clk_hw*[]) { 1264 &cam_cc_xo_clk_src.clkr.hw, 1265 }, 1266 .num_parents = 1, 1267 .flags = CLK_SET_RATE_PARENT, 1268 .ops = &clk_branch2_ops, 1269 }, 1270 }, 1271 }; 1272 1273 static struct clk_branch cam_cc_camnoc_xo_clk = { 1274 .halt_reg = 0x13930, 1275 .halt_check = BRANCH_HALT, 1276 .clkr = { 1277 .enable_reg = 0x13930, 1278 .enable_mask = BIT(0), 1279 .hw.init = &(const struct clk_init_data) { 1280 .name = "cam_cc_camnoc_xo_clk", 1281 .parent_hws = (const struct clk_hw*[]) { 1282 &cam_cc_xo_clk_src.clkr.hw, 1283 }, 1284 .num_parents = 1, 1285 .flags = CLK_SET_RATE_PARENT, 1286 .ops = &clk_branch2_ops, 1287 }, 1288 }, 1289 }; 1290 1291 static struct clk_branch cam_cc_cci_0_clk = { 1292 .halt_reg = 0x13788, 1293 .halt_check = BRANCH_HALT, 1294 .clkr = { 1295 .enable_reg = 0x13788, 1296 .enable_mask = BIT(0), 1297 .hw.init = &(const struct clk_init_data) { 1298 .name = "cam_cc_cci_0_clk", 1299 .parent_hws = (const struct clk_hw*[]) { 1300 &cam_cc_cci_0_clk_src.clkr.hw, 1301 }, 1302 .num_parents = 1, 1303 .flags = CLK_SET_RATE_PARENT, 1304 .ops = &clk_branch2_ops, 1305 }, 1306 }, 1307 }; 1308 1309 static struct clk_branch cam_cc_cci_1_clk = { 1310 .halt_reg = 0x138b8, 1311 .halt_check = BRANCH_HALT, 1312 .clkr = { 1313 .enable_reg = 0x138b8, 1314 .enable_mask = BIT(0), 1315 .hw.init = &(const struct clk_init_data) { 1316 .name = "cam_cc_cci_1_clk", 1317 .parent_hws = (const struct clk_hw*[]) { 1318 &cam_cc_cci_1_clk_src.clkr.hw, 1319 }, 1320 .num_parents = 1, 1321 .flags = CLK_SET_RATE_PARENT, 1322 .ops = &clk_branch2_ops, 1323 }, 1324 }, 1325 }; 1326 1327 static struct clk_branch cam_cc_core_ahb_clk = { 1328 .halt_reg = 0x13a80, 1329 .halt_check = BRANCH_HALT_VOTED, 1330 .clkr = { 1331 .enable_reg = 0x13a80, 1332 .enable_mask = BIT(0), 1333 .hw.init = &(const struct clk_init_data) { 1334 .name = "cam_cc_core_ahb_clk", 1335 .parent_hws = (const struct clk_hw*[]) { 1336 &cam_cc_slow_ahb_clk_src.clkr.hw, 1337 }, 1338 .num_parents = 1, 1339 .flags = CLK_SET_RATE_PARENT, 1340 .ops = &clk_branch2_ops, 1341 }, 1342 }, 1343 }; 1344 1345 static struct clk_branch cam_cc_cpas_ahb_clk = { 1346 .halt_reg = 0x138bc, 1347 .halt_check = BRANCH_HALT, 1348 .clkr = { 1349 .enable_reg = 0x138bc, 1350 .enable_mask = BIT(0), 1351 .hw.init = &(const struct clk_init_data) { 1352 .name = "cam_cc_cpas_ahb_clk", 1353 .parent_hws = (const struct clk_hw*[]) { 1354 &cam_cc_slow_ahb_clk_src.clkr.hw, 1355 }, 1356 .num_parents = 1, 1357 .flags = CLK_SET_RATE_PARENT, 1358 .ops = &clk_branch2_ops, 1359 }, 1360 }, 1361 }; 1362 1363 static struct clk_branch cam_cc_cpas_bps_clk = { 1364 .halt_reg = 0x103b0, 1365 .halt_check = BRANCH_HALT, 1366 .clkr = { 1367 .enable_reg = 0x103b0, 1368 .enable_mask = BIT(0), 1369 .hw.init = &(const struct clk_init_data) { 1370 .name = "cam_cc_cpas_bps_clk", 1371 .parent_hws = (const struct clk_hw*[]) { 1372 &cam_cc_bps_clk_src.clkr.hw, 1373 }, 1374 .num_parents = 1, 1375 .flags = CLK_SET_RATE_PARENT, 1376 .ops = &clk_branch2_ops, 1377 }, 1378 }, 1379 }; 1380 1381 static struct clk_branch cam_cc_cpas_fast_ahb_clk = { 1382 .halt_reg = 0x138c8, 1383 .halt_check = BRANCH_HALT, 1384 .clkr = { 1385 .enable_reg = 0x138c8, 1386 .enable_mask = BIT(0), 1387 .hw.init = &(const struct clk_init_data) { 1388 .name = "cam_cc_cpas_fast_ahb_clk", 1389 .parent_hws = (const struct clk_hw*[]) { 1390 &cam_cc_fast_ahb_clk_src.clkr.hw, 1391 }, 1392 .num_parents = 1, 1393 .flags = CLK_SET_RATE_PARENT, 1394 .ops = &clk_branch2_ops, 1395 }, 1396 }, 1397 }; 1398 1399 static struct clk_branch cam_cc_cpas_ife_0_clk = { 1400 .halt_reg = 0x11150, 1401 .halt_check = BRANCH_HALT, 1402 .clkr = { 1403 .enable_reg = 0x11150, 1404 .enable_mask = BIT(0), 1405 .hw.init = &(const struct clk_init_data) { 1406 .name = "cam_cc_cpas_ife_0_clk", 1407 .parent_hws = (const struct clk_hw*[]) { 1408 &cam_cc_ife_0_clk_src.clkr.hw, 1409 }, 1410 .num_parents = 1, 1411 .flags = CLK_SET_RATE_PARENT, 1412 .ops = &clk_branch2_ops, 1413 }, 1414 }, 1415 }; 1416 1417 static struct clk_branch cam_cc_cpas_ife_1_clk = { 1418 .halt_reg = 0x1203c, 1419 .halt_check = BRANCH_HALT, 1420 .clkr = { 1421 .enable_reg = 0x1203c, 1422 .enable_mask = BIT(0), 1423 .hw.init = &(const struct clk_init_data) { 1424 .name = "cam_cc_cpas_ife_1_clk", 1425 .parent_hws = (const struct clk_hw*[]) { 1426 &cam_cc_ife_1_clk_src.clkr.hw, 1427 }, 1428 .num_parents = 1, 1429 .flags = CLK_SET_RATE_PARENT, 1430 .ops = &clk_branch2_ops, 1431 }, 1432 }, 1433 }; 1434 1435 static struct clk_branch cam_cc_cpas_ife_lite_clk = { 1436 .halt_reg = 0x13138, 1437 .halt_check = BRANCH_HALT, 1438 .clkr = { 1439 .enable_reg = 0x13138, 1440 .enable_mask = BIT(0), 1441 .hw.init = &(const struct clk_init_data) { 1442 .name = "cam_cc_cpas_ife_lite_clk", 1443 .parent_hws = (const struct clk_hw*[]) { 1444 &cam_cc_ife_lite_clk_src.clkr.hw, 1445 }, 1446 .num_parents = 1, 1447 .flags = CLK_SET_RATE_PARENT, 1448 .ops = &clk_branch2_ops, 1449 }, 1450 }, 1451 }; 1452 1453 static struct clk_branch cam_cc_cpas_ipe_nps_clk = { 1454 .halt_reg = 0x10504, 1455 .halt_check = BRANCH_HALT, 1456 .clkr = { 1457 .enable_reg = 0x10504, 1458 .enable_mask = BIT(0), 1459 .hw.init = &(const struct clk_init_data) { 1460 .name = "cam_cc_cpas_ipe_nps_clk", 1461 .parent_hws = (const struct clk_hw*[]) { 1462 &cam_cc_ipe_nps_clk_src.clkr.hw, 1463 }, 1464 .num_parents = 1, 1465 .flags = CLK_SET_RATE_PARENT, 1466 .ops = &clk_branch2_ops, 1467 }, 1468 }, 1469 }; 1470 1471 static struct clk_branch cam_cc_cpas_sfe_0_clk = { 1472 .halt_reg = 0x133cc, 1473 .halt_check = BRANCH_HALT, 1474 .clkr = { 1475 .enable_reg = 0x133cc, 1476 .enable_mask = BIT(0), 1477 .hw.init = &(const struct clk_init_data) { 1478 .name = "cam_cc_cpas_sfe_0_clk", 1479 .parent_hws = (const struct clk_hw*[]) { 1480 &cam_cc_sfe_0_clk_src.clkr.hw, 1481 }, 1482 .num_parents = 1, 1483 .flags = CLK_SET_RATE_PARENT, 1484 .ops = &clk_branch2_ops, 1485 }, 1486 }, 1487 }; 1488 1489 static struct clk_branch cam_cc_csi0phytimer_clk = { 1490 .halt_reg = 0x150f8, 1491 .halt_check = BRANCH_HALT, 1492 .clkr = { 1493 .enable_reg = 0x150f8, 1494 .enable_mask = BIT(0), 1495 .hw.init = &(const struct clk_init_data) { 1496 .name = "cam_cc_csi0phytimer_clk", 1497 .parent_hws = (const struct clk_hw*[]) { 1498 &cam_cc_csi0phytimer_clk_src.clkr.hw, 1499 }, 1500 .num_parents = 1, 1501 .flags = CLK_SET_RATE_PARENT, 1502 .ops = &clk_branch2_ops, 1503 }, 1504 }, 1505 }; 1506 1507 static struct clk_branch cam_cc_csi1phytimer_clk = { 1508 .halt_reg = 0x1511c, 1509 .halt_check = BRANCH_HALT, 1510 .clkr = { 1511 .enable_reg = 0x1511c, 1512 .enable_mask = BIT(0), 1513 .hw.init = &(const struct clk_init_data) { 1514 .name = "cam_cc_csi1phytimer_clk", 1515 .parent_hws = (const struct clk_hw*[]) { 1516 &cam_cc_csi1phytimer_clk_src.clkr.hw, 1517 }, 1518 .num_parents = 1, 1519 .flags = CLK_SET_RATE_PARENT, 1520 .ops = &clk_branch2_ops, 1521 }, 1522 }, 1523 }; 1524 1525 static struct clk_branch cam_cc_csi2phytimer_clk = { 1526 .halt_reg = 0x15250, 1527 .halt_check = BRANCH_HALT, 1528 .clkr = { 1529 .enable_reg = 0x15250, 1530 .enable_mask = BIT(0), 1531 .hw.init = &(const struct clk_init_data) { 1532 .name = "cam_cc_csi2phytimer_clk", 1533 .parent_hws = (const struct clk_hw*[]) { 1534 &cam_cc_csi2phytimer_clk_src.clkr.hw, 1535 }, 1536 .num_parents = 1, 1537 .flags = CLK_SET_RATE_PARENT, 1538 .ops = &clk_branch2_ops, 1539 }, 1540 }, 1541 }; 1542 1543 static struct clk_branch cam_cc_csi3phytimer_clk = { 1544 .halt_reg = 0x15384, 1545 .halt_check = BRANCH_HALT, 1546 .clkr = { 1547 .enable_reg = 0x15384, 1548 .enable_mask = BIT(0), 1549 .hw.init = &(const struct clk_init_data) { 1550 .name = "cam_cc_csi3phytimer_clk", 1551 .parent_hws = (const struct clk_hw*[]) { 1552 &cam_cc_csi3phytimer_clk_src.clkr.hw, 1553 }, 1554 .num_parents = 1, 1555 .flags = CLK_SET_RATE_PARENT, 1556 .ops = &clk_branch2_ops, 1557 }, 1558 }, 1559 }; 1560 1561 static struct clk_branch cam_cc_csi4phytimer_clk = { 1562 .halt_reg = 0x154b8, 1563 .halt_check = BRANCH_HALT, 1564 .clkr = { 1565 .enable_reg = 0x154b8, 1566 .enable_mask = BIT(0), 1567 .hw.init = &(const struct clk_init_data) { 1568 .name = "cam_cc_csi4phytimer_clk", 1569 .parent_hws = (const struct clk_hw*[]) { 1570 &cam_cc_csi4phytimer_clk_src.clkr.hw, 1571 }, 1572 .num_parents = 1, 1573 .flags = CLK_SET_RATE_PARENT, 1574 .ops = &clk_branch2_ops, 1575 }, 1576 }, 1577 }; 1578 1579 static struct clk_branch cam_cc_csi5phytimer_clk = { 1580 .halt_reg = 0x155ec, 1581 .halt_check = BRANCH_HALT, 1582 .clkr = { 1583 .enable_reg = 0x155ec, 1584 .enable_mask = BIT(0), 1585 .hw.init = &(const struct clk_init_data) { 1586 .name = "cam_cc_csi5phytimer_clk", 1587 .parent_hws = (const struct clk_hw*[]) { 1588 &cam_cc_csi5phytimer_clk_src.clkr.hw, 1589 }, 1590 .num_parents = 1, 1591 .flags = CLK_SET_RATE_PARENT, 1592 .ops = &clk_branch2_ops, 1593 }, 1594 }, 1595 }; 1596 1597 static struct clk_branch cam_cc_csid_clk = { 1598 .halt_reg = 0x138ec, 1599 .halt_check = BRANCH_HALT, 1600 .clkr = { 1601 .enable_reg = 0x138ec, 1602 .enable_mask = BIT(0), 1603 .hw.init = &(const struct clk_init_data) { 1604 .name = "cam_cc_csid_clk", 1605 .parent_hws = (const struct clk_hw*[]) { 1606 &cam_cc_csid_clk_src.clkr.hw, 1607 }, 1608 .num_parents = 1, 1609 .flags = CLK_SET_RATE_PARENT, 1610 .ops = &clk_branch2_ops, 1611 }, 1612 }, 1613 }; 1614 1615 static struct clk_branch cam_cc_csid_csiphy_rx_clk = { 1616 .halt_reg = 0x15100, 1617 .halt_check = BRANCH_HALT, 1618 .clkr = { 1619 .enable_reg = 0x15100, 1620 .enable_mask = BIT(0), 1621 .hw.init = &(const struct clk_init_data) { 1622 .name = "cam_cc_csid_csiphy_rx_clk", 1623 .parent_hws = (const struct clk_hw*[]) { 1624 &cam_cc_cphy_rx_clk_src.clkr.hw, 1625 }, 1626 .num_parents = 1, 1627 .flags = CLK_SET_RATE_PARENT, 1628 .ops = &clk_branch2_ops, 1629 }, 1630 }, 1631 }; 1632 1633 static struct clk_branch cam_cc_csiphy0_clk = { 1634 .halt_reg = 0x150fc, 1635 .halt_check = BRANCH_HALT, 1636 .clkr = { 1637 .enable_reg = 0x150fc, 1638 .enable_mask = BIT(0), 1639 .hw.init = &(const struct clk_init_data) { 1640 .name = "cam_cc_csiphy0_clk", 1641 .parent_hws = (const struct clk_hw*[]) { 1642 &cam_cc_cphy_rx_clk_src.clkr.hw, 1643 }, 1644 .num_parents = 1, 1645 .flags = CLK_SET_RATE_PARENT, 1646 .ops = &clk_branch2_ops, 1647 }, 1648 }, 1649 }; 1650 1651 static struct clk_branch cam_cc_csiphy1_clk = { 1652 .halt_reg = 0x15120, 1653 .halt_check = BRANCH_HALT, 1654 .clkr = { 1655 .enable_reg = 0x15120, 1656 .enable_mask = BIT(0), 1657 .hw.init = &(const struct clk_init_data) { 1658 .name = "cam_cc_csiphy1_clk", 1659 .parent_hws = (const struct clk_hw*[]) { 1660 &cam_cc_cphy_rx_clk_src.clkr.hw, 1661 }, 1662 .num_parents = 1, 1663 .flags = CLK_SET_RATE_PARENT, 1664 .ops = &clk_branch2_ops, 1665 }, 1666 }, 1667 }; 1668 1669 static struct clk_branch cam_cc_csiphy2_clk = { 1670 .halt_reg = 0x15254, 1671 .halt_check = BRANCH_HALT, 1672 .clkr = { 1673 .enable_reg = 0x15254, 1674 .enable_mask = BIT(0), 1675 .hw.init = &(const struct clk_init_data) { 1676 .name = "cam_cc_csiphy2_clk", 1677 .parent_hws = (const struct clk_hw*[]) { 1678 &cam_cc_cphy_rx_clk_src.clkr.hw, 1679 }, 1680 .num_parents = 1, 1681 .flags = CLK_SET_RATE_PARENT, 1682 .ops = &clk_branch2_ops, 1683 }, 1684 }, 1685 }; 1686 1687 static struct clk_branch cam_cc_csiphy3_clk = { 1688 .halt_reg = 0x15388, 1689 .halt_check = BRANCH_HALT, 1690 .clkr = { 1691 .enable_reg = 0x15388, 1692 .enable_mask = BIT(0), 1693 .hw.init = &(const struct clk_init_data) { 1694 .name = "cam_cc_csiphy3_clk", 1695 .parent_hws = (const struct clk_hw*[]) { 1696 &cam_cc_cphy_rx_clk_src.clkr.hw, 1697 }, 1698 .num_parents = 1, 1699 .flags = CLK_SET_RATE_PARENT, 1700 .ops = &clk_branch2_ops, 1701 }, 1702 }, 1703 }; 1704 1705 static struct clk_branch cam_cc_csiphy4_clk = { 1706 .halt_reg = 0x154bc, 1707 .halt_check = BRANCH_HALT, 1708 .clkr = { 1709 .enable_reg = 0x154bc, 1710 .enable_mask = BIT(0), 1711 .hw.init = &(const struct clk_init_data) { 1712 .name = "cam_cc_csiphy4_clk", 1713 .parent_hws = (const struct clk_hw*[]) { 1714 &cam_cc_cphy_rx_clk_src.clkr.hw, 1715 }, 1716 .num_parents = 1, 1717 .flags = CLK_SET_RATE_PARENT, 1718 .ops = &clk_branch2_ops, 1719 }, 1720 }, 1721 }; 1722 1723 static struct clk_branch cam_cc_csiphy5_clk = { 1724 .halt_reg = 0x155f0, 1725 .halt_check = BRANCH_HALT, 1726 .clkr = { 1727 .enable_reg = 0x155f0, 1728 .enable_mask = BIT(0), 1729 .hw.init = &(const struct clk_init_data) { 1730 .name = "cam_cc_csiphy5_clk", 1731 .parent_hws = (const struct clk_hw*[]) { 1732 &cam_cc_cphy_rx_clk_src.clkr.hw, 1733 }, 1734 .num_parents = 1, 1735 .flags = CLK_SET_RATE_PARENT, 1736 .ops = &clk_branch2_ops, 1737 }, 1738 }, 1739 }; 1740 1741 static struct clk_branch cam_cc_icp_ahb_clk = { 1742 .halt_reg = 0x13658, 1743 .halt_check = BRANCH_HALT, 1744 .clkr = { 1745 .enable_reg = 0x13658, 1746 .enable_mask = BIT(0), 1747 .hw.init = &(const struct clk_init_data) { 1748 .name = "cam_cc_icp_ahb_clk", 1749 .parent_hws = (const struct clk_hw*[]) { 1750 &cam_cc_slow_ahb_clk_src.clkr.hw, 1751 }, 1752 .num_parents = 1, 1753 .flags = CLK_SET_RATE_PARENT, 1754 .ops = &clk_branch2_ops, 1755 }, 1756 }, 1757 }; 1758 1759 static struct clk_branch cam_cc_icp_clk = { 1760 .halt_reg = 0x1364c, 1761 .halt_check = BRANCH_HALT, 1762 .clkr = { 1763 .enable_reg = 0x1364c, 1764 .enable_mask = BIT(0), 1765 .hw.init = &(const struct clk_init_data) { 1766 .name = "cam_cc_icp_clk", 1767 .parent_hws = (const struct clk_hw*[]) { 1768 &cam_cc_icp_clk_src.clkr.hw, 1769 }, 1770 .num_parents = 1, 1771 .flags = CLK_SET_RATE_PARENT, 1772 .ops = &clk_branch2_ops, 1773 }, 1774 }, 1775 }; 1776 1777 static struct clk_branch cam_cc_ife_0_clk = { 1778 .halt_reg = 0x11144, 1779 .halt_check = BRANCH_HALT, 1780 .clkr = { 1781 .enable_reg = 0x11144, 1782 .enable_mask = BIT(0), 1783 .hw.init = &(const struct clk_init_data) { 1784 .name = "cam_cc_ife_0_clk", 1785 .parent_hws = (const struct clk_hw*[]) { 1786 &cam_cc_ife_0_clk_src.clkr.hw, 1787 }, 1788 .num_parents = 1, 1789 .flags = CLK_SET_RATE_PARENT, 1790 .ops = &clk_branch2_ops, 1791 }, 1792 }, 1793 }; 1794 1795 static struct clk_branch cam_cc_ife_0_dsp_clk = { 1796 .halt_reg = 0x11154, 1797 .halt_check = BRANCH_HALT, 1798 .clkr = { 1799 .enable_reg = 0x11154, 1800 .enable_mask = BIT(0), 1801 .hw.init = &(const struct clk_init_data) { 1802 .name = "cam_cc_ife_0_dsp_clk", 1803 .parent_hws = (const struct clk_hw*[]) { 1804 &cam_cc_ife_0_clk_src.clkr.hw, 1805 }, 1806 .num_parents = 1, 1807 .flags = CLK_SET_RATE_PARENT, 1808 .ops = &clk_branch2_ops, 1809 }, 1810 }, 1811 }; 1812 1813 static struct clk_branch cam_cc_ife_0_fast_ahb_clk = { 1814 .halt_reg = 0x11160, 1815 .halt_check = BRANCH_HALT, 1816 .clkr = { 1817 .enable_reg = 0x11160, 1818 .enable_mask = BIT(0), 1819 .hw.init = &(const struct clk_init_data) { 1820 .name = "cam_cc_ife_0_fast_ahb_clk", 1821 .parent_hws = (const struct clk_hw*[]) { 1822 &cam_cc_fast_ahb_clk_src.clkr.hw, 1823 }, 1824 .num_parents = 1, 1825 .flags = CLK_SET_RATE_PARENT, 1826 .ops = &clk_branch2_ops, 1827 }, 1828 }, 1829 }; 1830 1831 static struct clk_branch cam_cc_ife_1_clk = { 1832 .halt_reg = 0x12030, 1833 .halt_check = BRANCH_HALT, 1834 .clkr = { 1835 .enable_reg = 0x12030, 1836 .enable_mask = BIT(0), 1837 .hw.init = &(const struct clk_init_data) { 1838 .name = "cam_cc_ife_1_clk", 1839 .parent_hws = (const struct clk_hw*[]) { 1840 &cam_cc_ife_1_clk_src.clkr.hw, 1841 }, 1842 .num_parents = 1, 1843 .flags = CLK_SET_RATE_PARENT, 1844 .ops = &clk_branch2_ops, 1845 }, 1846 }, 1847 }; 1848 1849 static struct clk_branch cam_cc_ife_1_dsp_clk = { 1850 .halt_reg = 0x12040, 1851 .halt_check = BRANCH_HALT, 1852 .clkr = { 1853 .enable_reg = 0x12040, 1854 .enable_mask = BIT(0), 1855 .hw.init = &(const struct clk_init_data) { 1856 .name = "cam_cc_ife_1_dsp_clk", 1857 .parent_hws = (const struct clk_hw*[]) { 1858 &cam_cc_ife_1_clk_src.clkr.hw, 1859 }, 1860 .num_parents = 1, 1861 .flags = CLK_SET_RATE_PARENT, 1862 .ops = &clk_branch2_ops, 1863 }, 1864 }, 1865 }; 1866 1867 static struct clk_branch cam_cc_ife_1_fast_ahb_clk = { 1868 .halt_reg = 0x1204c, 1869 .halt_check = BRANCH_HALT, 1870 .clkr = { 1871 .enable_reg = 0x1204c, 1872 .enable_mask = BIT(0), 1873 .hw.init = &(const struct clk_init_data) { 1874 .name = "cam_cc_ife_1_fast_ahb_clk", 1875 .parent_hws = (const struct clk_hw*[]) { 1876 &cam_cc_fast_ahb_clk_src.clkr.hw, 1877 }, 1878 .num_parents = 1, 1879 .flags = CLK_SET_RATE_PARENT, 1880 .ops = &clk_branch2_ops, 1881 }, 1882 }, 1883 }; 1884 1885 static struct clk_branch cam_cc_ife_lite_ahb_clk = { 1886 .halt_reg = 0x13278, 1887 .halt_check = BRANCH_HALT, 1888 .clkr = { 1889 .enable_reg = 0x13278, 1890 .enable_mask = BIT(0), 1891 .hw.init = &(const struct clk_init_data) { 1892 .name = "cam_cc_ife_lite_ahb_clk", 1893 .parent_hws = (const struct clk_hw*[]) { 1894 &cam_cc_slow_ahb_clk_src.clkr.hw, 1895 }, 1896 .num_parents = 1, 1897 .flags = CLK_SET_RATE_PARENT, 1898 .ops = &clk_branch2_ops, 1899 }, 1900 }, 1901 }; 1902 1903 static struct clk_branch cam_cc_ife_lite_clk = { 1904 .halt_reg = 0x1312c, 1905 .halt_check = BRANCH_HALT, 1906 .clkr = { 1907 .enable_reg = 0x1312c, 1908 .enable_mask = BIT(0), 1909 .hw.init = &(const struct clk_init_data) { 1910 .name = "cam_cc_ife_lite_clk", 1911 .parent_hws = (const struct clk_hw*[]) { 1912 &cam_cc_ife_lite_clk_src.clkr.hw, 1913 }, 1914 .num_parents = 1, 1915 .flags = CLK_SET_RATE_PARENT, 1916 .ops = &clk_branch2_ops, 1917 }, 1918 }, 1919 }; 1920 1921 static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { 1922 .halt_reg = 0x13274, 1923 .halt_check = BRANCH_HALT, 1924 .clkr = { 1925 .enable_reg = 0x13274, 1926 .enable_mask = BIT(0), 1927 .hw.init = &(const struct clk_init_data) { 1928 .name = "cam_cc_ife_lite_cphy_rx_clk", 1929 .parent_hws = (const struct clk_hw*[]) { 1930 &cam_cc_cphy_rx_clk_src.clkr.hw, 1931 }, 1932 .num_parents = 1, 1933 .flags = CLK_SET_RATE_PARENT, 1934 .ops = &clk_branch2_ops, 1935 }, 1936 }, 1937 }; 1938 1939 static struct clk_branch cam_cc_ife_lite_csid_clk = { 1940 .halt_reg = 0x13268, 1941 .halt_check = BRANCH_HALT, 1942 .clkr = { 1943 .enable_reg = 0x13268, 1944 .enable_mask = BIT(0), 1945 .hw.init = &(const struct clk_init_data) { 1946 .name = "cam_cc_ife_lite_csid_clk", 1947 .parent_hws = (const struct clk_hw*[]) { 1948 &cam_cc_ife_lite_csid_clk_src.clkr.hw, 1949 }, 1950 .num_parents = 1, 1951 .flags = CLK_SET_RATE_PARENT, 1952 .ops = &clk_branch2_ops, 1953 }, 1954 }, 1955 }; 1956 1957 static struct clk_branch cam_cc_ipe_nps_ahb_clk = { 1958 .halt_reg = 0x1051c, 1959 .halt_check = BRANCH_HALT, 1960 .clkr = { 1961 .enable_reg = 0x1051c, 1962 .enable_mask = BIT(0), 1963 .hw.init = &(const struct clk_init_data) { 1964 .name = "cam_cc_ipe_nps_ahb_clk", 1965 .parent_hws = (const struct clk_hw*[]) { 1966 &cam_cc_slow_ahb_clk_src.clkr.hw, 1967 }, 1968 .num_parents = 1, 1969 .flags = CLK_SET_RATE_PARENT, 1970 .ops = &clk_branch2_ops, 1971 }, 1972 }, 1973 }; 1974 1975 static struct clk_branch cam_cc_ipe_nps_clk = { 1976 .halt_reg = 0x104f8, 1977 .halt_check = BRANCH_HALT, 1978 .clkr = { 1979 .enable_reg = 0x104f8, 1980 .enable_mask = BIT(0), 1981 .hw.init = &(const struct clk_init_data) { 1982 .name = "cam_cc_ipe_nps_clk", 1983 .parent_hws = (const struct clk_hw*[]) { 1984 &cam_cc_ipe_nps_clk_src.clkr.hw, 1985 }, 1986 .num_parents = 1, 1987 .flags = CLK_SET_RATE_PARENT, 1988 .ops = &clk_branch2_ops, 1989 }, 1990 }, 1991 }; 1992 1993 static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = { 1994 .halt_reg = 0x10520, 1995 .halt_check = BRANCH_HALT, 1996 .clkr = { 1997 .enable_reg = 0x10520, 1998 .enable_mask = BIT(0), 1999 .hw.init = &(const struct clk_init_data) { 2000 .name = "cam_cc_ipe_nps_fast_ahb_clk", 2001 .parent_hws = (const struct clk_hw*[]) { 2002 &cam_cc_fast_ahb_clk_src.clkr.hw, 2003 }, 2004 .num_parents = 1, 2005 .flags = CLK_SET_RATE_PARENT, 2006 .ops = &clk_branch2_ops, 2007 }, 2008 }, 2009 }; 2010 2011 static struct clk_branch cam_cc_ipe_pps_clk = { 2012 .halt_reg = 0x10508, 2013 .halt_check = BRANCH_HALT, 2014 .clkr = { 2015 .enable_reg = 0x10508, 2016 .enable_mask = BIT(0), 2017 .hw.init = &(const struct clk_init_data) { 2018 .name = "cam_cc_ipe_pps_clk", 2019 .parent_hws = (const struct clk_hw*[]) { 2020 &cam_cc_ipe_nps_clk_src.clkr.hw, 2021 }, 2022 .num_parents = 1, 2023 .flags = CLK_SET_RATE_PARENT, 2024 .ops = &clk_branch2_ops, 2025 }, 2026 }, 2027 }; 2028 2029 static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = { 2030 .halt_reg = 0x10524, 2031 .halt_check = BRANCH_HALT, 2032 .clkr = { 2033 .enable_reg = 0x10524, 2034 .enable_mask = BIT(0), 2035 .hw.init = &(const struct clk_init_data) { 2036 .name = "cam_cc_ipe_pps_fast_ahb_clk", 2037 .parent_hws = (const struct clk_hw*[]) { 2038 &cam_cc_fast_ahb_clk_src.clkr.hw, 2039 }, 2040 .num_parents = 1, 2041 .flags = CLK_SET_RATE_PARENT, 2042 .ops = &clk_branch2_ops, 2043 }, 2044 }, 2045 }; 2046 2047 static struct clk_branch cam_cc_jpeg_clk = { 2048 .halt_reg = 0x13508, 2049 .halt_check = BRANCH_HALT, 2050 .clkr = { 2051 .enable_reg = 0x13508, 2052 .enable_mask = BIT(0), 2053 .hw.init = &(const struct clk_init_data) { 2054 .name = "cam_cc_jpeg_clk", 2055 .parent_hws = (const struct clk_hw*[]) { 2056 &cam_cc_jpeg_clk_src.clkr.hw, 2057 }, 2058 .num_parents = 1, 2059 .flags = CLK_SET_RATE_PARENT, 2060 .ops = &clk_branch2_ops, 2061 }, 2062 }, 2063 }; 2064 2065 static struct clk_branch cam_cc_mclk0_clk = { 2066 .halt_reg = 0x15018, 2067 .halt_check = BRANCH_HALT, 2068 .clkr = { 2069 .enable_reg = 0x15018, 2070 .enable_mask = BIT(0), 2071 .hw.init = &(const struct clk_init_data) { 2072 .name = "cam_cc_mclk0_clk", 2073 .parent_hws = (const struct clk_hw*[]) { 2074 &cam_cc_mclk0_clk_src.clkr.hw, 2075 }, 2076 .num_parents = 1, 2077 .flags = CLK_SET_RATE_PARENT, 2078 .ops = &clk_branch2_ops, 2079 }, 2080 }, 2081 }; 2082 2083 static struct clk_branch cam_cc_mclk1_clk = { 2084 .halt_reg = 0x15034, 2085 .halt_check = BRANCH_HALT, 2086 .clkr = { 2087 .enable_reg = 0x15034, 2088 .enable_mask = BIT(0), 2089 .hw.init = &(const struct clk_init_data) { 2090 .name = "cam_cc_mclk1_clk", 2091 .parent_hws = (const struct clk_hw*[]) { 2092 &cam_cc_mclk1_clk_src.clkr.hw, 2093 }, 2094 .num_parents = 1, 2095 .flags = CLK_SET_RATE_PARENT, 2096 .ops = &clk_branch2_ops, 2097 }, 2098 }, 2099 }; 2100 2101 static struct clk_branch cam_cc_mclk2_clk = { 2102 .halt_reg = 0x15050, 2103 .halt_check = BRANCH_HALT, 2104 .clkr = { 2105 .enable_reg = 0x15050, 2106 .enable_mask = BIT(0), 2107 .hw.init = &(const struct clk_init_data) { 2108 .name = "cam_cc_mclk2_clk", 2109 .parent_hws = (const struct clk_hw*[]) { 2110 &cam_cc_mclk2_clk_src.clkr.hw, 2111 }, 2112 .num_parents = 1, 2113 .flags = CLK_SET_RATE_PARENT, 2114 .ops = &clk_branch2_ops, 2115 }, 2116 }, 2117 }; 2118 2119 static struct clk_branch cam_cc_mclk3_clk = { 2120 .halt_reg = 0x1506c, 2121 .halt_check = BRANCH_HALT, 2122 .clkr = { 2123 .enable_reg = 0x1506c, 2124 .enable_mask = BIT(0), 2125 .hw.init = &(const struct clk_init_data) { 2126 .name = "cam_cc_mclk3_clk", 2127 .parent_hws = (const struct clk_hw*[]) { 2128 &cam_cc_mclk3_clk_src.clkr.hw, 2129 }, 2130 .num_parents = 1, 2131 .flags = CLK_SET_RATE_PARENT, 2132 .ops = &clk_branch2_ops, 2133 }, 2134 }, 2135 }; 2136 2137 static struct clk_branch cam_cc_mclk4_clk = { 2138 .halt_reg = 0x15088, 2139 .halt_check = BRANCH_HALT, 2140 .clkr = { 2141 .enable_reg = 0x15088, 2142 .enable_mask = BIT(0), 2143 .hw.init = &(const struct clk_init_data) { 2144 .name = "cam_cc_mclk4_clk", 2145 .parent_hws = (const struct clk_hw*[]) { 2146 &cam_cc_mclk4_clk_src.clkr.hw, 2147 }, 2148 .num_parents = 1, 2149 .flags = CLK_SET_RATE_PARENT, 2150 .ops = &clk_branch2_ops, 2151 }, 2152 }, 2153 }; 2154 2155 static struct clk_branch cam_cc_mclk5_clk = { 2156 .halt_reg = 0x150a4, 2157 .halt_check = BRANCH_HALT, 2158 .clkr = { 2159 .enable_reg = 0x150a4, 2160 .enable_mask = BIT(0), 2161 .hw.init = &(const struct clk_init_data) { 2162 .name = "cam_cc_mclk5_clk", 2163 .parent_hws = (const struct clk_hw*[]) { 2164 &cam_cc_mclk5_clk_src.clkr.hw, 2165 }, 2166 .num_parents = 1, 2167 .flags = CLK_SET_RATE_PARENT, 2168 .ops = &clk_branch2_ops, 2169 }, 2170 }, 2171 }; 2172 2173 static struct clk_branch cam_cc_mclk6_clk = { 2174 .halt_reg = 0x150c0, 2175 .halt_check = BRANCH_HALT, 2176 .clkr = { 2177 .enable_reg = 0x150c0, 2178 .enable_mask = BIT(0), 2179 .hw.init = &(const struct clk_init_data) { 2180 .name = "cam_cc_mclk6_clk", 2181 .parent_hws = (const struct clk_hw*[]) { 2182 &cam_cc_mclk6_clk_src.clkr.hw, 2183 }, 2184 .num_parents = 1, 2185 .flags = CLK_SET_RATE_PARENT, 2186 .ops = &clk_branch2_ops, 2187 }, 2188 }, 2189 }; 2190 2191 static struct clk_branch cam_cc_mclk7_clk = { 2192 .halt_reg = 0x150dc, 2193 .halt_check = BRANCH_HALT, 2194 .clkr = { 2195 .enable_reg = 0x150dc, 2196 .enable_mask = BIT(0), 2197 .hw.init = &(const struct clk_init_data) { 2198 .name = "cam_cc_mclk7_clk", 2199 .parent_hws = (const struct clk_hw*[]) { 2200 &cam_cc_mclk7_clk_src.clkr.hw, 2201 }, 2202 .num_parents = 1, 2203 .flags = CLK_SET_RATE_PARENT, 2204 .ops = &clk_branch2_ops, 2205 }, 2206 }, 2207 }; 2208 2209 static struct clk_branch cam_cc_qdss_debug_clk = { 2210 .halt_reg = 0x13a64, 2211 .halt_check = BRANCH_HALT, 2212 .clkr = { 2213 .enable_reg = 0x13a64, 2214 .enable_mask = BIT(0), 2215 .hw.init = &(const struct clk_init_data) { 2216 .name = "cam_cc_qdss_debug_clk", 2217 .parent_hws = (const struct clk_hw*[]) { 2218 &cam_cc_qdss_debug_clk_src.clkr.hw, 2219 }, 2220 .num_parents = 1, 2221 .flags = CLK_SET_RATE_PARENT, 2222 .ops = &clk_branch2_ops, 2223 }, 2224 }, 2225 }; 2226 2227 static struct clk_branch cam_cc_qdss_debug_xo_clk = { 2228 .halt_reg = 0x13a68, 2229 .halt_check = BRANCH_HALT, 2230 .clkr = { 2231 .enable_reg = 0x13a68, 2232 .enable_mask = BIT(0), 2233 .hw.init = &(const struct clk_init_data) { 2234 .name = "cam_cc_qdss_debug_xo_clk", 2235 .parent_hws = (const struct clk_hw*[]) { 2236 &cam_cc_xo_clk_src.clkr.hw, 2237 }, 2238 .num_parents = 1, 2239 .flags = CLK_SET_RATE_PARENT, 2240 .ops = &clk_branch2_ops, 2241 }, 2242 }, 2243 }; 2244 2245 static struct clk_branch cam_cc_sfe_0_clk = { 2246 .halt_reg = 0x133c0, 2247 .halt_check = BRANCH_HALT, 2248 .clkr = { 2249 .enable_reg = 0x133c0, 2250 .enable_mask = BIT(0), 2251 .hw.init = &(const struct clk_init_data) { 2252 .name = "cam_cc_sfe_0_clk", 2253 .parent_hws = (const struct clk_hw*[]) { 2254 &cam_cc_sfe_0_clk_src.clkr.hw, 2255 }, 2256 .num_parents = 1, 2257 .flags = CLK_SET_RATE_PARENT, 2258 .ops = &clk_branch2_ops, 2259 }, 2260 }, 2261 }; 2262 2263 static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = { 2264 .halt_reg = 0x133d8, 2265 .halt_check = BRANCH_HALT, 2266 .clkr = { 2267 .enable_reg = 0x133d8, 2268 .enable_mask = BIT(0), 2269 .hw.init = &(const struct clk_init_data) { 2270 .name = "cam_cc_sfe_0_fast_ahb_clk", 2271 .parent_hws = (const struct clk_hw*[]) { 2272 &cam_cc_fast_ahb_clk_src.clkr.hw, 2273 }, 2274 .num_parents = 1, 2275 .flags = CLK_SET_RATE_PARENT, 2276 .ops = &clk_branch2_ops, 2277 }, 2278 }, 2279 }; 2280 2281 static struct gdsc cam_cc_titan_top_gdsc; 2282 2283 static struct gdsc cam_cc_bps_gdsc = { 2284 .gdscr = 0x10004, 2285 .en_rest_wait_val = 0x2, 2286 .en_few_wait_val = 0x2, 2287 .clk_dis_wait_val = 0xf, 2288 .pd = { 2289 .name = "cam_cc_bps_gdsc", 2290 }, 2291 .pwrsts = PWRSTS_OFF_ON, 2292 .parent = &cam_cc_titan_top_gdsc.pd, 2293 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2294 }; 2295 2296 static struct gdsc cam_cc_ife_0_gdsc = { 2297 .gdscr = 0x11004, 2298 .en_rest_wait_val = 0x2, 2299 .en_few_wait_val = 0x2, 2300 .clk_dis_wait_val = 0xf, 2301 .pd = { 2302 .name = "cam_cc_ife_0_gdsc", 2303 }, 2304 .pwrsts = PWRSTS_OFF_ON, 2305 .parent = &cam_cc_titan_top_gdsc.pd, 2306 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2307 }; 2308 2309 static struct gdsc cam_cc_ife_1_gdsc = { 2310 .gdscr = 0x12004, 2311 .en_rest_wait_val = 0x2, 2312 .en_few_wait_val = 0x2, 2313 .clk_dis_wait_val = 0xf, 2314 .pd = { 2315 .name = "cam_cc_ife_1_gdsc", 2316 }, 2317 .pwrsts = PWRSTS_OFF_ON, 2318 .parent = &cam_cc_titan_top_gdsc.pd, 2319 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2320 }; 2321 2322 static struct gdsc cam_cc_ipe_0_gdsc = { 2323 .gdscr = 0x103b8, 2324 .en_rest_wait_val = 0x2, 2325 .en_few_wait_val = 0x2, 2326 .clk_dis_wait_val = 0xf, 2327 .pd = { 2328 .name = "cam_cc_ipe_0_gdsc", 2329 }, 2330 .pwrsts = PWRSTS_OFF_ON, 2331 .parent = &cam_cc_titan_top_gdsc.pd, 2332 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2333 }; 2334 2335 static struct gdsc cam_cc_sfe_0_gdsc = { 2336 .gdscr = 0x13280, 2337 .en_rest_wait_val = 0x2, 2338 .en_few_wait_val = 0x2, 2339 .clk_dis_wait_val = 0xf, 2340 .pd = { 2341 .name = "cam_cc_sfe_0_gdsc", 2342 }, 2343 .pwrsts = PWRSTS_OFF_ON, 2344 .parent = &cam_cc_titan_top_gdsc.pd, 2345 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2346 }; 2347 2348 static struct gdsc cam_cc_titan_top_gdsc = { 2349 .gdscr = 0x13a6c, 2350 .en_rest_wait_val = 0x2, 2351 .en_few_wait_val = 0x2, 2352 .clk_dis_wait_val = 0xf, 2353 .pd = { 2354 .name = "cam_cc_titan_top_gdsc", 2355 }, 2356 .pwrsts = PWRSTS_OFF_ON, 2357 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2358 }; 2359 2360 static struct clk_regmap *cam_cc_x1e80100_clocks[] = { 2361 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, 2362 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, 2363 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, 2364 [CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr, 2365 [CAM_CC_CAMNOC_AXI_NRT_CLK] = &cam_cc_camnoc_axi_nrt_clk.clkr, 2366 [CAM_CC_CAMNOC_AXI_RT_CLK] = &cam_cc_camnoc_axi_rt_clk.clkr, 2367 [CAM_CC_CAMNOC_AXI_RT_CLK_SRC] = &cam_cc_camnoc_axi_rt_clk_src.clkr, 2368 [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, 2369 [CAM_CC_CAMNOC_XO_CLK] = &cam_cc_camnoc_xo_clk.clkr, 2370 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, 2371 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, 2372 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, 2373 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, 2374 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 2375 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 2376 [CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr, 2377 [CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr, 2378 [CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr, 2379 [CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr, 2380 [CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr, 2381 [CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr, 2382 [CAM_CC_CPAS_SFE_0_CLK] = &cam_cc_cpas_sfe_0_clk.clkr, 2383 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 2384 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 2385 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 2386 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 2387 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 2388 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 2389 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 2390 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 2391 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 2392 [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr, 2393 [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr, 2394 [CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr, 2395 [CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr, 2396 [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr, 2397 [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr, 2398 [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr, 2399 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 2400 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 2401 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 2402 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 2403 [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, 2404 [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr, 2405 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 2406 [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr, 2407 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 2408 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 2409 [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, 2410 [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, 2411 [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, 2412 [CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr, 2413 [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, 2414 [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, 2415 [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, 2416 [CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr, 2417 [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr, 2418 [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, 2419 [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, 2420 [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, 2421 [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, 2422 [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, 2423 [CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr, 2424 [CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr, 2425 [CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr, 2426 [CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr, 2427 [CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr, 2428 [CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr, 2429 [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, 2430 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, 2431 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 2432 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 2433 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 2434 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 2435 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 2436 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 2437 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 2438 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 2439 [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, 2440 [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, 2441 [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr, 2442 [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr, 2443 [CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr, 2444 [CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr, 2445 [CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr, 2446 [CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr, 2447 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 2448 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, 2449 [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, 2450 [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 2451 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, 2452 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 2453 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 2454 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, 2455 [CAM_CC_PLL4] = &cam_cc_pll4.clkr, 2456 [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, 2457 [CAM_CC_PLL6] = &cam_cc_pll6.clkr, 2458 [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, 2459 [CAM_CC_PLL8] = &cam_cc_pll8.clkr, 2460 [CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr, 2461 [CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr, 2462 [CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr, 2463 [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr, 2464 [CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr, 2465 [CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr, 2466 [CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr, 2467 [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, 2468 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 2469 [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, 2470 }; 2471 2472 static struct gdsc *cam_cc_x1e80100_gdscs[] = { 2473 [CAM_CC_BPS_GDSC] = &cam_cc_bps_gdsc, 2474 [CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc, 2475 [CAM_CC_IFE_1_GDSC] = &cam_cc_ife_1_gdsc, 2476 [CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc, 2477 [CAM_CC_SFE_0_GDSC] = &cam_cc_sfe_0_gdsc, 2478 [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc, 2479 }; 2480 2481 static const struct qcom_reset_map cam_cc_x1e80100_resets[] = { 2482 [CAM_CC_BPS_BCR] = { 0x10000 }, 2483 [CAM_CC_ICP_BCR] = { 0x1351c }, 2484 [CAM_CC_IFE_0_BCR] = { 0x11000 }, 2485 [CAM_CC_IFE_1_BCR] = { 0x12000 }, 2486 [CAM_CC_IPE_0_BCR] = { 0x103b4 }, 2487 [CAM_CC_SFE_0_BCR] = { 0x1327c }, 2488 }; 2489 2490 static struct clk_alpha_pll *cam_cc_x1e80100_plls[] = { 2491 &cam_cc_pll0, 2492 &cam_cc_pll1, 2493 &cam_cc_pll2, 2494 &cam_cc_pll3, 2495 &cam_cc_pll4, 2496 &cam_cc_pll6, 2497 &cam_cc_pll8, 2498 }; 2499 2500 static const u32 cam_cc_x1e80100_critical_cbcrs[] = { 2501 0x13a9c, /* CAM_CC_GDSC_CLK */ 2502 0x13ab8, /* CAM_CC_SLEEP_CLK */ 2503 }; 2504 2505 static const struct regmap_config cam_cc_x1e80100_regmap_config = { 2506 .reg_bits = 32, 2507 .reg_stride = 4, 2508 .val_bits = 32, 2509 .max_register = 0x1603c, 2510 .fast_io = true, 2511 }; 2512 2513 static const struct qcom_cc_driver_data cam_cc_x1e80100_driver_data = { 2514 .alpha_plls = cam_cc_x1e80100_plls, 2515 .num_alpha_plls = ARRAY_SIZE(cam_cc_x1e80100_plls), 2516 .clk_cbcrs = cam_cc_x1e80100_critical_cbcrs, 2517 .num_clk_cbcrs = ARRAY_SIZE(cam_cc_x1e80100_critical_cbcrs), 2518 }; 2519 2520 static const struct qcom_cc_desc cam_cc_x1e80100_desc = { 2521 .config = &cam_cc_x1e80100_regmap_config, 2522 .clks = cam_cc_x1e80100_clocks, 2523 .num_clks = ARRAY_SIZE(cam_cc_x1e80100_clocks), 2524 .resets = cam_cc_x1e80100_resets, 2525 .num_resets = ARRAY_SIZE(cam_cc_x1e80100_resets), 2526 .gdscs = cam_cc_x1e80100_gdscs, 2527 .num_gdscs = ARRAY_SIZE(cam_cc_x1e80100_gdscs), 2528 .use_rpm = true, 2529 .driver_data = &cam_cc_x1e80100_driver_data, 2530 }; 2531 2532 static const struct of_device_id cam_cc_x1e80100_match_table[] = { 2533 { .compatible = "qcom,x1e80100-camcc" }, 2534 { } 2535 }; 2536 MODULE_DEVICE_TABLE(of, cam_cc_x1e80100_match_table); 2537 2538 static int cam_cc_x1e80100_probe(struct platform_device *pdev) 2539 { 2540 return qcom_cc_probe(pdev, &cam_cc_x1e80100_desc); 2541 } 2542 2543 static struct platform_driver cam_cc_x1e80100_driver = { 2544 .probe = cam_cc_x1e80100_probe, 2545 .driver = { 2546 .name = "camcc-x1e80100", 2547 .of_match_table = cam_cc_x1e80100_match_table, 2548 }, 2549 }; 2550 2551 module_platform_driver(cam_cc_x1e80100_driver); 2552 2553 MODULE_DESCRIPTION("QTI Camera Clock Controller X1E80100 Driver"); 2554 MODULE_LICENSE("GPL"); 2555