1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,camcc-sm8250.h> 12 13 #include "clk-alpha-pll.h" 14 #include "clk-branch.h" 15 #include "clk-rcg.h" 16 #include "clk-regmap-divider.h" 17 #include "common.h" 18 #include "gdsc.h" 19 #include "reset.h" 20 21 enum { 22 P_BI_TCXO, 23 P_CAM_CC_PLL0_OUT_EVEN, 24 P_CAM_CC_PLL0_OUT_MAIN, 25 P_CAM_CC_PLL0_OUT_ODD, 26 P_CAM_CC_PLL1_OUT_EVEN, 27 P_CAM_CC_PLL2_OUT_EARLY, 28 P_CAM_CC_PLL2_OUT_MAIN, 29 P_CAM_CC_PLL3_OUT_EVEN, 30 P_CAM_CC_PLL4_OUT_EVEN, 31 P_SLEEP_CLK, 32 }; 33 34 static const struct pll_vco lucid_vco[] = { 35 { 249600000, 2000000000, 0 }, 36 }; 37 38 static const struct pll_vco zonda_vco[] = { 39 { 595200000UL, 3600000000UL, 0 }, 40 }; 41 42 static const struct alpha_pll_config cam_cc_pll0_config = { 43 .l = 0x3e, 44 .alpha = 0x8000, 45 .config_ctl_val = 0x20485699, 46 .config_ctl_hi_val = 0x00002261, 47 .config_ctl_hi1_val = 0x329A699c, 48 .user_ctl_val = 0x00003100, 49 .user_ctl_hi_val = 0x00000805, 50 .user_ctl_hi1_val = 0x00000000, 51 }; 52 53 static struct clk_alpha_pll cam_cc_pll0 = { 54 .offset = 0x0, 55 .vco_table = lucid_vco, 56 .num_vco = ARRAY_SIZE(lucid_vco), 57 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 58 .clkr = { 59 .hw.init = &(struct clk_init_data){ 60 .name = "cam_cc_pll0", 61 .parent_data = &(const struct clk_parent_data){ 62 .fw_name = "bi_tcxo", 63 }, 64 .num_parents = 1, 65 .ops = &clk_alpha_pll_lucid_ops, 66 }, 67 }, 68 }; 69 70 static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { 71 { 0x1, 2 }, 72 { } 73 }; 74 75 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { 76 .offset = 0x0, 77 .post_div_shift = 8, 78 .post_div_table = post_div_table_cam_cc_pll0_out_even, 79 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), 80 .width = 4, 81 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 82 .clkr.hw.init = &(struct clk_init_data){ 83 .name = "cam_cc_pll0_out_even", 84 .parent_hws = (const struct clk_hw*[]){ 85 &cam_cc_pll0.clkr.hw, 86 }, 87 .num_parents = 1, 88 .flags = CLK_SET_RATE_PARENT, 89 .ops = &clk_alpha_pll_postdiv_lucid_ops, 90 }, 91 }; 92 93 static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { 94 { 0x3, 3 }, 95 { } 96 }; 97 98 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { 99 .offset = 0x0, 100 .post_div_shift = 12, 101 .post_div_table = post_div_table_cam_cc_pll0_out_odd, 102 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), 103 .width = 4, 104 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 105 .clkr.hw.init = &(struct clk_init_data){ 106 .name = "cam_cc_pll0_out_odd", 107 .parent_hws = (const struct clk_hw*[]){ 108 &cam_cc_pll0.clkr.hw, 109 }, 110 .num_parents = 1, 111 .flags = CLK_SET_RATE_PARENT, 112 .ops = &clk_alpha_pll_postdiv_lucid_ops, 113 }, 114 }; 115 116 static const struct alpha_pll_config cam_cc_pll1_config = { 117 .l = 0x1f, 118 .alpha = 0x4000, 119 .config_ctl_val = 0x20485699, 120 .config_ctl_hi_val = 0x00002261, 121 .config_ctl_hi1_val = 0x329A699c, 122 .user_ctl_val = 0x00000100, 123 .user_ctl_hi_val = 0x00000805, 124 .user_ctl_hi1_val = 0x00000000, 125 }; 126 127 static struct clk_alpha_pll cam_cc_pll1 = { 128 .offset = 0x1000, 129 .vco_table = lucid_vco, 130 .num_vco = ARRAY_SIZE(lucid_vco), 131 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 132 .clkr = { 133 .hw.init = &(struct clk_init_data){ 134 .name = "cam_cc_pll1", 135 .parent_data = &(const struct clk_parent_data){ 136 .fw_name = "bi_tcxo", 137 }, 138 .num_parents = 1, 139 .ops = &clk_alpha_pll_lucid_ops, 140 }, 141 }, 142 }; 143 144 static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { 145 { 0x1, 2 }, 146 { } 147 }; 148 149 static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { 150 .offset = 0x1000, 151 .post_div_shift = 8, 152 .post_div_table = post_div_table_cam_cc_pll1_out_even, 153 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), 154 .width = 4, 155 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 156 .clkr.hw.init = &(struct clk_init_data){ 157 .name = "cam_cc_pll1_out_even", 158 .parent_hws = (const struct clk_hw*[]){ 159 &cam_cc_pll1.clkr.hw, 160 }, 161 .num_parents = 1, 162 .flags = CLK_SET_RATE_PARENT, 163 .ops = &clk_alpha_pll_postdiv_lucid_ops, 164 }, 165 }; 166 167 static const struct alpha_pll_config cam_cc_pll2_config = { 168 .l = 0x4b, 169 .alpha = 0x0, 170 .config_ctl_val = 0x08200920, 171 .config_ctl_hi_val = 0x05002015, 172 .config_ctl_hi1_val = 0x00000000, 173 .user_ctl_val = 0x00000100, 174 .user_ctl_hi_val = 0x00000000, 175 .user_ctl_hi1_val = 0x00000000, 176 }; 177 178 static struct clk_alpha_pll cam_cc_pll2 = { 179 .offset = 0x2000, 180 .vco_table = zonda_vco, 181 .num_vco = ARRAY_SIZE(zonda_vco), 182 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], 183 .clkr = { 184 .hw.init = &(struct clk_init_data){ 185 .name = "cam_cc_pll2", 186 .parent_data = &(const struct clk_parent_data){ 187 .fw_name = "bi_tcxo", 188 }, 189 .num_parents = 1, 190 .ops = &clk_alpha_pll_zonda_ops, 191 }, 192 }, 193 }; 194 195 static const struct clk_div_table post_div_table_cam_cc_pll2_out_main[] = { 196 { 0x1, 2 }, 197 { } 198 }; 199 200 static struct clk_alpha_pll_postdiv cam_cc_pll2_out_main = { 201 .offset = 0x2000, 202 .post_div_shift = 8, 203 .post_div_table = post_div_table_cam_cc_pll2_out_main, 204 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_main), 205 .width = 2, 206 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], 207 .clkr.hw.init = &(struct clk_init_data){ 208 .name = "cam_cc_pll2_out_main", 209 .parent_hws = (const struct clk_hw*[]){ 210 &cam_cc_pll2.clkr.hw, 211 }, 212 .num_parents = 1, 213 .flags = CLK_SET_RATE_PARENT, 214 .ops = &clk_alpha_pll_postdiv_zonda_ops, 215 }, 216 }; 217 218 static const struct alpha_pll_config cam_cc_pll3_config = { 219 .l = 0x24, 220 .alpha = 0x7555, 221 .config_ctl_val = 0x20485699, 222 .config_ctl_hi_val = 0x00002261, 223 .config_ctl_hi1_val = 0x329A699c, 224 .user_ctl_val = 0x00000100, 225 .user_ctl_hi_val = 0x00000805, 226 .user_ctl_hi1_val = 0x00000000, 227 }; 228 229 static struct clk_alpha_pll cam_cc_pll3 = { 230 .offset = 0x3000, 231 .vco_table = lucid_vco, 232 .num_vco = ARRAY_SIZE(lucid_vco), 233 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 234 .clkr = { 235 .hw.init = &(struct clk_init_data){ 236 .name = "cam_cc_pll3", 237 .parent_data = &(const struct clk_parent_data){ 238 .fw_name = "bi_tcxo", 239 }, 240 .num_parents = 1, 241 .ops = &clk_alpha_pll_lucid_ops, 242 }, 243 }, 244 }; 245 246 static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { 247 { 0x1, 2 }, 248 { } 249 }; 250 251 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 252 .offset = 0x3000, 253 .post_div_shift = 8, 254 .post_div_table = post_div_table_cam_cc_pll3_out_even, 255 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), 256 .width = 4, 257 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 258 .clkr.hw.init = &(struct clk_init_data){ 259 .name = "cam_cc_pll3_out_even", 260 .parent_hws = (const struct clk_hw*[]){ 261 &cam_cc_pll3.clkr.hw, 262 }, 263 .num_parents = 1, 264 .flags = CLK_SET_RATE_PARENT, 265 .ops = &clk_alpha_pll_postdiv_lucid_ops, 266 }, 267 }; 268 269 static const struct alpha_pll_config cam_cc_pll4_config = { 270 .l = 0x24, 271 .alpha = 0x7555, 272 .config_ctl_val = 0x20485699, 273 .config_ctl_hi_val = 0x00002261, 274 .config_ctl_hi1_val = 0x329A699c, 275 .user_ctl_val = 0x00000100, 276 .user_ctl_hi_val = 0x00000805, 277 .user_ctl_hi1_val = 0x00000000, 278 }; 279 280 static struct clk_alpha_pll cam_cc_pll4 = { 281 .offset = 0x4000, 282 .vco_table = lucid_vco, 283 .num_vco = ARRAY_SIZE(lucid_vco), 284 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 285 .clkr = { 286 .hw.init = &(struct clk_init_data){ 287 .name = "cam_cc_pll4", 288 .parent_data = &(const struct clk_parent_data){ 289 .fw_name = "bi_tcxo", 290 }, 291 .num_parents = 1, 292 .ops = &clk_alpha_pll_lucid_ops, 293 }, 294 }, 295 }; 296 297 static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { 298 { 0x1, 2 }, 299 { } 300 }; 301 302 static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { 303 .offset = 0x4000, 304 .post_div_shift = 8, 305 .post_div_table = post_div_table_cam_cc_pll4_out_even, 306 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), 307 .width = 4, 308 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 309 .clkr.hw.init = &(struct clk_init_data){ 310 .name = "cam_cc_pll4_out_even", 311 .parent_hws = (const struct clk_hw*[]){ 312 &cam_cc_pll4.clkr.hw, 313 }, 314 .num_parents = 1, 315 .flags = CLK_SET_RATE_PARENT, 316 .ops = &clk_alpha_pll_postdiv_lucid_ops, 317 }, 318 }; 319 320 static const struct parent_map cam_cc_parent_map_0[] = { 321 { P_BI_TCXO, 0 }, 322 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 323 { P_CAM_CC_PLL0_OUT_EVEN, 2 }, 324 { P_CAM_CC_PLL0_OUT_ODD, 3 }, 325 { P_CAM_CC_PLL2_OUT_MAIN, 5 }, 326 }; 327 328 static const struct clk_parent_data cam_cc_parent_data_0[] = { 329 { .fw_name = "bi_tcxo" }, 330 { .hw = &cam_cc_pll0.clkr.hw }, 331 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 332 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 333 { .hw = &cam_cc_pll2_out_main.clkr.hw }, 334 }; 335 336 static const struct parent_map cam_cc_parent_map_1[] = { 337 { P_BI_TCXO, 0 }, 338 { P_CAM_CC_PLL2_OUT_EARLY, 5 }, 339 }; 340 341 static const struct clk_parent_data cam_cc_parent_data_1[] = { 342 { .fw_name = "bi_tcxo" }, 343 { .hw = &cam_cc_pll2.clkr.hw }, 344 }; 345 346 static const struct parent_map cam_cc_parent_map_2[] = { 347 { P_BI_TCXO, 0 }, 348 { P_CAM_CC_PLL3_OUT_EVEN, 6 }, 349 }; 350 351 static const struct clk_parent_data cam_cc_parent_data_2[] = { 352 { .fw_name = "bi_tcxo" }, 353 { .hw = &cam_cc_pll3_out_even.clkr.hw }, 354 }; 355 356 static const struct parent_map cam_cc_parent_map_3[] = { 357 { P_BI_TCXO, 0 }, 358 { P_CAM_CC_PLL4_OUT_EVEN, 6 }, 359 }; 360 361 static const struct clk_parent_data cam_cc_parent_data_3[] = { 362 { .fw_name = "bi_tcxo" }, 363 { .hw = &cam_cc_pll4_out_even.clkr.hw }, 364 }; 365 366 static const struct parent_map cam_cc_parent_map_4[] = { 367 { P_BI_TCXO, 0 }, 368 { P_CAM_CC_PLL1_OUT_EVEN, 4 }, 369 }; 370 371 static const struct clk_parent_data cam_cc_parent_data_4[] = { 372 { .fw_name = "bi_tcxo" }, 373 { .hw = &cam_cc_pll1_out_even.clkr.hw }, 374 }; 375 376 static const struct parent_map cam_cc_parent_map_5[] = { 377 { P_SLEEP_CLK, 0 }, 378 }; 379 380 static const struct clk_parent_data cam_cc_parent_data_5[] = { 381 { .fw_name = "sleep_clk" }, 382 }; 383 384 static const struct parent_map cam_cc_parent_map_6[] = { 385 { P_BI_TCXO, 0 }, 386 }; 387 388 static const struct clk_parent_data cam_cc_parent_data_6[] = { 389 { .fw_name = "bi_tcxo" }, 390 }; 391 392 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { 393 F(19200000, P_BI_TCXO, 1, 0, 0), 394 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 395 F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), 396 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 397 F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0), 398 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 399 { } 400 }; 401 402 static struct clk_rcg2 cam_cc_bps_clk_src = { 403 .cmd_rcgr = 0x7010, 404 .mnd_width = 0, 405 .hid_width = 5, 406 .parent_map = cam_cc_parent_map_0, 407 .freq_tbl = ftbl_cam_cc_bps_clk_src, 408 .clkr.hw.init = &(struct clk_init_data){ 409 .name = "cam_cc_bps_clk_src", 410 .parent_data = cam_cc_parent_data_0, 411 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 412 .flags = CLK_SET_RATE_PARENT, 413 .ops = &clk_rcg2_shared_ops, 414 }, 415 }; 416 417 static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = { 418 F(19200000, P_BI_TCXO, 1, 0, 0), 419 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 420 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 421 { } 422 }; 423 424 static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = { 425 .cmd_rcgr = 0xc0f8, 426 .mnd_width = 0, 427 .hid_width = 5, 428 .parent_map = cam_cc_parent_map_0, 429 .freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src, 430 .clkr.hw.init = &(struct clk_init_data){ 431 .name = "cam_cc_camnoc_axi_clk_src", 432 .parent_data = cam_cc_parent_data_0, 433 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 434 .flags = CLK_SET_RATE_PARENT, 435 .ops = &clk_rcg2_shared_ops, 436 }, 437 }; 438 439 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { 440 F(19200000, P_BI_TCXO, 1, 0, 0), 441 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 442 { } 443 }; 444 445 static struct clk_rcg2 cam_cc_cci_0_clk_src = { 446 .cmd_rcgr = 0xc0bc, 447 .mnd_width = 8, 448 .hid_width = 5, 449 .parent_map = cam_cc_parent_map_0, 450 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 451 .clkr.hw.init = &(struct clk_init_data){ 452 .name = "cam_cc_cci_0_clk_src", 453 .parent_data = cam_cc_parent_data_0, 454 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 455 .flags = CLK_SET_RATE_PARENT, 456 .ops = &clk_rcg2_shared_ops, 457 }, 458 }; 459 460 static struct clk_rcg2 cam_cc_cci_1_clk_src = { 461 .cmd_rcgr = 0xc0d8, 462 .mnd_width = 8, 463 .hid_width = 5, 464 .parent_map = cam_cc_parent_map_0, 465 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 466 .clkr.hw.init = &(struct clk_init_data){ 467 .name = "cam_cc_cci_1_clk_src", 468 .parent_data = cam_cc_parent_data_0, 469 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 470 .flags = CLK_SET_RATE_PARENT, 471 .ops = &clk_rcg2_shared_ops, 472 }, 473 }; 474 475 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 476 F(19200000, P_BI_TCXO, 1, 0, 0), 477 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 478 { } 479 }; 480 481 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 482 .cmd_rcgr = 0xa068, 483 .mnd_width = 0, 484 .hid_width = 5, 485 .parent_map = cam_cc_parent_map_0, 486 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 487 .clkr.hw.init = &(struct clk_init_data){ 488 .name = "cam_cc_cphy_rx_clk_src", 489 .parent_data = cam_cc_parent_data_0, 490 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 491 .flags = CLK_SET_RATE_PARENT, 492 .ops = &clk_rcg2_shared_ops, 493 }, 494 }; 495 496 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 497 F(19200000, P_BI_TCXO, 1, 0, 0), 498 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 499 { } 500 }; 501 502 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 503 .cmd_rcgr = 0x6000, 504 .mnd_width = 0, 505 .hid_width = 5, 506 .parent_map = cam_cc_parent_map_0, 507 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 508 .clkr.hw.init = &(struct clk_init_data){ 509 .name = "cam_cc_csi0phytimer_clk_src", 510 .parent_data = cam_cc_parent_data_0, 511 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 512 .flags = CLK_SET_RATE_PARENT, 513 .ops = &clk_rcg2_shared_ops, 514 }, 515 }; 516 517 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 518 .cmd_rcgr = 0x6020, 519 .mnd_width = 0, 520 .hid_width = 5, 521 .parent_map = cam_cc_parent_map_0, 522 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 523 .clkr.hw.init = &(struct clk_init_data){ 524 .name = "cam_cc_csi1phytimer_clk_src", 525 .parent_data = cam_cc_parent_data_0, 526 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 527 .flags = CLK_SET_RATE_PARENT, 528 .ops = &clk_rcg2_shared_ops, 529 }, 530 }; 531 532 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 533 .cmd_rcgr = 0x6040, 534 .mnd_width = 0, 535 .hid_width = 5, 536 .parent_map = cam_cc_parent_map_0, 537 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 538 .clkr.hw.init = &(struct clk_init_data){ 539 .name = "cam_cc_csi2phytimer_clk_src", 540 .parent_data = cam_cc_parent_data_0, 541 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 542 .flags = CLK_SET_RATE_PARENT, 543 .ops = &clk_rcg2_ops, 544 }, 545 }; 546 547 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 548 .cmd_rcgr = 0x6060, 549 .mnd_width = 0, 550 .hid_width = 5, 551 .parent_map = cam_cc_parent_map_0, 552 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 553 .clkr.hw.init = &(struct clk_init_data){ 554 .name = "cam_cc_csi3phytimer_clk_src", 555 .parent_data = cam_cc_parent_data_0, 556 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 557 .flags = CLK_SET_RATE_PARENT, 558 .ops = &clk_rcg2_shared_ops, 559 }, 560 }; 561 562 static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { 563 .cmd_rcgr = 0x6080, 564 .mnd_width = 0, 565 .hid_width = 5, 566 .parent_map = cam_cc_parent_map_0, 567 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 568 .clkr.hw.init = &(struct clk_init_data){ 569 .name = "cam_cc_csi4phytimer_clk_src", 570 .parent_data = cam_cc_parent_data_0, 571 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 572 .flags = CLK_SET_RATE_PARENT, 573 .ops = &clk_rcg2_shared_ops, 574 }, 575 }; 576 577 static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = { 578 .cmd_rcgr = 0x60a0, 579 .mnd_width = 0, 580 .hid_width = 5, 581 .parent_map = cam_cc_parent_map_0, 582 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 583 .clkr.hw.init = &(struct clk_init_data){ 584 .name = "cam_cc_csi5phytimer_clk_src", 585 .parent_data = cam_cc_parent_data_0, 586 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 587 .flags = CLK_SET_RATE_PARENT, 588 .ops = &clk_rcg2_shared_ops, 589 }, 590 }; 591 592 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 593 F(19200000, P_BI_TCXO, 1, 0, 0), 594 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0), 595 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 596 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 597 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), 598 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 599 { } 600 }; 601 602 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 603 .cmd_rcgr = 0x703c, 604 .mnd_width = 0, 605 .hid_width = 5, 606 .parent_map = cam_cc_parent_map_0, 607 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 608 .clkr.hw.init = &(struct clk_init_data){ 609 .name = "cam_cc_fast_ahb_clk_src", 610 .parent_data = cam_cc_parent_data_0, 611 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 612 .flags = CLK_SET_RATE_PARENT, 613 .ops = &clk_rcg2_shared_ops, 614 }, 615 }; 616 617 static const struct freq_tbl ftbl_cam_cc_fd_core_clk_src[] = { 618 F(19200000, P_BI_TCXO, 1, 0, 0), 619 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 620 F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0), 621 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 622 { } 623 }; 624 625 static struct clk_rcg2 cam_cc_fd_core_clk_src = { 626 .cmd_rcgr = 0xc098, 627 .mnd_width = 0, 628 .hid_width = 5, 629 .parent_map = cam_cc_parent_map_0, 630 .freq_tbl = ftbl_cam_cc_fd_core_clk_src, 631 .clkr.hw.init = &(struct clk_init_data){ 632 .name = "cam_cc_fd_core_clk_src", 633 .parent_data = cam_cc_parent_data_0, 634 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 635 .flags = CLK_SET_RATE_PARENT, 636 .ops = &clk_rcg2_shared_ops, 637 }, 638 }; 639 640 static struct clk_rcg2 cam_cc_icp_clk_src = { 641 .cmd_rcgr = 0xc074, 642 .mnd_width = 0, 643 .hid_width = 5, 644 .parent_map = cam_cc_parent_map_0, 645 .freq_tbl = ftbl_cam_cc_fd_core_clk_src, 646 .clkr.hw.init = &(struct clk_init_data){ 647 .name = "cam_cc_icp_clk_src", 648 .parent_data = cam_cc_parent_data_0, 649 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 650 .flags = CLK_SET_RATE_PARENT, 651 .ops = &clk_rcg2_shared_ops, 652 }, 653 }; 654 655 static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { 656 F(19200000, P_BI_TCXO, 1, 0, 0), 657 F(350000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 658 F(475000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 659 F(576000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 660 F(680000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 661 { } 662 }; 663 664 static struct clk_rcg2 cam_cc_ife_0_clk_src = { 665 .cmd_rcgr = 0xa010, 666 .mnd_width = 0, 667 .hid_width = 5, 668 .parent_map = cam_cc_parent_map_2, 669 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 670 .clkr.hw.init = &(struct clk_init_data){ 671 .name = "cam_cc_ife_0_clk_src", 672 .parent_data = cam_cc_parent_data_2, 673 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 674 .flags = CLK_SET_RATE_PARENT, 675 .ops = &clk_rcg2_shared_ops, 676 }, 677 }; 678 679 static struct clk_regmap_div cam_cc_sbi_div_clk_src = { 680 .reg = 0x9010, 681 .shift = 0, 682 .width = 3, 683 .clkr.hw.init = &(struct clk_init_data) { 684 .name = "cam_cc_sbi_div_clk_src", 685 .parent_hws = (const struct clk_hw*[]){ 686 &cam_cc_ife_0_clk_src.clkr.hw, 687 }, 688 .num_parents = 1, 689 .flags = CLK_SET_RATE_PARENT, 690 .ops = &clk_regmap_div_ro_ops, 691 }, 692 }; 693 694 static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = { 695 F(19200000, P_BI_TCXO, 1, 0, 0), 696 F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0), 697 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 698 { } 699 }; 700 701 static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { 702 .cmd_rcgr = 0xa040, 703 .mnd_width = 0, 704 .hid_width = 5, 705 .parent_map = cam_cc_parent_map_0, 706 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 707 .clkr.hw.init = &(struct clk_init_data){ 708 .name = "cam_cc_ife_0_csid_clk_src", 709 .parent_data = cam_cc_parent_data_0, 710 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 711 .flags = CLK_SET_RATE_PARENT, 712 .ops = &clk_rcg2_shared_ops, 713 }, 714 }; 715 716 static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = { 717 F(19200000, P_BI_TCXO, 1, 0, 0), 718 F(350000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 719 F(475000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 720 F(576000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 721 F(680000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 722 { } 723 }; 724 725 static struct clk_rcg2 cam_cc_ife_1_clk_src = { 726 .cmd_rcgr = 0xb010, 727 .mnd_width = 0, 728 .hid_width = 5, 729 .parent_map = cam_cc_parent_map_3, 730 .freq_tbl = ftbl_cam_cc_ife_1_clk_src, 731 .clkr.hw.init = &(struct clk_init_data){ 732 .name = "cam_cc_ife_1_clk_src", 733 .parent_data = cam_cc_parent_data_3, 734 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 735 .flags = CLK_SET_RATE_PARENT, 736 .ops = &clk_rcg2_shared_ops, 737 }, 738 }; 739 740 static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { 741 .cmd_rcgr = 0xb040, 742 .mnd_width = 0, 743 .hid_width = 5, 744 .parent_map = cam_cc_parent_map_0, 745 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 746 .clkr.hw.init = &(struct clk_init_data){ 747 .name = "cam_cc_ife_1_csid_clk_src", 748 .parent_data = cam_cc_parent_data_0, 749 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 750 .flags = CLK_SET_RATE_PARENT, 751 .ops = &clk_rcg2_shared_ops, 752 }, 753 }; 754 755 static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = { 756 F(19200000, P_BI_TCXO, 1, 0, 0), 757 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 758 F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0), 759 { } 760 }; 761 762 static struct clk_rcg2 cam_cc_ife_lite_clk_src = { 763 .cmd_rcgr = 0xc000, 764 .mnd_width = 0, 765 .hid_width = 5, 766 .parent_map = cam_cc_parent_map_0, 767 .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, 768 .clkr.hw.init = &(struct clk_init_data){ 769 .name = "cam_cc_ife_lite_clk_src", 770 .parent_data = cam_cc_parent_data_0, 771 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 772 .flags = CLK_SET_RATE_PARENT, 773 .ops = &clk_rcg2_shared_ops, 774 }, 775 }; 776 777 static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { 778 .cmd_rcgr = 0xc01c, 779 .mnd_width = 0, 780 .hid_width = 5, 781 .parent_map = cam_cc_parent_map_0, 782 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 783 .clkr.hw.init = &(struct clk_init_data){ 784 .name = "cam_cc_ife_lite_csid_clk_src", 785 .parent_data = cam_cc_parent_data_0, 786 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 787 .flags = CLK_SET_RATE_PARENT, 788 .ops = &clk_rcg2_shared_ops, 789 }, 790 }; 791 792 static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = { 793 F(19200000, P_BI_TCXO, 1, 0, 0), 794 F(300000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 795 F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 796 F(525000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 797 F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 798 { } 799 }; 800 801 static struct clk_rcg2 cam_cc_ipe_0_clk_src = { 802 .cmd_rcgr = 0x8010, 803 .mnd_width = 0, 804 .hid_width = 5, 805 .parent_map = cam_cc_parent_map_4, 806 .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, 807 .clkr.hw.init = &(struct clk_init_data){ 808 .name = "cam_cc_ipe_0_clk_src", 809 .parent_data = cam_cc_parent_data_4, 810 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 811 .flags = CLK_SET_RATE_PARENT, 812 .ops = &clk_rcg2_shared_ops, 813 }, 814 }; 815 816 static struct clk_rcg2 cam_cc_jpeg_clk_src = { 817 .cmd_rcgr = 0xc048, 818 .mnd_width = 0, 819 .hid_width = 5, 820 .parent_map = cam_cc_parent_map_0, 821 .freq_tbl = ftbl_cam_cc_bps_clk_src, 822 .clkr.hw.init = &(struct clk_init_data){ 823 .name = "cam_cc_jpeg_clk_src", 824 .parent_data = cam_cc_parent_data_0, 825 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 826 .flags = CLK_SET_RATE_PARENT, 827 .ops = &clk_rcg2_shared_ops, 828 }, 829 }; 830 831 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 832 F(19200000, P_BI_TCXO, 1, 0, 0), 833 F(24000000, P_CAM_CC_PLL2_OUT_EARLY, 10, 1, 6), 834 F(68571429, P_CAM_CC_PLL2_OUT_EARLY, 1, 1, 21), 835 { } 836 }; 837 838 static struct clk_rcg2 cam_cc_mclk0_clk_src = { 839 .cmd_rcgr = 0x5000, 840 .mnd_width = 8, 841 .hid_width = 5, 842 .parent_map = cam_cc_parent_map_1, 843 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 844 .clkr.hw.init = &(struct clk_init_data){ 845 .name = "cam_cc_mclk0_clk_src", 846 .parent_data = cam_cc_parent_data_1, 847 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 848 .flags = CLK_SET_RATE_PARENT, 849 .ops = &clk_rcg2_shared_ops, 850 }, 851 }; 852 853 static struct clk_rcg2 cam_cc_mclk1_clk_src = { 854 .cmd_rcgr = 0x501c, 855 .mnd_width = 8, 856 .hid_width = 5, 857 .parent_map = cam_cc_parent_map_1, 858 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 859 .clkr.hw.init = &(struct clk_init_data){ 860 .name = "cam_cc_mclk1_clk_src", 861 .parent_data = cam_cc_parent_data_1, 862 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 863 .flags = CLK_SET_RATE_PARENT, 864 .ops = &clk_rcg2_shared_ops, 865 }, 866 }; 867 868 static struct clk_rcg2 cam_cc_mclk2_clk_src = { 869 .cmd_rcgr = 0x5038, 870 .mnd_width = 8, 871 .hid_width = 5, 872 .parent_map = cam_cc_parent_map_1, 873 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 874 .clkr.hw.init = &(struct clk_init_data){ 875 .name = "cam_cc_mclk2_clk_src", 876 .parent_data = cam_cc_parent_data_1, 877 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 878 .flags = CLK_SET_RATE_PARENT, 879 .ops = &clk_rcg2_shared_ops, 880 }, 881 }; 882 883 static struct clk_rcg2 cam_cc_mclk3_clk_src = { 884 .cmd_rcgr = 0x5054, 885 .mnd_width = 8, 886 .hid_width = 5, 887 .parent_map = cam_cc_parent_map_1, 888 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 889 .clkr.hw.init = &(struct clk_init_data){ 890 .name = "cam_cc_mclk3_clk_src", 891 .parent_data = cam_cc_parent_data_1, 892 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 893 .flags = CLK_SET_RATE_PARENT, 894 .ops = &clk_rcg2_shared_ops, 895 }, 896 }; 897 898 static struct clk_rcg2 cam_cc_mclk4_clk_src = { 899 .cmd_rcgr = 0x5070, 900 .mnd_width = 8, 901 .hid_width = 5, 902 .parent_map = cam_cc_parent_map_1, 903 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 904 .clkr.hw.init = &(struct clk_init_data){ 905 .name = "cam_cc_mclk4_clk_src", 906 .parent_data = cam_cc_parent_data_1, 907 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 908 .flags = CLK_SET_RATE_PARENT, 909 .ops = &clk_rcg2_shared_ops, 910 }, 911 }; 912 913 static struct clk_rcg2 cam_cc_mclk5_clk_src = { 914 .cmd_rcgr = 0x508c, 915 .mnd_width = 8, 916 .hid_width = 5, 917 .parent_map = cam_cc_parent_map_1, 918 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 919 .clkr.hw.init = &(struct clk_init_data){ 920 .name = "cam_cc_mclk5_clk_src", 921 .parent_data = cam_cc_parent_data_1, 922 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 923 .flags = CLK_SET_RATE_PARENT, 924 .ops = &clk_rcg2_shared_ops, 925 }, 926 }; 927 928 static struct clk_rcg2 cam_cc_mclk6_clk_src = { 929 .cmd_rcgr = 0x50a8, 930 .mnd_width = 8, 931 .hid_width = 5, 932 .parent_map = cam_cc_parent_map_1, 933 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 934 .clkr.hw.init = &(struct clk_init_data){ 935 .name = "cam_cc_mclk6_clk_src", 936 .parent_data = cam_cc_parent_data_1, 937 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 938 .flags = CLK_SET_RATE_PARENT, 939 .ops = &clk_rcg2_ops, 940 }, 941 }; 942 943 static struct clk_rcg2 cam_cc_sbi_csid_clk_src = { 944 .cmd_rcgr = 0x901c, 945 .mnd_width = 0, 946 .hid_width = 5, 947 .parent_map = cam_cc_parent_map_0, 948 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 949 .clkr.hw.init = &(struct clk_init_data){ 950 .name = "cam_cc_sbi_csid_clk_src", 951 .parent_data = cam_cc_parent_data_0, 952 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 953 .flags = CLK_SET_RATE_PARENT, 954 .ops = &clk_rcg2_ops, 955 }, 956 }; 957 958 static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { 959 F(32768, P_SLEEP_CLK, 1, 0, 0), 960 { } 961 }; 962 963 static struct clk_rcg2 cam_cc_sleep_clk_src = { 964 .cmd_rcgr = 0xc170, 965 .mnd_width = 0, 966 .hid_width = 5, 967 .parent_map = cam_cc_parent_map_5, 968 .freq_tbl = ftbl_cam_cc_sleep_clk_src, 969 .clkr.hw.init = &(struct clk_init_data){ 970 .name = "cam_cc_sleep_clk_src", 971 .parent_data = cam_cc_parent_data_5, 972 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 973 .flags = CLK_SET_RATE_PARENT, 974 .ops = &clk_rcg2_ops, 975 }, 976 }; 977 978 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 979 F(19200000, P_BI_TCXO, 1, 0, 0), 980 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 981 { } 982 }; 983 984 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 985 .cmd_rcgr = 0x7058, 986 .mnd_width = 8, 987 .hid_width = 5, 988 .parent_map = cam_cc_parent_map_0, 989 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 990 .clkr.hw.init = &(struct clk_init_data){ 991 .name = "cam_cc_slow_ahb_clk_src", 992 .parent_data = cam_cc_parent_data_0, 993 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 994 .flags = CLK_SET_RATE_PARENT, 995 .ops = &clk_rcg2_shared_ops, 996 }, 997 }; 998 999 static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { 1000 F(19200000, P_BI_TCXO, 1, 0, 0), 1001 { } 1002 }; 1003 1004 static struct clk_rcg2 cam_cc_xo_clk_src = { 1005 .cmd_rcgr = 0xc154, 1006 .mnd_width = 0, 1007 .hid_width = 5, 1008 .parent_map = cam_cc_parent_map_6, 1009 .freq_tbl = ftbl_cam_cc_xo_clk_src, 1010 .clkr.hw.init = &(struct clk_init_data){ 1011 .name = "cam_cc_xo_clk_src", 1012 .parent_data = cam_cc_parent_data_6, 1013 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), 1014 .flags = CLK_SET_RATE_PARENT, 1015 .ops = &clk_rcg2_ops, 1016 }, 1017 }; 1018 1019 static struct clk_branch cam_cc_bps_ahb_clk = { 1020 .halt_reg = 0x7070, 1021 .halt_check = BRANCH_HALT, 1022 .clkr = { 1023 .enable_reg = 0x7070, 1024 .enable_mask = BIT(0), 1025 .hw.init = &(struct clk_init_data){ 1026 .name = "cam_cc_bps_ahb_clk", 1027 .parent_hws = (const struct clk_hw*[]){ 1028 &cam_cc_slow_ahb_clk_src.clkr.hw 1029 }, 1030 .num_parents = 1, 1031 .flags = CLK_SET_RATE_PARENT, 1032 .ops = &clk_branch2_ops, 1033 }, 1034 }, 1035 }; 1036 1037 static struct clk_branch cam_cc_bps_areg_clk = { 1038 .halt_reg = 0x7054, 1039 .halt_check = BRANCH_HALT, 1040 .clkr = { 1041 .enable_reg = 0x7054, 1042 .enable_mask = BIT(0), 1043 .hw.init = &(struct clk_init_data){ 1044 .name = "cam_cc_bps_areg_clk", 1045 .parent_hws = (const struct clk_hw*[]){ 1046 &cam_cc_fast_ahb_clk_src.clkr.hw 1047 }, 1048 .num_parents = 1, 1049 .flags = CLK_SET_RATE_PARENT, 1050 .ops = &clk_branch2_ops, 1051 }, 1052 }, 1053 }; 1054 1055 static struct clk_branch cam_cc_bps_axi_clk = { 1056 .halt_reg = 0x7038, 1057 .halt_check = BRANCH_HALT, 1058 .clkr = { 1059 .enable_reg = 0x7038, 1060 .enable_mask = BIT(0), 1061 .hw.init = &(struct clk_init_data){ 1062 .name = "cam_cc_bps_axi_clk", 1063 .parent_hws = (const struct clk_hw*[]){ 1064 &cam_cc_camnoc_axi_clk_src.clkr.hw 1065 }, 1066 .num_parents = 1, 1067 .flags = CLK_SET_RATE_PARENT, 1068 .ops = &clk_branch2_ops, 1069 }, 1070 }, 1071 }; 1072 1073 static struct clk_branch cam_cc_bps_clk = { 1074 .halt_reg = 0x7028, 1075 .halt_check = BRANCH_HALT, 1076 .clkr = { 1077 .enable_reg = 0x7028, 1078 .enable_mask = BIT(0), 1079 .hw.init = &(struct clk_init_data){ 1080 .name = "cam_cc_bps_clk", 1081 .parent_hws = (const struct clk_hw*[]){ 1082 &cam_cc_bps_clk_src.clkr.hw 1083 }, 1084 .num_parents = 1, 1085 .flags = CLK_SET_RATE_PARENT, 1086 .ops = &clk_branch2_ops, 1087 }, 1088 }, 1089 }; 1090 1091 static struct clk_branch cam_cc_camnoc_axi_clk = { 1092 .halt_reg = 0xc114, 1093 .halt_check = BRANCH_HALT, 1094 .clkr = { 1095 .enable_reg = 0xc114, 1096 .enable_mask = BIT(0), 1097 .hw.init = &(struct clk_init_data){ 1098 .name = "cam_cc_camnoc_axi_clk", 1099 .parent_hws = (const struct clk_hw*[]){ 1100 &cam_cc_camnoc_axi_clk_src.clkr.hw 1101 }, 1102 .num_parents = 1, 1103 .flags = CLK_SET_RATE_PARENT, 1104 .ops = &clk_branch2_ops, 1105 }, 1106 }, 1107 }; 1108 1109 static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { 1110 .halt_reg = 0xc11c, 1111 .halt_check = BRANCH_HALT, 1112 .clkr = { 1113 .enable_reg = 0xc11c, 1114 .enable_mask = BIT(0), 1115 .hw.init = &(struct clk_init_data){ 1116 .name = "cam_cc_camnoc_dcd_xo_clk", 1117 .parent_hws = (const struct clk_hw*[]){ 1118 &cam_cc_xo_clk_src.clkr.hw 1119 }, 1120 .num_parents = 1, 1121 .flags = CLK_SET_RATE_PARENT, 1122 .ops = &clk_branch2_ops, 1123 }, 1124 }, 1125 }; 1126 1127 static struct clk_branch cam_cc_cci_0_clk = { 1128 .halt_reg = 0xc0d4, 1129 .halt_check = BRANCH_HALT, 1130 .clkr = { 1131 .enable_reg = 0xc0d4, 1132 .enable_mask = BIT(0), 1133 .hw.init = &(struct clk_init_data){ 1134 .name = "cam_cc_cci_0_clk", 1135 .parent_hws = (const struct clk_hw*[]){ 1136 &cam_cc_cci_0_clk_src.clkr.hw 1137 }, 1138 .num_parents = 1, 1139 .flags = CLK_SET_RATE_PARENT, 1140 .ops = &clk_branch2_ops, 1141 }, 1142 }, 1143 }; 1144 1145 static struct clk_branch cam_cc_cci_1_clk = { 1146 .halt_reg = 0xc0f0, 1147 .halt_check = BRANCH_HALT, 1148 .clkr = { 1149 .enable_reg = 0xc0f0, 1150 .enable_mask = BIT(0), 1151 .hw.init = &(struct clk_init_data){ 1152 .name = "cam_cc_cci_1_clk", 1153 .parent_hws = (const struct clk_hw*[]){ 1154 &cam_cc_cci_1_clk_src.clkr.hw 1155 }, 1156 .num_parents = 1, 1157 .flags = CLK_SET_RATE_PARENT, 1158 .ops = &clk_branch2_ops, 1159 }, 1160 }, 1161 }; 1162 1163 static struct clk_branch cam_cc_core_ahb_clk = { 1164 .halt_reg = 0xc150, 1165 .halt_check = BRANCH_HALT_DELAY, 1166 .clkr = { 1167 .enable_reg = 0xc150, 1168 .enable_mask = BIT(0), 1169 .hw.init = &(struct clk_init_data){ 1170 .name = "cam_cc_core_ahb_clk", 1171 .parent_hws = (const struct clk_hw*[]){ 1172 &cam_cc_slow_ahb_clk_src.clkr.hw 1173 }, 1174 .num_parents = 1, 1175 .flags = CLK_SET_RATE_PARENT, 1176 .ops = &clk_branch2_ops, 1177 }, 1178 }, 1179 }; 1180 1181 static struct clk_branch cam_cc_cpas_ahb_clk = { 1182 .halt_reg = 0xc0f4, 1183 .halt_check = BRANCH_HALT, 1184 .clkr = { 1185 .enable_reg = 0xc0f4, 1186 .enable_mask = BIT(0), 1187 .hw.init = &(struct clk_init_data){ 1188 .name = "cam_cc_cpas_ahb_clk", 1189 .parent_hws = (const struct clk_hw*[]){ 1190 &cam_cc_slow_ahb_clk_src.clkr.hw 1191 }, 1192 .num_parents = 1, 1193 .flags = CLK_SET_RATE_PARENT, 1194 .ops = &clk_branch2_ops, 1195 }, 1196 }, 1197 }; 1198 1199 static struct clk_branch cam_cc_csi0phytimer_clk = { 1200 .halt_reg = 0x6018, 1201 .halt_check = BRANCH_HALT, 1202 .clkr = { 1203 .enable_reg = 0x6018, 1204 .enable_mask = BIT(0), 1205 .hw.init = &(struct clk_init_data){ 1206 .name = "cam_cc_csi0phytimer_clk", 1207 .parent_hws = (const struct clk_hw*[]){ 1208 &cam_cc_csi0phytimer_clk_src.clkr.hw 1209 }, 1210 .num_parents = 1, 1211 .flags = CLK_SET_RATE_PARENT, 1212 .ops = &clk_branch2_ops, 1213 }, 1214 }, 1215 }; 1216 1217 static struct clk_branch cam_cc_csi1phytimer_clk = { 1218 .halt_reg = 0x6038, 1219 .halt_check = BRANCH_HALT, 1220 .clkr = { 1221 .enable_reg = 0x6038, 1222 .enable_mask = BIT(0), 1223 .hw.init = &(struct clk_init_data){ 1224 .name = "cam_cc_csi1phytimer_clk", 1225 .parent_hws = (const struct clk_hw*[]){ 1226 &cam_cc_csi1phytimer_clk_src.clkr.hw 1227 }, 1228 .num_parents = 1, 1229 .flags = CLK_SET_RATE_PARENT, 1230 .ops = &clk_branch2_ops, 1231 }, 1232 }, 1233 }; 1234 1235 static struct clk_branch cam_cc_csi2phytimer_clk = { 1236 .halt_reg = 0x6058, 1237 .halt_check = BRANCH_HALT, 1238 .clkr = { 1239 .enable_reg = 0x6058, 1240 .enable_mask = BIT(0), 1241 .hw.init = &(struct clk_init_data){ 1242 .name = "cam_cc_csi2phytimer_clk", 1243 .parent_hws = (const struct clk_hw*[]){ 1244 &cam_cc_csi2phytimer_clk_src.clkr.hw 1245 }, 1246 .num_parents = 1, 1247 .flags = CLK_SET_RATE_PARENT, 1248 .ops = &clk_branch2_ops, 1249 }, 1250 }, 1251 }; 1252 1253 static struct clk_branch cam_cc_csi3phytimer_clk = { 1254 .halt_reg = 0x6078, 1255 .halt_check = BRANCH_HALT, 1256 .clkr = { 1257 .enable_reg = 0x6078, 1258 .enable_mask = BIT(0), 1259 .hw.init = &(struct clk_init_data){ 1260 .name = "cam_cc_csi3phytimer_clk", 1261 .parent_hws = (const struct clk_hw*[]){ 1262 &cam_cc_csi3phytimer_clk_src.clkr.hw 1263 }, 1264 .num_parents = 1, 1265 .flags = CLK_SET_RATE_PARENT, 1266 .ops = &clk_branch2_ops, 1267 }, 1268 }, 1269 }; 1270 1271 static struct clk_branch cam_cc_csi4phytimer_clk = { 1272 .halt_reg = 0x6098, 1273 .halt_check = BRANCH_HALT, 1274 .clkr = { 1275 .enable_reg = 0x6098, 1276 .enable_mask = BIT(0), 1277 .hw.init = &(struct clk_init_data){ 1278 .name = "cam_cc_csi4phytimer_clk", 1279 .parent_hws = (const struct clk_hw*[]){ 1280 &cam_cc_csi4phytimer_clk_src.clkr.hw 1281 }, 1282 .num_parents = 1, 1283 .flags = CLK_SET_RATE_PARENT, 1284 .ops = &clk_branch2_ops, 1285 }, 1286 }, 1287 }; 1288 1289 static struct clk_branch cam_cc_csi5phytimer_clk = { 1290 .halt_reg = 0x60b8, 1291 .halt_check = BRANCH_HALT, 1292 .clkr = { 1293 .enable_reg = 0x60b8, 1294 .enable_mask = BIT(0), 1295 .hw.init = &(struct clk_init_data){ 1296 .name = "cam_cc_csi5phytimer_clk", 1297 .parent_hws = (const struct clk_hw*[]){ 1298 &cam_cc_csi5phytimer_clk_src.clkr.hw 1299 }, 1300 .num_parents = 1, 1301 .flags = CLK_SET_RATE_PARENT, 1302 .ops = &clk_branch2_ops, 1303 }, 1304 }, 1305 }; 1306 1307 static struct clk_branch cam_cc_csiphy0_clk = { 1308 .halt_reg = 0x601c, 1309 .halt_check = BRANCH_HALT, 1310 .clkr = { 1311 .enable_reg = 0x601c, 1312 .enable_mask = BIT(0), 1313 .hw.init = &(struct clk_init_data){ 1314 .name = "cam_cc_csiphy0_clk", 1315 .parent_hws = (const struct clk_hw*[]){ 1316 &cam_cc_cphy_rx_clk_src.clkr.hw 1317 }, 1318 .num_parents = 1, 1319 .flags = CLK_SET_RATE_PARENT, 1320 .ops = &clk_branch2_ops, 1321 }, 1322 }, 1323 }; 1324 1325 static struct clk_branch cam_cc_csiphy1_clk = { 1326 .halt_reg = 0x603c, 1327 .halt_check = BRANCH_HALT, 1328 .clkr = { 1329 .enable_reg = 0x603c, 1330 .enable_mask = BIT(0), 1331 .hw.init = &(struct clk_init_data){ 1332 .name = "cam_cc_csiphy1_clk", 1333 .parent_hws = (const struct clk_hw*[]){ 1334 &cam_cc_cphy_rx_clk_src.clkr.hw 1335 }, 1336 .num_parents = 1, 1337 .flags = CLK_SET_RATE_PARENT, 1338 .ops = &clk_branch2_ops, 1339 }, 1340 }, 1341 }; 1342 1343 static struct clk_branch cam_cc_csiphy2_clk = { 1344 .halt_reg = 0x605c, 1345 .halt_check = BRANCH_HALT, 1346 .clkr = { 1347 .enable_reg = 0x605c, 1348 .enable_mask = BIT(0), 1349 .hw.init = &(struct clk_init_data){ 1350 .name = "cam_cc_csiphy2_clk", 1351 .parent_hws = (const struct clk_hw*[]){ 1352 &cam_cc_cphy_rx_clk_src.clkr.hw 1353 }, 1354 .num_parents = 1, 1355 .flags = CLK_SET_RATE_PARENT, 1356 .ops = &clk_branch2_ops, 1357 }, 1358 }, 1359 }; 1360 1361 static struct clk_branch cam_cc_csiphy3_clk = { 1362 .halt_reg = 0x607c, 1363 .halt_check = BRANCH_HALT, 1364 .clkr = { 1365 .enable_reg = 0x607c, 1366 .enable_mask = BIT(0), 1367 .hw.init = &(struct clk_init_data){ 1368 .name = "cam_cc_csiphy3_clk", 1369 .parent_hws = (const struct clk_hw*[]){ 1370 &cam_cc_cphy_rx_clk_src.clkr.hw 1371 }, 1372 .num_parents = 1, 1373 .flags = CLK_SET_RATE_PARENT, 1374 .ops = &clk_branch2_ops, 1375 }, 1376 }, 1377 }; 1378 1379 static struct clk_branch cam_cc_csiphy4_clk = { 1380 .halt_reg = 0x609c, 1381 .halt_check = BRANCH_HALT, 1382 .clkr = { 1383 .enable_reg = 0x609c, 1384 .enable_mask = BIT(0), 1385 .hw.init = &(struct clk_init_data){ 1386 .name = "cam_cc_csiphy4_clk", 1387 .parent_hws = (const struct clk_hw*[]){ 1388 &cam_cc_cphy_rx_clk_src.clkr.hw 1389 }, 1390 .num_parents = 1, 1391 .flags = CLK_SET_RATE_PARENT, 1392 .ops = &clk_branch2_ops, 1393 }, 1394 }, 1395 }; 1396 1397 static struct clk_branch cam_cc_csiphy5_clk = { 1398 .halt_reg = 0x60bc, 1399 .halt_check = BRANCH_HALT, 1400 .clkr = { 1401 .enable_reg = 0x60bc, 1402 .enable_mask = BIT(0), 1403 .hw.init = &(struct clk_init_data){ 1404 .name = "cam_cc_csiphy5_clk", 1405 .parent_hws = (const struct clk_hw*[]){ 1406 &cam_cc_cphy_rx_clk_src.clkr.hw 1407 }, 1408 .num_parents = 1, 1409 .flags = CLK_SET_RATE_PARENT, 1410 .ops = &clk_branch2_ops, 1411 }, 1412 }, 1413 }; 1414 1415 static struct clk_branch cam_cc_fd_core_clk = { 1416 .halt_reg = 0xc0b0, 1417 .halt_check = BRANCH_HALT, 1418 .clkr = { 1419 .enable_reg = 0xc0b0, 1420 .enable_mask = BIT(0), 1421 .hw.init = &(struct clk_init_data){ 1422 .name = "cam_cc_fd_core_clk", 1423 .parent_hws = (const struct clk_hw*[]){ 1424 &cam_cc_fd_core_clk_src.clkr.hw 1425 }, 1426 .num_parents = 1, 1427 .flags = CLK_SET_RATE_PARENT, 1428 .ops = &clk_branch2_ops, 1429 }, 1430 }, 1431 }; 1432 1433 static struct clk_branch cam_cc_fd_core_uar_clk = { 1434 .halt_reg = 0xc0b8, 1435 .halt_check = BRANCH_HALT, 1436 .clkr = { 1437 .enable_reg = 0xc0b8, 1438 .enable_mask = BIT(0), 1439 .hw.init = &(struct clk_init_data){ 1440 .name = "cam_cc_fd_core_uar_clk", 1441 .parent_hws = (const struct clk_hw*[]){ 1442 &cam_cc_fd_core_clk_src.clkr.hw 1443 }, 1444 .num_parents = 1, 1445 .flags = CLK_SET_RATE_PARENT, 1446 .ops = &clk_branch2_ops, 1447 }, 1448 }, 1449 }; 1450 1451 static struct clk_branch cam_cc_gdsc_clk = { 1452 .halt_reg = 0xc16c, 1453 .halt_check = BRANCH_HALT, 1454 .clkr = { 1455 .enable_reg = 0xc16c, 1456 .enable_mask = BIT(0), 1457 .hw.init = &(struct clk_init_data){ 1458 .name = "cam_cc_gdsc_clk", 1459 .parent_hws = (const struct clk_hw*[]){ 1460 &cam_cc_xo_clk_src.clkr.hw 1461 }, 1462 .num_parents = 1, 1463 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 1464 .ops = &clk_branch2_ops, 1465 }, 1466 }, 1467 }; 1468 1469 static struct clk_branch cam_cc_icp_ahb_clk = { 1470 .halt_reg = 0xc094, 1471 .halt_check = BRANCH_HALT, 1472 .clkr = { 1473 .enable_reg = 0xc094, 1474 .enable_mask = BIT(0), 1475 .hw.init = &(struct clk_init_data){ 1476 .name = "cam_cc_icp_ahb_clk", 1477 .parent_hws = (const struct clk_hw*[]){ 1478 &cam_cc_slow_ahb_clk_src.clkr.hw 1479 }, 1480 .num_parents = 1, 1481 .flags = CLK_SET_RATE_PARENT, 1482 .ops = &clk_branch2_ops, 1483 }, 1484 }, 1485 }; 1486 1487 static struct clk_branch cam_cc_icp_clk = { 1488 .halt_reg = 0xc08c, 1489 .halt_check = BRANCH_HALT, 1490 .clkr = { 1491 .enable_reg = 0xc08c, 1492 .enable_mask = BIT(0), 1493 .hw.init = &(struct clk_init_data){ 1494 .name = "cam_cc_icp_clk", 1495 .parent_hws = (const struct clk_hw*[]){ 1496 &cam_cc_icp_clk_src.clkr.hw 1497 }, 1498 .num_parents = 1, 1499 .flags = CLK_SET_RATE_PARENT, 1500 .ops = &clk_branch2_ops, 1501 }, 1502 }, 1503 }; 1504 1505 static struct clk_branch cam_cc_ife_0_ahb_clk = { 1506 .halt_reg = 0xa088, 1507 .halt_check = BRANCH_HALT, 1508 .clkr = { 1509 .enable_reg = 0xa088, 1510 .enable_mask = BIT(0), 1511 .hw.init = &(struct clk_init_data){ 1512 .name = "cam_cc_ife_0_ahb_clk", 1513 .parent_hws = (const struct clk_hw*[]){ 1514 &cam_cc_slow_ahb_clk_src.clkr.hw 1515 }, 1516 .num_parents = 1, 1517 .flags = CLK_SET_RATE_PARENT, 1518 .ops = &clk_branch2_ops, 1519 }, 1520 }, 1521 }; 1522 1523 static struct clk_branch cam_cc_ife_0_areg_clk = { 1524 .halt_reg = 0xa030, 1525 .halt_check = BRANCH_HALT, 1526 .clkr = { 1527 .enable_reg = 0xa030, 1528 .enable_mask = BIT(0), 1529 .hw.init = &(struct clk_init_data){ 1530 .name = "cam_cc_ife_0_areg_clk", 1531 .parent_hws = (const struct clk_hw*[]){ 1532 &cam_cc_fast_ahb_clk_src.clkr.hw 1533 }, 1534 .num_parents = 1, 1535 .flags = CLK_SET_RATE_PARENT, 1536 .ops = &clk_branch2_ops, 1537 }, 1538 }, 1539 }; 1540 1541 static struct clk_branch cam_cc_ife_0_axi_clk = { 1542 .halt_reg = 0xa084, 1543 .halt_check = BRANCH_HALT, 1544 .clkr = { 1545 .enable_reg = 0xa084, 1546 .enable_mask = BIT(0), 1547 .hw.init = &(struct clk_init_data){ 1548 .name = "cam_cc_ife_0_axi_clk", 1549 .parent_hws = (const struct clk_hw*[]){ 1550 &cam_cc_camnoc_axi_clk_src.clkr.hw 1551 }, 1552 .num_parents = 1, 1553 .flags = CLK_SET_RATE_PARENT, 1554 .ops = &clk_branch2_ops, 1555 }, 1556 }, 1557 }; 1558 1559 static struct clk_branch cam_cc_ife_0_clk = { 1560 .halt_reg = 0xa028, 1561 .halt_check = BRANCH_HALT, 1562 .clkr = { 1563 .enable_reg = 0xa028, 1564 .enable_mask = BIT(0), 1565 .hw.init = &(struct clk_init_data){ 1566 .name = "cam_cc_ife_0_clk", 1567 .parent_hws = (const struct clk_hw*[]){ 1568 &cam_cc_ife_0_clk_src.clkr.hw 1569 }, 1570 .num_parents = 1, 1571 .flags = CLK_SET_RATE_PARENT, 1572 .ops = &clk_branch2_ops, 1573 }, 1574 }, 1575 }; 1576 1577 static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { 1578 .halt_reg = 0xa080, 1579 .halt_check = BRANCH_HALT, 1580 .clkr = { 1581 .enable_reg = 0xa080, 1582 .enable_mask = BIT(0), 1583 .hw.init = &(struct clk_init_data){ 1584 .name = "cam_cc_ife_0_cphy_rx_clk", 1585 .parent_hws = (const struct clk_hw*[]){ 1586 &cam_cc_cphy_rx_clk_src.clkr.hw 1587 }, 1588 .num_parents = 1, 1589 .flags = CLK_SET_RATE_PARENT, 1590 .ops = &clk_branch2_ops, 1591 }, 1592 }, 1593 }; 1594 1595 static struct clk_branch cam_cc_ife_0_csid_clk = { 1596 .halt_reg = 0xa058, 1597 .halt_check = BRANCH_HALT, 1598 .clkr = { 1599 .enable_reg = 0xa058, 1600 .enable_mask = BIT(0), 1601 .hw.init = &(struct clk_init_data){ 1602 .name = "cam_cc_ife_0_csid_clk", 1603 .parent_hws = (const struct clk_hw*[]){ 1604 &cam_cc_ife_0_csid_clk_src.clkr.hw 1605 }, 1606 .num_parents = 1, 1607 .flags = CLK_SET_RATE_PARENT, 1608 .ops = &clk_branch2_ops, 1609 }, 1610 }, 1611 }; 1612 1613 static struct clk_branch cam_cc_ife_0_dsp_clk = { 1614 .halt_reg = 0xa03c, 1615 .halt_check = BRANCH_HALT, 1616 .clkr = { 1617 .enable_reg = 0xa03c, 1618 .enable_mask = BIT(0), 1619 .hw.init = &(struct clk_init_data){ 1620 .name = "cam_cc_ife_0_dsp_clk", 1621 .parent_hws = (const struct clk_hw*[]){ 1622 &cam_cc_ife_0_clk_src.clkr.hw 1623 }, 1624 .num_parents = 1, 1625 .flags = CLK_SET_RATE_PARENT, 1626 .ops = &clk_branch2_ops, 1627 }, 1628 }, 1629 }; 1630 1631 static struct clk_branch cam_cc_ife_1_ahb_clk = { 1632 .halt_reg = 0xb068, 1633 .halt_check = BRANCH_HALT, 1634 .clkr = { 1635 .enable_reg = 0xb068, 1636 .enable_mask = BIT(0), 1637 .hw.init = &(struct clk_init_data){ 1638 .name = "cam_cc_ife_1_ahb_clk", 1639 .parent_hws = (const struct clk_hw*[]){ 1640 &cam_cc_slow_ahb_clk_src.clkr.hw 1641 }, 1642 .num_parents = 1, 1643 .flags = CLK_SET_RATE_PARENT, 1644 .ops = &clk_branch2_ops, 1645 }, 1646 }, 1647 }; 1648 1649 static struct clk_branch cam_cc_ife_1_areg_clk = { 1650 .halt_reg = 0xb030, 1651 .halt_check = BRANCH_HALT, 1652 .clkr = { 1653 .enable_reg = 0xb030, 1654 .enable_mask = BIT(0), 1655 .hw.init = &(struct clk_init_data){ 1656 .name = "cam_cc_ife_1_areg_clk", 1657 .parent_hws = (const struct clk_hw*[]){ 1658 &cam_cc_fast_ahb_clk_src.clkr.hw 1659 }, 1660 .num_parents = 1, 1661 .flags = CLK_SET_RATE_PARENT, 1662 .ops = &clk_branch2_ops, 1663 }, 1664 }, 1665 }; 1666 1667 static struct clk_branch cam_cc_ife_1_axi_clk = { 1668 .halt_reg = 0xb064, 1669 .halt_check = BRANCH_HALT, 1670 .clkr = { 1671 .enable_reg = 0xb064, 1672 .enable_mask = BIT(0), 1673 .hw.init = &(struct clk_init_data){ 1674 .name = "cam_cc_ife_1_axi_clk", 1675 .parent_hws = (const struct clk_hw*[]){ 1676 &cam_cc_camnoc_axi_clk_src.clkr.hw 1677 }, 1678 .num_parents = 1, 1679 .flags = CLK_SET_RATE_PARENT, 1680 .ops = &clk_branch2_ops, 1681 }, 1682 }, 1683 }; 1684 1685 static struct clk_branch cam_cc_ife_1_clk = { 1686 .halt_reg = 0xb028, 1687 .halt_check = BRANCH_HALT, 1688 .clkr = { 1689 .enable_reg = 0xb028, 1690 .enable_mask = BIT(0), 1691 .hw.init = &(struct clk_init_data){ 1692 .name = "cam_cc_ife_1_clk", 1693 .parent_hws = (const struct clk_hw*[]){ 1694 &cam_cc_ife_1_clk_src.clkr.hw 1695 }, 1696 .num_parents = 1, 1697 .flags = CLK_SET_RATE_PARENT, 1698 .ops = &clk_branch2_ops, 1699 }, 1700 }, 1701 }; 1702 1703 static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { 1704 .halt_reg = 0xb060, 1705 .halt_check = BRANCH_HALT, 1706 .clkr = { 1707 .enable_reg = 0xb060, 1708 .enable_mask = BIT(0), 1709 .hw.init = &(struct clk_init_data){ 1710 .name = "cam_cc_ife_1_cphy_rx_clk", 1711 .parent_hws = (const struct clk_hw*[]){ 1712 &cam_cc_cphy_rx_clk_src.clkr.hw 1713 }, 1714 .num_parents = 1, 1715 .flags = CLK_SET_RATE_PARENT, 1716 .ops = &clk_branch2_ops, 1717 }, 1718 }, 1719 }; 1720 1721 static struct clk_branch cam_cc_ife_1_csid_clk = { 1722 .halt_reg = 0xb058, 1723 .halt_check = BRANCH_HALT, 1724 .clkr = { 1725 .enable_reg = 0xb058, 1726 .enable_mask = BIT(0), 1727 .hw.init = &(struct clk_init_data){ 1728 .name = "cam_cc_ife_1_csid_clk", 1729 .parent_hws = (const struct clk_hw*[]){ 1730 &cam_cc_ife_1_csid_clk_src.clkr.hw 1731 }, 1732 .num_parents = 1, 1733 .flags = CLK_SET_RATE_PARENT, 1734 .ops = &clk_branch2_ops, 1735 }, 1736 }, 1737 }; 1738 1739 static struct clk_branch cam_cc_ife_1_dsp_clk = { 1740 .halt_reg = 0xb03c, 1741 .halt_check = BRANCH_HALT, 1742 .clkr = { 1743 .enable_reg = 0xb03c, 1744 .enable_mask = BIT(0), 1745 .hw.init = &(struct clk_init_data){ 1746 .name = "cam_cc_ife_1_dsp_clk", 1747 .parent_hws = (const struct clk_hw*[]){ 1748 &cam_cc_ife_1_clk_src.clkr.hw 1749 }, 1750 .num_parents = 1, 1751 .flags = CLK_SET_RATE_PARENT, 1752 .ops = &clk_branch2_ops, 1753 }, 1754 }, 1755 }; 1756 1757 static struct clk_branch cam_cc_ife_lite_ahb_clk = { 1758 .halt_reg = 0xc040, 1759 .halt_check = BRANCH_HALT, 1760 .clkr = { 1761 .enable_reg = 0xc040, 1762 .enable_mask = BIT(0), 1763 .hw.init = &(struct clk_init_data){ 1764 .name = "cam_cc_ife_lite_ahb_clk", 1765 .parent_hws = (const struct clk_hw*[]){ 1766 &cam_cc_slow_ahb_clk_src.clkr.hw 1767 }, 1768 .num_parents = 1, 1769 .flags = CLK_SET_RATE_PARENT, 1770 .ops = &clk_branch2_ops, 1771 }, 1772 }, 1773 }; 1774 1775 static struct clk_branch cam_cc_ife_lite_axi_clk = { 1776 .halt_reg = 0xc044, 1777 .halt_check = BRANCH_HALT, 1778 .clkr = { 1779 .enable_reg = 0xc044, 1780 .enable_mask = BIT(0), 1781 .hw.init = &(struct clk_init_data){ 1782 .name = "cam_cc_ife_lite_axi_clk", 1783 .parent_hws = (const struct clk_hw*[]){ 1784 &cam_cc_camnoc_axi_clk_src.clkr.hw 1785 }, 1786 .num_parents = 1, 1787 .flags = CLK_SET_RATE_PARENT, 1788 .ops = &clk_branch2_ops, 1789 }, 1790 }, 1791 }; 1792 1793 static struct clk_branch cam_cc_ife_lite_clk = { 1794 .halt_reg = 0xc018, 1795 .halt_check = BRANCH_HALT, 1796 .clkr = { 1797 .enable_reg = 0xc018, 1798 .enable_mask = BIT(0), 1799 .hw.init = &(struct clk_init_data){ 1800 .name = "cam_cc_ife_lite_clk", 1801 .parent_hws = (const struct clk_hw*[]){ 1802 &cam_cc_ife_lite_clk_src.clkr.hw 1803 }, 1804 .num_parents = 1, 1805 .flags = CLK_SET_RATE_PARENT, 1806 .ops = &clk_branch2_ops, 1807 }, 1808 }, 1809 }; 1810 1811 static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { 1812 .halt_reg = 0xc03c, 1813 .halt_check = BRANCH_HALT, 1814 .clkr = { 1815 .enable_reg = 0xc03c, 1816 .enable_mask = BIT(0), 1817 .hw.init = &(struct clk_init_data){ 1818 .name = "cam_cc_ife_lite_cphy_rx_clk", 1819 .parent_hws = (const struct clk_hw*[]){ 1820 &cam_cc_cphy_rx_clk_src.clkr.hw 1821 }, 1822 .num_parents = 1, 1823 .flags = CLK_SET_RATE_PARENT, 1824 .ops = &clk_branch2_ops, 1825 }, 1826 }, 1827 }; 1828 1829 static struct clk_branch cam_cc_ife_lite_csid_clk = { 1830 .halt_reg = 0xc034, 1831 .halt_check = BRANCH_HALT, 1832 .clkr = { 1833 .enable_reg = 0xc034, 1834 .enable_mask = BIT(0), 1835 .hw.init = &(struct clk_init_data){ 1836 .name = "cam_cc_ife_lite_csid_clk", 1837 .parent_hws = (const struct clk_hw*[]){ 1838 &cam_cc_ife_lite_csid_clk_src.clkr.hw 1839 }, 1840 .num_parents = 1, 1841 .flags = CLK_SET_RATE_PARENT, 1842 .ops = &clk_branch2_ops, 1843 }, 1844 }, 1845 }; 1846 1847 static struct clk_branch cam_cc_ipe_0_ahb_clk = { 1848 .halt_reg = 0x8040, 1849 .halt_check = BRANCH_HALT, 1850 .clkr = { 1851 .enable_reg = 0x8040, 1852 .enable_mask = BIT(0), 1853 .hw.init = &(struct clk_init_data){ 1854 .name = "cam_cc_ipe_0_ahb_clk", 1855 .parent_hws = (const struct clk_hw*[]){ 1856 &cam_cc_slow_ahb_clk_src.clkr.hw 1857 }, 1858 .num_parents = 1, 1859 .flags = CLK_SET_RATE_PARENT, 1860 .ops = &clk_branch2_ops, 1861 }, 1862 }, 1863 }; 1864 1865 static struct clk_branch cam_cc_ipe_0_areg_clk = { 1866 .halt_reg = 0x803c, 1867 .halt_check = BRANCH_HALT, 1868 .clkr = { 1869 .enable_reg = 0x803c, 1870 .enable_mask = BIT(0), 1871 .hw.init = &(struct clk_init_data){ 1872 .name = "cam_cc_ipe_0_areg_clk", 1873 .parent_hws = (const struct clk_hw*[]){ 1874 &cam_cc_fast_ahb_clk_src.clkr.hw 1875 }, 1876 .num_parents = 1, 1877 .flags = CLK_SET_RATE_PARENT, 1878 .ops = &clk_branch2_ops, 1879 }, 1880 }, 1881 }; 1882 1883 static struct clk_branch cam_cc_ipe_0_axi_clk = { 1884 .halt_reg = 0x8038, 1885 .halt_check = BRANCH_HALT, 1886 .clkr = { 1887 .enable_reg = 0x8038, 1888 .enable_mask = BIT(0), 1889 .hw.init = &(struct clk_init_data){ 1890 .name = "cam_cc_ipe_0_axi_clk", 1891 .parent_hws = (const struct clk_hw*[]){ 1892 &cam_cc_camnoc_axi_clk_src.clkr.hw 1893 }, 1894 .num_parents = 1, 1895 .flags = CLK_SET_RATE_PARENT, 1896 .ops = &clk_branch2_ops, 1897 }, 1898 }, 1899 }; 1900 1901 static struct clk_branch cam_cc_ipe_0_clk = { 1902 .halt_reg = 0x8028, 1903 .halt_check = BRANCH_HALT, 1904 .clkr = { 1905 .enable_reg = 0x8028, 1906 .enable_mask = BIT(0), 1907 .hw.init = &(struct clk_init_data){ 1908 .name = "cam_cc_ipe_0_clk", 1909 .parent_hws = (const struct clk_hw*[]){ 1910 &cam_cc_ipe_0_clk_src.clkr.hw 1911 }, 1912 .num_parents = 1, 1913 .flags = CLK_SET_RATE_PARENT, 1914 .ops = &clk_branch2_ops, 1915 }, 1916 }, 1917 }; 1918 1919 static struct clk_branch cam_cc_jpeg_clk = { 1920 .halt_reg = 0xc060, 1921 .halt_check = BRANCH_HALT, 1922 .clkr = { 1923 .enable_reg = 0xc060, 1924 .enable_mask = BIT(0), 1925 .hw.init = &(struct clk_init_data){ 1926 .name = "cam_cc_jpeg_clk", 1927 .parent_hws = (const struct clk_hw*[]){ 1928 &cam_cc_jpeg_clk_src.clkr.hw 1929 }, 1930 .num_parents = 1, 1931 .flags = CLK_SET_RATE_PARENT, 1932 .ops = &clk_branch2_ops, 1933 }, 1934 }, 1935 }; 1936 1937 static struct clk_branch cam_cc_mclk0_clk = { 1938 .halt_reg = 0x5018, 1939 .halt_check = BRANCH_HALT, 1940 .clkr = { 1941 .enable_reg = 0x5018, 1942 .enable_mask = BIT(0), 1943 .hw.init = &(struct clk_init_data){ 1944 .name = "cam_cc_mclk0_clk", 1945 .parent_hws = (const struct clk_hw*[]){ 1946 &cam_cc_mclk0_clk_src.clkr.hw 1947 }, 1948 .num_parents = 1, 1949 .flags = CLK_SET_RATE_PARENT, 1950 .ops = &clk_branch2_ops, 1951 }, 1952 }, 1953 }; 1954 1955 static struct clk_branch cam_cc_mclk1_clk = { 1956 .halt_reg = 0x5034, 1957 .halt_check = BRANCH_HALT, 1958 .clkr = { 1959 .enable_reg = 0x5034, 1960 .enable_mask = BIT(0), 1961 .hw.init = &(struct clk_init_data){ 1962 .name = "cam_cc_mclk1_clk", 1963 .parent_hws = (const struct clk_hw*[]){ 1964 &cam_cc_mclk1_clk_src.clkr.hw 1965 }, 1966 .num_parents = 1, 1967 .flags = CLK_SET_RATE_PARENT, 1968 .ops = &clk_branch2_ops, 1969 }, 1970 }, 1971 }; 1972 1973 static struct clk_branch cam_cc_mclk2_clk = { 1974 .halt_reg = 0x5050, 1975 .halt_check = BRANCH_HALT, 1976 .clkr = { 1977 .enable_reg = 0x5050, 1978 .enable_mask = BIT(0), 1979 .hw.init = &(struct clk_init_data){ 1980 .name = "cam_cc_mclk2_clk", 1981 .parent_hws = (const struct clk_hw*[]){ 1982 &cam_cc_mclk2_clk_src.clkr.hw 1983 }, 1984 .num_parents = 1, 1985 .flags = CLK_SET_RATE_PARENT, 1986 .ops = &clk_branch2_ops, 1987 }, 1988 }, 1989 }; 1990 1991 static struct clk_branch cam_cc_mclk3_clk = { 1992 .halt_reg = 0x506c, 1993 .halt_check = BRANCH_HALT, 1994 .clkr = { 1995 .enable_reg = 0x506c, 1996 .enable_mask = BIT(0), 1997 .hw.init = &(struct clk_init_data){ 1998 .name = "cam_cc_mclk3_clk", 1999 .parent_hws = (const struct clk_hw*[]){ 2000 &cam_cc_mclk3_clk_src.clkr.hw 2001 }, 2002 .num_parents = 1, 2003 .flags = CLK_SET_RATE_PARENT, 2004 .ops = &clk_branch2_ops, 2005 }, 2006 }, 2007 }; 2008 2009 static struct clk_branch cam_cc_mclk4_clk = { 2010 .halt_reg = 0x5088, 2011 .halt_check = BRANCH_HALT, 2012 .clkr = { 2013 .enable_reg = 0x5088, 2014 .enable_mask = BIT(0), 2015 .hw.init = &(struct clk_init_data){ 2016 .name = "cam_cc_mclk4_clk", 2017 .parent_hws = (const struct clk_hw*[]){ 2018 &cam_cc_mclk4_clk_src.clkr.hw 2019 }, 2020 .num_parents = 1, 2021 .flags = CLK_SET_RATE_PARENT, 2022 .ops = &clk_branch2_ops, 2023 }, 2024 }, 2025 }; 2026 2027 static struct clk_branch cam_cc_mclk5_clk = { 2028 .halt_reg = 0x50a4, 2029 .halt_check = BRANCH_HALT, 2030 .clkr = { 2031 .enable_reg = 0x50a4, 2032 .enable_mask = BIT(0), 2033 .hw.init = &(struct clk_init_data){ 2034 .name = "cam_cc_mclk5_clk", 2035 .parent_hws = (const struct clk_hw*[]){ 2036 &cam_cc_mclk5_clk_src.clkr.hw 2037 }, 2038 .num_parents = 1, 2039 .flags = CLK_SET_RATE_PARENT, 2040 .ops = &clk_branch2_ops, 2041 }, 2042 }, 2043 }; 2044 2045 static struct clk_branch cam_cc_mclk6_clk = { 2046 .halt_reg = 0x50c0, 2047 .halt_check = BRANCH_HALT, 2048 .clkr = { 2049 .enable_reg = 0x50c0, 2050 .enable_mask = BIT(0), 2051 .hw.init = &(struct clk_init_data){ 2052 .name = "cam_cc_mclk6_clk", 2053 .parent_hws = (const struct clk_hw*[]){ 2054 &cam_cc_mclk6_clk_src.clkr.hw 2055 }, 2056 .num_parents = 1, 2057 .flags = CLK_SET_RATE_PARENT, 2058 .ops = &clk_branch2_ops, 2059 }, 2060 }, 2061 }; 2062 2063 static struct clk_branch cam_cc_sbi_ahb_clk = { 2064 .halt_reg = 0x9040, 2065 .halt_check = BRANCH_HALT, 2066 .clkr = { 2067 .enable_reg = 0x9040, 2068 .enable_mask = BIT(0), 2069 .hw.init = &(struct clk_init_data){ 2070 .name = "cam_cc_sbi_ahb_clk", 2071 .parent_hws = (const struct clk_hw*[]){ 2072 &cam_cc_slow_ahb_clk_src.clkr.hw 2073 }, 2074 .num_parents = 1, 2075 .flags = CLK_SET_RATE_PARENT, 2076 .ops = &clk_branch2_ops, 2077 }, 2078 }, 2079 }; 2080 2081 static struct clk_branch cam_cc_sbi_axi_clk = { 2082 .halt_reg = 0x903c, 2083 .halt_check = BRANCH_HALT, 2084 .clkr = { 2085 .enable_reg = 0x903c, 2086 .enable_mask = BIT(0), 2087 .hw.init = &(struct clk_init_data){ 2088 .name = "cam_cc_sbi_axi_clk", 2089 .parent_hws = (const struct clk_hw*[]){ 2090 &cam_cc_camnoc_axi_clk_src.clkr.hw 2091 }, 2092 .num_parents = 1, 2093 .flags = CLK_SET_RATE_PARENT, 2094 .ops = &clk_branch2_ops, 2095 }, 2096 }, 2097 }; 2098 2099 static struct clk_branch cam_cc_sbi_clk = { 2100 .halt_reg = 0x9014, 2101 .halt_check = BRANCH_HALT, 2102 .clkr = { 2103 .enable_reg = 0x9014, 2104 .enable_mask = BIT(0), 2105 .hw.init = &(struct clk_init_data){ 2106 .name = "cam_cc_sbi_clk", 2107 .parent_hws = (const struct clk_hw*[]){ 2108 &cam_cc_sbi_div_clk_src.clkr.hw 2109 }, 2110 .num_parents = 1, 2111 .flags = CLK_SET_RATE_PARENT, 2112 .ops = &clk_branch2_ops, 2113 }, 2114 }, 2115 }; 2116 2117 static struct clk_branch cam_cc_sbi_cphy_rx_clk = { 2118 .halt_reg = 0x9038, 2119 .halt_check = BRANCH_HALT, 2120 .clkr = { 2121 .enable_reg = 0x9038, 2122 .enable_mask = BIT(0), 2123 .hw.init = &(struct clk_init_data){ 2124 .name = "cam_cc_sbi_cphy_rx_clk", 2125 .parent_hws = (const struct clk_hw*[]){ 2126 &cam_cc_cphy_rx_clk_src.clkr.hw 2127 }, 2128 .num_parents = 1, 2129 .flags = CLK_SET_RATE_PARENT, 2130 .ops = &clk_branch2_ops, 2131 }, 2132 }, 2133 }; 2134 2135 static struct clk_branch cam_cc_sbi_csid_clk = { 2136 .halt_reg = 0x9034, 2137 .halt_check = BRANCH_HALT, 2138 .clkr = { 2139 .enable_reg = 0x9034, 2140 .enable_mask = BIT(0), 2141 .hw.init = &(struct clk_init_data){ 2142 .name = "cam_cc_sbi_csid_clk", 2143 .parent_hws = (const struct clk_hw*[]){ 2144 &cam_cc_sbi_csid_clk_src.clkr.hw 2145 }, 2146 .num_parents = 1, 2147 .flags = CLK_SET_RATE_PARENT, 2148 .ops = &clk_branch2_ops, 2149 }, 2150 }, 2151 }; 2152 2153 static struct clk_branch cam_cc_sbi_ife_0_clk = { 2154 .halt_reg = 0x9044, 2155 .halt_check = BRANCH_HALT, 2156 .clkr = { 2157 .enable_reg = 0x9044, 2158 .enable_mask = BIT(0), 2159 .hw.init = &(struct clk_init_data){ 2160 .name = "cam_cc_sbi_ife_0_clk", 2161 .parent_hws = (const struct clk_hw*[]){ 2162 &cam_cc_ife_0_clk_src.clkr.hw 2163 }, 2164 .num_parents = 1, 2165 .flags = CLK_SET_RATE_PARENT, 2166 .ops = &clk_branch2_ops, 2167 }, 2168 }, 2169 }; 2170 2171 static struct clk_branch cam_cc_sbi_ife_1_clk = { 2172 .halt_reg = 0x9048, 2173 .halt_check = BRANCH_HALT, 2174 .clkr = { 2175 .enable_reg = 0x9048, 2176 .enable_mask = BIT(0), 2177 .hw.init = &(struct clk_init_data){ 2178 .name = "cam_cc_sbi_ife_1_clk", 2179 .parent_hws = (const struct clk_hw*[]){ 2180 &cam_cc_ife_1_clk_src.clkr.hw 2181 }, 2182 .num_parents = 1, 2183 .flags = CLK_SET_RATE_PARENT, 2184 .ops = &clk_branch2_ops, 2185 }, 2186 }, 2187 }; 2188 2189 static struct clk_branch cam_cc_sleep_clk = { 2190 .halt_reg = 0xc188, 2191 .halt_check = BRANCH_HALT, 2192 .clkr = { 2193 .enable_reg = 0xc188, 2194 .enable_mask = BIT(0), 2195 .hw.init = &(struct clk_init_data){ 2196 .name = "cam_cc_sleep_clk", 2197 .parent_hws = (const struct clk_hw*[]){ 2198 &cam_cc_sleep_clk_src.clkr.hw 2199 }, 2200 .num_parents = 1, 2201 .flags = CLK_SET_RATE_PARENT, 2202 .ops = &clk_branch2_ops, 2203 }, 2204 }, 2205 }; 2206 2207 static struct gdsc titan_top_gdsc; 2208 2209 static struct gdsc bps_gdsc = { 2210 .gdscr = 0x7004, 2211 .pd = { 2212 .name = "bps_gdsc", 2213 }, 2214 .flags = HW_CTRL | POLL_CFG_GDSCR, 2215 .parent = &titan_top_gdsc.pd, 2216 .pwrsts = PWRSTS_OFF_ON, 2217 }; 2218 2219 static struct gdsc ipe_0_gdsc = { 2220 .gdscr = 0x8004, 2221 .pd = { 2222 .name = "ipe_0_gdsc", 2223 }, 2224 .flags = HW_CTRL | POLL_CFG_GDSCR, 2225 .parent = &titan_top_gdsc.pd, 2226 .pwrsts = PWRSTS_OFF_ON, 2227 }; 2228 2229 static struct gdsc sbi_gdsc = { 2230 .gdscr = 0x9004, 2231 .pd = { 2232 .name = "sbi_gdsc", 2233 }, 2234 .flags = HW_CTRL | POLL_CFG_GDSCR, 2235 .parent = &titan_top_gdsc.pd, 2236 .pwrsts = PWRSTS_OFF_ON, 2237 }; 2238 2239 static struct gdsc ife_0_gdsc = { 2240 .gdscr = 0xa004, 2241 .pd = { 2242 .name = "ife_0_gdsc", 2243 }, 2244 .flags = POLL_CFG_GDSCR, 2245 .parent = &titan_top_gdsc.pd, 2246 .pwrsts = PWRSTS_OFF_ON, 2247 }; 2248 2249 static struct gdsc ife_1_gdsc = { 2250 .gdscr = 0xb004, 2251 .pd = { 2252 .name = "ife_1_gdsc", 2253 }, 2254 .flags = POLL_CFG_GDSCR, 2255 .parent = &titan_top_gdsc.pd, 2256 .pwrsts = PWRSTS_OFF_ON, 2257 }; 2258 2259 static struct gdsc titan_top_gdsc = { 2260 .gdscr = 0xc144, 2261 .pd = { 2262 .name = "titan_top_gdsc", 2263 }, 2264 .flags = POLL_CFG_GDSCR, 2265 .pwrsts = PWRSTS_OFF_ON, 2266 }; 2267 2268 static struct clk_regmap *cam_cc_sm8250_clocks[] = { 2269 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, 2270 [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr, 2271 [CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr, 2272 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, 2273 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, 2274 [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr, 2275 [CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr, 2276 [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, 2277 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, 2278 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, 2279 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, 2280 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, 2281 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 2282 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 2283 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 2284 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 2285 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 2286 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 2287 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 2288 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 2289 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 2290 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 2291 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 2292 [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr, 2293 [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr, 2294 [CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr, 2295 [CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr, 2296 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 2297 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 2298 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 2299 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 2300 [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, 2301 [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr, 2302 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 2303 [CAM_CC_FD_CORE_CLK] = &cam_cc_fd_core_clk.clkr, 2304 [CAM_CC_FD_CORE_CLK_SRC] = &cam_cc_fd_core_clk_src.clkr, 2305 [CAM_CC_FD_CORE_UAR_CLK] = &cam_cc_fd_core_uar_clk.clkr, 2306 [CAM_CC_GDSC_CLK] = &cam_cc_gdsc_clk.clkr, 2307 [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr, 2308 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 2309 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 2310 [CAM_CC_IFE_0_AHB_CLK] = &cam_cc_ife_0_ahb_clk.clkr, 2311 [CAM_CC_IFE_0_AREG_CLK] = &cam_cc_ife_0_areg_clk.clkr, 2312 [CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr, 2313 [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, 2314 [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, 2315 [CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr, 2316 [CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr, 2317 [CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr, 2318 [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, 2319 [CAM_CC_IFE_1_AHB_CLK] = &cam_cc_ife_1_ahb_clk.clkr, 2320 [CAM_CC_IFE_1_AREG_CLK] = &cam_cc_ife_1_areg_clk.clkr, 2321 [CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr, 2322 [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, 2323 [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, 2324 [CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr, 2325 [CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr, 2326 [CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr, 2327 [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, 2328 [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr, 2329 [CAM_CC_IFE_LITE_AXI_CLK] = &cam_cc_ife_lite_axi_clk.clkr, 2330 [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, 2331 [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, 2332 [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, 2333 [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, 2334 [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, 2335 [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr, 2336 [CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr, 2337 [CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr, 2338 [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr, 2339 [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr, 2340 [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, 2341 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, 2342 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 2343 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 2344 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 2345 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 2346 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 2347 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 2348 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 2349 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 2350 [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, 2351 [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, 2352 [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr, 2353 [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr, 2354 [CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr, 2355 [CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr, 2356 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 2357 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, 2358 [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, 2359 [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 2360 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, 2361 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 2362 [CAM_CC_PLL2_OUT_MAIN] = &cam_cc_pll2_out_main.clkr, 2363 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 2364 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, 2365 [CAM_CC_PLL4] = &cam_cc_pll4.clkr, 2366 [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, 2367 [CAM_CC_SBI_AHB_CLK] = &cam_cc_sbi_ahb_clk.clkr, 2368 [CAM_CC_SBI_AXI_CLK] = &cam_cc_sbi_axi_clk.clkr, 2369 [CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr, 2370 [CAM_CC_SBI_CPHY_RX_CLK] = &cam_cc_sbi_cphy_rx_clk.clkr, 2371 [CAM_CC_SBI_CSID_CLK] = &cam_cc_sbi_csid_clk.clkr, 2372 [CAM_CC_SBI_CSID_CLK_SRC] = &cam_cc_sbi_csid_clk_src.clkr, 2373 [CAM_CC_SBI_DIV_CLK_SRC] = &cam_cc_sbi_div_clk_src.clkr, 2374 [CAM_CC_SBI_IFE_0_CLK] = &cam_cc_sbi_ife_0_clk.clkr, 2375 [CAM_CC_SBI_IFE_1_CLK] = &cam_cc_sbi_ife_1_clk.clkr, 2376 [CAM_CC_SLEEP_CLK] = &cam_cc_sleep_clk.clkr, 2377 [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, 2378 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 2379 [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, 2380 }; 2381 2382 static struct gdsc *cam_cc_sm8250_gdscs[] = { 2383 [BPS_GDSC] = &bps_gdsc, 2384 [IPE_0_GDSC] = &ipe_0_gdsc, 2385 [SBI_GDSC] = &sbi_gdsc, 2386 [IFE_0_GDSC] = &ife_0_gdsc, 2387 [IFE_1_GDSC] = &ife_1_gdsc, 2388 [TITAN_TOP_GDSC] = &titan_top_gdsc, 2389 }; 2390 2391 static const struct qcom_reset_map cam_cc_sm8250_resets[] = { 2392 [CAM_CC_BPS_BCR] = { 0x7000 }, 2393 [CAM_CC_ICP_BCR] = { 0xc070 }, 2394 [CAM_CC_IFE_0_BCR] = { 0xa000 }, 2395 [CAM_CC_IFE_1_BCR] = { 0xb000 }, 2396 [CAM_CC_IPE_0_BCR] = { 0x8000 }, 2397 [CAM_CC_SBI_BCR] = { 0x9000 }, 2398 }; 2399 2400 static const struct regmap_config cam_cc_sm8250_regmap_config = { 2401 .reg_bits = 32, 2402 .reg_stride = 4, 2403 .val_bits = 32, 2404 .max_register = 0xe004, 2405 .fast_io = true, 2406 }; 2407 2408 static const struct qcom_cc_desc cam_cc_sm8250_desc = { 2409 .config = &cam_cc_sm8250_regmap_config, 2410 .clks = cam_cc_sm8250_clocks, 2411 .num_clks = ARRAY_SIZE(cam_cc_sm8250_clocks), 2412 .resets = cam_cc_sm8250_resets, 2413 .num_resets = ARRAY_SIZE(cam_cc_sm8250_resets), 2414 .gdscs = cam_cc_sm8250_gdscs, 2415 .num_gdscs = ARRAY_SIZE(cam_cc_sm8250_gdscs), 2416 }; 2417 2418 static const struct of_device_id cam_cc_sm8250_match_table[] = { 2419 { .compatible = "qcom,sm8250-camcc" }, 2420 { } 2421 }; 2422 MODULE_DEVICE_TABLE(of, cam_cc_sm8250_match_table); 2423 2424 static int cam_cc_sm8250_probe(struct platform_device *pdev) 2425 { 2426 struct regmap *regmap; 2427 2428 regmap = qcom_cc_map(pdev, &cam_cc_sm8250_desc); 2429 if (IS_ERR(regmap)) 2430 return PTR_ERR(regmap); 2431 2432 clk_lucid_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); 2433 clk_lucid_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); 2434 clk_zonda_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); 2435 clk_lucid_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); 2436 clk_lucid_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); 2437 2438 return qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8250_desc, regmap); 2439 } 2440 2441 static struct platform_driver cam_cc_sm8250_driver = { 2442 .probe = cam_cc_sm8250_probe, 2443 .driver = { 2444 .name = "cam_cc-sm8250", 2445 .of_match_table = cam_cc_sm8250_match_table, 2446 }, 2447 }; 2448 2449 module_platform_driver(cam_cc_sm8250_driver); 2450 2451 MODULE_DESCRIPTION("QTI CAMCC SM8250 Driver"); 2452 MODULE_LICENSE("GPL v2"); 2453