1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/err.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 #include <linux/pm_runtime.h> 13 14 #include <dt-bindings/clock/qcom,sm8150-camcc.h> 15 16 #include "clk-alpha-pll.h" 17 #include "clk-branch.h" 18 #include "clk-rcg.h" 19 #include "clk-regmap.h" 20 #include "common.h" 21 #include "gdsc.h" 22 #include "reset.h" 23 24 enum { 25 DT_BI_TCXO, 26 DT_IFACE, 27 }; 28 29 enum { 30 P_BI_TCXO, 31 P_CAM_CC_PLL0_OUT_EVEN, 32 P_CAM_CC_PLL0_OUT_MAIN, 33 P_CAM_CC_PLL0_OUT_ODD, 34 P_CAM_CC_PLL1_OUT_EVEN, 35 P_CAM_CC_PLL2_OUT_EARLY, 36 P_CAM_CC_PLL2_OUT_MAIN, 37 P_CAM_CC_PLL3_OUT_EVEN, 38 P_CAM_CC_PLL4_OUT_EVEN, 39 }; 40 41 static const struct pll_vco regera_vco[] = { 42 { 600000000, 3300000000, 0 }, 43 }; 44 45 static const struct pll_vco trion_vco[] = { 46 { 249600000, 2000000000, 0 }, 47 }; 48 49 static const struct alpha_pll_config cam_cc_pll0_config = { 50 .l = 0x3e, 51 .alpha = 0x8000, 52 .config_ctl_val = 0x20485699, 53 .config_ctl_hi_val = 0x00002267, 54 .config_ctl_hi1_val = 0x00000024, 55 .test_ctl_val = 0x00000000, 56 .test_ctl_hi_val = 0x00000000, 57 .test_ctl_hi1_val = 0x00000020, 58 .user_ctl_val = 0x00003100, 59 .user_ctl_hi_val = 0x00000805, 60 .user_ctl_hi1_val = 0x000000D0, 61 }; 62 63 static struct clk_alpha_pll cam_cc_pll0 = { 64 .offset = 0x0, 65 .vco_table = trion_vco, 66 .num_vco = ARRAY_SIZE(trion_vco), 67 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 68 .clkr = { 69 .hw.init = &(const struct clk_init_data) { 70 .name = "cam_cc_pll0", 71 .parent_data = &(const struct clk_parent_data) { 72 .index = DT_BI_TCXO, 73 }, 74 .num_parents = 1, 75 .ops = &clk_alpha_pll_trion_ops, 76 }, 77 }, 78 }; 79 80 static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { 81 { 0x1, 2 }, 82 { } 83 }; 84 85 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { 86 .offset = 0x0, 87 .post_div_shift = 8, 88 .post_div_table = post_div_table_cam_cc_pll0_out_even, 89 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), 90 .width = 4, 91 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 92 .clkr.hw.init = &(const struct clk_init_data) { 93 .name = "cam_cc_pll0_out_even", 94 .parent_hws = (const struct clk_hw*[]) { 95 &cam_cc_pll0.clkr.hw, 96 }, 97 .num_parents = 1, 98 .flags = CLK_SET_RATE_PARENT, 99 .ops = &clk_alpha_pll_postdiv_trion_ops, 100 }, 101 }; 102 103 static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { 104 { 0x3, 3 }, 105 { } 106 }; 107 108 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { 109 .offset = 0x0, 110 .post_div_shift = 12, 111 .post_div_table = post_div_table_cam_cc_pll0_out_odd, 112 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), 113 .width = 4, 114 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 115 .clkr.hw.init = &(const struct clk_init_data) { 116 .name = "cam_cc_pll0_out_odd", 117 .parent_hws = (const struct clk_hw*[]) { 118 &cam_cc_pll0.clkr.hw, 119 }, 120 .num_parents = 1, 121 .flags = CLK_SET_RATE_PARENT, 122 .ops = &clk_alpha_pll_postdiv_trion_ops, 123 }, 124 }; 125 126 static const struct alpha_pll_config cam_cc_pll1_config = { 127 .l = 0x1f, 128 .alpha = 0x4000, 129 .config_ctl_val = 0x20485699, 130 .config_ctl_hi_val = 0x00002267, 131 .config_ctl_hi1_val = 0x00000024, 132 .test_ctl_val = 0x00000000, 133 .test_ctl_hi_val = 0x00000000, 134 .test_ctl_hi1_val = 0x00000020, 135 .user_ctl_val = 0x00000100, 136 .user_ctl_hi_val = 0x00000805, 137 .user_ctl_hi1_val = 0x000000D0, 138 }; 139 140 static struct clk_alpha_pll cam_cc_pll1 = { 141 .offset = 0x1000, 142 .vco_table = trion_vco, 143 .num_vco = ARRAY_SIZE(trion_vco), 144 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 145 .clkr = { 146 .hw.init = &(const struct clk_init_data) { 147 .name = "cam_cc_pll1", 148 .parent_data = &(const struct clk_parent_data) { 149 .index = DT_BI_TCXO, 150 }, 151 .num_parents = 1, 152 .ops = &clk_alpha_pll_trion_ops, 153 }, 154 }, 155 }; 156 157 static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { 158 { 0x1, 2 }, 159 { } 160 }; 161 162 static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { 163 .offset = 0x1000, 164 .post_div_shift = 8, 165 .post_div_table = post_div_table_cam_cc_pll1_out_even, 166 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), 167 .width = 4, 168 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 169 .clkr.hw.init = &(const struct clk_init_data) { 170 .name = "cam_cc_pll1_out_even", 171 .parent_hws = (const struct clk_hw*[]) { 172 &cam_cc_pll1.clkr.hw, 173 }, 174 .num_parents = 1, 175 .flags = CLK_SET_RATE_PARENT, 176 .ops = &clk_alpha_pll_postdiv_trion_ops, 177 }, 178 }; 179 180 static const struct alpha_pll_config cam_cc_pll2_config = { 181 .l = 0x32, 182 .alpha = 0x0, 183 .config_ctl_val = 0x10000807, 184 .config_ctl_hi_val = 0x00000011, 185 .config_ctl_hi1_val = 0x04300142, 186 .test_ctl_val = 0x04000400, 187 .test_ctl_hi_val = 0x00004000, 188 .test_ctl_hi1_val = 0x00000000, 189 .user_ctl_val = 0x00000100, 190 .user_ctl_hi_val = 0x00000000, 191 .user_ctl_hi1_val = 0x00000000, 192 }; 193 194 static struct clk_alpha_pll cam_cc_pll2 = { 195 .offset = 0x2000, 196 .vco_table = regera_vco, 197 .num_vco = ARRAY_SIZE(regera_vco), 198 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_REGERA], 199 .clkr = { 200 .hw.init = &(const struct clk_init_data) { 201 .name = "cam_cc_pll2", 202 .parent_data = &(const struct clk_parent_data) { 203 .index = DT_BI_TCXO, 204 }, 205 .num_parents = 1, 206 .ops = &clk_alpha_pll_regera_ops, 207 }, 208 }, 209 }; 210 211 static const struct clk_div_table post_div_table_cam_cc_pll2_out_main[] = { 212 { 0x1, 2 }, 213 { } 214 }; 215 216 static struct clk_alpha_pll_postdiv cam_cc_pll2_out_main = { 217 .offset = 0x2000, 218 .post_div_shift = 8, 219 .post_div_table = post_div_table_cam_cc_pll2_out_main, 220 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_main), 221 .width = 2, 222 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_REGERA], 223 .clkr.hw.init = &(const struct clk_init_data) { 224 .name = "cam_cc_pll2_out_main", 225 .parent_hws = (const struct clk_hw*[]) { 226 &cam_cc_pll2.clkr.hw, 227 }, 228 .num_parents = 1, 229 .flags = CLK_SET_RATE_PARENT, 230 .ops = &clk_alpha_pll_postdiv_trion_ops, 231 }, 232 }; 233 234 static const struct alpha_pll_config cam_cc_pll3_config = { 235 .l = 0x29, 236 .alpha = 0xaaaa, 237 .config_ctl_val = 0x20485699, 238 .config_ctl_hi_val = 0x00002267, 239 .config_ctl_hi1_val = 0x00000024, 240 .test_ctl_val = 0x00000000, 241 .test_ctl_hi_val = 0x00000000, 242 .test_ctl_hi1_val = 0x00000020, 243 .user_ctl_val = 0x00000100, 244 .user_ctl_hi_val = 0x00000805, 245 .user_ctl_hi1_val = 0x000000D0, 246 }; 247 248 static struct clk_alpha_pll cam_cc_pll3 = { 249 .offset = 0x3000, 250 .vco_table = trion_vco, 251 .num_vco = ARRAY_SIZE(trion_vco), 252 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 253 .clkr = { 254 .hw.init = &(const struct clk_init_data) { 255 .name = "cam_cc_pll3", 256 .parent_data = &(const struct clk_parent_data) { 257 .index = DT_BI_TCXO, 258 }, 259 .num_parents = 1, 260 .ops = &clk_alpha_pll_trion_ops, 261 }, 262 }, 263 }; 264 265 static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { 266 { 0x1, 2 }, 267 { } 268 }; 269 270 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 271 .offset = 0x3000, 272 .post_div_shift = 8, 273 .post_div_table = post_div_table_cam_cc_pll3_out_even, 274 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), 275 .width = 4, 276 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 277 .clkr.hw.init = &(const struct clk_init_data) { 278 .name = "cam_cc_pll3_out_even", 279 .parent_hws = (const struct clk_hw*[]) { 280 &cam_cc_pll3.clkr.hw, 281 }, 282 .num_parents = 1, 283 .flags = CLK_SET_RATE_PARENT, 284 .ops = &clk_alpha_pll_postdiv_trion_ops, 285 }, 286 }; 287 288 static const struct alpha_pll_config cam_cc_pll4_config = { 289 .l = 0x29, 290 .alpha = 0xaaaa, 291 .config_ctl_val = 0x20485699, 292 .config_ctl_hi_val = 0x00002267, 293 .config_ctl_hi1_val = 0x00000024, 294 .test_ctl_val = 0x00000000, 295 .test_ctl_hi_val = 0x00000000, 296 .test_ctl_hi1_val = 0x00000020, 297 .user_ctl_val = 0x00000100, 298 .user_ctl_hi_val = 0x00000805, 299 .user_ctl_hi1_val = 0x000000D0, 300 }; 301 302 static struct clk_alpha_pll cam_cc_pll4 = { 303 .offset = 0x4000, 304 .vco_table = trion_vco, 305 .num_vco = ARRAY_SIZE(trion_vco), 306 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 307 .clkr = { 308 .hw.init = &(const struct clk_init_data) { 309 .name = "cam_cc_pll4", 310 .parent_data = &(const struct clk_parent_data) { 311 .index = DT_BI_TCXO, 312 }, 313 .num_parents = 1, 314 .ops = &clk_alpha_pll_trion_ops, 315 }, 316 }, 317 }; 318 319 static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { 320 { 0x1, 2 }, 321 { } 322 }; 323 324 static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { 325 .offset = 0x4000, 326 .post_div_shift = 8, 327 .post_div_table = post_div_table_cam_cc_pll4_out_even, 328 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), 329 .width = 4, 330 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 331 .clkr.hw.init = &(const struct clk_init_data) { 332 .name = "cam_cc_pll4_out_even", 333 .parent_hws = (const struct clk_hw*[]) { 334 &cam_cc_pll4.clkr.hw, 335 }, 336 .num_parents = 1, 337 .flags = CLK_SET_RATE_PARENT, 338 .ops = &clk_alpha_pll_postdiv_trion_ops, 339 }, 340 }; 341 342 static const struct parent_map cam_cc_parent_map_0[] = { 343 { P_BI_TCXO, 0 }, 344 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 345 { P_CAM_CC_PLL0_OUT_EVEN, 2 }, 346 { P_CAM_CC_PLL0_OUT_ODD, 3 }, 347 { P_CAM_CC_PLL2_OUT_MAIN, 5 }, 348 }; 349 350 static const struct clk_parent_data cam_cc_parent_data_0[] = { 351 { .index = DT_BI_TCXO }, 352 { .hw = &cam_cc_pll0.clkr.hw }, 353 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 354 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 355 { .hw = &cam_cc_pll2_out_main.clkr.hw }, 356 }; 357 358 static const struct parent_map cam_cc_parent_map_1[] = { 359 { P_BI_TCXO, 0 }, 360 { P_CAM_CC_PLL2_OUT_EARLY, 5 }, 361 }; 362 363 static const struct clk_parent_data cam_cc_parent_data_1[] = { 364 { .index = DT_BI_TCXO }, 365 { .hw = &cam_cc_pll2.clkr.hw }, 366 }; 367 368 static const struct parent_map cam_cc_parent_map_2[] = { 369 { P_BI_TCXO, 0 }, 370 { P_CAM_CC_PLL3_OUT_EVEN, 6 }, 371 }; 372 373 static const struct clk_parent_data cam_cc_parent_data_2[] = { 374 { .index = DT_BI_TCXO }, 375 { .hw = &cam_cc_pll3_out_even.clkr.hw }, 376 }; 377 378 static const struct parent_map cam_cc_parent_map_3[] = { 379 { P_BI_TCXO, 0 }, 380 { P_CAM_CC_PLL4_OUT_EVEN, 6 }, 381 }; 382 383 static const struct clk_parent_data cam_cc_parent_data_3[] = { 384 { .index = DT_BI_TCXO }, 385 { .hw = &cam_cc_pll4_out_even.clkr.hw }, 386 }; 387 388 static const struct parent_map cam_cc_parent_map_4[] = { 389 { P_BI_TCXO, 0 }, 390 { P_CAM_CC_PLL1_OUT_EVEN, 4 }, 391 }; 392 393 static const struct clk_parent_data cam_cc_parent_data_4[] = { 394 { .index = DT_BI_TCXO }, 395 { .hw = &cam_cc_pll1_out_even.clkr.hw }, 396 }; 397 398 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { 399 F(19200000, P_BI_TCXO, 1, 0, 0), 400 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 401 F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), 402 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 403 F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0), 404 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 405 { } 406 }; 407 408 static struct clk_rcg2 cam_cc_bps_clk_src = { 409 .cmd_rcgr = 0x7010, 410 .mnd_width = 0, 411 .hid_width = 5, 412 .parent_map = cam_cc_parent_map_0, 413 .freq_tbl = ftbl_cam_cc_bps_clk_src, 414 .clkr.hw.init = &(const struct clk_init_data) { 415 .name = "cam_cc_bps_clk_src", 416 .parent_data = cam_cc_parent_data_0, 417 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 418 .flags = CLK_SET_RATE_PARENT, 419 .ops = &clk_rcg2_shared_ops, 420 }, 421 }; 422 423 static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = { 424 F(19200000, P_BI_TCXO, 1, 0, 0), 425 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), 426 F(266666667, P_CAM_CC_PLL0_OUT_ODD, 1.5, 0, 0), 427 F(320000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0), 428 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 429 F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0), 430 { } 431 }; 432 433 static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = { 434 .cmd_rcgr = 0xc170, 435 .mnd_width = 0, 436 .hid_width = 5, 437 .parent_map = cam_cc_parent_map_0, 438 .freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src, 439 .clkr.hw.init = &(const struct clk_init_data) { 440 .name = "cam_cc_camnoc_axi_clk_src", 441 .parent_data = cam_cc_parent_data_0, 442 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 443 .flags = CLK_SET_RATE_PARENT, 444 .ops = &clk_rcg2_shared_ops, 445 }, 446 }; 447 448 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { 449 F(19200000, P_BI_TCXO, 1, 0, 0), 450 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 451 { } 452 }; 453 454 static struct clk_rcg2 cam_cc_cci_0_clk_src = { 455 .cmd_rcgr = 0xc108, 456 .mnd_width = 8, 457 .hid_width = 5, 458 .parent_map = cam_cc_parent_map_0, 459 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 460 .clkr.hw.init = &(const struct clk_init_data) { 461 .name = "cam_cc_cci_0_clk_src", 462 .parent_data = cam_cc_parent_data_0, 463 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 464 .flags = CLK_SET_RATE_PARENT, 465 .ops = &clk_rcg2_shared_ops, 466 }, 467 }; 468 469 static struct clk_rcg2 cam_cc_cci_1_clk_src = { 470 .cmd_rcgr = 0xc124, 471 .mnd_width = 8, 472 .hid_width = 5, 473 .parent_map = cam_cc_parent_map_0, 474 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 475 .clkr.hw.init = &(const struct clk_init_data) { 476 .name = "cam_cc_cci_1_clk_src", 477 .parent_data = cam_cc_parent_data_0, 478 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 479 .flags = CLK_SET_RATE_PARENT, 480 .ops = &clk_rcg2_shared_ops, 481 }, 482 }; 483 484 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 485 F(19200000, P_BI_TCXO, 1, 0, 0), 486 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 487 { } 488 }; 489 490 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 491 .cmd_rcgr = 0xa064, 492 .mnd_width = 0, 493 .hid_width = 5, 494 .parent_map = cam_cc_parent_map_0, 495 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 496 .clkr.hw.init = &(const struct clk_init_data) { 497 .name = "cam_cc_cphy_rx_clk_src", 498 .parent_data = cam_cc_parent_data_0, 499 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 500 .flags = CLK_SET_RATE_PARENT, 501 .ops = &clk_rcg2_shared_ops, 502 }, 503 }; 504 505 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 506 F(19200000, P_BI_TCXO, 1, 0, 0), 507 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 508 { } 509 }; 510 511 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 512 .cmd_rcgr = 0x6004, 513 .mnd_width = 0, 514 .hid_width = 5, 515 .parent_map = cam_cc_parent_map_0, 516 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 517 .clkr.hw.init = &(const struct clk_init_data) { 518 .name = "cam_cc_csi0phytimer_clk_src", 519 .parent_data = cam_cc_parent_data_0, 520 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 521 .flags = CLK_SET_RATE_PARENT, 522 .ops = &clk_rcg2_shared_ops, 523 }, 524 }; 525 526 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 527 .cmd_rcgr = 0x6028, 528 .mnd_width = 0, 529 .hid_width = 5, 530 .parent_map = cam_cc_parent_map_0, 531 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 532 .clkr.hw.init = &(const struct clk_init_data) { 533 .name = "cam_cc_csi1phytimer_clk_src", 534 .parent_data = cam_cc_parent_data_0, 535 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 536 .flags = CLK_SET_RATE_PARENT, 537 .ops = &clk_rcg2_shared_ops, 538 }, 539 }; 540 541 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 542 .cmd_rcgr = 0x604c, 543 .mnd_width = 0, 544 .hid_width = 5, 545 .parent_map = cam_cc_parent_map_0, 546 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 547 .clkr.hw.init = &(const struct clk_init_data) { 548 .name = "cam_cc_csi2phytimer_clk_src", 549 .parent_data = cam_cc_parent_data_0, 550 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 551 .flags = CLK_SET_RATE_PARENT, 552 .ops = &clk_rcg2_shared_ops, 553 }, 554 }; 555 556 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 557 .cmd_rcgr = 0x6070, 558 .mnd_width = 0, 559 .hid_width = 5, 560 .parent_map = cam_cc_parent_map_0, 561 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 562 .clkr.hw.init = &(const struct clk_init_data) { 563 .name = "cam_cc_csi3phytimer_clk_src", 564 .parent_data = cam_cc_parent_data_0, 565 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 566 .flags = CLK_SET_RATE_PARENT, 567 .ops = &clk_rcg2_shared_ops, 568 }, 569 }; 570 571 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 572 F(19200000, P_BI_TCXO, 1, 0, 0), 573 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0), 574 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 575 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 576 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), 577 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 578 { } 579 }; 580 581 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 582 .cmd_rcgr = 0x703c, 583 .mnd_width = 0, 584 .hid_width = 5, 585 .parent_map = cam_cc_parent_map_0, 586 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 587 .clkr.hw.init = &(const struct clk_init_data) { 588 .name = "cam_cc_fast_ahb_clk_src", 589 .parent_data = cam_cc_parent_data_0, 590 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 591 .flags = CLK_SET_RATE_PARENT, 592 .ops = &clk_rcg2_shared_ops, 593 }, 594 }; 595 596 static const struct freq_tbl ftbl_cam_cc_fd_core_clk_src[] = { 597 F(19200000, P_BI_TCXO, 1, 0, 0), 598 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 599 F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0), 600 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 601 { } 602 }; 603 604 static struct clk_rcg2 cam_cc_fd_core_clk_src = { 605 .cmd_rcgr = 0xc0e0, 606 .mnd_width = 0, 607 .hid_width = 5, 608 .parent_map = cam_cc_parent_map_0, 609 .freq_tbl = ftbl_cam_cc_fd_core_clk_src, 610 .clkr.hw.init = &(const struct clk_init_data) { 611 .name = "cam_cc_fd_core_clk_src", 612 .parent_data = cam_cc_parent_data_0, 613 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 614 .flags = CLK_SET_RATE_PARENT, 615 .ops = &clk_rcg2_shared_ops, 616 }, 617 }; 618 619 static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 620 F(19200000, P_BI_TCXO, 1, 0, 0), 621 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 622 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 623 { } 624 }; 625 626 static struct clk_rcg2 cam_cc_icp_clk_src = { 627 .cmd_rcgr = 0xc0b8, 628 .mnd_width = 0, 629 .hid_width = 5, 630 .parent_map = cam_cc_parent_map_0, 631 .freq_tbl = ftbl_cam_cc_icp_clk_src, 632 .clkr.hw.init = &(const struct clk_init_data) { 633 .name = "cam_cc_icp_clk_src", 634 .parent_data = cam_cc_parent_data_0, 635 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 636 .flags = CLK_SET_RATE_PARENT, 637 .ops = &clk_rcg2_shared_ops, 638 }, 639 }; 640 641 static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { 642 F(19200000, P_BI_TCXO, 1, 0, 0), 643 F(400000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 644 F(558000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 645 F(637000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 646 F(847000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 647 F(950000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 648 { } 649 }; 650 651 static struct clk_rcg2 cam_cc_ife_0_clk_src = { 652 .cmd_rcgr = 0xa010, 653 .mnd_width = 0, 654 .hid_width = 5, 655 .parent_map = cam_cc_parent_map_2, 656 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 657 .clkr.hw.init = &(const struct clk_init_data) { 658 .name = "cam_cc_ife_0_clk_src", 659 .parent_data = cam_cc_parent_data_2, 660 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 661 .flags = CLK_SET_RATE_PARENT, 662 .ops = &clk_rcg2_shared_ops, 663 }, 664 }; 665 666 static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = { 667 F(19200000, P_BI_TCXO, 1, 0, 0), 668 F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0), 669 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 670 F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0), 671 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 672 { } 673 }; 674 675 static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { 676 .cmd_rcgr = 0xa03c, 677 .mnd_width = 0, 678 .hid_width = 5, 679 .parent_map = cam_cc_parent_map_0, 680 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 681 .clkr.hw.init = &(const struct clk_init_data) { 682 .name = "cam_cc_ife_0_csid_clk_src", 683 .parent_data = cam_cc_parent_data_0, 684 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 685 .flags = CLK_SET_RATE_PARENT, 686 .ops = &clk_rcg2_shared_ops, 687 }, 688 }; 689 690 static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = { 691 F(19200000, P_BI_TCXO, 1, 0, 0), 692 F(400000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 693 F(558000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 694 F(637000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 695 F(847000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 696 F(950000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 697 { } 698 }; 699 700 static struct clk_rcg2 cam_cc_ife_1_clk_src = { 701 .cmd_rcgr = 0xb010, 702 .mnd_width = 0, 703 .hid_width = 5, 704 .parent_map = cam_cc_parent_map_3, 705 .freq_tbl = ftbl_cam_cc_ife_1_clk_src, 706 .clkr.hw.init = &(const struct clk_init_data) { 707 .name = "cam_cc_ife_1_clk_src", 708 .parent_data = cam_cc_parent_data_3, 709 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 710 .flags = CLK_SET_RATE_PARENT, 711 .ops = &clk_rcg2_shared_ops, 712 }, 713 }; 714 715 static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { 716 .cmd_rcgr = 0xb034, 717 .mnd_width = 0, 718 .hid_width = 5, 719 .parent_map = cam_cc_parent_map_0, 720 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 721 .clkr.hw.init = &(const struct clk_init_data) { 722 .name = "cam_cc_ife_1_csid_clk_src", 723 .parent_data = cam_cc_parent_data_0, 724 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 725 .flags = CLK_SET_RATE_PARENT, 726 .ops = &clk_rcg2_shared_ops, 727 }, 728 }; 729 730 static const struct freq_tbl ftbl_cam_cc_ife_lite_0_clk_src[] = { 731 F(19200000, P_BI_TCXO, 1, 0, 0), 732 F(320000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0), 733 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 734 F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0), 735 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 736 { } 737 }; 738 739 static struct clk_rcg2 cam_cc_ife_lite_0_clk_src = { 740 .cmd_rcgr = 0xc004, 741 .mnd_width = 0, 742 .hid_width = 5, 743 .parent_map = cam_cc_parent_map_0, 744 .freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src, 745 .clkr.hw.init = &(const struct clk_init_data) { 746 .name = "cam_cc_ife_lite_0_clk_src", 747 .parent_data = cam_cc_parent_data_0, 748 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 749 .flags = CLK_SET_RATE_PARENT, 750 .ops = &clk_rcg2_shared_ops, 751 }, 752 }; 753 754 static struct clk_rcg2 cam_cc_ife_lite_0_csid_clk_src = { 755 .cmd_rcgr = 0xc020, 756 .mnd_width = 0, 757 .hid_width = 5, 758 .parent_map = cam_cc_parent_map_0, 759 .freq_tbl = ftbl_cam_cc_fd_core_clk_src, 760 .clkr.hw.init = &(const struct clk_init_data) { 761 .name = "cam_cc_ife_lite_0_csid_clk_src", 762 .parent_data = cam_cc_parent_data_0, 763 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 764 .flags = CLK_SET_RATE_PARENT, 765 .ops = &clk_rcg2_shared_ops, 766 }, 767 }; 768 769 static struct clk_rcg2 cam_cc_ife_lite_1_clk_src = { 770 .cmd_rcgr = 0xc048, 771 .mnd_width = 0, 772 .hid_width = 5, 773 .parent_map = cam_cc_parent_map_0, 774 .freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src, 775 .clkr.hw.init = &(const struct clk_init_data) { 776 .name = "cam_cc_ife_lite_1_clk_src", 777 .parent_data = cam_cc_parent_data_0, 778 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 779 .flags = CLK_SET_RATE_PARENT, 780 .ops = &clk_rcg2_shared_ops, 781 }, 782 }; 783 784 static struct clk_rcg2 cam_cc_ife_lite_1_csid_clk_src = { 785 .cmd_rcgr = 0xc064, 786 .mnd_width = 0, 787 .hid_width = 5, 788 .parent_map = cam_cc_parent_map_0, 789 .freq_tbl = ftbl_cam_cc_fd_core_clk_src, 790 .clkr.hw.init = &(const struct clk_init_data) { 791 .name = "cam_cc_ife_lite_1_csid_clk_src", 792 .parent_data = cam_cc_parent_data_0, 793 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 794 .flags = CLK_SET_RATE_PARENT, 795 .ops = &clk_rcg2_shared_ops, 796 }, 797 }; 798 799 static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = { 800 F(19200000, P_BI_TCXO, 1, 0, 0), 801 F(300000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 802 F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 803 F(520000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 804 F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 805 { } 806 }; 807 808 static struct clk_rcg2 cam_cc_ipe_0_clk_src = { 809 .cmd_rcgr = 0x8010, 810 .mnd_width = 0, 811 .hid_width = 5, 812 .parent_map = cam_cc_parent_map_4, 813 .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, 814 .clkr.hw.init = &(const struct clk_init_data) { 815 .name = "cam_cc_ipe_0_clk_src", 816 .parent_data = cam_cc_parent_data_4, 817 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 818 .flags = CLK_SET_RATE_PARENT, 819 .ops = &clk_rcg2_shared_ops, 820 }, 821 }; 822 823 static struct clk_rcg2 cam_cc_jpeg_clk_src = { 824 .cmd_rcgr = 0xc08c, 825 .mnd_width = 0, 826 .hid_width = 5, 827 .parent_map = cam_cc_parent_map_0, 828 .freq_tbl = ftbl_cam_cc_bps_clk_src, 829 .clkr.hw.init = &(const struct clk_init_data) { 830 .name = "cam_cc_jpeg_clk_src", 831 .parent_data = cam_cc_parent_data_0, 832 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 833 .flags = CLK_SET_RATE_PARENT, 834 .ops = &clk_rcg2_shared_ops, 835 }, 836 }; 837 838 static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = { 839 F(19200000, P_BI_TCXO, 1, 0, 0), 840 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 841 F(240000000, P_CAM_CC_PLL2_OUT_MAIN, 2, 0, 0), 842 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 843 F(320000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0), 844 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 845 { } 846 }; 847 848 static struct clk_rcg2 cam_cc_lrme_clk_src = { 849 .cmd_rcgr = 0xc144, 850 .mnd_width = 0, 851 .hid_width = 5, 852 .parent_map = cam_cc_parent_map_0, 853 .freq_tbl = ftbl_cam_cc_lrme_clk_src, 854 .clkr.hw.init = &(const struct clk_init_data) { 855 .name = "cam_cc_lrme_clk_src", 856 .parent_data = cam_cc_parent_data_0, 857 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 858 .flags = CLK_SET_RATE_PARENT, 859 .ops = &clk_rcg2_shared_ops, 860 }, 861 }; 862 863 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 864 F(12000000, P_CAM_CC_PLL2_OUT_EARLY, 10, 1, 8), 865 F(19200000, P_BI_TCXO, 1, 0, 0), 866 F(24000000, P_CAM_CC_PLL2_OUT_EARLY, 10, 1, 4), 867 F(68571429, P_CAM_CC_PLL2_OUT_EARLY, 14, 0, 0), 868 { } 869 }; 870 871 static struct clk_rcg2 cam_cc_mclk0_clk_src = { 872 .cmd_rcgr = 0x5004, 873 .mnd_width = 8, 874 .hid_width = 5, 875 .parent_map = cam_cc_parent_map_1, 876 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 877 .clkr.hw.init = &(const struct clk_init_data) { 878 .name = "cam_cc_mclk0_clk_src", 879 .parent_data = cam_cc_parent_data_1, 880 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 881 .flags = CLK_SET_RATE_PARENT, 882 .ops = &clk_rcg2_shared_ops, 883 }, 884 }; 885 886 static struct clk_rcg2 cam_cc_mclk1_clk_src = { 887 .cmd_rcgr = 0x5024, 888 .mnd_width = 8, 889 .hid_width = 5, 890 .parent_map = cam_cc_parent_map_1, 891 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 892 .clkr.hw.init = &(const struct clk_init_data) { 893 .name = "cam_cc_mclk1_clk_src", 894 .parent_data = cam_cc_parent_data_1, 895 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 896 .flags = CLK_SET_RATE_PARENT, 897 .ops = &clk_rcg2_shared_ops, 898 }, 899 }; 900 901 static struct clk_rcg2 cam_cc_mclk2_clk_src = { 902 .cmd_rcgr = 0x5044, 903 .mnd_width = 8, 904 .hid_width = 5, 905 .parent_map = cam_cc_parent_map_1, 906 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 907 .clkr.hw.init = &(const struct clk_init_data) { 908 .name = "cam_cc_mclk2_clk_src", 909 .parent_data = cam_cc_parent_data_1, 910 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 911 .flags = CLK_SET_RATE_PARENT, 912 .ops = &clk_rcg2_shared_ops, 913 }, 914 }; 915 916 static struct clk_rcg2 cam_cc_mclk3_clk_src = { 917 .cmd_rcgr = 0x5064, 918 .mnd_width = 8, 919 .hid_width = 5, 920 .parent_map = cam_cc_parent_map_1, 921 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 922 .clkr.hw.init = &(const struct clk_init_data) { 923 .name = "cam_cc_mclk3_clk_src", 924 .parent_data = cam_cc_parent_data_1, 925 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 926 .flags = CLK_SET_RATE_PARENT, 927 .ops = &clk_rcg2_shared_ops, 928 }, 929 }; 930 931 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 932 F(19200000, P_BI_TCXO, 1, 0, 0), 933 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 934 { } 935 }; 936 937 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 938 .cmd_rcgr = 0x7058, 939 .mnd_width = 8, 940 .hid_width = 5, 941 .parent_map = cam_cc_parent_map_0, 942 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 943 .clkr.hw.init = &(const struct clk_init_data) { 944 .name = "cam_cc_slow_ahb_clk_src", 945 .parent_data = cam_cc_parent_data_0, 946 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 947 .flags = CLK_SET_RATE_PARENT, 948 .ops = &clk_rcg2_shared_ops, 949 }, 950 }; 951 952 static struct clk_branch cam_cc_bps_ahb_clk = { 953 .halt_reg = 0x7070, 954 .halt_check = BRANCH_HALT, 955 .clkr = { 956 .enable_reg = 0x7070, 957 .enable_mask = BIT(0), 958 .hw.init = &(const struct clk_init_data) { 959 .name = "cam_cc_bps_ahb_clk", 960 .parent_hws = (const struct clk_hw*[]) { 961 &cam_cc_slow_ahb_clk_src.clkr.hw, 962 }, 963 .num_parents = 1, 964 .flags = CLK_SET_RATE_PARENT, 965 .ops = &clk_branch2_ops, 966 }, 967 }, 968 }; 969 970 static struct clk_branch cam_cc_bps_areg_clk = { 971 .halt_reg = 0x7054, 972 .halt_check = BRANCH_HALT, 973 .clkr = { 974 .enable_reg = 0x7054, 975 .enable_mask = BIT(0), 976 .hw.init = &(const struct clk_init_data) { 977 .name = "cam_cc_bps_areg_clk", 978 .parent_hws = (const struct clk_hw*[]) { 979 &cam_cc_fast_ahb_clk_src.clkr.hw, 980 }, 981 .num_parents = 1, 982 .flags = CLK_SET_RATE_PARENT, 983 .ops = &clk_branch2_ops, 984 }, 985 }, 986 }; 987 988 static struct clk_branch cam_cc_bps_axi_clk = { 989 .halt_reg = 0x7038, 990 .halt_check = BRANCH_HALT, 991 .clkr = { 992 .enable_reg = 0x7038, 993 .enable_mask = BIT(0), 994 .hw.init = &(const struct clk_init_data) { 995 .name = "cam_cc_bps_axi_clk", 996 .parent_hws = (const struct clk_hw*[]) { 997 &cam_cc_camnoc_axi_clk_src.clkr.hw, 998 }, 999 .num_parents = 1, 1000 .flags = CLK_SET_RATE_PARENT, 1001 .ops = &clk_branch2_ops, 1002 }, 1003 }, 1004 }; 1005 1006 static struct clk_branch cam_cc_bps_clk = { 1007 .halt_reg = 0x7028, 1008 .halt_check = BRANCH_HALT, 1009 .clkr = { 1010 .enable_reg = 0x7028, 1011 .enable_mask = BIT(0), 1012 .hw.init = &(const struct clk_init_data) { 1013 .name = "cam_cc_bps_clk", 1014 .parent_hws = (const struct clk_hw*[]) { 1015 &cam_cc_bps_clk_src.clkr.hw, 1016 }, 1017 .num_parents = 1, 1018 .flags = CLK_SET_RATE_PARENT, 1019 .ops = &clk_branch2_ops, 1020 }, 1021 }, 1022 }; 1023 1024 static struct clk_branch cam_cc_camnoc_axi_clk = { 1025 .halt_reg = 0xc18c, 1026 .halt_check = BRANCH_HALT, 1027 .clkr = { 1028 .enable_reg = 0xc18c, 1029 .enable_mask = BIT(0), 1030 .hw.init = &(const struct clk_init_data) { 1031 .name = "cam_cc_camnoc_axi_clk", 1032 .parent_hws = (const struct clk_hw*[]) { 1033 &cam_cc_camnoc_axi_clk_src.clkr.hw, 1034 }, 1035 .num_parents = 1, 1036 .flags = CLK_SET_RATE_PARENT, 1037 .ops = &clk_branch2_ops, 1038 }, 1039 }, 1040 }; 1041 1042 static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { 1043 .halt_reg = 0xc194, 1044 .halt_check = BRANCH_HALT, 1045 .clkr = { 1046 .enable_reg = 0xc194, 1047 .enable_mask = BIT(0), 1048 .hw.init = &(const struct clk_init_data) { 1049 .name = "cam_cc_camnoc_dcd_xo_clk", 1050 .ops = &clk_branch2_ops, 1051 }, 1052 }, 1053 }; 1054 1055 static struct clk_branch cam_cc_cci_0_clk = { 1056 .halt_reg = 0xc120, 1057 .halt_check = BRANCH_HALT, 1058 .clkr = { 1059 .enable_reg = 0xc120, 1060 .enable_mask = BIT(0), 1061 .hw.init = &(const struct clk_init_data) { 1062 .name = "cam_cc_cci_0_clk", 1063 .parent_hws = (const struct clk_hw*[]) { 1064 &cam_cc_cci_0_clk_src.clkr.hw, 1065 }, 1066 .num_parents = 1, 1067 .flags = CLK_SET_RATE_PARENT, 1068 .ops = &clk_branch2_ops, 1069 }, 1070 }, 1071 }; 1072 1073 static struct clk_branch cam_cc_cci_1_clk = { 1074 .halt_reg = 0xc13c, 1075 .halt_check = BRANCH_HALT, 1076 .clkr = { 1077 .enable_reg = 0xc13c, 1078 .enable_mask = BIT(0), 1079 .hw.init = &(const struct clk_init_data) { 1080 .name = "cam_cc_cci_1_clk", 1081 .parent_hws = (const struct clk_hw*[]) { 1082 &cam_cc_cci_1_clk_src.clkr.hw, 1083 }, 1084 .num_parents = 1, 1085 .flags = CLK_SET_RATE_PARENT, 1086 .ops = &clk_branch2_ops, 1087 }, 1088 }, 1089 }; 1090 1091 static struct clk_branch cam_cc_core_ahb_clk = { 1092 .halt_reg = 0xc1c8, 1093 .halt_check = BRANCH_HALT_DELAY, 1094 .clkr = { 1095 .enable_reg = 0xc1c8, 1096 .enable_mask = BIT(0), 1097 .hw.init = &(const struct clk_init_data) { 1098 .name = "cam_cc_core_ahb_clk", 1099 .parent_hws = (const struct clk_hw*[]) { 1100 &cam_cc_slow_ahb_clk_src.clkr.hw, 1101 }, 1102 .num_parents = 1, 1103 .flags = CLK_SET_RATE_PARENT, 1104 .ops = &clk_branch2_ops, 1105 }, 1106 }, 1107 }; 1108 1109 static struct clk_branch cam_cc_cpas_ahb_clk = { 1110 .halt_reg = 0xc168, 1111 .halt_check = BRANCH_HALT, 1112 .clkr = { 1113 .enable_reg = 0xc168, 1114 .enable_mask = BIT(0), 1115 .hw.init = &(const struct clk_init_data) { 1116 .name = "cam_cc_cpas_ahb_clk", 1117 .parent_hws = (const struct clk_hw*[]) { 1118 &cam_cc_slow_ahb_clk_src.clkr.hw, 1119 }, 1120 .num_parents = 1, 1121 .flags = CLK_SET_RATE_PARENT, 1122 .ops = &clk_branch2_ops, 1123 }, 1124 }, 1125 }; 1126 1127 static struct clk_branch cam_cc_csi0phytimer_clk = { 1128 .halt_reg = 0x601c, 1129 .halt_check = BRANCH_HALT, 1130 .clkr = { 1131 .enable_reg = 0x601c, 1132 .enable_mask = BIT(0), 1133 .hw.init = &(const struct clk_init_data) { 1134 .name = "cam_cc_csi0phytimer_clk", 1135 .parent_hws = (const struct clk_hw*[]) { 1136 &cam_cc_csi0phytimer_clk_src.clkr.hw, 1137 }, 1138 .num_parents = 1, 1139 .flags = CLK_SET_RATE_PARENT, 1140 .ops = &clk_branch2_ops, 1141 }, 1142 }, 1143 }; 1144 1145 static struct clk_branch cam_cc_csi1phytimer_clk = { 1146 .halt_reg = 0x6040, 1147 .halt_check = BRANCH_HALT, 1148 .clkr = { 1149 .enable_reg = 0x6040, 1150 .enable_mask = BIT(0), 1151 .hw.init = &(const struct clk_init_data) { 1152 .name = "cam_cc_csi1phytimer_clk", 1153 .parent_hws = (const struct clk_hw*[]) { 1154 &cam_cc_csi1phytimer_clk_src.clkr.hw, 1155 }, 1156 .num_parents = 1, 1157 .flags = CLK_SET_RATE_PARENT, 1158 .ops = &clk_branch2_ops, 1159 }, 1160 }, 1161 }; 1162 1163 static struct clk_branch cam_cc_csi2phytimer_clk = { 1164 .halt_reg = 0x6064, 1165 .halt_check = BRANCH_HALT, 1166 .clkr = { 1167 .enable_reg = 0x6064, 1168 .enable_mask = BIT(0), 1169 .hw.init = &(const struct clk_init_data) { 1170 .name = "cam_cc_csi2phytimer_clk", 1171 .parent_hws = (const struct clk_hw*[]) { 1172 &cam_cc_csi2phytimer_clk_src.clkr.hw, 1173 }, 1174 .num_parents = 1, 1175 .flags = CLK_SET_RATE_PARENT, 1176 .ops = &clk_branch2_ops, 1177 }, 1178 }, 1179 }; 1180 1181 static struct clk_branch cam_cc_csi3phytimer_clk = { 1182 .halt_reg = 0x6088, 1183 .halt_check = BRANCH_HALT, 1184 .clkr = { 1185 .enable_reg = 0x6088, 1186 .enable_mask = BIT(0), 1187 .hw.init = &(const struct clk_init_data) { 1188 .name = "cam_cc_csi3phytimer_clk", 1189 .parent_hws = (const struct clk_hw*[]) { 1190 &cam_cc_csi3phytimer_clk_src.clkr.hw, 1191 }, 1192 .num_parents = 1, 1193 .flags = CLK_SET_RATE_PARENT, 1194 .ops = &clk_branch2_ops, 1195 }, 1196 }, 1197 }; 1198 1199 static struct clk_branch cam_cc_csiphy0_clk = { 1200 .halt_reg = 0x6020, 1201 .halt_check = BRANCH_HALT, 1202 .clkr = { 1203 .enable_reg = 0x6020, 1204 .enable_mask = BIT(0), 1205 .hw.init = &(const struct clk_init_data) { 1206 .name = "cam_cc_csiphy0_clk", 1207 .parent_hws = (const struct clk_hw*[]) { 1208 &cam_cc_cphy_rx_clk_src.clkr.hw, 1209 }, 1210 .num_parents = 1, 1211 .flags = CLK_SET_RATE_PARENT, 1212 .ops = &clk_branch2_ops, 1213 }, 1214 }, 1215 }; 1216 1217 static struct clk_branch cam_cc_csiphy1_clk = { 1218 .halt_reg = 0x6044, 1219 .halt_check = BRANCH_HALT, 1220 .clkr = { 1221 .enable_reg = 0x6044, 1222 .enable_mask = BIT(0), 1223 .hw.init = &(const struct clk_init_data) { 1224 .name = "cam_cc_csiphy1_clk", 1225 .parent_hws = (const struct clk_hw*[]) { 1226 &cam_cc_cphy_rx_clk_src.clkr.hw, 1227 }, 1228 .num_parents = 1, 1229 .flags = CLK_SET_RATE_PARENT, 1230 .ops = &clk_branch2_ops, 1231 }, 1232 }, 1233 }; 1234 1235 static struct clk_branch cam_cc_csiphy2_clk = { 1236 .halt_reg = 0x6068, 1237 .halt_check = BRANCH_HALT, 1238 .clkr = { 1239 .enable_reg = 0x6068, 1240 .enable_mask = BIT(0), 1241 .hw.init = &(const struct clk_init_data) { 1242 .name = "cam_cc_csiphy2_clk", 1243 .parent_hws = (const struct clk_hw*[]) { 1244 &cam_cc_cphy_rx_clk_src.clkr.hw, 1245 }, 1246 .num_parents = 1, 1247 .flags = CLK_SET_RATE_PARENT, 1248 .ops = &clk_branch2_ops, 1249 }, 1250 }, 1251 }; 1252 1253 static struct clk_branch cam_cc_csiphy3_clk = { 1254 .halt_reg = 0x608c, 1255 .halt_check = BRANCH_HALT, 1256 .clkr = { 1257 .enable_reg = 0x608c, 1258 .enable_mask = BIT(0), 1259 .hw.init = &(const struct clk_init_data) { 1260 .name = "cam_cc_csiphy3_clk", 1261 .parent_hws = (const struct clk_hw*[]) { 1262 &cam_cc_cphy_rx_clk_src.clkr.hw, 1263 }, 1264 .num_parents = 1, 1265 .flags = CLK_SET_RATE_PARENT, 1266 .ops = &clk_branch2_ops, 1267 }, 1268 }, 1269 }; 1270 1271 static struct clk_branch cam_cc_fd_core_clk = { 1272 .halt_reg = 0xc0f8, 1273 .halt_check = BRANCH_HALT, 1274 .clkr = { 1275 .enable_reg = 0xc0f8, 1276 .enable_mask = BIT(0), 1277 .hw.init = &(const struct clk_init_data) { 1278 .name = "cam_cc_fd_core_clk", 1279 .parent_hws = (const struct clk_hw*[]) { 1280 &cam_cc_fd_core_clk_src.clkr.hw, 1281 }, 1282 .num_parents = 1, 1283 .flags = CLK_SET_RATE_PARENT, 1284 .ops = &clk_branch2_ops, 1285 }, 1286 }, 1287 }; 1288 1289 static struct clk_branch cam_cc_fd_core_uar_clk = { 1290 .halt_reg = 0xc100, 1291 .halt_check = BRANCH_HALT, 1292 .clkr = { 1293 .enable_reg = 0xc100, 1294 .enable_mask = BIT(0), 1295 .hw.init = &(const struct clk_init_data) { 1296 .name = "cam_cc_fd_core_uar_clk", 1297 .parent_hws = (const struct clk_hw*[]) { 1298 &cam_cc_fd_core_clk_src.clkr.hw, 1299 }, 1300 .num_parents = 1, 1301 .flags = CLK_SET_RATE_PARENT, 1302 .ops = &clk_branch2_ops, 1303 }, 1304 }, 1305 }; 1306 1307 static struct clk_branch cam_cc_icp_ahb_clk = { 1308 .halt_reg = 0xc0d8, 1309 .halt_check = BRANCH_HALT, 1310 .clkr = { 1311 .enable_reg = 0xc0d8, 1312 .enable_mask = BIT(0), 1313 .hw.init = &(const struct clk_init_data) { 1314 .name = "cam_cc_icp_ahb_clk", 1315 .parent_hws = (const struct clk_hw*[]) { 1316 &cam_cc_slow_ahb_clk_src.clkr.hw, 1317 }, 1318 .num_parents = 1, 1319 .flags = CLK_SET_RATE_PARENT, 1320 .ops = &clk_branch2_ops, 1321 }, 1322 }, 1323 }; 1324 1325 static struct clk_branch cam_cc_icp_clk = { 1326 .halt_reg = 0xc0d0, 1327 .halt_check = BRANCH_HALT, 1328 .clkr = { 1329 .enable_reg = 0xc0d0, 1330 .enable_mask = BIT(0), 1331 .hw.init = &(const struct clk_init_data) { 1332 .name = "cam_cc_icp_clk", 1333 .parent_hws = (const struct clk_hw*[]) { 1334 &cam_cc_icp_clk_src.clkr.hw, 1335 }, 1336 .num_parents = 1, 1337 .flags = CLK_SET_RATE_PARENT, 1338 .ops = &clk_branch2_ops, 1339 }, 1340 }, 1341 }; 1342 1343 static struct clk_branch cam_cc_ife_0_axi_clk = { 1344 .halt_reg = 0xa080, 1345 .halt_check = BRANCH_HALT, 1346 .clkr = { 1347 .enable_reg = 0xa080, 1348 .enable_mask = BIT(0), 1349 .hw.init = &(const struct clk_init_data) { 1350 .name = "cam_cc_ife_0_axi_clk", 1351 .parent_hws = (const struct clk_hw*[]) { 1352 &cam_cc_camnoc_axi_clk_src.clkr.hw, 1353 }, 1354 .num_parents = 1, 1355 .flags = CLK_SET_RATE_PARENT, 1356 .ops = &clk_branch2_ops, 1357 }, 1358 }, 1359 }; 1360 1361 static struct clk_branch cam_cc_ife_0_clk = { 1362 .halt_reg = 0xa028, 1363 .halt_check = BRANCH_HALT, 1364 .clkr = { 1365 .enable_reg = 0xa028, 1366 .enable_mask = BIT(0), 1367 .hw.init = &(const struct clk_init_data) { 1368 .name = "cam_cc_ife_0_clk", 1369 .parent_hws = (const struct clk_hw*[]) { 1370 &cam_cc_ife_0_clk_src.clkr.hw, 1371 }, 1372 .num_parents = 1, 1373 .flags = CLK_SET_RATE_PARENT, 1374 .ops = &clk_branch2_ops, 1375 }, 1376 }, 1377 }; 1378 1379 static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { 1380 .halt_reg = 0xa07c, 1381 .halt_check = BRANCH_HALT, 1382 .clkr = { 1383 .enable_reg = 0xa07c, 1384 .enable_mask = BIT(0), 1385 .hw.init = &(const struct clk_init_data) { 1386 .name = "cam_cc_ife_0_cphy_rx_clk", 1387 .parent_hws = (const struct clk_hw*[]) { 1388 &cam_cc_cphy_rx_clk_src.clkr.hw, 1389 }, 1390 .num_parents = 1, 1391 .flags = CLK_SET_RATE_PARENT, 1392 .ops = &clk_branch2_ops, 1393 }, 1394 }, 1395 }; 1396 1397 static struct clk_branch cam_cc_ife_0_csid_clk = { 1398 .halt_reg = 0xa054, 1399 .halt_check = BRANCH_HALT, 1400 .clkr = { 1401 .enable_reg = 0xa054, 1402 .enable_mask = BIT(0), 1403 .hw.init = &(const struct clk_init_data) { 1404 .name = "cam_cc_ife_0_csid_clk", 1405 .parent_hws = (const struct clk_hw*[]) { 1406 &cam_cc_ife_0_csid_clk_src.clkr.hw, 1407 }, 1408 .num_parents = 1, 1409 .flags = CLK_SET_RATE_PARENT, 1410 .ops = &clk_branch2_ops, 1411 }, 1412 }, 1413 }; 1414 1415 static struct clk_branch cam_cc_ife_0_dsp_clk = { 1416 .halt_reg = 0xa038, 1417 .halt_check = BRANCH_HALT, 1418 .clkr = { 1419 .enable_reg = 0xa038, 1420 .enable_mask = BIT(0), 1421 .hw.init = &(const struct clk_init_data) { 1422 .name = "cam_cc_ife_0_dsp_clk", 1423 .parent_hws = (const struct clk_hw*[]) { 1424 &cam_cc_ife_0_clk_src.clkr.hw, 1425 }, 1426 .num_parents = 1, 1427 .flags = CLK_SET_RATE_PARENT, 1428 .ops = &clk_branch2_ops, 1429 }, 1430 }, 1431 }; 1432 1433 static struct clk_branch cam_cc_ife_1_axi_clk = { 1434 .halt_reg = 0xb058, 1435 .halt_check = BRANCH_HALT, 1436 .clkr = { 1437 .enable_reg = 0xb058, 1438 .enable_mask = BIT(0), 1439 .hw.init = &(const struct clk_init_data) { 1440 .name = "cam_cc_ife_1_axi_clk", 1441 .parent_hws = (const struct clk_hw*[]) { 1442 &cam_cc_camnoc_axi_clk_src.clkr.hw, 1443 }, 1444 .num_parents = 1, 1445 .flags = CLK_SET_RATE_PARENT, 1446 .ops = &clk_branch2_ops, 1447 }, 1448 }, 1449 }; 1450 1451 static struct clk_branch cam_cc_ife_1_clk = { 1452 .halt_reg = 0xb028, 1453 .halt_check = BRANCH_HALT, 1454 .clkr = { 1455 .enable_reg = 0xb028, 1456 .enable_mask = BIT(0), 1457 .hw.init = &(const struct clk_init_data) { 1458 .name = "cam_cc_ife_1_clk", 1459 .parent_hws = (const struct clk_hw*[]) { 1460 &cam_cc_ife_1_clk_src.clkr.hw, 1461 }, 1462 .num_parents = 1, 1463 .flags = CLK_SET_RATE_PARENT, 1464 .ops = &clk_branch2_ops, 1465 }, 1466 }, 1467 }; 1468 1469 static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { 1470 .halt_reg = 0xb054, 1471 .halt_check = BRANCH_HALT, 1472 .clkr = { 1473 .enable_reg = 0xb054, 1474 .enable_mask = BIT(0), 1475 .hw.init = &(const struct clk_init_data) { 1476 .name = "cam_cc_ife_1_cphy_rx_clk", 1477 .parent_hws = (const struct clk_hw*[]) { 1478 &cam_cc_cphy_rx_clk_src.clkr.hw, 1479 }, 1480 .num_parents = 1, 1481 .flags = CLK_SET_RATE_PARENT, 1482 .ops = &clk_branch2_ops, 1483 }, 1484 }, 1485 }; 1486 1487 static struct clk_branch cam_cc_ife_1_csid_clk = { 1488 .halt_reg = 0xb04c, 1489 .halt_check = BRANCH_HALT, 1490 .clkr = { 1491 .enable_reg = 0xb04c, 1492 .enable_mask = BIT(0), 1493 .hw.init = &(const struct clk_init_data) { 1494 .name = "cam_cc_ife_1_csid_clk", 1495 .parent_hws = (const struct clk_hw*[]) { 1496 &cam_cc_ife_1_csid_clk_src.clkr.hw, 1497 }, 1498 .num_parents = 1, 1499 .flags = CLK_SET_RATE_PARENT, 1500 .ops = &clk_branch2_ops, 1501 }, 1502 }, 1503 }; 1504 1505 static struct clk_branch cam_cc_ife_1_dsp_clk = { 1506 .halt_reg = 0xb030, 1507 .halt_check = BRANCH_HALT, 1508 .clkr = { 1509 .enable_reg = 0xb030, 1510 .enable_mask = BIT(0), 1511 .hw.init = &(const struct clk_init_data) { 1512 .name = "cam_cc_ife_1_dsp_clk", 1513 .parent_hws = (const struct clk_hw*[]) { 1514 &cam_cc_ife_1_clk_src.clkr.hw, 1515 }, 1516 .num_parents = 1, 1517 .flags = CLK_SET_RATE_PARENT, 1518 .ops = &clk_branch2_ops, 1519 }, 1520 }, 1521 }; 1522 1523 static struct clk_branch cam_cc_ife_lite_0_clk = { 1524 .halt_reg = 0xc01c, 1525 .halt_check = BRANCH_HALT, 1526 .clkr = { 1527 .enable_reg = 0xc01c, 1528 .enable_mask = BIT(0), 1529 .hw.init = &(const struct clk_init_data) { 1530 .name = "cam_cc_ife_lite_0_clk", 1531 .parent_hws = (const struct clk_hw*[]) { 1532 &cam_cc_ife_lite_0_clk_src.clkr.hw, 1533 }, 1534 .num_parents = 1, 1535 .flags = CLK_SET_RATE_PARENT, 1536 .ops = &clk_branch2_ops, 1537 }, 1538 }, 1539 }; 1540 1541 static struct clk_branch cam_cc_ife_lite_0_cphy_rx_clk = { 1542 .halt_reg = 0xc040, 1543 .halt_check = BRANCH_HALT, 1544 .clkr = { 1545 .enable_reg = 0xc040, 1546 .enable_mask = BIT(0), 1547 .hw.init = &(const struct clk_init_data) { 1548 .name = "cam_cc_ife_lite_0_cphy_rx_clk", 1549 .parent_hws = (const struct clk_hw*[]) { 1550 &cam_cc_cphy_rx_clk_src.clkr.hw, 1551 }, 1552 .num_parents = 1, 1553 .flags = CLK_SET_RATE_PARENT, 1554 .ops = &clk_branch2_ops, 1555 }, 1556 }, 1557 }; 1558 1559 static struct clk_branch cam_cc_ife_lite_0_csid_clk = { 1560 .halt_reg = 0xc038, 1561 .halt_check = BRANCH_HALT, 1562 .clkr = { 1563 .enable_reg = 0xc038, 1564 .enable_mask = BIT(0), 1565 .hw.init = &(const struct clk_init_data) { 1566 .name = "cam_cc_ife_lite_0_csid_clk", 1567 .parent_hws = (const struct clk_hw*[]) { 1568 &cam_cc_ife_lite_0_csid_clk_src.clkr.hw, 1569 }, 1570 .num_parents = 1, 1571 .flags = CLK_SET_RATE_PARENT, 1572 .ops = &clk_branch2_ops, 1573 }, 1574 }, 1575 }; 1576 1577 static struct clk_branch cam_cc_ife_lite_1_clk = { 1578 .halt_reg = 0xc060, 1579 .halt_check = BRANCH_HALT, 1580 .clkr = { 1581 .enable_reg = 0xc060, 1582 .enable_mask = BIT(0), 1583 .hw.init = &(const struct clk_init_data) { 1584 .name = "cam_cc_ife_lite_1_clk", 1585 .parent_hws = (const struct clk_hw*[]) { 1586 &cam_cc_ife_lite_1_clk_src.clkr.hw, 1587 }, 1588 .num_parents = 1, 1589 .flags = CLK_SET_RATE_PARENT, 1590 .ops = &clk_branch2_ops, 1591 }, 1592 }, 1593 }; 1594 1595 static struct clk_branch cam_cc_ife_lite_1_cphy_rx_clk = { 1596 .halt_reg = 0xc084, 1597 .halt_check = BRANCH_HALT, 1598 .clkr = { 1599 .enable_reg = 0xc084, 1600 .enable_mask = BIT(0), 1601 .hw.init = &(const struct clk_init_data) { 1602 .name = "cam_cc_ife_lite_1_cphy_rx_clk", 1603 .parent_hws = (const struct clk_hw*[]) { 1604 &cam_cc_cphy_rx_clk_src.clkr.hw, 1605 }, 1606 .num_parents = 1, 1607 .flags = CLK_SET_RATE_PARENT, 1608 .ops = &clk_branch2_ops, 1609 }, 1610 }, 1611 }; 1612 1613 static struct clk_branch cam_cc_ife_lite_1_csid_clk = { 1614 .halt_reg = 0xc07c, 1615 .halt_check = BRANCH_HALT, 1616 .clkr = { 1617 .enable_reg = 0xc07c, 1618 .enable_mask = BIT(0), 1619 .hw.init = &(const struct clk_init_data) { 1620 .name = "cam_cc_ife_lite_1_csid_clk", 1621 .parent_hws = (const struct clk_hw*[]) { 1622 &cam_cc_ife_lite_1_csid_clk_src.clkr.hw, 1623 }, 1624 .num_parents = 1, 1625 .flags = CLK_SET_RATE_PARENT, 1626 .ops = &clk_branch2_ops, 1627 }, 1628 }, 1629 }; 1630 1631 static struct clk_branch cam_cc_ipe_0_ahb_clk = { 1632 .halt_reg = 0x8040, 1633 .halt_check = BRANCH_HALT, 1634 .clkr = { 1635 .enable_reg = 0x8040, 1636 .enable_mask = BIT(0), 1637 .hw.init = &(const struct clk_init_data) { 1638 .name = "cam_cc_ipe_0_ahb_clk", 1639 .parent_hws = (const struct clk_hw*[]) { 1640 &cam_cc_slow_ahb_clk_src.clkr.hw, 1641 }, 1642 .num_parents = 1, 1643 .flags = CLK_SET_RATE_PARENT, 1644 .ops = &clk_branch2_ops, 1645 }, 1646 }, 1647 }; 1648 1649 static struct clk_branch cam_cc_ipe_0_areg_clk = { 1650 .halt_reg = 0x803c, 1651 .halt_check = BRANCH_HALT, 1652 .clkr = { 1653 .enable_reg = 0x803c, 1654 .enable_mask = BIT(0), 1655 .hw.init = &(const struct clk_init_data) { 1656 .name = "cam_cc_ipe_0_areg_clk", 1657 .parent_hws = (const struct clk_hw*[]) { 1658 &cam_cc_fast_ahb_clk_src.clkr.hw, 1659 }, 1660 .num_parents = 1, 1661 .flags = CLK_SET_RATE_PARENT, 1662 .ops = &clk_branch2_ops, 1663 }, 1664 }, 1665 }; 1666 1667 static struct clk_branch cam_cc_ipe_0_axi_clk = { 1668 .halt_reg = 0x8038, 1669 .halt_check = BRANCH_HALT, 1670 .clkr = { 1671 .enable_reg = 0x8038, 1672 .enable_mask = BIT(0), 1673 .hw.init = &(const struct clk_init_data) { 1674 .name = "cam_cc_ipe_0_axi_clk", 1675 .parent_hws = (const struct clk_hw*[]) { 1676 &cam_cc_camnoc_axi_clk_src.clkr.hw, 1677 }, 1678 .num_parents = 1, 1679 .flags = CLK_SET_RATE_PARENT, 1680 .ops = &clk_branch2_ops, 1681 }, 1682 }, 1683 }; 1684 1685 static struct clk_branch cam_cc_ipe_0_clk = { 1686 .halt_reg = 0x8028, 1687 .halt_check = BRANCH_HALT, 1688 .clkr = { 1689 .enable_reg = 0x8028, 1690 .enable_mask = BIT(0), 1691 .hw.init = &(const struct clk_init_data) { 1692 .name = "cam_cc_ipe_0_clk", 1693 .parent_hws = (const struct clk_hw*[]) { 1694 &cam_cc_ipe_0_clk_src.clkr.hw, 1695 }, 1696 .num_parents = 1, 1697 .flags = CLK_SET_RATE_PARENT, 1698 .ops = &clk_branch2_ops, 1699 }, 1700 }, 1701 }; 1702 1703 static struct clk_branch cam_cc_ipe_1_ahb_clk = { 1704 .halt_reg = 0x9028, 1705 .halt_check = BRANCH_HALT, 1706 .clkr = { 1707 .enable_reg = 0x9028, 1708 .enable_mask = BIT(0), 1709 .hw.init = &(const struct clk_init_data) { 1710 .name = "cam_cc_ipe_1_ahb_clk", 1711 .parent_hws = (const struct clk_hw*[]) { 1712 &cam_cc_slow_ahb_clk_src.clkr.hw, 1713 }, 1714 .num_parents = 1, 1715 .flags = CLK_SET_RATE_PARENT, 1716 .ops = &clk_branch2_ops, 1717 }, 1718 }, 1719 }; 1720 1721 static struct clk_branch cam_cc_ipe_1_areg_clk = { 1722 .halt_reg = 0x9024, 1723 .halt_check = BRANCH_HALT, 1724 .clkr = { 1725 .enable_reg = 0x9024, 1726 .enable_mask = BIT(0), 1727 .hw.init = &(const struct clk_init_data) { 1728 .name = "cam_cc_ipe_1_areg_clk", 1729 .parent_hws = (const struct clk_hw*[]) { 1730 &cam_cc_fast_ahb_clk_src.clkr.hw, 1731 }, 1732 .num_parents = 1, 1733 .flags = CLK_SET_RATE_PARENT, 1734 .ops = &clk_branch2_ops, 1735 }, 1736 }, 1737 }; 1738 1739 static struct clk_branch cam_cc_ipe_1_axi_clk = { 1740 .halt_reg = 0x9020, 1741 .halt_check = BRANCH_HALT, 1742 .clkr = { 1743 .enable_reg = 0x9020, 1744 .enable_mask = BIT(0), 1745 .hw.init = &(const struct clk_init_data) { 1746 .name = "cam_cc_ipe_1_axi_clk", 1747 .parent_hws = (const struct clk_hw*[]) { 1748 &cam_cc_camnoc_axi_clk_src.clkr.hw, 1749 }, 1750 .num_parents = 1, 1751 .flags = CLK_SET_RATE_PARENT, 1752 .ops = &clk_branch2_ops, 1753 }, 1754 }, 1755 }; 1756 1757 static struct clk_branch cam_cc_ipe_1_clk = { 1758 .halt_reg = 0x9010, 1759 .halt_check = BRANCH_HALT, 1760 .clkr = { 1761 .enable_reg = 0x9010, 1762 .enable_mask = BIT(0), 1763 .hw.init = &(const struct clk_init_data) { 1764 .name = "cam_cc_ipe_1_clk", 1765 .parent_hws = (const struct clk_hw*[]) { 1766 &cam_cc_ipe_0_clk_src.clkr.hw, 1767 }, 1768 .num_parents = 1, 1769 .flags = CLK_SET_RATE_PARENT, 1770 .ops = &clk_branch2_ops, 1771 }, 1772 }, 1773 }; 1774 1775 static struct clk_branch cam_cc_jpeg_clk = { 1776 .halt_reg = 0xc0a4, 1777 .halt_check = BRANCH_HALT, 1778 .clkr = { 1779 .enable_reg = 0xc0a4, 1780 .enable_mask = BIT(0), 1781 .hw.init = &(const struct clk_init_data) { 1782 .name = "cam_cc_jpeg_clk", 1783 .parent_hws = (const struct clk_hw*[]) { 1784 &cam_cc_jpeg_clk_src.clkr.hw, 1785 }, 1786 .num_parents = 1, 1787 .flags = CLK_SET_RATE_PARENT, 1788 .ops = &clk_branch2_ops, 1789 }, 1790 }, 1791 }; 1792 1793 static struct clk_branch cam_cc_lrme_clk = { 1794 .halt_reg = 0xc15c, 1795 .halt_check = BRANCH_HALT, 1796 .clkr = { 1797 .enable_reg = 0xc15c, 1798 .enable_mask = BIT(0), 1799 .hw.init = &(const struct clk_init_data) { 1800 .name = "cam_cc_lrme_clk", 1801 .parent_hws = (const struct clk_hw*[]) { 1802 &cam_cc_lrme_clk_src.clkr.hw, 1803 }, 1804 .num_parents = 1, 1805 .flags = CLK_SET_RATE_PARENT, 1806 .ops = &clk_branch2_ops, 1807 }, 1808 }, 1809 }; 1810 1811 static struct clk_branch cam_cc_mclk0_clk = { 1812 .halt_reg = 0x501c, 1813 .halt_check = BRANCH_HALT, 1814 .clkr = { 1815 .enable_reg = 0x501c, 1816 .enable_mask = BIT(0), 1817 .hw.init = &(const struct clk_init_data) { 1818 .name = "cam_cc_mclk0_clk", 1819 .parent_hws = (const struct clk_hw*[]) { 1820 &cam_cc_mclk0_clk_src.clkr.hw, 1821 }, 1822 .num_parents = 1, 1823 .flags = CLK_SET_RATE_PARENT, 1824 .ops = &clk_branch2_ops, 1825 }, 1826 }, 1827 }; 1828 1829 static struct clk_branch cam_cc_mclk1_clk = { 1830 .halt_reg = 0x503c, 1831 .halt_check = BRANCH_HALT, 1832 .clkr = { 1833 .enable_reg = 0x503c, 1834 .enable_mask = BIT(0), 1835 .hw.init = &(const struct clk_init_data) { 1836 .name = "cam_cc_mclk1_clk", 1837 .parent_hws = (const struct clk_hw*[]) { 1838 &cam_cc_mclk1_clk_src.clkr.hw, 1839 }, 1840 .num_parents = 1, 1841 .flags = CLK_SET_RATE_PARENT, 1842 .ops = &clk_branch2_ops, 1843 }, 1844 }, 1845 }; 1846 1847 static struct clk_branch cam_cc_mclk2_clk = { 1848 .halt_reg = 0x505c, 1849 .halt_check = BRANCH_HALT, 1850 .clkr = { 1851 .enable_reg = 0x505c, 1852 .enable_mask = BIT(0), 1853 .hw.init = &(const struct clk_init_data) { 1854 .name = "cam_cc_mclk2_clk", 1855 .parent_hws = (const struct clk_hw*[]) { 1856 &cam_cc_mclk2_clk_src.clkr.hw, 1857 }, 1858 .num_parents = 1, 1859 .flags = CLK_SET_RATE_PARENT, 1860 .ops = &clk_branch2_ops, 1861 }, 1862 }, 1863 }; 1864 1865 static struct clk_branch cam_cc_mclk3_clk = { 1866 .halt_reg = 0x507c, 1867 .halt_check = BRANCH_HALT, 1868 .clkr = { 1869 .enable_reg = 0x507c, 1870 .enable_mask = BIT(0), 1871 .hw.init = &(const struct clk_init_data) { 1872 .name = "cam_cc_mclk3_clk", 1873 .parent_hws = (const struct clk_hw*[]) { 1874 &cam_cc_mclk3_clk_src.clkr.hw, 1875 }, 1876 .num_parents = 1, 1877 .flags = CLK_SET_RATE_PARENT, 1878 .ops = &clk_branch2_ops, 1879 }, 1880 }, 1881 }; 1882 1883 static struct gdsc titan_top_gdsc = { 1884 .gdscr = 0xc1bc, 1885 .en_rest_wait_val = 0x2, 1886 .en_few_wait_val = 0x2, 1887 .clk_dis_wait_val = 0xf, 1888 .pd = { 1889 .name = "titan_top_gdsc", 1890 }, 1891 .pwrsts = PWRSTS_OFF_ON, 1892 .flags = POLL_CFG_GDSCR, 1893 }; 1894 1895 static struct gdsc bps_gdsc = { 1896 .gdscr = 0x7004, 1897 .en_rest_wait_val = 0x2, 1898 .en_few_wait_val = 0x2, 1899 .clk_dis_wait_val = 0xf, 1900 .pd = { 1901 .name = "bps_gdsc", 1902 }, 1903 .pwrsts = PWRSTS_OFF_ON, 1904 .parent = &titan_top_gdsc.pd, 1905 .flags = POLL_CFG_GDSCR, 1906 }; 1907 1908 static struct gdsc ife_0_gdsc = { 1909 .gdscr = 0xa004, 1910 .en_rest_wait_val = 0x2, 1911 .en_few_wait_val = 0x2, 1912 .clk_dis_wait_val = 0xf, 1913 .pd = { 1914 .name = "ife_0_gdsc", 1915 }, 1916 .pwrsts = PWRSTS_OFF_ON, 1917 .parent = &titan_top_gdsc.pd, 1918 .flags = POLL_CFG_GDSCR, 1919 }; 1920 1921 static struct gdsc ife_1_gdsc = { 1922 .gdscr = 0xb004, 1923 .en_rest_wait_val = 0x2, 1924 .en_few_wait_val = 0x2, 1925 .clk_dis_wait_val = 0xf, 1926 .pd = { 1927 .name = "ife_1_gdsc", 1928 }, 1929 .pwrsts = PWRSTS_OFF_ON, 1930 .parent = &titan_top_gdsc.pd, 1931 .flags = POLL_CFG_GDSCR, 1932 }; 1933 1934 static struct gdsc ipe_0_gdsc = { 1935 .gdscr = 0x8004, 1936 .en_rest_wait_val = 0x2, 1937 .en_few_wait_val = 0x2, 1938 .clk_dis_wait_val = 0xf, 1939 .pd = { 1940 .name = "ipe_0_gdsc", 1941 }, 1942 .pwrsts = PWRSTS_OFF_ON, 1943 .parent = &titan_top_gdsc.pd, 1944 .flags = POLL_CFG_GDSCR, 1945 }; 1946 1947 static struct gdsc ipe_1_gdsc = { 1948 .gdscr = 0x9004, 1949 .en_rest_wait_val = 0x2, 1950 .en_few_wait_val = 0x2, 1951 .clk_dis_wait_val = 0xf, 1952 .pd = { 1953 .name = "ipe_1_gdsc", 1954 }, 1955 .pwrsts = PWRSTS_OFF_ON, 1956 .parent = &titan_top_gdsc.pd, 1957 .flags = POLL_CFG_GDSCR, 1958 }; 1959 1960 static struct clk_regmap *cam_cc_sm8150_clocks[] = { 1961 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 1962 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, 1963 [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, 1964 [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 1965 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, 1966 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 1967 [CAM_CC_PLL2_OUT_MAIN] = &cam_cc_pll2_out_main.clkr, 1968 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 1969 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, 1970 [CAM_CC_PLL4] = &cam_cc_pll4.clkr, 1971 [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, 1972 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, 1973 [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr, 1974 [CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr, 1975 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, 1976 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, 1977 [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr, 1978 [CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr, 1979 [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, 1980 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, 1981 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, 1982 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, 1983 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, 1984 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 1985 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 1986 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 1987 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 1988 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 1989 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 1990 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 1991 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 1992 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 1993 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 1994 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 1995 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 1996 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 1997 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 1998 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 1999 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 2000 [CAM_CC_FD_CORE_CLK] = &cam_cc_fd_core_clk.clkr, 2001 [CAM_CC_FD_CORE_CLK_SRC] = &cam_cc_fd_core_clk_src.clkr, 2002 [CAM_CC_FD_CORE_UAR_CLK] = &cam_cc_fd_core_uar_clk.clkr, 2003 [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr, 2004 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 2005 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 2006 [CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr, 2007 [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, 2008 [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, 2009 [CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr, 2010 [CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr, 2011 [CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr, 2012 [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, 2013 [CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr, 2014 [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, 2015 [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, 2016 [CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr, 2017 [CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr, 2018 [CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr, 2019 [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, 2020 [CAM_CC_IFE_LITE_0_CLK] = &cam_cc_ife_lite_0_clk.clkr, 2021 [CAM_CC_IFE_LITE_0_CLK_SRC] = &cam_cc_ife_lite_0_clk_src.clkr, 2022 [CAM_CC_IFE_LITE_0_CPHY_RX_CLK] = &cam_cc_ife_lite_0_cphy_rx_clk.clkr, 2023 [CAM_CC_IFE_LITE_0_CSID_CLK] = &cam_cc_ife_lite_0_csid_clk.clkr, 2024 [CAM_CC_IFE_LITE_0_CSID_CLK_SRC] = &cam_cc_ife_lite_0_csid_clk_src.clkr, 2025 [CAM_CC_IFE_LITE_1_CLK] = &cam_cc_ife_lite_1_clk.clkr, 2026 [CAM_CC_IFE_LITE_1_CLK_SRC] = &cam_cc_ife_lite_1_clk_src.clkr, 2027 [CAM_CC_IFE_LITE_1_CPHY_RX_CLK] = &cam_cc_ife_lite_1_cphy_rx_clk.clkr, 2028 [CAM_CC_IFE_LITE_1_CSID_CLK] = &cam_cc_ife_lite_1_csid_clk.clkr, 2029 [CAM_CC_IFE_LITE_1_CSID_CLK_SRC] = &cam_cc_ife_lite_1_csid_clk_src.clkr, 2030 [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr, 2031 [CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr, 2032 [CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr, 2033 [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr, 2034 [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr, 2035 [CAM_CC_IPE_1_AHB_CLK] = &cam_cc_ipe_1_ahb_clk.clkr, 2036 [CAM_CC_IPE_1_AREG_CLK] = &cam_cc_ipe_1_areg_clk.clkr, 2037 [CAM_CC_IPE_1_AXI_CLK] = &cam_cc_ipe_1_axi_clk.clkr, 2038 [CAM_CC_IPE_1_CLK] = &cam_cc_ipe_1_clk.clkr, 2039 [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, 2040 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, 2041 [CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr, 2042 [CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr, 2043 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 2044 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 2045 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 2046 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 2047 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 2048 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 2049 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 2050 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 2051 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 2052 }; 2053 2054 static struct gdsc *cam_cc_sm8150_gdscs[] = { 2055 [TITAN_TOP_GDSC] = &titan_top_gdsc, 2056 [BPS_GDSC] = &bps_gdsc, 2057 [IFE_0_GDSC] = &ife_0_gdsc, 2058 [IFE_1_GDSC] = &ife_1_gdsc, 2059 [IPE_0_GDSC] = &ipe_0_gdsc, 2060 [IPE_1_GDSC] = &ipe_1_gdsc, 2061 }; 2062 2063 static const struct qcom_reset_map cam_cc_sm8150_resets[] = { 2064 [CAM_CC_BPS_BCR] = { 0x7000 }, 2065 [CAM_CC_CAMNOC_BCR] = { 0xc16c }, 2066 [CAM_CC_CCI_BCR] = { 0xc104 }, 2067 [CAM_CC_CPAS_BCR] = { 0xc164 }, 2068 [CAM_CC_CSI0PHY_BCR] = { 0x6000 }, 2069 [CAM_CC_CSI1PHY_BCR] = { 0x6024 }, 2070 [CAM_CC_CSI2PHY_BCR] = { 0x6048 }, 2071 [CAM_CC_CSI3PHY_BCR] = { 0x606c }, 2072 [CAM_CC_FD_BCR] = { 0xc0dc }, 2073 [CAM_CC_ICP_BCR] = { 0xc0b4 }, 2074 [CAM_CC_IFE_0_BCR] = { 0xa000 }, 2075 [CAM_CC_IFE_1_BCR] = { 0xb000 }, 2076 [CAM_CC_IFE_LITE_0_BCR] = { 0xc000 }, 2077 [CAM_CC_IFE_LITE_1_BCR] = { 0xc044 }, 2078 [CAM_CC_IPE_0_BCR] = { 0x8000 }, 2079 [CAM_CC_IPE_1_BCR] = { 0x9000 }, 2080 [CAM_CC_JPEG_BCR] = { 0xc088 }, 2081 [CAM_CC_LRME_BCR] = { 0xc140 }, 2082 [CAM_CC_MCLK0_BCR] = { 0x5000 }, 2083 [CAM_CC_MCLK1_BCR] = { 0x5020 }, 2084 [CAM_CC_MCLK2_BCR] = { 0x5040 }, 2085 [CAM_CC_MCLK3_BCR] = { 0x5060 }, 2086 }; 2087 2088 static const struct regmap_config cam_cc_sm8150_regmap_config = { 2089 .reg_bits = 32, 2090 .reg_stride = 4, 2091 .val_bits = 32, 2092 .max_register = 0xe004, 2093 .fast_io = true, 2094 }; 2095 2096 static const struct qcom_cc_desc cam_cc_sm8150_desc = { 2097 .config = &cam_cc_sm8150_regmap_config, 2098 .clks = cam_cc_sm8150_clocks, 2099 .num_clks = ARRAY_SIZE(cam_cc_sm8150_clocks), 2100 .resets = cam_cc_sm8150_resets, 2101 .num_resets = ARRAY_SIZE(cam_cc_sm8150_resets), 2102 .gdscs = cam_cc_sm8150_gdscs, 2103 .num_gdscs = ARRAY_SIZE(cam_cc_sm8150_gdscs), 2104 }; 2105 2106 static const struct of_device_id cam_cc_sm8150_match_table[] = { 2107 { .compatible = "qcom,sm8150-camcc" }, 2108 { } 2109 }; 2110 MODULE_DEVICE_TABLE(of, cam_cc_sm8150_match_table); 2111 2112 static int cam_cc_sm8150_probe(struct platform_device *pdev) 2113 { 2114 struct regmap *regmap; 2115 int ret; 2116 2117 ret = devm_pm_runtime_enable(&pdev->dev); 2118 if (ret) 2119 return ret; 2120 2121 ret = pm_runtime_resume_and_get(&pdev->dev); 2122 if (ret) 2123 return ret; 2124 2125 regmap = qcom_cc_map(pdev, &cam_cc_sm8150_desc); 2126 if (IS_ERR(regmap)) { 2127 pm_runtime_put(&pdev->dev); 2128 return PTR_ERR(regmap); 2129 } 2130 2131 clk_trion_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); 2132 clk_trion_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); 2133 clk_regera_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); 2134 clk_trion_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); 2135 clk_trion_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); 2136 2137 /* Keep the critical clock always-on */ 2138 qcom_branch_set_clk_en(regmap, 0xc1e4); /* cam_cc_gdsc_clk */ 2139 2140 ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8150_desc, regmap); 2141 2142 pm_runtime_put(&pdev->dev); 2143 2144 return ret; 2145 } 2146 2147 static struct platform_driver cam_cc_sm8150_driver = { 2148 .probe = cam_cc_sm8150_probe, 2149 .driver = { 2150 .name = "camcc-sm8150", 2151 .of_match_table = cam_cc_sm8150_match_table, 2152 }, 2153 }; 2154 2155 module_platform_driver(cam_cc_sm8150_driver); 2156 2157 MODULE_DESCRIPTION("QTI CAM_CC SM8150 Driver"); 2158 MODULE_LICENSE("GPL"); 2159