1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2018, 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,sm7150-camcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "common.h" 19 #include "gdsc.h" 20 21 enum { 22 DT_BI_TCXO, 23 DT_BI_TCXO_AO, 24 DT_CHIP_SLEEP_CLK, 25 }; 26 27 enum { 28 P_BI_TCXO, 29 P_BI_TCXO_MX, 30 P_CAMCC_PLL0_OUT_EVEN, 31 P_CAMCC_PLL0_OUT_MAIN, 32 P_CAMCC_PLL0_OUT_ODD, 33 P_CAMCC_PLL1_OUT_EVEN, 34 P_CAMCC_PLL2_OUT_AUX, 35 P_CAMCC_PLL2_OUT_EARLY, 36 P_CAMCC_PLL2_OUT_MAIN, 37 P_CAMCC_PLL3_OUT_EVEN, 38 P_CAMCC_PLL4_OUT_EVEN, 39 P_CHIP_SLEEP_CLK, 40 }; 41 42 static const struct pll_vco fabia_vco[] = { 43 { 249600000, 2000000000, 0 }, 44 }; 45 46 /* 1200MHz configuration */ 47 static const struct alpha_pll_config camcc_pll0_config = { 48 .l = 0x3e, 49 .alpha = 0x8000, 50 .post_div_mask = 0xff << 8, 51 .post_div_val = 0x31 << 8, 52 .test_ctl_val = 0x40000000, 53 }; 54 55 static struct clk_alpha_pll camcc_pll0 = { 56 .offset = 0x0, 57 .vco_table = fabia_vco, 58 .num_vco = ARRAY_SIZE(fabia_vco), 59 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 60 .clkr = { 61 .hw.init = &(const struct clk_init_data) { 62 .name = "camcc_pll0", 63 .parent_data = &(const struct clk_parent_data) { 64 .index = DT_BI_TCXO, 65 }, 66 .num_parents = 1, 67 .ops = &clk_alpha_pll_fabia_ops, 68 }, 69 }, 70 }; 71 72 static struct clk_fixed_factor camcc_pll0_out_even = { 73 .mult = 1, 74 .div = 2, 75 .hw.init = &(const struct clk_init_data) { 76 .name = "camcc_pll0_out_even", 77 .parent_hws = (const struct clk_hw*[]) { 78 &camcc_pll0.clkr.hw, 79 }, 80 .num_parents = 1, 81 .ops = &clk_fixed_factor_ops, 82 }, 83 }; 84 85 static struct clk_fixed_factor camcc_pll0_out_odd = { 86 .mult = 1, 87 .div = 3, 88 .hw.init = &(const struct clk_init_data) { 89 .name = "camcc_pll0_out_odd", 90 .parent_hws = (const struct clk_hw*[]) { 91 &camcc_pll0.clkr.hw, 92 }, 93 .num_parents = 1, 94 .ops = &clk_fixed_factor_ops, 95 }, 96 }; 97 98 /* 680MHz configuration */ 99 static const struct alpha_pll_config camcc_pll1_config = { 100 .l = 0x23, 101 .alpha = 0x6aaa, 102 .post_div_mask = 0xf << 8, 103 .post_div_val = 0x1 << 8, 104 .test_ctl_val = 0x40000000, 105 }; 106 107 static struct clk_alpha_pll camcc_pll1 = { 108 .offset = 0x1000, 109 .vco_table = fabia_vco, 110 .num_vco = ARRAY_SIZE(fabia_vco), 111 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 112 .clkr = { 113 .hw.init = &(const struct clk_init_data) { 114 .name = "camcc_pll1", 115 .parent_data = &(const struct clk_parent_data) { 116 .index = DT_BI_TCXO, 117 }, 118 .num_parents = 1, 119 .ops = &clk_alpha_pll_fabia_ops, 120 }, 121 }, 122 }; 123 124 static struct clk_fixed_factor camcc_pll1_out_even = { 125 .mult = 1, 126 .div = 2, 127 .hw.init = &(const struct clk_init_data) { 128 .name = "camcc_pll1_out_even", 129 .parent_hws = (const struct clk_hw*[]) { 130 &camcc_pll1.clkr.hw, 131 }, 132 .num_parents = 1, 133 .flags = CLK_SET_RATE_PARENT, 134 .ops = &clk_fixed_factor_ops, 135 }, 136 }; 137 138 /* 1920MHz configuration */ 139 static const struct alpha_pll_config camcc_pll2_config = { 140 .l = 0x64, 141 .config_ctl_hi_val = 0x400003d6, 142 .config_ctl_val = 0x20000954, 143 .user_ctl_val = 0x0000030b, 144 }; 145 146 static struct clk_alpha_pll camcc_pll2 = { 147 .offset = 0x2000, 148 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 149 .clkr = { 150 .hw.init = &(const struct clk_init_data) { 151 .name = "camcc_pll2", 152 .parent_data = &(const struct clk_parent_data) { 153 .index = DT_BI_TCXO, 154 }, 155 .num_parents = 1, 156 .ops = &clk_alpha_pll_agera_ops, 157 }, 158 }, 159 }; 160 161 static struct clk_fixed_factor camcc_pll2_out_early = { 162 .mult = 1, 163 .div = 2, 164 .hw.init = &(const struct clk_init_data) { 165 .name = "camcc_pll2_out_early", 166 .parent_hws = (const struct clk_hw*[]) { 167 &camcc_pll2.clkr.hw, 168 }, 169 .num_parents = 1, 170 .ops = &clk_fixed_factor_ops, 171 }, 172 }; 173 174 static struct clk_alpha_pll_postdiv camcc_pll2_out_aux = { 175 .offset = 0x2000, 176 .post_div_shift = 8, 177 .width = 2, 178 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 179 .clkr.hw.init = &(const struct clk_init_data) { 180 .name = "camcc_pll2_out_aux", 181 .parent_hws = (const struct clk_hw*[]) { 182 &camcc_pll2.clkr.hw, 183 }, 184 .num_parents = 1, 185 .flags = CLK_SET_RATE_PARENT, 186 .ops = &clk_alpha_pll_postdiv_ops, 187 }, 188 }; 189 190 static struct clk_alpha_pll_postdiv camcc_pll2_out_main = { 191 .offset = 0x2000, 192 .post_div_shift = 8, 193 .width = 2, 194 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 195 .clkr.hw.init = &(const struct clk_init_data) { 196 .name = "camcc_pll2_out_main", 197 .parent_hws = (const struct clk_hw*[]) { 198 &camcc_pll2.clkr.hw, 199 }, 200 .num_parents = 1, 201 .flags = CLK_SET_RATE_PARENT, 202 .ops = &clk_alpha_pll_postdiv_ops, 203 }, 204 }; 205 206 /* 760MHz configuration */ 207 static const struct alpha_pll_config camcc_pll3_config = { 208 .l = 0x27, 209 .alpha = 0x9555, 210 .post_div_mask = 0xf << 8, 211 .post_div_val = 0x1 << 8, 212 .test_ctl_val = 0x40000000, 213 }; 214 215 static struct clk_alpha_pll camcc_pll3 = { 216 .offset = 0x3000, 217 .vco_table = fabia_vco, 218 .num_vco = ARRAY_SIZE(fabia_vco), 219 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 220 .clkr = { 221 .hw.init = &(const struct clk_init_data) { 222 .name = "camcc_pll3", 223 .parent_data = &(const struct clk_parent_data) { 224 .index = DT_BI_TCXO, 225 }, 226 .num_parents = 1, 227 .ops = &clk_alpha_pll_fabia_ops, 228 }, 229 }, 230 }; 231 232 static struct clk_fixed_factor camcc_pll3_out_even = { 233 .mult = 1, 234 .div = 2, 235 .hw.init = &(const struct clk_init_data) { 236 .name = "camcc_pll3_out_even", 237 .parent_hws = (const struct clk_hw*[]) { 238 &camcc_pll3.clkr.hw, 239 }, 240 .num_parents = 1, 241 .flags = CLK_SET_RATE_PARENT, 242 .ops = &clk_fixed_factor_ops, 243 }, 244 }; 245 246 static struct clk_alpha_pll camcc_pll4 = { 247 .offset = 0x4000, 248 .vco_table = fabia_vco, 249 .num_vco = ARRAY_SIZE(fabia_vco), 250 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 251 .clkr = { 252 .hw.init = &(const struct clk_init_data) { 253 .name = "camcc_pll4", 254 .parent_data = &(const struct clk_parent_data) { 255 .index = DT_BI_TCXO, 256 }, 257 .num_parents = 1, 258 .ops = &clk_alpha_pll_fabia_ops, 259 }, 260 }, 261 }; 262 263 static struct clk_fixed_factor camcc_pll4_out_even = { 264 .mult = 1, 265 .div = 2, 266 .hw.init = &(const struct clk_init_data) { 267 .name = "camcc_pll4_out_even", 268 .parent_hws = (const struct clk_hw*[]) { 269 &camcc_pll4.clkr.hw, 270 }, 271 .num_parents = 1, 272 .flags = CLK_SET_RATE_PARENT, 273 .ops = &clk_fixed_factor_ops, 274 }, 275 }; 276 277 static const struct parent_map camcc_parent_map_0[] = { 278 { P_BI_TCXO, 0 }, 279 { P_CAMCC_PLL0_OUT_MAIN, 1 }, 280 { P_CAMCC_PLL0_OUT_EVEN, 2 }, 281 { P_CAMCC_PLL0_OUT_ODD, 3 }, 282 { P_CAMCC_PLL2_OUT_MAIN, 5 }, 283 }; 284 285 static const struct clk_parent_data camcc_parent_data_0[] = { 286 { .index = DT_BI_TCXO }, 287 { .hw = &camcc_pll0.clkr.hw }, 288 { .hw = &camcc_pll0_out_even.hw }, 289 { .hw = &camcc_pll0_out_odd.hw }, 290 { .hw = &camcc_pll2_out_main.clkr.hw }, 291 }; 292 293 static const struct parent_map camcc_parent_map_1[] = { 294 { P_BI_TCXO, 0 }, 295 { P_CAMCC_PLL0_OUT_MAIN, 1 }, 296 { P_CAMCC_PLL0_OUT_EVEN, 2 }, 297 { P_CAMCC_PLL0_OUT_ODD, 3 }, 298 { P_CAMCC_PLL1_OUT_EVEN, 4 }, 299 { P_CAMCC_PLL2_OUT_EARLY, 5 }, 300 }; 301 302 static const struct clk_parent_data camcc_parent_data_1[] = { 303 { .index = DT_BI_TCXO }, 304 { .hw = &camcc_pll0.clkr.hw }, 305 { .hw = &camcc_pll0_out_even.hw }, 306 { .hw = &camcc_pll0_out_odd.hw }, 307 { .hw = &camcc_pll1_out_even.hw }, 308 { .hw = &camcc_pll2_out_early.hw }, 309 }; 310 311 static const struct parent_map camcc_parent_map_2[] = { 312 { P_BI_TCXO_MX, 0 }, 313 { P_CAMCC_PLL2_OUT_AUX, 5 }, 314 }; 315 316 static const struct clk_parent_data camcc_parent_data_2[] = { 317 { .index = DT_BI_TCXO }, 318 { .hw = &camcc_pll2_out_aux.clkr.hw }, 319 }; 320 321 static const struct parent_map camcc_parent_map_3[] = { 322 { P_BI_TCXO, 0 }, 323 { P_CAMCC_PLL0_OUT_MAIN, 1 }, 324 { P_CAMCC_PLL0_OUT_EVEN, 2 }, 325 { P_CAMCC_PLL0_OUT_ODD, 3 }, 326 { P_CAMCC_PLL2_OUT_EARLY, 5 }, 327 { P_CAMCC_PLL4_OUT_EVEN, 6 }, 328 }; 329 330 static const struct clk_parent_data camcc_parent_data_3[] = { 331 { .index = DT_BI_TCXO }, 332 { .hw = &camcc_pll0.clkr.hw }, 333 { .hw = &camcc_pll0_out_even.hw }, 334 { .hw = &camcc_pll0_out_odd.hw }, 335 { .hw = &camcc_pll2_out_early.hw }, 336 { .hw = &camcc_pll4_out_even.hw }, 337 }; 338 339 static const struct parent_map camcc_parent_map_4[] = { 340 { P_BI_TCXO, 0 }, 341 { P_CAMCC_PLL3_OUT_EVEN, 6 }, 342 }; 343 344 static const struct clk_parent_data camcc_parent_data_4[] = { 345 { .index = DT_BI_TCXO }, 346 { .hw = &camcc_pll3_out_even.hw }, 347 }; 348 349 static const struct parent_map camcc_parent_map_5[] = { 350 { P_BI_TCXO, 0 }, 351 { P_CAMCC_PLL4_OUT_EVEN, 6 }, 352 }; 353 354 static const struct clk_parent_data camcc_parent_data_5[] = { 355 { .index = DT_BI_TCXO }, 356 { .hw = &camcc_pll4_out_even.hw }, 357 }; 358 359 static const struct parent_map camcc_parent_map_6[] = { 360 { P_BI_TCXO, 0 }, 361 { P_CAMCC_PLL1_OUT_EVEN, 4 }, 362 }; 363 364 static const struct clk_parent_data camcc_parent_data_6[] = { 365 { .index = DT_BI_TCXO }, 366 { .hw = &camcc_pll1_out_even.hw }, 367 }; 368 369 static const struct parent_map camcc_parent_map_7[] = { 370 { P_CHIP_SLEEP_CLK, 0 }, 371 }; 372 373 static const struct clk_parent_data camcc_parent_data_7[] = { 374 { .index = DT_CHIP_SLEEP_CLK }, 375 }; 376 377 static const struct parent_map camcc_parent_map_8[] = { 378 { P_BI_TCXO, 0 }, 379 { P_CAMCC_PLL0_OUT_ODD, 3 }, 380 }; 381 382 static const struct clk_parent_data camcc_parent_data_8[] = { 383 { .index = DT_BI_TCXO }, 384 { .hw = &camcc_pll0_out_odd.hw }, 385 }; 386 387 static const struct parent_map camcc_parent_map_9[] = { 388 { P_BI_TCXO, 0 }, 389 }; 390 391 static const struct clk_parent_data camcc_parent_data_9[] = { 392 { .index = DT_BI_TCXO_AO }, 393 }; 394 395 static const struct freq_tbl ftbl_camcc_bps_clk_src[] = { 396 F(19200000, P_BI_TCXO, 1, 0, 0), 397 F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0), 398 F(200000000, P_CAMCC_PLL0_OUT_ODD, 2, 0, 0), 399 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 400 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0), 401 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 402 { } 403 }; 404 405 static struct clk_rcg2 camcc_bps_clk_src = { 406 .cmd_rcgr = 0x7010, 407 .mnd_width = 0, 408 .hid_width = 5, 409 .parent_map = camcc_parent_map_0, 410 .freq_tbl = ftbl_camcc_bps_clk_src, 411 .clkr.hw.init = &(const struct clk_init_data) { 412 .name = "camcc_bps_clk_src", 413 .parent_data = camcc_parent_data_0, 414 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 415 .ops = &clk_rcg2_shared_ops, 416 }, 417 }; 418 419 static const struct freq_tbl ftbl_camcc_camnoc_axi_clk_src[] = { 420 F(19200000, P_BI_TCXO, 1, 0, 0), 421 F(150000000, P_CAMCC_PLL0_OUT_EVEN, 4, 0, 0), 422 F(240000000, P_CAMCC_PLL2_OUT_MAIN, 2, 0, 0), 423 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0), 424 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), 425 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0), 426 { } 427 }; 428 429 static struct clk_rcg2 camcc_camnoc_axi_clk_src = { 430 .cmd_rcgr = 0xc12c, 431 .mnd_width = 0, 432 .hid_width = 5, 433 .parent_map = camcc_parent_map_0, 434 .freq_tbl = ftbl_camcc_camnoc_axi_clk_src, 435 .clkr.hw.init = &(const struct clk_init_data) { 436 .name = "camcc_camnoc_axi_clk_src", 437 .parent_data = camcc_parent_data_0, 438 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 439 .ops = &clk_rcg2_shared_ops, 440 }, 441 }; 442 443 static const struct freq_tbl ftbl_camcc_cci_0_clk_src[] = { 444 F(19200000, P_BI_TCXO, 1, 0, 0), 445 F(37500000, P_CAMCC_PLL0_OUT_EVEN, 16, 0, 0), 446 { } 447 }; 448 449 static struct clk_rcg2 camcc_cci_0_clk_src = { 450 .cmd_rcgr = 0xc0c4, 451 .mnd_width = 8, 452 .hid_width = 5, 453 .parent_map = camcc_parent_map_0, 454 .freq_tbl = ftbl_camcc_cci_0_clk_src, 455 .clkr.hw.init = &(const struct clk_init_data) { 456 .name = "camcc_cci_0_clk_src", 457 .parent_data = camcc_parent_data_0, 458 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 459 .ops = &clk_rcg2_ops, 460 }, 461 }; 462 463 static struct clk_rcg2 camcc_cci_1_clk_src = { 464 .cmd_rcgr = 0xc0e0, 465 .mnd_width = 8, 466 .hid_width = 5, 467 .parent_map = camcc_parent_map_0, 468 .freq_tbl = ftbl_camcc_cci_0_clk_src, 469 .clkr.hw.init = &(const struct clk_init_data) { 470 .name = "camcc_cci_1_clk_src", 471 .parent_data = camcc_parent_data_0, 472 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 473 .ops = &clk_rcg2_ops, 474 }, 475 }; 476 477 static const struct freq_tbl ftbl_camcc_cphy_rx_clk_src[] = { 478 F(19200000, P_BI_TCXO, 1, 0, 0), 479 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0), 480 F(384000000, P_CAMCC_PLL2_OUT_EARLY, 2.5, 0, 0), 481 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), 482 { } 483 }; 484 485 static struct clk_rcg2 camcc_cphy_rx_clk_src = { 486 .cmd_rcgr = 0xa064, 487 .mnd_width = 0, 488 .hid_width = 5, 489 .parent_map = camcc_parent_map_1, 490 .freq_tbl = ftbl_camcc_cphy_rx_clk_src, 491 .clkr.hw.init = &(const struct clk_init_data) { 492 .name = "camcc_cphy_rx_clk_src", 493 .parent_data = camcc_parent_data_1, 494 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 495 .ops = &clk_rcg2_ops, 496 }, 497 }; 498 499 static const struct freq_tbl ftbl_camcc_csi0phytimer_clk_src[] = { 500 F(19200000, P_BI_TCXO, 1, 0, 0), 501 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0), 502 { } 503 }; 504 505 static struct clk_rcg2 camcc_csi0phytimer_clk_src = { 506 .cmd_rcgr = 0x6004, 507 .mnd_width = 0, 508 .hid_width = 5, 509 .parent_map = camcc_parent_map_0, 510 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, 511 .clkr.hw.init = &(const struct clk_init_data) { 512 .name = "camcc_csi0phytimer_clk_src", 513 .parent_data = camcc_parent_data_0, 514 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 515 .ops = &clk_rcg2_ops, 516 }, 517 }; 518 519 static struct clk_rcg2 camcc_csi1phytimer_clk_src = { 520 .cmd_rcgr = 0x6028, 521 .mnd_width = 0, 522 .hid_width = 5, 523 .parent_map = camcc_parent_map_0, 524 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, 525 .clkr.hw.init = &(const struct clk_init_data) { 526 .name = "camcc_csi1phytimer_clk_src", 527 .parent_data = camcc_parent_data_0, 528 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 529 .ops = &clk_rcg2_ops, 530 }, 531 }; 532 533 static struct clk_rcg2 camcc_csi2phytimer_clk_src = { 534 .cmd_rcgr = 0x604c, 535 .mnd_width = 0, 536 .hid_width = 5, 537 .parent_map = camcc_parent_map_0, 538 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, 539 .clkr.hw.init = &(const struct clk_init_data) { 540 .name = "camcc_csi2phytimer_clk_src", 541 .parent_data = camcc_parent_data_0, 542 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 543 .ops = &clk_rcg2_ops, 544 }, 545 }; 546 547 static struct clk_rcg2 camcc_csi3phytimer_clk_src = { 548 .cmd_rcgr = 0x6070, 549 .mnd_width = 0, 550 .hid_width = 5, 551 .parent_map = camcc_parent_map_0, 552 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, 553 .clkr.hw.init = &(const struct clk_init_data) { 554 .name = "camcc_csi3phytimer_clk_src", 555 .parent_data = camcc_parent_data_0, 556 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 557 .ops = &clk_rcg2_ops, 558 }, 559 }; 560 561 static const struct freq_tbl ftbl_camcc_fast_ahb_clk_src[] = { 562 F(19200000, P_BI_TCXO, 1, 0, 0), 563 F(50000000, P_CAMCC_PLL0_OUT_EVEN, 12, 0, 0), 564 F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0), 565 F(200000000, P_CAMCC_PLL0_OUT_EVEN, 3, 0, 0), 566 F(300000000, P_CAMCC_PLL0_OUT_MAIN, 4, 0, 0), 567 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), 568 { } 569 }; 570 571 static struct clk_rcg2 camcc_fast_ahb_clk_src = { 572 .cmd_rcgr = 0x703c, 573 .mnd_width = 0, 574 .hid_width = 5, 575 .parent_map = camcc_parent_map_0, 576 .freq_tbl = ftbl_camcc_fast_ahb_clk_src, 577 .clkr.hw.init = &(const struct clk_init_data) { 578 .name = "camcc_fast_ahb_clk_src", 579 .parent_data = camcc_parent_data_0, 580 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 581 .ops = &clk_rcg2_ops, 582 }, 583 }; 584 585 static const struct freq_tbl ftbl_camcc_fd_core_clk_src[] = { 586 F(19200000, P_BI_TCXO, 1, 0, 0), 587 F(380000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), 588 F(384000000, P_CAMCC_PLL2_OUT_EARLY, 2.5, 0, 0), 589 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), 590 F(480000000, P_CAMCC_PLL2_OUT_EARLY, 2, 0, 0), 591 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 592 { } 593 }; 594 595 static struct clk_rcg2 camcc_fd_core_clk_src = { 596 .cmd_rcgr = 0xc09c, 597 .mnd_width = 0, 598 .hid_width = 5, 599 .parent_map = camcc_parent_map_3, 600 .freq_tbl = ftbl_camcc_fd_core_clk_src, 601 .clkr.hw.init = &(const struct clk_init_data) { 602 .name = "camcc_fd_core_clk_src", 603 .parent_data = camcc_parent_data_3, 604 .num_parents = ARRAY_SIZE(camcc_parent_data_3), 605 .flags = CLK_SET_RATE_PARENT, 606 .ops = &clk_rcg2_shared_ops, 607 }, 608 }; 609 610 static const struct freq_tbl ftbl_camcc_icp_clk_src[] = { 611 F(19200000, P_BI_TCXO, 1, 0, 0), 612 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 613 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 614 { } 615 }; 616 617 static struct clk_rcg2 camcc_icp_clk_src = { 618 .cmd_rcgr = 0xc074, 619 .mnd_width = 0, 620 .hid_width = 5, 621 .parent_map = camcc_parent_map_0, 622 .freq_tbl = ftbl_camcc_icp_clk_src, 623 .clkr.hw.init = &(const struct clk_init_data) { 624 .name = "camcc_icp_clk_src", 625 .parent_data = camcc_parent_data_0, 626 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 627 .ops = &clk_rcg2_shared_ops, 628 }, 629 }; 630 631 static const struct freq_tbl ftbl_camcc_ife_0_clk_src[] = { 632 F(19200000, P_BI_TCXO, 1, 0, 0), 633 F(380000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), 634 F(510000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), 635 F(637000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), 636 F(760000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), 637 { } 638 }; 639 640 static struct clk_rcg2 camcc_ife_0_clk_src = { 641 .cmd_rcgr = 0xa010, 642 .mnd_width = 0, 643 .hid_width = 5, 644 .parent_map = camcc_parent_map_4, 645 .freq_tbl = ftbl_camcc_ife_0_clk_src, 646 .clkr.hw.init = &(const struct clk_init_data) { 647 .name = "camcc_ife_0_clk_src", 648 .parent_data = camcc_parent_data_4, 649 .num_parents = ARRAY_SIZE(camcc_parent_data_4), 650 .flags = CLK_SET_RATE_PARENT, 651 .ops = &clk_rcg2_shared_ops, 652 }, 653 }; 654 655 static const struct freq_tbl ftbl_camcc_ife_0_csid_clk_src[] = { 656 F(19200000, P_BI_TCXO, 1, 0, 0), 657 F(75000000, P_CAMCC_PLL0_OUT_EVEN, 8, 0, 0), 658 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0), 659 F(384000000, P_CAMCC_PLL2_OUT_EARLY, 2.5, 0, 0), 660 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), 661 { } 662 }; 663 664 static struct clk_rcg2 camcc_ife_0_csid_clk_src = { 665 .cmd_rcgr = 0xa03c, 666 .mnd_width = 0, 667 .hid_width = 5, 668 .parent_map = camcc_parent_map_1, 669 .freq_tbl = ftbl_camcc_ife_0_csid_clk_src, 670 .clkr.hw.init = &(const struct clk_init_data) { 671 .name = "camcc_ife_0_csid_clk_src", 672 .parent_data = camcc_parent_data_1, 673 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 674 .ops = &clk_rcg2_shared_ops, 675 }, 676 }; 677 678 static const struct freq_tbl ftbl_camcc_ife_1_clk_src[] = { 679 F(19200000, P_BI_TCXO, 1, 0, 0), 680 F(380000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), 681 F(510000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), 682 F(637000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), 683 F(760000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), 684 { } 685 }; 686 687 static struct clk_rcg2 camcc_ife_1_clk_src = { 688 .cmd_rcgr = 0xb010, 689 .mnd_width = 0, 690 .hid_width = 5, 691 .parent_map = camcc_parent_map_5, 692 .freq_tbl = ftbl_camcc_ife_1_clk_src, 693 .clkr.hw.init = &(const struct clk_init_data) { 694 .name = "camcc_ife_1_clk_src", 695 .parent_data = camcc_parent_data_5, 696 .num_parents = ARRAY_SIZE(camcc_parent_data_5), 697 .flags = CLK_SET_RATE_PARENT, 698 .ops = &clk_rcg2_shared_ops, 699 }, 700 }; 701 702 static struct clk_rcg2 camcc_ife_1_csid_clk_src = { 703 .cmd_rcgr = 0xb034, 704 .mnd_width = 0, 705 .hid_width = 5, 706 .parent_map = camcc_parent_map_1, 707 .freq_tbl = ftbl_camcc_ife_0_csid_clk_src, 708 .clkr.hw.init = &(const struct clk_init_data) { 709 .name = "camcc_ife_1_csid_clk_src", 710 .parent_data = camcc_parent_data_1, 711 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 712 .ops = &clk_rcg2_shared_ops, 713 }, 714 }; 715 716 static const struct freq_tbl ftbl_camcc_ife_lite_clk_src[] = { 717 F(19200000, P_BI_TCXO, 1, 0, 0), 718 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0), 719 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 720 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0), 721 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 722 { } 723 }; 724 725 static struct clk_rcg2 camcc_ife_lite_clk_src = { 726 .cmd_rcgr = 0xc004, 727 .mnd_width = 0, 728 .hid_width = 5, 729 .parent_map = camcc_parent_map_0, 730 .freq_tbl = ftbl_camcc_ife_lite_clk_src, 731 .clkr.hw.init = &(const struct clk_init_data) { 732 .name = "camcc_ife_lite_clk_src", 733 .parent_data = camcc_parent_data_0, 734 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 735 .ops = &clk_rcg2_ops, 736 }, 737 }; 738 739 static struct clk_rcg2 camcc_ife_lite_csid_clk_src = { 740 .cmd_rcgr = 0xc020, 741 .mnd_width = 0, 742 .hid_width = 5, 743 .parent_map = camcc_parent_map_1, 744 .freq_tbl = ftbl_camcc_cphy_rx_clk_src, 745 .clkr.hw.init = &(const struct clk_init_data) { 746 .name = "camcc_ife_lite_csid_clk_src", 747 .parent_data = camcc_parent_data_1, 748 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 749 .ops = &clk_rcg2_shared_ops, 750 }, 751 }; 752 753 static const struct freq_tbl ftbl_camcc_ipe_0_clk_src[] = { 754 F(19200000, P_BI_TCXO, 1, 0, 0), 755 F(340000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), 756 F(430000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), 757 F(520000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), 758 F(600000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), 759 { } 760 }; 761 762 static struct clk_rcg2 camcc_ipe_0_clk_src = { 763 .cmd_rcgr = 0x8010, 764 .mnd_width = 0, 765 .hid_width = 5, 766 .parent_map = camcc_parent_map_6, 767 .freq_tbl = ftbl_camcc_ipe_0_clk_src, 768 .clkr.hw.init = &(const struct clk_init_data) { 769 .name = "camcc_ipe_0_clk_src", 770 .parent_data = camcc_parent_data_6, 771 .num_parents = ARRAY_SIZE(camcc_parent_data_6), 772 .flags = CLK_SET_RATE_PARENT, 773 .ops = &clk_rcg2_shared_ops, 774 }, 775 }; 776 777 static struct clk_rcg2 camcc_jpeg_clk_src = { 778 .cmd_rcgr = 0xc048, 779 .mnd_width = 0, 780 .hid_width = 5, 781 .parent_map = camcc_parent_map_0, 782 .freq_tbl = ftbl_camcc_bps_clk_src, 783 .clkr.hw.init = &(const struct clk_init_data) { 784 .name = "camcc_jpeg_clk_src", 785 .parent_data = camcc_parent_data_0, 786 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 787 .ops = &clk_rcg2_shared_ops, 788 }, 789 }; 790 791 static const struct freq_tbl ftbl_camcc_lrme_clk_src[] = { 792 F(19200000, P_BI_TCXO, 1, 0, 0), 793 F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0), 794 F(240000000, P_CAMCC_PLL2_OUT_MAIN, 2, 0, 0), 795 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0), 796 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0), 797 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), 798 { } 799 }; 800 801 static struct clk_rcg2 camcc_lrme_clk_src = { 802 .cmd_rcgr = 0xc100, 803 .mnd_width = 0, 804 .hid_width = 5, 805 .parent_map = camcc_parent_map_0, 806 .freq_tbl = ftbl_camcc_lrme_clk_src, 807 .clkr.hw.init = &(const struct clk_init_data) { 808 .name = "camcc_lrme_clk_src", 809 .parent_data = camcc_parent_data_0, 810 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 811 .ops = &clk_rcg2_shared_ops, 812 }, 813 }; 814 815 static const struct freq_tbl ftbl_camcc_mclk0_clk_src[] = { 816 F(19200000, P_BI_TCXO_MX, 1, 0, 0), 817 F(24000000, P_CAMCC_PLL2_OUT_AUX, 1, 1, 20), 818 F(34285714, P_CAMCC_PLL2_OUT_AUX, 14, 0, 0), 819 { } 820 }; 821 822 static struct clk_rcg2 camcc_mclk0_clk_src = { 823 .cmd_rcgr = 0x5004, 824 .mnd_width = 8, 825 .hid_width = 5, 826 .parent_map = camcc_parent_map_2, 827 .freq_tbl = ftbl_camcc_mclk0_clk_src, 828 .clkr.hw.init = &(const struct clk_init_data) { 829 .name = "camcc_mclk0_clk_src", 830 .parent_data = camcc_parent_data_2, 831 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 832 .ops = &clk_rcg2_ops, 833 }, 834 }; 835 836 static struct clk_rcg2 camcc_mclk1_clk_src = { 837 .cmd_rcgr = 0x5024, 838 .mnd_width = 8, 839 .hid_width = 5, 840 .parent_map = camcc_parent_map_2, 841 .freq_tbl = ftbl_camcc_mclk0_clk_src, 842 .clkr.hw.init = &(const struct clk_init_data) { 843 .name = "camcc_mclk1_clk_src", 844 .parent_data = camcc_parent_data_2, 845 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 846 .ops = &clk_rcg2_ops, 847 }, 848 }; 849 850 static struct clk_rcg2 camcc_mclk2_clk_src = { 851 .cmd_rcgr = 0x5044, 852 .mnd_width = 8, 853 .hid_width = 5, 854 .parent_map = camcc_parent_map_2, 855 .freq_tbl = ftbl_camcc_mclk0_clk_src, 856 .clkr.hw.init = &(const struct clk_init_data) { 857 .name = "camcc_mclk2_clk_src", 858 .parent_data = camcc_parent_data_2, 859 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 860 .ops = &clk_rcg2_ops, 861 }, 862 }; 863 864 static struct clk_rcg2 camcc_mclk3_clk_src = { 865 .cmd_rcgr = 0x5064, 866 .mnd_width = 8, 867 .hid_width = 5, 868 .parent_map = camcc_parent_map_2, 869 .freq_tbl = ftbl_camcc_mclk0_clk_src, 870 .clkr.hw.init = &(const struct clk_init_data) { 871 .name = "camcc_mclk3_clk_src", 872 .parent_data = camcc_parent_data_2, 873 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 874 .ops = &clk_rcg2_ops, 875 }, 876 }; 877 878 static const struct freq_tbl ftbl_camcc_sleep_clk_src[] = { 879 F(32000, P_CHIP_SLEEP_CLK, 1, 0, 0), 880 { } 881 }; 882 883 static struct clk_rcg2 camcc_sleep_clk_src = { 884 .cmd_rcgr = 0xc1a4, 885 .mnd_width = 0, 886 .hid_width = 5, 887 .parent_map = camcc_parent_map_7, 888 .freq_tbl = ftbl_camcc_sleep_clk_src, 889 .clkr.hw.init = &(const struct clk_init_data) { 890 .name = "camcc_sleep_clk_src", 891 .parent_data = camcc_parent_data_7, 892 .num_parents = ARRAY_SIZE(camcc_parent_data_7), 893 .ops = &clk_rcg2_ops, 894 }, 895 }; 896 897 static const struct freq_tbl ftbl_camcc_slow_ahb_clk_src[] = { 898 F(19200000, P_BI_TCXO, 1, 0, 0), 899 F(80000000, P_CAMCC_PLL0_OUT_ODD, 5, 0, 0), 900 { } 901 }; 902 903 static struct clk_rcg2 camcc_slow_ahb_clk_src = { 904 .cmd_rcgr = 0x7058, 905 .mnd_width = 0, 906 .hid_width = 5, 907 .parent_map = camcc_parent_map_8, 908 .freq_tbl = ftbl_camcc_slow_ahb_clk_src, 909 .clkr.hw.init = &(const struct clk_init_data) { 910 .name = "camcc_slow_ahb_clk_src", 911 .parent_data = camcc_parent_data_8, 912 .num_parents = ARRAY_SIZE(camcc_parent_data_8), 913 .ops = &clk_rcg2_shared_ops, 914 }, 915 }; 916 917 static const struct freq_tbl ftbl_camcc_xo_clk_src[] = { 918 F(19200000, P_BI_TCXO, 1, 0, 0), 919 { } 920 }; 921 922 static struct clk_rcg2 camcc_xo_clk_src = { 923 .cmd_rcgr = 0xc188, 924 .mnd_width = 0, 925 .hid_width = 5, 926 .parent_map = camcc_parent_map_9, 927 .freq_tbl = ftbl_camcc_xo_clk_src, 928 .clkr.hw.init = &(const struct clk_init_data) { 929 .name = "camcc_xo_clk_src", 930 .parent_data = camcc_parent_data_9, 931 .num_parents = ARRAY_SIZE(camcc_parent_data_9), 932 .ops = &clk_rcg2_ops, 933 }, 934 }; 935 936 static struct clk_branch camcc_bps_ahb_clk = { 937 .halt_reg = 0x7070, 938 .halt_check = BRANCH_HALT, 939 .clkr = { 940 .enable_reg = 0x7070, 941 .enable_mask = BIT(0), 942 .hw.init = &(const struct clk_init_data) { 943 .name = "camcc_bps_ahb_clk", 944 .parent_hws = (const struct clk_hw*[]) { 945 &camcc_slow_ahb_clk_src.clkr.hw, 946 }, 947 .num_parents = 1, 948 .flags = CLK_SET_RATE_PARENT, 949 .ops = &clk_branch2_ops, 950 }, 951 }, 952 }; 953 954 static struct clk_branch camcc_bps_areg_clk = { 955 .halt_reg = 0x7054, 956 .halt_check = BRANCH_HALT, 957 .clkr = { 958 .enable_reg = 0x7054, 959 .enable_mask = BIT(0), 960 .hw.init = &(const struct clk_init_data) { 961 .name = "camcc_bps_areg_clk", 962 .parent_hws = (const struct clk_hw*[]) { 963 &camcc_fast_ahb_clk_src.clkr.hw, 964 }, 965 .num_parents = 1, 966 .flags = CLK_SET_RATE_PARENT, 967 .ops = &clk_branch2_ops, 968 }, 969 }, 970 }; 971 972 static struct clk_branch camcc_bps_axi_clk = { 973 .halt_reg = 0x7038, 974 .halt_check = BRANCH_HALT, 975 .clkr = { 976 .enable_reg = 0x7038, 977 .enable_mask = BIT(0), 978 .hw.init = &(const struct clk_init_data) { 979 .name = "camcc_bps_axi_clk", 980 .parent_hws = (const struct clk_hw*[]) { 981 &camcc_camnoc_axi_clk_src.clkr.hw, 982 }, 983 .num_parents = 1, 984 .flags = CLK_SET_RATE_PARENT, 985 .ops = &clk_branch2_ops, 986 }, 987 }, 988 }; 989 990 static struct clk_branch camcc_bps_clk = { 991 .halt_reg = 0x7028, 992 .halt_check = BRANCH_HALT, 993 .clkr = { 994 .enable_reg = 0x7028, 995 .enable_mask = BIT(0), 996 .hw.init = &(const struct clk_init_data) { 997 .name = "camcc_bps_clk", 998 .parent_hws = (const struct clk_hw*[]) { 999 &camcc_bps_clk_src.clkr.hw, 1000 }, 1001 .num_parents = 1, 1002 .flags = CLK_SET_RATE_PARENT, 1003 .ops = &clk_branch2_ops, 1004 }, 1005 }, 1006 }; 1007 1008 static struct clk_branch camcc_camnoc_axi_clk = { 1009 .halt_reg = 0xc148, 1010 .halt_check = BRANCH_HALT, 1011 .clkr = { 1012 .enable_reg = 0xc148, 1013 .enable_mask = BIT(0), 1014 .hw.init = &(const struct clk_init_data) { 1015 .name = "camcc_camnoc_axi_clk", 1016 .parent_hws = (const struct clk_hw*[]) { 1017 &camcc_camnoc_axi_clk_src.clkr.hw, 1018 }, 1019 .num_parents = 1, 1020 .flags = CLK_SET_RATE_PARENT, 1021 .ops = &clk_branch2_ops, 1022 }, 1023 }, 1024 }; 1025 1026 static struct clk_branch camcc_camnoc_dcd_xo_clk = { 1027 .halt_reg = 0xc150, 1028 .halt_check = BRANCH_HALT, 1029 .clkr = { 1030 .enable_reg = 0xc150, 1031 .enable_mask = BIT(0), 1032 .hw.init = &(const struct clk_init_data) { 1033 .name = "camcc_camnoc_dcd_xo_clk", 1034 .parent_hws = (const struct clk_hw*[]) { 1035 &camcc_xo_clk_src.clkr.hw, 1036 }, 1037 .num_parents = 1, 1038 .flags = CLK_SET_RATE_PARENT, 1039 .ops = &clk_branch2_ops, 1040 }, 1041 }, 1042 }; 1043 1044 static struct clk_branch camcc_cci_0_clk = { 1045 .halt_reg = 0xc0dc, 1046 .halt_check = BRANCH_HALT, 1047 .clkr = { 1048 .enable_reg = 0xc0dc, 1049 .enable_mask = BIT(0), 1050 .hw.init = &(const struct clk_init_data) { 1051 .name = "camcc_cci_0_clk", 1052 .parent_hws = (const struct clk_hw*[]) { 1053 &camcc_cci_0_clk_src.clkr.hw, 1054 }, 1055 .num_parents = 1, 1056 .flags = CLK_SET_RATE_PARENT, 1057 .ops = &clk_branch2_ops, 1058 }, 1059 }, 1060 }; 1061 1062 static struct clk_branch camcc_cci_1_clk = { 1063 .halt_reg = 0xc0f8, 1064 .halt_check = BRANCH_HALT, 1065 .clkr = { 1066 .enable_reg = 0xc0f8, 1067 .enable_mask = BIT(0), 1068 .hw.init = &(const struct clk_init_data) { 1069 .name = "camcc_cci_1_clk", 1070 .parent_hws = (const struct clk_hw*[]) { 1071 &camcc_cci_1_clk_src.clkr.hw, 1072 }, 1073 .num_parents = 1, 1074 .flags = CLK_SET_RATE_PARENT, 1075 .ops = &clk_branch2_ops, 1076 }, 1077 }, 1078 }; 1079 1080 static struct clk_branch camcc_core_ahb_clk = { 1081 .halt_reg = 0xc184, 1082 .halt_check = BRANCH_HALT_DELAY, 1083 .clkr = { 1084 .enable_reg = 0xc184, 1085 .enable_mask = BIT(0), 1086 .hw.init = &(const struct clk_init_data) { 1087 .name = "camcc_core_ahb_clk", 1088 .parent_hws = (const struct clk_hw*[]) { 1089 &camcc_slow_ahb_clk_src.clkr.hw, 1090 }, 1091 .num_parents = 1, 1092 .flags = CLK_SET_RATE_PARENT, 1093 .ops = &clk_branch2_ops, 1094 }, 1095 }, 1096 }; 1097 1098 static struct clk_branch camcc_cpas_ahb_clk = { 1099 .halt_reg = 0xc124, 1100 .halt_check = BRANCH_HALT, 1101 .clkr = { 1102 .enable_reg = 0xc124, 1103 .enable_mask = BIT(0), 1104 .hw.init = &(const struct clk_init_data) { 1105 .name = "camcc_cpas_ahb_clk", 1106 .parent_hws = (const struct clk_hw*[]) { 1107 &camcc_slow_ahb_clk_src.clkr.hw, 1108 }, 1109 .num_parents = 1, 1110 .flags = CLK_SET_RATE_PARENT, 1111 .ops = &clk_branch2_ops, 1112 }, 1113 }, 1114 }; 1115 1116 static struct clk_branch camcc_csi0phytimer_clk = { 1117 .halt_reg = 0x601c, 1118 .halt_check = BRANCH_HALT, 1119 .clkr = { 1120 .enable_reg = 0x601c, 1121 .enable_mask = BIT(0), 1122 .hw.init = &(const struct clk_init_data) { 1123 .name = "camcc_csi0phytimer_clk", 1124 .parent_hws = (const struct clk_hw*[]) { 1125 &camcc_csi0phytimer_clk_src.clkr.hw, 1126 }, 1127 .num_parents = 1, 1128 .flags = CLK_SET_RATE_PARENT, 1129 .ops = &clk_branch2_ops, 1130 }, 1131 }, 1132 }; 1133 1134 static struct clk_branch camcc_csi1phytimer_clk = { 1135 .halt_reg = 0x6040, 1136 .halt_check = BRANCH_HALT, 1137 .clkr = { 1138 .enable_reg = 0x6040, 1139 .enable_mask = BIT(0), 1140 .hw.init = &(const struct clk_init_data) { 1141 .name = "camcc_csi1phytimer_clk", 1142 .parent_hws = (const struct clk_hw*[]) { 1143 &camcc_csi1phytimer_clk_src.clkr.hw, 1144 }, 1145 .num_parents = 1, 1146 .flags = CLK_SET_RATE_PARENT, 1147 .ops = &clk_branch2_ops, 1148 }, 1149 }, 1150 }; 1151 1152 static struct clk_branch camcc_csi2phytimer_clk = { 1153 .halt_reg = 0x6064, 1154 .halt_check = BRANCH_HALT, 1155 .clkr = { 1156 .enable_reg = 0x6064, 1157 .enable_mask = BIT(0), 1158 .hw.init = &(const struct clk_init_data) { 1159 .name = "camcc_csi2phytimer_clk", 1160 .parent_hws = (const struct clk_hw*[]) { 1161 &camcc_csi2phytimer_clk_src.clkr.hw, 1162 }, 1163 .num_parents = 1, 1164 .flags = CLK_SET_RATE_PARENT, 1165 .ops = &clk_branch2_ops, 1166 }, 1167 }, 1168 }; 1169 1170 static struct clk_branch camcc_csi3phytimer_clk = { 1171 .halt_reg = 0x6088, 1172 .halt_check = BRANCH_HALT, 1173 .clkr = { 1174 .enable_reg = 0x6088, 1175 .enable_mask = BIT(0), 1176 .hw.init = &(const struct clk_init_data) { 1177 .name = "camcc_csi3phytimer_clk", 1178 .parent_hws = (const struct clk_hw*[]) { 1179 &camcc_csi3phytimer_clk_src.clkr.hw, 1180 }, 1181 .num_parents = 1, 1182 .flags = CLK_SET_RATE_PARENT, 1183 .ops = &clk_branch2_ops, 1184 }, 1185 }, 1186 }; 1187 1188 static struct clk_branch camcc_csiphy0_clk = { 1189 .halt_reg = 0x6020, 1190 .halt_check = BRANCH_HALT, 1191 .clkr = { 1192 .enable_reg = 0x6020, 1193 .enable_mask = BIT(0), 1194 .hw.init = &(const struct clk_init_data) { 1195 .name = "camcc_csiphy0_clk", 1196 .parent_hws = (const struct clk_hw*[]) { 1197 &camcc_cphy_rx_clk_src.clkr.hw, 1198 }, 1199 .num_parents = 1, 1200 .flags = CLK_SET_RATE_PARENT, 1201 .ops = &clk_branch2_ops, 1202 }, 1203 }, 1204 }; 1205 1206 static struct clk_branch camcc_csiphy1_clk = { 1207 .halt_reg = 0x6044, 1208 .halt_check = BRANCH_HALT, 1209 .clkr = { 1210 .enable_reg = 0x6044, 1211 .enable_mask = BIT(0), 1212 .hw.init = &(const struct clk_init_data) { 1213 .name = "camcc_csiphy1_clk", 1214 .parent_hws = (const struct clk_hw*[]) { 1215 &camcc_cphy_rx_clk_src.clkr.hw, 1216 }, 1217 .num_parents = 1, 1218 .flags = CLK_SET_RATE_PARENT, 1219 .ops = &clk_branch2_ops, 1220 }, 1221 }, 1222 }; 1223 1224 static struct clk_branch camcc_csiphy2_clk = { 1225 .halt_reg = 0x6068, 1226 .halt_check = BRANCH_HALT, 1227 .clkr = { 1228 .enable_reg = 0x6068, 1229 .enable_mask = BIT(0), 1230 .hw.init = &(const struct clk_init_data) { 1231 .name = "camcc_csiphy2_clk", 1232 .parent_hws = (const struct clk_hw*[]) { 1233 &camcc_cphy_rx_clk_src.clkr.hw, 1234 }, 1235 .num_parents = 1, 1236 .flags = CLK_SET_RATE_PARENT, 1237 .ops = &clk_branch2_ops, 1238 }, 1239 }, 1240 }; 1241 1242 static struct clk_branch camcc_csiphy3_clk = { 1243 .halt_reg = 0x608c, 1244 .halt_check = BRANCH_HALT, 1245 .clkr = { 1246 .enable_reg = 0x608c, 1247 .enable_mask = BIT(0), 1248 .hw.init = &(const struct clk_init_data) { 1249 .name = "camcc_csiphy3_clk", 1250 .parent_hws = (const struct clk_hw*[]) { 1251 &camcc_cphy_rx_clk_src.clkr.hw, 1252 }, 1253 .num_parents = 1, 1254 .flags = CLK_SET_RATE_PARENT, 1255 .ops = &clk_branch2_ops, 1256 }, 1257 }, 1258 }; 1259 1260 static struct clk_branch camcc_fd_core_clk = { 1261 .halt_reg = 0xc0b4, 1262 .halt_check = BRANCH_HALT, 1263 .clkr = { 1264 .enable_reg = 0xc0b4, 1265 .enable_mask = BIT(0), 1266 .hw.init = &(const struct clk_init_data) { 1267 .name = "camcc_fd_core_clk", 1268 .parent_hws = (const struct clk_hw*[]) { 1269 &camcc_fd_core_clk_src.clkr.hw, 1270 }, 1271 .num_parents = 1, 1272 .flags = CLK_SET_RATE_PARENT, 1273 .ops = &clk_branch2_ops, 1274 }, 1275 }, 1276 }; 1277 1278 static struct clk_branch camcc_fd_core_uar_clk = { 1279 .halt_reg = 0xc0bc, 1280 .halt_check = BRANCH_HALT, 1281 .clkr = { 1282 .enable_reg = 0xc0bc, 1283 .enable_mask = BIT(0), 1284 .hw.init = &(const struct clk_init_data) { 1285 .name = "camcc_fd_core_uar_clk", 1286 .parent_hws = (const struct clk_hw*[]) { 1287 &camcc_fd_core_clk_src.clkr.hw, 1288 }, 1289 .num_parents = 1, 1290 .flags = CLK_SET_RATE_PARENT, 1291 .ops = &clk_branch2_ops, 1292 }, 1293 }, 1294 }; 1295 1296 static struct clk_branch camcc_icp_ahb_clk = { 1297 .halt_reg = 0xc094, 1298 .halt_check = BRANCH_HALT, 1299 .clkr = { 1300 .enable_reg = 0xc094, 1301 .enable_mask = BIT(0), 1302 .hw.init = &(const struct clk_init_data) { 1303 .name = "camcc_icp_ahb_clk", 1304 .parent_hws = (const struct clk_hw*[]) { 1305 &camcc_slow_ahb_clk_src.clkr.hw, 1306 }, 1307 .num_parents = 1, 1308 .flags = CLK_SET_RATE_PARENT, 1309 .ops = &clk_branch2_ops, 1310 }, 1311 }, 1312 }; 1313 1314 static struct clk_branch camcc_icp_clk = { 1315 .halt_reg = 0xc08c, 1316 .halt_check = BRANCH_HALT, 1317 .clkr = { 1318 .enable_reg = 0xc08c, 1319 .enable_mask = BIT(0), 1320 .hw.init = &(const struct clk_init_data) { 1321 .name = "camcc_icp_clk", 1322 .parent_hws = (const struct clk_hw*[]) { 1323 &camcc_icp_clk_src.clkr.hw, 1324 }, 1325 .num_parents = 1, 1326 .flags = CLK_SET_RATE_PARENT, 1327 .ops = &clk_branch2_ops, 1328 }, 1329 }, 1330 }; 1331 1332 static struct clk_branch camcc_ife_0_axi_clk = { 1333 .halt_reg = 0xa080, 1334 .halt_check = BRANCH_HALT, 1335 .clkr = { 1336 .enable_reg = 0xa080, 1337 .enable_mask = BIT(0), 1338 .hw.init = &(const struct clk_init_data) { 1339 .name = "camcc_ife_0_axi_clk", 1340 .parent_hws = (const struct clk_hw*[]) { 1341 &camcc_camnoc_axi_clk_src.clkr.hw, 1342 }, 1343 .num_parents = 1, 1344 .flags = CLK_SET_RATE_PARENT, 1345 .ops = &clk_branch2_ops, 1346 }, 1347 }, 1348 }; 1349 1350 static struct clk_branch camcc_ife_0_clk = { 1351 .halt_reg = 0xa028, 1352 .halt_check = BRANCH_HALT, 1353 .clkr = { 1354 .enable_reg = 0xa028, 1355 .enable_mask = BIT(0), 1356 .hw.init = &(const struct clk_init_data) { 1357 .name = "camcc_ife_0_clk", 1358 .parent_hws = (const struct clk_hw*[]) { 1359 &camcc_ife_0_clk_src.clkr.hw, 1360 }, 1361 .num_parents = 1, 1362 .flags = CLK_SET_RATE_PARENT, 1363 .ops = &clk_branch2_ops, 1364 }, 1365 }, 1366 }; 1367 1368 static struct clk_branch camcc_ife_0_cphy_rx_clk = { 1369 .halt_reg = 0xa07c, 1370 .halt_check = BRANCH_HALT, 1371 .clkr = { 1372 .enable_reg = 0xa07c, 1373 .enable_mask = BIT(0), 1374 .hw.init = &(const struct clk_init_data) { 1375 .name = "camcc_ife_0_cphy_rx_clk", 1376 .parent_hws = (const struct clk_hw*[]) { 1377 &camcc_cphy_rx_clk_src.clkr.hw, 1378 }, 1379 .num_parents = 1, 1380 .flags = CLK_SET_RATE_PARENT, 1381 .ops = &clk_branch2_ops, 1382 }, 1383 }, 1384 }; 1385 1386 static struct clk_branch camcc_ife_0_csid_clk = { 1387 .halt_reg = 0xa054, 1388 .halt_check = BRANCH_HALT, 1389 .clkr = { 1390 .enable_reg = 0xa054, 1391 .enable_mask = BIT(0), 1392 .hw.init = &(const struct clk_init_data) { 1393 .name = "camcc_ife_0_csid_clk", 1394 .parent_hws = (const struct clk_hw*[]) { 1395 &camcc_ife_0_csid_clk_src.clkr.hw, 1396 }, 1397 .num_parents = 1, 1398 .flags = CLK_SET_RATE_PARENT, 1399 .ops = &clk_branch2_ops, 1400 }, 1401 }, 1402 }; 1403 1404 static struct clk_branch camcc_ife_0_dsp_clk = { 1405 .halt_reg = 0xa038, 1406 .halt_check = BRANCH_HALT, 1407 .clkr = { 1408 .enable_reg = 0xa038, 1409 .enable_mask = BIT(0), 1410 .hw.init = &(const struct clk_init_data) { 1411 .name = "camcc_ife_0_dsp_clk", 1412 .parent_hws = (const struct clk_hw*[]) { 1413 &camcc_ife_0_clk_src.clkr.hw, 1414 }, 1415 .num_parents = 1, 1416 .flags = CLK_SET_RATE_PARENT, 1417 .ops = &clk_branch2_ops, 1418 }, 1419 }, 1420 }; 1421 1422 static struct clk_branch camcc_ife_1_axi_clk = { 1423 .halt_reg = 0xb058, 1424 .halt_check = BRANCH_HALT, 1425 .clkr = { 1426 .enable_reg = 0xb058, 1427 .enable_mask = BIT(0), 1428 .hw.init = &(const struct clk_init_data) { 1429 .name = "camcc_ife_1_axi_clk", 1430 .parent_hws = (const struct clk_hw*[]) { 1431 &camcc_camnoc_axi_clk_src.clkr.hw, 1432 }, 1433 .num_parents = 1, 1434 .flags = CLK_SET_RATE_PARENT, 1435 .ops = &clk_branch2_ops, 1436 }, 1437 }, 1438 }; 1439 1440 static struct clk_branch camcc_ife_1_clk = { 1441 .halt_reg = 0xb028, 1442 .halt_check = BRANCH_HALT, 1443 .clkr = { 1444 .enable_reg = 0xb028, 1445 .enable_mask = BIT(0), 1446 .hw.init = &(const struct clk_init_data) { 1447 .name = "camcc_ife_1_clk", 1448 .parent_hws = (const struct clk_hw*[]) { 1449 &camcc_ife_1_clk_src.clkr.hw, 1450 }, 1451 .num_parents = 1, 1452 .flags = CLK_SET_RATE_PARENT, 1453 .ops = &clk_branch2_ops, 1454 }, 1455 }, 1456 }; 1457 1458 static struct clk_branch camcc_ife_1_cphy_rx_clk = { 1459 .halt_reg = 0xb054, 1460 .halt_check = BRANCH_HALT, 1461 .clkr = { 1462 .enable_reg = 0xb054, 1463 .enable_mask = BIT(0), 1464 .hw.init = &(const struct clk_init_data) { 1465 .name = "camcc_ife_1_cphy_rx_clk", 1466 .parent_hws = (const struct clk_hw*[]) { 1467 &camcc_cphy_rx_clk_src.clkr.hw, 1468 }, 1469 .num_parents = 1, 1470 .flags = CLK_SET_RATE_PARENT, 1471 .ops = &clk_branch2_ops, 1472 }, 1473 }, 1474 }; 1475 1476 static struct clk_branch camcc_ife_1_csid_clk = { 1477 .halt_reg = 0xb04c, 1478 .halt_check = BRANCH_HALT, 1479 .clkr = { 1480 .enable_reg = 0xb04c, 1481 .enable_mask = BIT(0), 1482 .hw.init = &(const struct clk_init_data) { 1483 .name = "camcc_ife_1_csid_clk", 1484 .parent_hws = (const struct clk_hw*[]) { 1485 &camcc_ife_1_csid_clk_src.clkr.hw, 1486 }, 1487 .num_parents = 1, 1488 .flags = CLK_SET_RATE_PARENT, 1489 .ops = &clk_branch2_ops, 1490 }, 1491 }, 1492 }; 1493 1494 static struct clk_branch camcc_ife_1_dsp_clk = { 1495 .halt_reg = 0xb030, 1496 .halt_check = BRANCH_HALT, 1497 .clkr = { 1498 .enable_reg = 0xb030, 1499 .enable_mask = BIT(0), 1500 .hw.init = &(const struct clk_init_data) { 1501 .name = "camcc_ife_1_dsp_clk", 1502 .parent_hws = (const struct clk_hw*[]) { 1503 &camcc_ife_1_clk_src.clkr.hw, 1504 }, 1505 .num_parents = 1, 1506 .flags = CLK_SET_RATE_PARENT, 1507 .ops = &clk_branch2_ops, 1508 }, 1509 }, 1510 }; 1511 1512 static struct clk_branch camcc_ife_lite_clk = { 1513 .halt_reg = 0xc01c, 1514 .halt_check = BRANCH_HALT, 1515 .clkr = { 1516 .enable_reg = 0xc01c, 1517 .enable_mask = BIT(0), 1518 .hw.init = &(const struct clk_init_data) { 1519 .name = "camcc_ife_lite_clk", 1520 .parent_hws = (const struct clk_hw*[]) { 1521 &camcc_ife_lite_clk_src.clkr.hw, 1522 }, 1523 .num_parents = 1, 1524 .flags = CLK_SET_RATE_PARENT, 1525 .ops = &clk_branch2_ops, 1526 }, 1527 }, 1528 }; 1529 1530 static struct clk_branch camcc_ife_lite_cphy_rx_clk = { 1531 .halt_reg = 0xc040, 1532 .halt_check = BRANCH_HALT, 1533 .clkr = { 1534 .enable_reg = 0xc040, 1535 .enable_mask = BIT(0), 1536 .hw.init = &(const struct clk_init_data) { 1537 .name = "camcc_ife_lite_cphy_rx_clk", 1538 .parent_hws = (const struct clk_hw*[]) { 1539 &camcc_cphy_rx_clk_src.clkr.hw, 1540 }, 1541 .num_parents = 1, 1542 .flags = CLK_SET_RATE_PARENT, 1543 .ops = &clk_branch2_ops, 1544 }, 1545 }, 1546 }; 1547 1548 static struct clk_branch camcc_ife_lite_csid_clk = { 1549 .halt_reg = 0xc038, 1550 .halt_check = BRANCH_HALT, 1551 .clkr = { 1552 .enable_reg = 0xc038, 1553 .enable_mask = BIT(0), 1554 .hw.init = &(const struct clk_init_data) { 1555 .name = "camcc_ife_lite_csid_clk", 1556 .parent_hws = (const struct clk_hw*[]) { 1557 &camcc_ife_lite_csid_clk_src.clkr.hw, 1558 }, 1559 .num_parents = 1, 1560 .flags = CLK_SET_RATE_PARENT, 1561 .ops = &clk_branch2_ops, 1562 }, 1563 }, 1564 }; 1565 1566 static struct clk_branch camcc_ipe_0_ahb_clk = { 1567 .halt_reg = 0x8040, 1568 .halt_check = BRANCH_HALT, 1569 .clkr = { 1570 .enable_reg = 0x8040, 1571 .enable_mask = BIT(0), 1572 .hw.init = &(const struct clk_init_data) { 1573 .name = "camcc_ipe_0_ahb_clk", 1574 .parent_hws = (const struct clk_hw*[]) { 1575 &camcc_slow_ahb_clk_src.clkr.hw, 1576 }, 1577 .num_parents = 1, 1578 .flags = CLK_SET_RATE_PARENT, 1579 .ops = &clk_branch2_ops, 1580 }, 1581 }, 1582 }; 1583 1584 static struct clk_branch camcc_ipe_0_areg_clk = { 1585 .halt_reg = 0x803c, 1586 .halt_check = BRANCH_HALT, 1587 .clkr = { 1588 .enable_reg = 0x803c, 1589 .enable_mask = BIT(0), 1590 .hw.init = &(const struct clk_init_data) { 1591 .name = "camcc_ipe_0_areg_clk", 1592 .parent_hws = (const struct clk_hw*[]) { 1593 &camcc_fast_ahb_clk_src.clkr.hw, 1594 }, 1595 .num_parents = 1, 1596 .flags = CLK_SET_RATE_PARENT, 1597 .ops = &clk_branch2_ops, 1598 }, 1599 }, 1600 }; 1601 1602 static struct clk_branch camcc_ipe_0_axi_clk = { 1603 .halt_reg = 0x8038, 1604 .halt_check = BRANCH_HALT, 1605 .clkr = { 1606 .enable_reg = 0x8038, 1607 .enable_mask = BIT(0), 1608 .hw.init = &(const struct clk_init_data) { 1609 .name = "camcc_ipe_0_axi_clk", 1610 .parent_hws = (const struct clk_hw*[]) { 1611 &camcc_camnoc_axi_clk_src.clkr.hw, 1612 }, 1613 .num_parents = 1, 1614 .flags = CLK_SET_RATE_PARENT, 1615 .ops = &clk_branch2_ops, 1616 }, 1617 }, 1618 }; 1619 1620 static struct clk_branch camcc_ipe_0_clk = { 1621 .halt_reg = 0x8028, 1622 .halt_check = BRANCH_HALT, 1623 .clkr = { 1624 .enable_reg = 0x8028, 1625 .enable_mask = BIT(0), 1626 .hw.init = &(const struct clk_init_data) { 1627 .name = "camcc_ipe_0_clk", 1628 .parent_hws = (const struct clk_hw*[]) { 1629 &camcc_ipe_0_clk_src.clkr.hw, 1630 }, 1631 .num_parents = 1, 1632 .flags = CLK_SET_RATE_PARENT, 1633 .ops = &clk_branch2_ops, 1634 }, 1635 }, 1636 }; 1637 1638 static struct clk_branch camcc_ipe_1_ahb_clk = { 1639 .halt_reg = 0x9028, 1640 .halt_check = BRANCH_HALT, 1641 .clkr = { 1642 .enable_reg = 0x9028, 1643 .enable_mask = BIT(0), 1644 .hw.init = &(const struct clk_init_data) { 1645 .name = "camcc_ipe_1_ahb_clk", 1646 .parent_hws = (const struct clk_hw*[]) { 1647 &camcc_slow_ahb_clk_src.clkr.hw, 1648 }, 1649 .num_parents = 1, 1650 .flags = CLK_SET_RATE_PARENT, 1651 .ops = &clk_branch2_ops, 1652 }, 1653 }, 1654 }; 1655 1656 static struct clk_branch camcc_ipe_1_areg_clk = { 1657 .halt_reg = 0x9024, 1658 .halt_check = BRANCH_HALT, 1659 .clkr = { 1660 .enable_reg = 0x9024, 1661 .enable_mask = BIT(0), 1662 .hw.init = &(const struct clk_init_data) { 1663 .name = "camcc_ipe_1_areg_clk", 1664 .parent_hws = (const struct clk_hw*[]) { 1665 &camcc_fast_ahb_clk_src.clkr.hw, 1666 }, 1667 .num_parents = 1, 1668 .flags = CLK_SET_RATE_PARENT, 1669 .ops = &clk_branch2_ops, 1670 }, 1671 }, 1672 }; 1673 1674 static struct clk_branch camcc_ipe_1_axi_clk = { 1675 .halt_reg = 0x9020, 1676 .halt_check = BRANCH_HALT, 1677 .clkr = { 1678 .enable_reg = 0x9020, 1679 .enable_mask = BIT(0), 1680 .hw.init = &(const struct clk_init_data) { 1681 .name = "camcc_ipe_1_axi_clk", 1682 .parent_hws = (const struct clk_hw*[]) { 1683 &camcc_camnoc_axi_clk_src.clkr.hw, 1684 }, 1685 .num_parents = 1, 1686 .flags = CLK_SET_RATE_PARENT, 1687 .ops = &clk_branch2_ops, 1688 }, 1689 }, 1690 }; 1691 1692 static struct clk_branch camcc_ipe_1_clk = { 1693 .halt_reg = 0x9010, 1694 .halt_check = BRANCH_HALT, 1695 .clkr = { 1696 .enable_reg = 0x9010, 1697 .enable_mask = BIT(0), 1698 .hw.init = &(const struct clk_init_data) { 1699 .name = "camcc_ipe_1_clk", 1700 .parent_hws = (const struct clk_hw*[]) { 1701 &camcc_ipe_0_clk_src.clkr.hw, 1702 }, 1703 .num_parents = 1, 1704 .flags = CLK_SET_RATE_PARENT, 1705 .ops = &clk_branch2_ops, 1706 }, 1707 }, 1708 }; 1709 1710 static struct clk_branch camcc_jpeg_clk = { 1711 .halt_reg = 0xc060, 1712 .halt_check = BRANCH_HALT, 1713 .clkr = { 1714 .enable_reg = 0xc060, 1715 .enable_mask = BIT(0), 1716 .hw.init = &(const struct clk_init_data) { 1717 .name = "camcc_jpeg_clk", 1718 .parent_hws = (const struct clk_hw*[]) { 1719 &camcc_jpeg_clk_src.clkr.hw, 1720 }, 1721 .num_parents = 1, 1722 .flags = CLK_SET_RATE_PARENT, 1723 .ops = &clk_branch2_ops, 1724 }, 1725 }, 1726 }; 1727 1728 static struct clk_branch camcc_lrme_clk = { 1729 .halt_reg = 0xc118, 1730 .halt_check = BRANCH_HALT, 1731 .clkr = { 1732 .enable_reg = 0xc118, 1733 .enable_mask = BIT(0), 1734 .hw.init = &(const struct clk_init_data) { 1735 .name = "camcc_lrme_clk", 1736 .parent_hws = (const struct clk_hw*[]) { 1737 &camcc_lrme_clk_src.clkr.hw, 1738 }, 1739 .num_parents = 1, 1740 .flags = CLK_SET_RATE_PARENT, 1741 .ops = &clk_branch2_ops, 1742 }, 1743 }, 1744 }; 1745 1746 static struct clk_branch camcc_mclk0_clk = { 1747 .halt_reg = 0x501c, 1748 .halt_check = BRANCH_HALT, 1749 .clkr = { 1750 .enable_reg = 0x501c, 1751 .enable_mask = BIT(0), 1752 .hw.init = &(const struct clk_init_data) { 1753 .name = "camcc_mclk0_clk", 1754 .parent_hws = (const struct clk_hw*[]) { 1755 &camcc_mclk0_clk_src.clkr.hw, 1756 }, 1757 .num_parents = 1, 1758 .flags = CLK_SET_RATE_PARENT, 1759 .ops = &clk_branch2_ops, 1760 }, 1761 }, 1762 }; 1763 1764 static struct clk_branch camcc_mclk1_clk = { 1765 .halt_reg = 0x503c, 1766 .halt_check = BRANCH_HALT, 1767 .clkr = { 1768 .enable_reg = 0x503c, 1769 .enable_mask = BIT(0), 1770 .hw.init = &(const struct clk_init_data) { 1771 .name = "camcc_mclk1_clk", 1772 .parent_hws = (const struct clk_hw*[]) { 1773 &camcc_mclk1_clk_src.clkr.hw, 1774 }, 1775 .num_parents = 1, 1776 .flags = CLK_SET_RATE_PARENT, 1777 .ops = &clk_branch2_ops, 1778 }, 1779 }, 1780 }; 1781 1782 static struct clk_branch camcc_mclk2_clk = { 1783 .halt_reg = 0x505c, 1784 .halt_check = BRANCH_HALT, 1785 .clkr = { 1786 .enable_reg = 0x505c, 1787 .enable_mask = BIT(0), 1788 .hw.init = &(const struct clk_init_data) { 1789 .name = "camcc_mclk2_clk", 1790 .parent_hws = (const struct clk_hw*[]) { 1791 &camcc_mclk2_clk_src.clkr.hw, 1792 }, 1793 .num_parents = 1, 1794 .flags = CLK_SET_RATE_PARENT, 1795 .ops = &clk_branch2_ops, 1796 }, 1797 }, 1798 }; 1799 1800 static struct clk_branch camcc_mclk3_clk = { 1801 .halt_reg = 0x507c, 1802 .halt_check = BRANCH_HALT, 1803 .clkr = { 1804 .enable_reg = 0x507c, 1805 .enable_mask = BIT(0), 1806 .hw.init = &(const struct clk_init_data) { 1807 .name = "camcc_mclk3_clk", 1808 .parent_hws = (const struct clk_hw*[]) { 1809 &camcc_mclk3_clk_src.clkr.hw, 1810 }, 1811 .num_parents = 1, 1812 .flags = CLK_SET_RATE_PARENT, 1813 .ops = &clk_branch2_ops, 1814 }, 1815 }, 1816 }; 1817 1818 static struct clk_branch camcc_sleep_clk = { 1819 .halt_reg = 0xc1bc, 1820 .halt_check = BRANCH_HALT, 1821 .clkr = { 1822 .enable_reg = 0xc1bc, 1823 .enable_mask = BIT(0), 1824 .hw.init = &(const struct clk_init_data) { 1825 .name = "camcc_sleep_clk", 1826 .parent_hws = (const struct clk_hw*[]) { 1827 &camcc_sleep_clk_src.clkr.hw, 1828 }, 1829 .num_parents = 1, 1830 .flags = CLK_SET_RATE_PARENT, 1831 .ops = &clk_branch2_ops, 1832 }, 1833 }, 1834 }; 1835 1836 static struct gdsc camcc_titan_top_gdsc; 1837 1838 static struct gdsc camcc_bps_gdsc = { 1839 .gdscr = 0x7004, 1840 .pd = { 1841 .name = "camcc_bps_gdsc", 1842 }, 1843 .flags = HW_CTRL | POLL_CFG_GDSCR, 1844 .parent = &camcc_titan_top_gdsc.pd, 1845 .pwrsts = PWRSTS_OFF_ON, 1846 }; 1847 1848 static struct gdsc camcc_ife_0_gdsc = { 1849 .gdscr = 0xa004, 1850 .pd = { 1851 .name = "camcc_ife_0_gdsc", 1852 }, 1853 .flags = POLL_CFG_GDSCR, 1854 .parent = &camcc_titan_top_gdsc.pd, 1855 .pwrsts = PWRSTS_OFF_ON, 1856 }; 1857 1858 static struct gdsc camcc_ife_1_gdsc = { 1859 .gdscr = 0xb004, 1860 .pd = { 1861 .name = "camcc_ife_1_gdsc", 1862 }, 1863 .flags = POLL_CFG_GDSCR, 1864 .parent = &camcc_titan_top_gdsc.pd, 1865 .pwrsts = PWRSTS_OFF_ON, 1866 }; 1867 1868 static struct gdsc camcc_ipe_0_gdsc = { 1869 .gdscr = 0x8004, 1870 .pd = { 1871 .name = "camcc_ipe_0_gdsc", 1872 }, 1873 .flags = HW_CTRL | POLL_CFG_GDSCR, 1874 .parent = &camcc_titan_top_gdsc.pd, 1875 .pwrsts = PWRSTS_OFF_ON, 1876 }; 1877 1878 static struct gdsc camcc_ipe_1_gdsc = { 1879 .gdscr = 0x9004, 1880 .pd = { 1881 .name = "camcc_ipe_1_gdsc", 1882 }, 1883 .flags = HW_CTRL | POLL_CFG_GDSCR, 1884 .parent = &camcc_titan_top_gdsc.pd, 1885 .pwrsts = PWRSTS_OFF_ON, 1886 }; 1887 1888 static struct gdsc camcc_titan_top_gdsc = { 1889 .gdscr = 0xc1c4, 1890 .pd = { 1891 .name = "camcc_titan_top_gdsc", 1892 }, 1893 .flags = POLL_CFG_GDSCR, 1894 .pwrsts = PWRSTS_OFF_ON, 1895 }; 1896 1897 static struct clk_hw *camcc_sm7150_hws[] = { 1898 [CAMCC_PLL0_OUT_EVEN] = &camcc_pll0_out_even.hw, 1899 [CAMCC_PLL0_OUT_ODD] = &camcc_pll0_out_odd.hw, 1900 [CAMCC_PLL1_OUT_EVEN] = &camcc_pll1_out_even.hw, 1901 [CAMCC_PLL2_OUT_EARLY] = &camcc_pll2_out_early.hw, 1902 [CAMCC_PLL3_OUT_EVEN] = &camcc_pll3_out_even.hw, 1903 [CAMCC_PLL4_OUT_EVEN] = &camcc_pll4_out_even.hw, 1904 }; 1905 1906 static struct clk_regmap *camcc_sm7150_clocks[] = { 1907 [CAMCC_BPS_AHB_CLK] = &camcc_bps_ahb_clk.clkr, 1908 [CAMCC_BPS_AREG_CLK] = &camcc_bps_areg_clk.clkr, 1909 [CAMCC_BPS_AXI_CLK] = &camcc_bps_axi_clk.clkr, 1910 [CAMCC_BPS_CLK] = &camcc_bps_clk.clkr, 1911 [CAMCC_BPS_CLK_SRC] = &camcc_bps_clk_src.clkr, 1912 [CAMCC_CAMNOC_AXI_CLK] = &camcc_camnoc_axi_clk.clkr, 1913 [CAMCC_CAMNOC_AXI_CLK_SRC] = &camcc_camnoc_axi_clk_src.clkr, 1914 [CAMCC_CAMNOC_DCD_XO_CLK] = &camcc_camnoc_dcd_xo_clk.clkr, 1915 [CAMCC_CCI_0_CLK] = &camcc_cci_0_clk.clkr, 1916 [CAMCC_CCI_0_CLK_SRC] = &camcc_cci_0_clk_src.clkr, 1917 [CAMCC_CCI_1_CLK] = &camcc_cci_1_clk.clkr, 1918 [CAMCC_CCI_1_CLK_SRC] = &camcc_cci_1_clk_src.clkr, 1919 [CAMCC_CORE_AHB_CLK] = &camcc_core_ahb_clk.clkr, 1920 [CAMCC_CPAS_AHB_CLK] = &camcc_cpas_ahb_clk.clkr, 1921 [CAMCC_CPHY_RX_CLK_SRC] = &camcc_cphy_rx_clk_src.clkr, 1922 [CAMCC_CSI0PHYTIMER_CLK] = &camcc_csi0phytimer_clk.clkr, 1923 [CAMCC_CSI0PHYTIMER_CLK_SRC] = &camcc_csi0phytimer_clk_src.clkr, 1924 [CAMCC_CSI1PHYTIMER_CLK] = &camcc_csi1phytimer_clk.clkr, 1925 [CAMCC_CSI1PHYTIMER_CLK_SRC] = &camcc_csi1phytimer_clk_src.clkr, 1926 [CAMCC_CSI2PHYTIMER_CLK] = &camcc_csi2phytimer_clk.clkr, 1927 [CAMCC_CSI2PHYTIMER_CLK_SRC] = &camcc_csi2phytimer_clk_src.clkr, 1928 [CAMCC_CSI3PHYTIMER_CLK] = &camcc_csi3phytimer_clk.clkr, 1929 [CAMCC_CSI3PHYTIMER_CLK_SRC] = &camcc_csi3phytimer_clk_src.clkr, 1930 [CAMCC_CSIPHY0_CLK] = &camcc_csiphy0_clk.clkr, 1931 [CAMCC_CSIPHY1_CLK] = &camcc_csiphy1_clk.clkr, 1932 [CAMCC_CSIPHY2_CLK] = &camcc_csiphy2_clk.clkr, 1933 [CAMCC_CSIPHY3_CLK] = &camcc_csiphy3_clk.clkr, 1934 [CAMCC_FAST_AHB_CLK_SRC] = &camcc_fast_ahb_clk_src.clkr, 1935 [CAMCC_FD_CORE_CLK] = &camcc_fd_core_clk.clkr, 1936 [CAMCC_FD_CORE_CLK_SRC] = &camcc_fd_core_clk_src.clkr, 1937 [CAMCC_FD_CORE_UAR_CLK] = &camcc_fd_core_uar_clk.clkr, 1938 [CAMCC_ICP_AHB_CLK] = &camcc_icp_ahb_clk.clkr, 1939 [CAMCC_ICP_CLK] = &camcc_icp_clk.clkr, 1940 [CAMCC_ICP_CLK_SRC] = &camcc_icp_clk_src.clkr, 1941 [CAMCC_IFE_0_AXI_CLK] = &camcc_ife_0_axi_clk.clkr, 1942 [CAMCC_IFE_0_CLK] = &camcc_ife_0_clk.clkr, 1943 [CAMCC_IFE_0_CLK_SRC] = &camcc_ife_0_clk_src.clkr, 1944 [CAMCC_IFE_0_CPHY_RX_CLK] = &camcc_ife_0_cphy_rx_clk.clkr, 1945 [CAMCC_IFE_0_CSID_CLK] = &camcc_ife_0_csid_clk.clkr, 1946 [CAMCC_IFE_0_CSID_CLK_SRC] = &camcc_ife_0_csid_clk_src.clkr, 1947 [CAMCC_IFE_0_DSP_CLK] = &camcc_ife_0_dsp_clk.clkr, 1948 [CAMCC_IFE_1_AXI_CLK] = &camcc_ife_1_axi_clk.clkr, 1949 [CAMCC_IFE_1_CLK] = &camcc_ife_1_clk.clkr, 1950 [CAMCC_IFE_1_CLK_SRC] = &camcc_ife_1_clk_src.clkr, 1951 [CAMCC_IFE_1_CPHY_RX_CLK] = &camcc_ife_1_cphy_rx_clk.clkr, 1952 [CAMCC_IFE_1_CSID_CLK] = &camcc_ife_1_csid_clk.clkr, 1953 [CAMCC_IFE_1_CSID_CLK_SRC] = &camcc_ife_1_csid_clk_src.clkr, 1954 [CAMCC_IFE_1_DSP_CLK] = &camcc_ife_1_dsp_clk.clkr, 1955 [CAMCC_IFE_LITE_CLK] = &camcc_ife_lite_clk.clkr, 1956 [CAMCC_IFE_LITE_CLK_SRC] = &camcc_ife_lite_clk_src.clkr, 1957 [CAMCC_IFE_LITE_CPHY_RX_CLK] = &camcc_ife_lite_cphy_rx_clk.clkr, 1958 [CAMCC_IFE_LITE_CSID_CLK] = &camcc_ife_lite_csid_clk.clkr, 1959 [CAMCC_IFE_LITE_CSID_CLK_SRC] = &camcc_ife_lite_csid_clk_src.clkr, 1960 [CAMCC_IPE_0_AHB_CLK] = &camcc_ipe_0_ahb_clk.clkr, 1961 [CAMCC_IPE_0_AREG_CLK] = &camcc_ipe_0_areg_clk.clkr, 1962 [CAMCC_IPE_0_AXI_CLK] = &camcc_ipe_0_axi_clk.clkr, 1963 [CAMCC_IPE_0_CLK] = &camcc_ipe_0_clk.clkr, 1964 [CAMCC_IPE_0_CLK_SRC] = &camcc_ipe_0_clk_src.clkr, 1965 [CAMCC_IPE_1_AHB_CLK] = &camcc_ipe_1_ahb_clk.clkr, 1966 [CAMCC_IPE_1_AREG_CLK] = &camcc_ipe_1_areg_clk.clkr, 1967 [CAMCC_IPE_1_AXI_CLK] = &camcc_ipe_1_axi_clk.clkr, 1968 [CAMCC_IPE_1_CLK] = &camcc_ipe_1_clk.clkr, 1969 [CAMCC_JPEG_CLK] = &camcc_jpeg_clk.clkr, 1970 [CAMCC_JPEG_CLK_SRC] = &camcc_jpeg_clk_src.clkr, 1971 [CAMCC_LRME_CLK] = &camcc_lrme_clk.clkr, 1972 [CAMCC_LRME_CLK_SRC] = &camcc_lrme_clk_src.clkr, 1973 [CAMCC_MCLK0_CLK] = &camcc_mclk0_clk.clkr, 1974 [CAMCC_MCLK0_CLK_SRC] = &camcc_mclk0_clk_src.clkr, 1975 [CAMCC_MCLK1_CLK] = &camcc_mclk1_clk.clkr, 1976 [CAMCC_MCLK1_CLK_SRC] = &camcc_mclk1_clk_src.clkr, 1977 [CAMCC_MCLK2_CLK] = &camcc_mclk2_clk.clkr, 1978 [CAMCC_MCLK2_CLK_SRC] = &camcc_mclk2_clk_src.clkr, 1979 [CAMCC_MCLK3_CLK] = &camcc_mclk3_clk.clkr, 1980 [CAMCC_MCLK3_CLK_SRC] = &camcc_mclk3_clk_src.clkr, 1981 [CAMCC_PLL0] = &camcc_pll0.clkr, 1982 [CAMCC_PLL1] = &camcc_pll1.clkr, 1983 [CAMCC_PLL2] = &camcc_pll2.clkr, 1984 [CAMCC_PLL2_OUT_AUX] = &camcc_pll2_out_aux.clkr, 1985 [CAMCC_PLL2_OUT_MAIN] = &camcc_pll2_out_main.clkr, 1986 [CAMCC_PLL3] = &camcc_pll3.clkr, 1987 [CAMCC_PLL4] = &camcc_pll4.clkr, 1988 [CAMCC_SLEEP_CLK] = &camcc_sleep_clk.clkr, 1989 [CAMCC_SLEEP_CLK_SRC] = &camcc_sleep_clk_src.clkr, 1990 [CAMCC_SLOW_AHB_CLK_SRC] = &camcc_slow_ahb_clk_src.clkr, 1991 [CAMCC_XO_CLK_SRC] = &camcc_xo_clk_src.clkr, 1992 }; 1993 1994 static struct gdsc *camcc_sm7150_gdscs[] = { 1995 [BPS_GDSC] = &camcc_bps_gdsc, 1996 [IFE_0_GDSC] = &camcc_ife_0_gdsc, 1997 [IFE_1_GDSC] = &camcc_ife_1_gdsc, 1998 [IPE_0_GDSC] = &camcc_ipe_0_gdsc, 1999 [IPE_1_GDSC] = &camcc_ipe_1_gdsc, 2000 [TITAN_TOP_GDSC] = &camcc_titan_top_gdsc, 2001 }; 2002 2003 static const struct regmap_config camcc_sm7150_regmap_config = { 2004 .reg_bits = 32, 2005 .reg_stride = 4, 2006 .val_bits = 32, 2007 .max_register = 0xd024, 2008 .fast_io = true, 2009 }; 2010 2011 static const struct qcom_cc_desc camcc_sm7150_desc = { 2012 .config = &camcc_sm7150_regmap_config, 2013 .clk_hws = camcc_sm7150_hws, 2014 .num_clk_hws = ARRAY_SIZE(camcc_sm7150_hws), 2015 .clks = camcc_sm7150_clocks, 2016 .num_clks = ARRAY_SIZE(camcc_sm7150_clocks), 2017 .gdscs = camcc_sm7150_gdscs, 2018 .num_gdscs = ARRAY_SIZE(camcc_sm7150_gdscs), 2019 }; 2020 2021 static const struct of_device_id camcc_sm7150_match_table[] = { 2022 { .compatible = "qcom,sm7150-camcc" }, 2023 { } 2024 }; 2025 MODULE_DEVICE_TABLE(of, camcc_sm7150_match_table); 2026 2027 static int camcc_sm7150_probe(struct platform_device *pdev) 2028 { 2029 struct regmap *regmap; 2030 2031 regmap = qcom_cc_map(pdev, &camcc_sm7150_desc); 2032 if (IS_ERR(regmap)) 2033 return PTR_ERR(regmap); 2034 2035 clk_fabia_pll_configure(&camcc_pll0, regmap, &camcc_pll0_config); 2036 clk_fabia_pll_configure(&camcc_pll1, regmap, &camcc_pll1_config); 2037 clk_agera_pll_configure(&camcc_pll2, regmap, &camcc_pll2_config); 2038 clk_fabia_pll_configure(&camcc_pll3, regmap, &camcc_pll3_config); 2039 clk_fabia_pll_configure(&camcc_pll4, regmap, &camcc_pll3_config); 2040 2041 /* Keep some clocks always-on */ 2042 qcom_branch_set_clk_en(regmap, 0xc1a0); /* CAMCC_GDSC_CLK */ 2043 2044 return qcom_cc_really_probe(&pdev->dev, &camcc_sm7150_desc, regmap); 2045 } 2046 2047 static struct platform_driver camcc_sm7150_driver = { 2048 .probe = camcc_sm7150_probe, 2049 .driver = { 2050 .name = "camcc-sm7150", 2051 .of_match_table = camcc_sm7150_match_table, 2052 }, 2053 }; 2054 2055 module_platform_driver(camcc_sm7150_driver); 2056 2057 MODULE_DESCRIPTION("Qualcomm SM7150 Camera Clock Controller"); 2058 MODULE_LICENSE("GPL"); 2059