1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2018, 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/mod_devicetable.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 13 #include <dt-bindings/clock/qcom,sm7150-camcc.h> 14 15 #include "clk-alpha-pll.h" 16 #include "clk-branch.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "common.h" 20 #include "gdsc.h" 21 22 enum { 23 DT_BI_TCXO, 24 DT_BI_TCXO_AO, 25 DT_CHIP_SLEEP_CLK, 26 }; 27 28 enum { 29 P_BI_TCXO, 30 P_BI_TCXO_MX, 31 P_CAMCC_PLL0_OUT_EVEN, 32 P_CAMCC_PLL0_OUT_MAIN, 33 P_CAMCC_PLL0_OUT_ODD, 34 P_CAMCC_PLL1_OUT_EVEN, 35 P_CAMCC_PLL2_OUT_AUX, 36 P_CAMCC_PLL2_OUT_EARLY, 37 P_CAMCC_PLL2_OUT_MAIN, 38 P_CAMCC_PLL3_OUT_EVEN, 39 P_CAMCC_PLL4_OUT_EVEN, 40 P_CHIP_SLEEP_CLK, 41 }; 42 43 static const struct pll_vco fabia_vco[] = { 44 { 249600000, 2000000000, 0 }, 45 }; 46 47 /* 1200MHz configuration */ 48 static const struct alpha_pll_config camcc_pll0_config = { 49 .l = 0x3e, 50 .alpha = 0x8000, 51 .post_div_mask = 0xff << 8, 52 .post_div_val = 0x31 << 8, 53 .test_ctl_val = 0x40000000, 54 }; 55 56 static struct clk_alpha_pll camcc_pll0 = { 57 .offset = 0x0, 58 .vco_table = fabia_vco, 59 .num_vco = ARRAY_SIZE(fabia_vco), 60 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 61 .clkr = { 62 .hw.init = &(const struct clk_init_data) { 63 .name = "camcc_pll0", 64 .parent_data = &(const struct clk_parent_data) { 65 .index = DT_BI_TCXO, 66 }, 67 .num_parents = 1, 68 .ops = &clk_alpha_pll_fabia_ops, 69 }, 70 }, 71 }; 72 73 static struct clk_fixed_factor camcc_pll0_out_even = { 74 .mult = 1, 75 .div = 2, 76 .hw.init = &(const struct clk_init_data) { 77 .name = "camcc_pll0_out_even", 78 .parent_hws = (const struct clk_hw*[]) { 79 &camcc_pll0.clkr.hw, 80 }, 81 .num_parents = 1, 82 .ops = &clk_fixed_factor_ops, 83 }, 84 }; 85 86 static struct clk_fixed_factor camcc_pll0_out_odd = { 87 .mult = 1, 88 .div = 3, 89 .hw.init = &(const struct clk_init_data) { 90 .name = "camcc_pll0_out_odd", 91 .parent_hws = (const struct clk_hw*[]) { 92 &camcc_pll0.clkr.hw, 93 }, 94 .num_parents = 1, 95 .ops = &clk_fixed_factor_ops, 96 }, 97 }; 98 99 /* 680MHz configuration */ 100 static const struct alpha_pll_config camcc_pll1_config = { 101 .l = 0x23, 102 .alpha = 0x6aaa, 103 .post_div_mask = 0xf << 8, 104 .post_div_val = 0x1 << 8, 105 .test_ctl_val = 0x40000000, 106 }; 107 108 static struct clk_alpha_pll camcc_pll1 = { 109 .offset = 0x1000, 110 .vco_table = fabia_vco, 111 .num_vco = ARRAY_SIZE(fabia_vco), 112 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 113 .clkr = { 114 .hw.init = &(const struct clk_init_data) { 115 .name = "camcc_pll1", 116 .parent_data = &(const struct clk_parent_data) { 117 .index = DT_BI_TCXO, 118 }, 119 .num_parents = 1, 120 .ops = &clk_alpha_pll_fabia_ops, 121 }, 122 }, 123 }; 124 125 static struct clk_fixed_factor camcc_pll1_out_even = { 126 .mult = 1, 127 .div = 2, 128 .hw.init = &(const struct clk_init_data) { 129 .name = "camcc_pll1_out_even", 130 .parent_hws = (const struct clk_hw*[]) { 131 &camcc_pll1.clkr.hw, 132 }, 133 .num_parents = 1, 134 .flags = CLK_SET_RATE_PARENT, 135 .ops = &clk_fixed_factor_ops, 136 }, 137 }; 138 139 /* 1920MHz configuration */ 140 static const struct alpha_pll_config camcc_pll2_config = { 141 .l = 0x64, 142 .post_div_val = 0x3 << 8, 143 .post_div_mask = 0x3 << 8, 144 .early_output_mask = BIT(3), 145 .aux_output_mask = BIT(1), 146 .main_output_mask = BIT(0), 147 .config_ctl_hi_val = 0x400003d6, 148 .config_ctl_val = 0x20000954, 149 }; 150 151 static struct clk_alpha_pll camcc_pll2 = { 152 .offset = 0x2000, 153 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 154 .clkr = { 155 .hw.init = &(const struct clk_init_data) { 156 .name = "camcc_pll2", 157 .parent_data = &(const struct clk_parent_data) { 158 .index = DT_BI_TCXO, 159 }, 160 .num_parents = 1, 161 .ops = &clk_alpha_pll_agera_ops, 162 }, 163 }, 164 }; 165 166 static struct clk_fixed_factor camcc_pll2_out_early = { 167 .mult = 1, 168 .div = 2, 169 .hw.init = &(const struct clk_init_data) { 170 .name = "camcc_pll2_out_early", 171 .parent_hws = (const struct clk_hw*[]) { 172 &camcc_pll2.clkr.hw, 173 }, 174 .num_parents = 1, 175 .ops = &clk_fixed_factor_ops, 176 }, 177 }; 178 179 static struct clk_alpha_pll_postdiv camcc_pll2_out_aux = { 180 .offset = 0x2000, 181 .post_div_shift = 8, 182 .width = 2, 183 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 184 .clkr.hw.init = &(const struct clk_init_data) { 185 .name = "camcc_pll2_out_aux", 186 .parent_hws = (const struct clk_hw*[]) { 187 &camcc_pll2.clkr.hw, 188 }, 189 .num_parents = 1, 190 .flags = CLK_SET_RATE_PARENT, 191 .ops = &clk_alpha_pll_postdiv_ops, 192 }, 193 }; 194 195 static struct clk_alpha_pll_postdiv camcc_pll2_out_main = { 196 .offset = 0x2000, 197 .post_div_shift = 8, 198 .width = 2, 199 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 200 .clkr.hw.init = &(const struct clk_init_data) { 201 .name = "camcc_pll2_out_main", 202 .parent_hws = (const struct clk_hw*[]) { 203 &camcc_pll2.clkr.hw, 204 }, 205 .num_parents = 1, 206 .flags = CLK_SET_RATE_PARENT, 207 .ops = &clk_alpha_pll_postdiv_ops, 208 }, 209 }; 210 211 /* 760MHz configuration */ 212 static const struct alpha_pll_config camcc_pll3_config = { 213 .l = 0x27, 214 .alpha = 0x9555, 215 .post_div_mask = 0xf << 8, 216 .post_div_val = 0x1 << 8, 217 .test_ctl_val = 0x40000000, 218 }; 219 220 static struct clk_alpha_pll camcc_pll3 = { 221 .offset = 0x3000, 222 .vco_table = fabia_vco, 223 .num_vco = ARRAY_SIZE(fabia_vco), 224 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 225 .clkr = { 226 .hw.init = &(const struct clk_init_data) { 227 .name = "camcc_pll3", 228 .parent_data = &(const struct clk_parent_data) { 229 .index = DT_BI_TCXO, 230 }, 231 .num_parents = 1, 232 .ops = &clk_alpha_pll_fabia_ops, 233 }, 234 }, 235 }; 236 237 static struct clk_fixed_factor camcc_pll3_out_even = { 238 .mult = 1, 239 .div = 2, 240 .hw.init = &(const struct clk_init_data) { 241 .name = "camcc_pll3_out_even", 242 .parent_hws = (const struct clk_hw*[]) { 243 &camcc_pll3.clkr.hw, 244 }, 245 .num_parents = 1, 246 .flags = CLK_SET_RATE_PARENT, 247 .ops = &clk_fixed_factor_ops, 248 }, 249 }; 250 251 static struct clk_alpha_pll camcc_pll4 = { 252 .offset = 0x4000, 253 .vco_table = fabia_vco, 254 .num_vco = ARRAY_SIZE(fabia_vco), 255 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 256 .clkr = { 257 .hw.init = &(const struct clk_init_data) { 258 .name = "camcc_pll4", 259 .parent_data = &(const struct clk_parent_data) { 260 .index = DT_BI_TCXO, 261 }, 262 .num_parents = 1, 263 .ops = &clk_alpha_pll_fabia_ops, 264 }, 265 }, 266 }; 267 268 static struct clk_fixed_factor camcc_pll4_out_even = { 269 .mult = 1, 270 .div = 2, 271 .hw.init = &(const struct clk_init_data) { 272 .name = "camcc_pll4_out_even", 273 .parent_hws = (const struct clk_hw*[]) { 274 &camcc_pll4.clkr.hw, 275 }, 276 .num_parents = 1, 277 .flags = CLK_SET_RATE_PARENT, 278 .ops = &clk_fixed_factor_ops, 279 }, 280 }; 281 282 static const struct parent_map camcc_parent_map_0[] = { 283 { P_BI_TCXO, 0 }, 284 { P_CAMCC_PLL0_OUT_MAIN, 1 }, 285 { P_CAMCC_PLL0_OUT_EVEN, 2 }, 286 { P_CAMCC_PLL0_OUT_ODD, 3 }, 287 { P_CAMCC_PLL2_OUT_MAIN, 5 }, 288 }; 289 290 static const struct clk_parent_data camcc_parent_data_0[] = { 291 { .index = DT_BI_TCXO }, 292 { .hw = &camcc_pll0.clkr.hw }, 293 { .hw = &camcc_pll0_out_even.hw }, 294 { .hw = &camcc_pll0_out_odd.hw }, 295 { .hw = &camcc_pll2_out_main.clkr.hw }, 296 }; 297 298 static const struct parent_map camcc_parent_map_1[] = { 299 { P_BI_TCXO, 0 }, 300 { P_CAMCC_PLL0_OUT_MAIN, 1 }, 301 { P_CAMCC_PLL0_OUT_EVEN, 2 }, 302 { P_CAMCC_PLL0_OUT_ODD, 3 }, 303 { P_CAMCC_PLL1_OUT_EVEN, 4 }, 304 { P_CAMCC_PLL2_OUT_EARLY, 5 }, 305 }; 306 307 static const struct clk_parent_data camcc_parent_data_1[] = { 308 { .index = DT_BI_TCXO }, 309 { .hw = &camcc_pll0.clkr.hw }, 310 { .hw = &camcc_pll0_out_even.hw }, 311 { .hw = &camcc_pll0_out_odd.hw }, 312 { .hw = &camcc_pll1_out_even.hw }, 313 { .hw = &camcc_pll2_out_early.hw }, 314 }; 315 316 static const struct parent_map camcc_parent_map_2[] = { 317 { P_BI_TCXO_MX, 0 }, 318 { P_CAMCC_PLL2_OUT_AUX, 5 }, 319 }; 320 321 static const struct clk_parent_data camcc_parent_data_2[] = { 322 { .index = DT_BI_TCXO }, 323 { .hw = &camcc_pll2_out_aux.clkr.hw }, 324 }; 325 326 static const struct parent_map camcc_parent_map_3[] = { 327 { P_BI_TCXO, 0 }, 328 { P_CAMCC_PLL0_OUT_MAIN, 1 }, 329 { P_CAMCC_PLL0_OUT_EVEN, 2 }, 330 { P_CAMCC_PLL0_OUT_ODD, 3 }, 331 { P_CAMCC_PLL2_OUT_EARLY, 5 }, 332 { P_CAMCC_PLL4_OUT_EVEN, 6 }, 333 }; 334 335 static const struct clk_parent_data camcc_parent_data_3[] = { 336 { .index = DT_BI_TCXO }, 337 { .hw = &camcc_pll0.clkr.hw }, 338 { .hw = &camcc_pll0_out_even.hw }, 339 { .hw = &camcc_pll0_out_odd.hw }, 340 { .hw = &camcc_pll2_out_early.hw }, 341 { .hw = &camcc_pll4_out_even.hw }, 342 }; 343 344 static const struct parent_map camcc_parent_map_4[] = { 345 { P_BI_TCXO, 0 }, 346 { P_CAMCC_PLL3_OUT_EVEN, 6 }, 347 }; 348 349 static const struct clk_parent_data camcc_parent_data_4[] = { 350 { .index = DT_BI_TCXO }, 351 { .hw = &camcc_pll3_out_even.hw }, 352 }; 353 354 static const struct parent_map camcc_parent_map_5[] = { 355 { P_BI_TCXO, 0 }, 356 { P_CAMCC_PLL4_OUT_EVEN, 6 }, 357 }; 358 359 static const struct clk_parent_data camcc_parent_data_5[] = { 360 { .index = DT_BI_TCXO }, 361 { .hw = &camcc_pll4_out_even.hw }, 362 }; 363 364 static const struct parent_map camcc_parent_map_6[] = { 365 { P_BI_TCXO, 0 }, 366 { P_CAMCC_PLL1_OUT_EVEN, 4 }, 367 }; 368 369 static const struct clk_parent_data camcc_parent_data_6[] = { 370 { .index = DT_BI_TCXO }, 371 { .hw = &camcc_pll1_out_even.hw }, 372 }; 373 374 static const struct parent_map camcc_parent_map_7[] = { 375 { P_CHIP_SLEEP_CLK, 0 }, 376 }; 377 378 static const struct clk_parent_data camcc_parent_data_7[] = { 379 { .index = DT_CHIP_SLEEP_CLK }, 380 }; 381 382 static const struct parent_map camcc_parent_map_8[] = { 383 { P_BI_TCXO, 0 }, 384 { P_CAMCC_PLL0_OUT_ODD, 3 }, 385 }; 386 387 static const struct clk_parent_data camcc_parent_data_8[] = { 388 { .index = DT_BI_TCXO }, 389 { .hw = &camcc_pll0_out_odd.hw }, 390 }; 391 392 static const struct parent_map camcc_parent_map_9[] = { 393 { P_BI_TCXO, 0 }, 394 }; 395 396 static const struct clk_parent_data camcc_parent_data_9[] = { 397 { .index = DT_BI_TCXO_AO }, 398 }; 399 400 static const struct freq_tbl ftbl_camcc_bps_clk_src[] = { 401 F(19200000, P_BI_TCXO, 1, 0, 0), 402 F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0), 403 F(200000000, P_CAMCC_PLL0_OUT_ODD, 2, 0, 0), 404 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 405 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0), 406 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 407 { } 408 }; 409 410 static struct clk_rcg2 camcc_bps_clk_src = { 411 .cmd_rcgr = 0x7010, 412 .mnd_width = 0, 413 .hid_width = 5, 414 .parent_map = camcc_parent_map_0, 415 .freq_tbl = ftbl_camcc_bps_clk_src, 416 .clkr.hw.init = &(const struct clk_init_data) { 417 .name = "camcc_bps_clk_src", 418 .parent_data = camcc_parent_data_0, 419 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 420 .ops = &clk_rcg2_shared_ops, 421 }, 422 }; 423 424 static const struct freq_tbl ftbl_camcc_camnoc_axi_clk_src[] = { 425 F(19200000, P_BI_TCXO, 1, 0, 0), 426 F(150000000, P_CAMCC_PLL0_OUT_EVEN, 4, 0, 0), 427 F(240000000, P_CAMCC_PLL2_OUT_MAIN, 2, 0, 0), 428 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0), 429 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), 430 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0), 431 { } 432 }; 433 434 static struct clk_rcg2 camcc_camnoc_axi_clk_src = { 435 .cmd_rcgr = 0xc12c, 436 .mnd_width = 0, 437 .hid_width = 5, 438 .parent_map = camcc_parent_map_0, 439 .freq_tbl = ftbl_camcc_camnoc_axi_clk_src, 440 .clkr.hw.init = &(const struct clk_init_data) { 441 .name = "camcc_camnoc_axi_clk_src", 442 .parent_data = camcc_parent_data_0, 443 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 444 .ops = &clk_rcg2_shared_ops, 445 }, 446 }; 447 448 static const struct freq_tbl ftbl_camcc_cci_0_clk_src[] = { 449 F(19200000, P_BI_TCXO, 1, 0, 0), 450 F(37500000, P_CAMCC_PLL0_OUT_EVEN, 16, 0, 0), 451 { } 452 }; 453 454 static struct clk_rcg2 camcc_cci_0_clk_src = { 455 .cmd_rcgr = 0xc0c4, 456 .mnd_width = 8, 457 .hid_width = 5, 458 .parent_map = camcc_parent_map_0, 459 .freq_tbl = ftbl_camcc_cci_0_clk_src, 460 .clkr.hw.init = &(const struct clk_init_data) { 461 .name = "camcc_cci_0_clk_src", 462 .parent_data = camcc_parent_data_0, 463 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 464 .ops = &clk_rcg2_ops, 465 }, 466 }; 467 468 static struct clk_rcg2 camcc_cci_1_clk_src = { 469 .cmd_rcgr = 0xc0e0, 470 .mnd_width = 8, 471 .hid_width = 5, 472 .parent_map = camcc_parent_map_0, 473 .freq_tbl = ftbl_camcc_cci_0_clk_src, 474 .clkr.hw.init = &(const struct clk_init_data) { 475 .name = "camcc_cci_1_clk_src", 476 .parent_data = camcc_parent_data_0, 477 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 478 .ops = &clk_rcg2_ops, 479 }, 480 }; 481 482 static const struct freq_tbl ftbl_camcc_cphy_rx_clk_src[] = { 483 F(19200000, P_BI_TCXO, 1, 0, 0), 484 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0), 485 F(384000000, P_CAMCC_PLL2_OUT_EARLY, 2.5, 0, 0), 486 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), 487 { } 488 }; 489 490 static struct clk_rcg2 camcc_cphy_rx_clk_src = { 491 .cmd_rcgr = 0xa064, 492 .mnd_width = 0, 493 .hid_width = 5, 494 .parent_map = camcc_parent_map_1, 495 .freq_tbl = ftbl_camcc_cphy_rx_clk_src, 496 .clkr.hw.init = &(const struct clk_init_data) { 497 .name = "camcc_cphy_rx_clk_src", 498 .parent_data = camcc_parent_data_1, 499 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 500 .ops = &clk_rcg2_ops, 501 }, 502 }; 503 504 static const struct freq_tbl ftbl_camcc_csi0phytimer_clk_src[] = { 505 F(19200000, P_BI_TCXO, 1, 0, 0), 506 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0), 507 { } 508 }; 509 510 static struct clk_rcg2 camcc_csi0phytimer_clk_src = { 511 .cmd_rcgr = 0x6004, 512 .mnd_width = 0, 513 .hid_width = 5, 514 .parent_map = camcc_parent_map_0, 515 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, 516 .clkr.hw.init = &(const struct clk_init_data) { 517 .name = "camcc_csi0phytimer_clk_src", 518 .parent_data = camcc_parent_data_0, 519 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 520 .ops = &clk_rcg2_ops, 521 }, 522 }; 523 524 static struct clk_rcg2 camcc_csi1phytimer_clk_src = { 525 .cmd_rcgr = 0x6028, 526 .mnd_width = 0, 527 .hid_width = 5, 528 .parent_map = camcc_parent_map_0, 529 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, 530 .clkr.hw.init = &(const struct clk_init_data) { 531 .name = "camcc_csi1phytimer_clk_src", 532 .parent_data = camcc_parent_data_0, 533 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 534 .ops = &clk_rcg2_ops, 535 }, 536 }; 537 538 static struct clk_rcg2 camcc_csi2phytimer_clk_src = { 539 .cmd_rcgr = 0x604c, 540 .mnd_width = 0, 541 .hid_width = 5, 542 .parent_map = camcc_parent_map_0, 543 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, 544 .clkr.hw.init = &(const struct clk_init_data) { 545 .name = "camcc_csi2phytimer_clk_src", 546 .parent_data = camcc_parent_data_0, 547 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 548 .ops = &clk_rcg2_ops, 549 }, 550 }; 551 552 static struct clk_rcg2 camcc_csi3phytimer_clk_src = { 553 .cmd_rcgr = 0x6070, 554 .mnd_width = 0, 555 .hid_width = 5, 556 .parent_map = camcc_parent_map_0, 557 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, 558 .clkr.hw.init = &(const struct clk_init_data) { 559 .name = "camcc_csi3phytimer_clk_src", 560 .parent_data = camcc_parent_data_0, 561 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 562 .ops = &clk_rcg2_ops, 563 }, 564 }; 565 566 static const struct freq_tbl ftbl_camcc_fast_ahb_clk_src[] = { 567 F(19200000, P_BI_TCXO, 1, 0, 0), 568 F(50000000, P_CAMCC_PLL0_OUT_EVEN, 12, 0, 0), 569 F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0), 570 F(200000000, P_CAMCC_PLL0_OUT_EVEN, 3, 0, 0), 571 F(300000000, P_CAMCC_PLL0_OUT_MAIN, 4, 0, 0), 572 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), 573 { } 574 }; 575 576 static struct clk_rcg2 camcc_fast_ahb_clk_src = { 577 .cmd_rcgr = 0x703c, 578 .mnd_width = 0, 579 .hid_width = 5, 580 .parent_map = camcc_parent_map_0, 581 .freq_tbl = ftbl_camcc_fast_ahb_clk_src, 582 .clkr.hw.init = &(const struct clk_init_data) { 583 .name = "camcc_fast_ahb_clk_src", 584 .parent_data = camcc_parent_data_0, 585 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 586 .ops = &clk_rcg2_ops, 587 }, 588 }; 589 590 static const struct freq_tbl ftbl_camcc_fd_core_clk_src[] = { 591 F(19200000, P_BI_TCXO, 1, 0, 0), 592 F(380000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), 593 F(384000000, P_CAMCC_PLL2_OUT_EARLY, 2.5, 0, 0), 594 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), 595 F(480000000, P_CAMCC_PLL2_OUT_EARLY, 2, 0, 0), 596 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 597 { } 598 }; 599 600 static struct clk_rcg2 camcc_fd_core_clk_src = { 601 .cmd_rcgr = 0xc09c, 602 .mnd_width = 0, 603 .hid_width = 5, 604 .parent_map = camcc_parent_map_3, 605 .freq_tbl = ftbl_camcc_fd_core_clk_src, 606 .clkr.hw.init = &(const struct clk_init_data) { 607 .name = "camcc_fd_core_clk_src", 608 .parent_data = camcc_parent_data_3, 609 .num_parents = ARRAY_SIZE(camcc_parent_data_3), 610 .flags = CLK_SET_RATE_PARENT, 611 .ops = &clk_rcg2_shared_ops, 612 }, 613 }; 614 615 static const struct freq_tbl ftbl_camcc_icp_clk_src[] = { 616 F(19200000, P_BI_TCXO, 1, 0, 0), 617 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 618 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 619 { } 620 }; 621 622 static struct clk_rcg2 camcc_icp_clk_src = { 623 .cmd_rcgr = 0xc074, 624 .mnd_width = 0, 625 .hid_width = 5, 626 .parent_map = camcc_parent_map_0, 627 .freq_tbl = ftbl_camcc_icp_clk_src, 628 .clkr.hw.init = &(const struct clk_init_data) { 629 .name = "camcc_icp_clk_src", 630 .parent_data = camcc_parent_data_0, 631 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 632 .ops = &clk_rcg2_shared_ops, 633 }, 634 }; 635 636 static const struct freq_tbl ftbl_camcc_ife_0_clk_src[] = { 637 F(19200000, P_BI_TCXO, 1, 0, 0), 638 F(380000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), 639 F(510000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), 640 F(637000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), 641 F(760000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), 642 { } 643 }; 644 645 static struct clk_rcg2 camcc_ife_0_clk_src = { 646 .cmd_rcgr = 0xa010, 647 .mnd_width = 0, 648 .hid_width = 5, 649 .parent_map = camcc_parent_map_4, 650 .freq_tbl = ftbl_camcc_ife_0_clk_src, 651 .clkr.hw.init = &(const struct clk_init_data) { 652 .name = "camcc_ife_0_clk_src", 653 .parent_data = camcc_parent_data_4, 654 .num_parents = ARRAY_SIZE(camcc_parent_data_4), 655 .flags = CLK_SET_RATE_PARENT, 656 .ops = &clk_rcg2_shared_ops, 657 }, 658 }; 659 660 static const struct freq_tbl ftbl_camcc_ife_0_csid_clk_src[] = { 661 F(19200000, P_BI_TCXO, 1, 0, 0), 662 F(75000000, P_CAMCC_PLL0_OUT_EVEN, 8, 0, 0), 663 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0), 664 F(384000000, P_CAMCC_PLL2_OUT_EARLY, 2.5, 0, 0), 665 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), 666 { } 667 }; 668 669 static struct clk_rcg2 camcc_ife_0_csid_clk_src = { 670 .cmd_rcgr = 0xa03c, 671 .mnd_width = 0, 672 .hid_width = 5, 673 .parent_map = camcc_parent_map_1, 674 .freq_tbl = ftbl_camcc_ife_0_csid_clk_src, 675 .clkr.hw.init = &(const struct clk_init_data) { 676 .name = "camcc_ife_0_csid_clk_src", 677 .parent_data = camcc_parent_data_1, 678 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 679 .ops = &clk_rcg2_shared_ops, 680 }, 681 }; 682 683 static const struct freq_tbl ftbl_camcc_ife_1_clk_src[] = { 684 F(19200000, P_BI_TCXO, 1, 0, 0), 685 F(380000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), 686 F(510000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), 687 F(637000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), 688 F(760000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), 689 { } 690 }; 691 692 static struct clk_rcg2 camcc_ife_1_clk_src = { 693 .cmd_rcgr = 0xb010, 694 .mnd_width = 0, 695 .hid_width = 5, 696 .parent_map = camcc_parent_map_5, 697 .freq_tbl = ftbl_camcc_ife_1_clk_src, 698 .clkr.hw.init = &(const struct clk_init_data) { 699 .name = "camcc_ife_1_clk_src", 700 .parent_data = camcc_parent_data_5, 701 .num_parents = ARRAY_SIZE(camcc_parent_data_5), 702 .flags = CLK_SET_RATE_PARENT, 703 .ops = &clk_rcg2_shared_ops, 704 }, 705 }; 706 707 static struct clk_rcg2 camcc_ife_1_csid_clk_src = { 708 .cmd_rcgr = 0xb034, 709 .mnd_width = 0, 710 .hid_width = 5, 711 .parent_map = camcc_parent_map_1, 712 .freq_tbl = ftbl_camcc_ife_0_csid_clk_src, 713 .clkr.hw.init = &(const struct clk_init_data) { 714 .name = "camcc_ife_1_csid_clk_src", 715 .parent_data = camcc_parent_data_1, 716 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 717 .ops = &clk_rcg2_shared_ops, 718 }, 719 }; 720 721 static const struct freq_tbl ftbl_camcc_ife_lite_clk_src[] = { 722 F(19200000, P_BI_TCXO, 1, 0, 0), 723 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0), 724 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 725 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0), 726 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 727 { } 728 }; 729 730 static struct clk_rcg2 camcc_ife_lite_clk_src = { 731 .cmd_rcgr = 0xc004, 732 .mnd_width = 0, 733 .hid_width = 5, 734 .parent_map = camcc_parent_map_0, 735 .freq_tbl = ftbl_camcc_ife_lite_clk_src, 736 .clkr.hw.init = &(const struct clk_init_data) { 737 .name = "camcc_ife_lite_clk_src", 738 .parent_data = camcc_parent_data_0, 739 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 740 .ops = &clk_rcg2_ops, 741 }, 742 }; 743 744 static struct clk_rcg2 camcc_ife_lite_csid_clk_src = { 745 .cmd_rcgr = 0xc020, 746 .mnd_width = 0, 747 .hid_width = 5, 748 .parent_map = camcc_parent_map_1, 749 .freq_tbl = ftbl_camcc_cphy_rx_clk_src, 750 .clkr.hw.init = &(const struct clk_init_data) { 751 .name = "camcc_ife_lite_csid_clk_src", 752 .parent_data = camcc_parent_data_1, 753 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 754 .ops = &clk_rcg2_shared_ops, 755 }, 756 }; 757 758 static const struct freq_tbl ftbl_camcc_ipe_0_clk_src[] = { 759 F(19200000, P_BI_TCXO, 1, 0, 0), 760 F(340000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), 761 F(430000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), 762 F(520000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), 763 F(600000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), 764 { } 765 }; 766 767 static struct clk_rcg2 camcc_ipe_0_clk_src = { 768 .cmd_rcgr = 0x8010, 769 .mnd_width = 0, 770 .hid_width = 5, 771 .parent_map = camcc_parent_map_6, 772 .freq_tbl = ftbl_camcc_ipe_0_clk_src, 773 .clkr.hw.init = &(const struct clk_init_data) { 774 .name = "camcc_ipe_0_clk_src", 775 .parent_data = camcc_parent_data_6, 776 .num_parents = ARRAY_SIZE(camcc_parent_data_6), 777 .flags = CLK_SET_RATE_PARENT, 778 .ops = &clk_rcg2_shared_ops, 779 }, 780 }; 781 782 static struct clk_rcg2 camcc_jpeg_clk_src = { 783 .cmd_rcgr = 0xc048, 784 .mnd_width = 0, 785 .hid_width = 5, 786 .parent_map = camcc_parent_map_0, 787 .freq_tbl = ftbl_camcc_bps_clk_src, 788 .clkr.hw.init = &(const struct clk_init_data) { 789 .name = "camcc_jpeg_clk_src", 790 .parent_data = camcc_parent_data_0, 791 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 792 .ops = &clk_rcg2_shared_ops, 793 }, 794 }; 795 796 static const struct freq_tbl ftbl_camcc_lrme_clk_src[] = { 797 F(19200000, P_BI_TCXO, 1, 0, 0), 798 F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0), 799 F(240000000, P_CAMCC_PLL2_OUT_MAIN, 2, 0, 0), 800 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0), 801 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0), 802 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), 803 { } 804 }; 805 806 static struct clk_rcg2 camcc_lrme_clk_src = { 807 .cmd_rcgr = 0xc100, 808 .mnd_width = 0, 809 .hid_width = 5, 810 .parent_map = camcc_parent_map_0, 811 .freq_tbl = ftbl_camcc_lrme_clk_src, 812 .clkr.hw.init = &(const struct clk_init_data) { 813 .name = "camcc_lrme_clk_src", 814 .parent_data = camcc_parent_data_0, 815 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 816 .ops = &clk_rcg2_shared_ops, 817 }, 818 }; 819 820 static const struct freq_tbl ftbl_camcc_mclk0_clk_src[] = { 821 F(19200000, P_BI_TCXO_MX, 1, 0, 0), 822 F(24000000, P_CAMCC_PLL2_OUT_AUX, 1, 1, 20), 823 F(34285714, P_CAMCC_PLL2_OUT_AUX, 14, 0, 0), 824 { } 825 }; 826 827 static struct clk_rcg2 camcc_mclk0_clk_src = { 828 .cmd_rcgr = 0x5004, 829 .mnd_width = 8, 830 .hid_width = 5, 831 .parent_map = camcc_parent_map_2, 832 .freq_tbl = ftbl_camcc_mclk0_clk_src, 833 .clkr.hw.init = &(const struct clk_init_data) { 834 .name = "camcc_mclk0_clk_src", 835 .parent_data = camcc_parent_data_2, 836 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 837 .ops = &clk_rcg2_ops, 838 }, 839 }; 840 841 static struct clk_rcg2 camcc_mclk1_clk_src = { 842 .cmd_rcgr = 0x5024, 843 .mnd_width = 8, 844 .hid_width = 5, 845 .parent_map = camcc_parent_map_2, 846 .freq_tbl = ftbl_camcc_mclk0_clk_src, 847 .clkr.hw.init = &(const struct clk_init_data) { 848 .name = "camcc_mclk1_clk_src", 849 .parent_data = camcc_parent_data_2, 850 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 851 .ops = &clk_rcg2_ops, 852 }, 853 }; 854 855 static struct clk_rcg2 camcc_mclk2_clk_src = { 856 .cmd_rcgr = 0x5044, 857 .mnd_width = 8, 858 .hid_width = 5, 859 .parent_map = camcc_parent_map_2, 860 .freq_tbl = ftbl_camcc_mclk0_clk_src, 861 .clkr.hw.init = &(const struct clk_init_data) { 862 .name = "camcc_mclk2_clk_src", 863 .parent_data = camcc_parent_data_2, 864 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 865 .ops = &clk_rcg2_ops, 866 }, 867 }; 868 869 static struct clk_rcg2 camcc_mclk3_clk_src = { 870 .cmd_rcgr = 0x5064, 871 .mnd_width = 8, 872 .hid_width = 5, 873 .parent_map = camcc_parent_map_2, 874 .freq_tbl = ftbl_camcc_mclk0_clk_src, 875 .clkr.hw.init = &(const struct clk_init_data) { 876 .name = "camcc_mclk3_clk_src", 877 .parent_data = camcc_parent_data_2, 878 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 879 .ops = &clk_rcg2_ops, 880 }, 881 }; 882 883 static const struct freq_tbl ftbl_camcc_sleep_clk_src[] = { 884 F(32000, P_CHIP_SLEEP_CLK, 1, 0, 0), 885 { } 886 }; 887 888 static struct clk_rcg2 camcc_sleep_clk_src = { 889 .cmd_rcgr = 0xc1a4, 890 .mnd_width = 0, 891 .hid_width = 5, 892 .parent_map = camcc_parent_map_7, 893 .freq_tbl = ftbl_camcc_sleep_clk_src, 894 .clkr.hw.init = &(const struct clk_init_data) { 895 .name = "camcc_sleep_clk_src", 896 .parent_data = camcc_parent_data_7, 897 .num_parents = ARRAY_SIZE(camcc_parent_data_7), 898 .ops = &clk_rcg2_ops, 899 }, 900 }; 901 902 static const struct freq_tbl ftbl_camcc_slow_ahb_clk_src[] = { 903 F(19200000, P_BI_TCXO, 1, 0, 0), 904 F(80000000, P_CAMCC_PLL0_OUT_ODD, 5, 0, 0), 905 { } 906 }; 907 908 static struct clk_rcg2 camcc_slow_ahb_clk_src = { 909 .cmd_rcgr = 0x7058, 910 .mnd_width = 0, 911 .hid_width = 5, 912 .parent_map = camcc_parent_map_8, 913 .freq_tbl = ftbl_camcc_slow_ahb_clk_src, 914 .clkr.hw.init = &(const struct clk_init_data) { 915 .name = "camcc_slow_ahb_clk_src", 916 .parent_data = camcc_parent_data_8, 917 .num_parents = ARRAY_SIZE(camcc_parent_data_8), 918 .ops = &clk_rcg2_shared_ops, 919 }, 920 }; 921 922 static const struct freq_tbl ftbl_camcc_xo_clk_src[] = { 923 F(19200000, P_BI_TCXO, 1, 0, 0), 924 { } 925 }; 926 927 static struct clk_rcg2 camcc_xo_clk_src = { 928 .cmd_rcgr = 0xc188, 929 .mnd_width = 0, 930 .hid_width = 5, 931 .parent_map = camcc_parent_map_9, 932 .freq_tbl = ftbl_camcc_xo_clk_src, 933 .clkr.hw.init = &(const struct clk_init_data) { 934 .name = "camcc_xo_clk_src", 935 .parent_data = camcc_parent_data_9, 936 .num_parents = ARRAY_SIZE(camcc_parent_data_9), 937 .ops = &clk_rcg2_ops, 938 }, 939 }; 940 941 static struct clk_branch camcc_bps_ahb_clk = { 942 .halt_reg = 0x7070, 943 .halt_check = BRANCH_HALT, 944 .clkr = { 945 .enable_reg = 0x7070, 946 .enable_mask = BIT(0), 947 .hw.init = &(const struct clk_init_data) { 948 .name = "camcc_bps_ahb_clk", 949 .parent_hws = (const struct clk_hw*[]) { 950 &camcc_slow_ahb_clk_src.clkr.hw, 951 }, 952 .num_parents = 1, 953 .flags = CLK_SET_RATE_PARENT, 954 .ops = &clk_branch2_ops, 955 }, 956 }, 957 }; 958 959 static struct clk_branch camcc_bps_areg_clk = { 960 .halt_reg = 0x7054, 961 .halt_check = BRANCH_HALT, 962 .clkr = { 963 .enable_reg = 0x7054, 964 .enable_mask = BIT(0), 965 .hw.init = &(const struct clk_init_data) { 966 .name = "camcc_bps_areg_clk", 967 .parent_hws = (const struct clk_hw*[]) { 968 &camcc_fast_ahb_clk_src.clkr.hw, 969 }, 970 .num_parents = 1, 971 .flags = CLK_SET_RATE_PARENT, 972 .ops = &clk_branch2_ops, 973 }, 974 }, 975 }; 976 977 static struct clk_branch camcc_bps_axi_clk = { 978 .halt_reg = 0x7038, 979 .halt_check = BRANCH_HALT, 980 .clkr = { 981 .enable_reg = 0x7038, 982 .enable_mask = BIT(0), 983 .hw.init = &(const struct clk_init_data) { 984 .name = "camcc_bps_axi_clk", 985 .parent_hws = (const struct clk_hw*[]) { 986 &camcc_camnoc_axi_clk_src.clkr.hw, 987 }, 988 .num_parents = 1, 989 .flags = CLK_SET_RATE_PARENT, 990 .ops = &clk_branch2_ops, 991 }, 992 }, 993 }; 994 995 static struct clk_branch camcc_bps_clk = { 996 .halt_reg = 0x7028, 997 .halt_check = BRANCH_HALT, 998 .clkr = { 999 .enable_reg = 0x7028, 1000 .enable_mask = BIT(0), 1001 .hw.init = &(const struct clk_init_data) { 1002 .name = "camcc_bps_clk", 1003 .parent_hws = (const struct clk_hw*[]) { 1004 &camcc_bps_clk_src.clkr.hw, 1005 }, 1006 .num_parents = 1, 1007 .flags = CLK_SET_RATE_PARENT, 1008 .ops = &clk_branch2_ops, 1009 }, 1010 }, 1011 }; 1012 1013 static struct clk_branch camcc_camnoc_axi_clk = { 1014 .halt_reg = 0xc148, 1015 .halt_check = BRANCH_HALT, 1016 .clkr = { 1017 .enable_reg = 0xc148, 1018 .enable_mask = BIT(0), 1019 .hw.init = &(const struct clk_init_data) { 1020 .name = "camcc_camnoc_axi_clk", 1021 .parent_hws = (const struct clk_hw*[]) { 1022 &camcc_camnoc_axi_clk_src.clkr.hw, 1023 }, 1024 .num_parents = 1, 1025 .flags = CLK_SET_RATE_PARENT, 1026 .ops = &clk_branch2_ops, 1027 }, 1028 }, 1029 }; 1030 1031 static struct clk_branch camcc_camnoc_dcd_xo_clk = { 1032 .halt_reg = 0xc150, 1033 .halt_check = BRANCH_HALT, 1034 .clkr = { 1035 .enable_reg = 0xc150, 1036 .enable_mask = BIT(0), 1037 .hw.init = &(const struct clk_init_data) { 1038 .name = "camcc_camnoc_dcd_xo_clk", 1039 .parent_hws = (const struct clk_hw*[]) { 1040 &camcc_xo_clk_src.clkr.hw, 1041 }, 1042 .num_parents = 1, 1043 .flags = CLK_SET_RATE_PARENT, 1044 .ops = &clk_branch2_ops, 1045 }, 1046 }, 1047 }; 1048 1049 static struct clk_branch camcc_cci_0_clk = { 1050 .halt_reg = 0xc0dc, 1051 .halt_check = BRANCH_HALT, 1052 .clkr = { 1053 .enable_reg = 0xc0dc, 1054 .enable_mask = BIT(0), 1055 .hw.init = &(const struct clk_init_data) { 1056 .name = "camcc_cci_0_clk", 1057 .parent_hws = (const struct clk_hw*[]) { 1058 &camcc_cci_0_clk_src.clkr.hw, 1059 }, 1060 .num_parents = 1, 1061 .flags = CLK_SET_RATE_PARENT, 1062 .ops = &clk_branch2_ops, 1063 }, 1064 }, 1065 }; 1066 1067 static struct clk_branch camcc_cci_1_clk = { 1068 .halt_reg = 0xc0f8, 1069 .halt_check = BRANCH_HALT, 1070 .clkr = { 1071 .enable_reg = 0xc0f8, 1072 .enable_mask = BIT(0), 1073 .hw.init = &(const struct clk_init_data) { 1074 .name = "camcc_cci_1_clk", 1075 .parent_hws = (const struct clk_hw*[]) { 1076 &camcc_cci_1_clk_src.clkr.hw, 1077 }, 1078 .num_parents = 1, 1079 .flags = CLK_SET_RATE_PARENT, 1080 .ops = &clk_branch2_ops, 1081 }, 1082 }, 1083 }; 1084 1085 static struct clk_branch camcc_core_ahb_clk = { 1086 .halt_reg = 0xc184, 1087 .halt_check = BRANCH_HALT_DELAY, 1088 .clkr = { 1089 .enable_reg = 0xc184, 1090 .enable_mask = BIT(0), 1091 .hw.init = &(const struct clk_init_data) { 1092 .name = "camcc_core_ahb_clk", 1093 .parent_hws = (const struct clk_hw*[]) { 1094 &camcc_slow_ahb_clk_src.clkr.hw, 1095 }, 1096 .num_parents = 1, 1097 .flags = CLK_SET_RATE_PARENT, 1098 .ops = &clk_branch2_ops, 1099 }, 1100 }, 1101 }; 1102 1103 static struct clk_branch camcc_cpas_ahb_clk = { 1104 .halt_reg = 0xc124, 1105 .halt_check = BRANCH_HALT, 1106 .clkr = { 1107 .enable_reg = 0xc124, 1108 .enable_mask = BIT(0), 1109 .hw.init = &(const struct clk_init_data) { 1110 .name = "camcc_cpas_ahb_clk", 1111 .parent_hws = (const struct clk_hw*[]) { 1112 &camcc_slow_ahb_clk_src.clkr.hw, 1113 }, 1114 .num_parents = 1, 1115 .flags = CLK_SET_RATE_PARENT, 1116 .ops = &clk_branch2_ops, 1117 }, 1118 }, 1119 }; 1120 1121 static struct clk_branch camcc_csi0phytimer_clk = { 1122 .halt_reg = 0x601c, 1123 .halt_check = BRANCH_HALT, 1124 .clkr = { 1125 .enable_reg = 0x601c, 1126 .enable_mask = BIT(0), 1127 .hw.init = &(const struct clk_init_data) { 1128 .name = "camcc_csi0phytimer_clk", 1129 .parent_hws = (const struct clk_hw*[]) { 1130 &camcc_csi0phytimer_clk_src.clkr.hw, 1131 }, 1132 .num_parents = 1, 1133 .flags = CLK_SET_RATE_PARENT, 1134 .ops = &clk_branch2_ops, 1135 }, 1136 }, 1137 }; 1138 1139 static struct clk_branch camcc_csi1phytimer_clk = { 1140 .halt_reg = 0x6040, 1141 .halt_check = BRANCH_HALT, 1142 .clkr = { 1143 .enable_reg = 0x6040, 1144 .enable_mask = BIT(0), 1145 .hw.init = &(const struct clk_init_data) { 1146 .name = "camcc_csi1phytimer_clk", 1147 .parent_hws = (const struct clk_hw*[]) { 1148 &camcc_csi1phytimer_clk_src.clkr.hw, 1149 }, 1150 .num_parents = 1, 1151 .flags = CLK_SET_RATE_PARENT, 1152 .ops = &clk_branch2_ops, 1153 }, 1154 }, 1155 }; 1156 1157 static struct clk_branch camcc_csi2phytimer_clk = { 1158 .halt_reg = 0x6064, 1159 .halt_check = BRANCH_HALT, 1160 .clkr = { 1161 .enable_reg = 0x6064, 1162 .enable_mask = BIT(0), 1163 .hw.init = &(const struct clk_init_data) { 1164 .name = "camcc_csi2phytimer_clk", 1165 .parent_hws = (const struct clk_hw*[]) { 1166 &camcc_csi2phytimer_clk_src.clkr.hw, 1167 }, 1168 .num_parents = 1, 1169 .flags = CLK_SET_RATE_PARENT, 1170 .ops = &clk_branch2_ops, 1171 }, 1172 }, 1173 }; 1174 1175 static struct clk_branch camcc_csi3phytimer_clk = { 1176 .halt_reg = 0x6088, 1177 .halt_check = BRANCH_HALT, 1178 .clkr = { 1179 .enable_reg = 0x6088, 1180 .enable_mask = BIT(0), 1181 .hw.init = &(const struct clk_init_data) { 1182 .name = "camcc_csi3phytimer_clk", 1183 .parent_hws = (const struct clk_hw*[]) { 1184 &camcc_csi3phytimer_clk_src.clkr.hw, 1185 }, 1186 .num_parents = 1, 1187 .flags = CLK_SET_RATE_PARENT, 1188 .ops = &clk_branch2_ops, 1189 }, 1190 }, 1191 }; 1192 1193 static struct clk_branch camcc_csiphy0_clk = { 1194 .halt_reg = 0x6020, 1195 .halt_check = BRANCH_HALT, 1196 .clkr = { 1197 .enable_reg = 0x6020, 1198 .enable_mask = BIT(0), 1199 .hw.init = &(const struct clk_init_data) { 1200 .name = "camcc_csiphy0_clk", 1201 .parent_hws = (const struct clk_hw*[]) { 1202 &camcc_cphy_rx_clk_src.clkr.hw, 1203 }, 1204 .num_parents = 1, 1205 .flags = CLK_SET_RATE_PARENT, 1206 .ops = &clk_branch2_ops, 1207 }, 1208 }, 1209 }; 1210 1211 static struct clk_branch camcc_csiphy1_clk = { 1212 .halt_reg = 0x6044, 1213 .halt_check = BRANCH_HALT, 1214 .clkr = { 1215 .enable_reg = 0x6044, 1216 .enable_mask = BIT(0), 1217 .hw.init = &(const struct clk_init_data) { 1218 .name = "camcc_csiphy1_clk", 1219 .parent_hws = (const struct clk_hw*[]) { 1220 &camcc_cphy_rx_clk_src.clkr.hw, 1221 }, 1222 .num_parents = 1, 1223 .flags = CLK_SET_RATE_PARENT, 1224 .ops = &clk_branch2_ops, 1225 }, 1226 }, 1227 }; 1228 1229 static struct clk_branch camcc_csiphy2_clk = { 1230 .halt_reg = 0x6068, 1231 .halt_check = BRANCH_HALT, 1232 .clkr = { 1233 .enable_reg = 0x6068, 1234 .enable_mask = BIT(0), 1235 .hw.init = &(const struct clk_init_data) { 1236 .name = "camcc_csiphy2_clk", 1237 .parent_hws = (const struct clk_hw*[]) { 1238 &camcc_cphy_rx_clk_src.clkr.hw, 1239 }, 1240 .num_parents = 1, 1241 .flags = CLK_SET_RATE_PARENT, 1242 .ops = &clk_branch2_ops, 1243 }, 1244 }, 1245 }; 1246 1247 static struct clk_branch camcc_csiphy3_clk = { 1248 .halt_reg = 0x608c, 1249 .halt_check = BRANCH_HALT, 1250 .clkr = { 1251 .enable_reg = 0x608c, 1252 .enable_mask = BIT(0), 1253 .hw.init = &(const struct clk_init_data) { 1254 .name = "camcc_csiphy3_clk", 1255 .parent_hws = (const struct clk_hw*[]) { 1256 &camcc_cphy_rx_clk_src.clkr.hw, 1257 }, 1258 .num_parents = 1, 1259 .flags = CLK_SET_RATE_PARENT, 1260 .ops = &clk_branch2_ops, 1261 }, 1262 }, 1263 }; 1264 1265 static struct clk_branch camcc_fd_core_clk = { 1266 .halt_reg = 0xc0b4, 1267 .halt_check = BRANCH_HALT, 1268 .clkr = { 1269 .enable_reg = 0xc0b4, 1270 .enable_mask = BIT(0), 1271 .hw.init = &(const struct clk_init_data) { 1272 .name = "camcc_fd_core_clk", 1273 .parent_hws = (const struct clk_hw*[]) { 1274 &camcc_fd_core_clk_src.clkr.hw, 1275 }, 1276 .num_parents = 1, 1277 .flags = CLK_SET_RATE_PARENT, 1278 .ops = &clk_branch2_ops, 1279 }, 1280 }, 1281 }; 1282 1283 static struct clk_branch camcc_fd_core_uar_clk = { 1284 .halt_reg = 0xc0bc, 1285 .halt_check = BRANCH_HALT, 1286 .clkr = { 1287 .enable_reg = 0xc0bc, 1288 .enable_mask = BIT(0), 1289 .hw.init = &(const struct clk_init_data) { 1290 .name = "camcc_fd_core_uar_clk", 1291 .parent_hws = (const struct clk_hw*[]) { 1292 &camcc_fd_core_clk_src.clkr.hw, 1293 }, 1294 .num_parents = 1, 1295 .flags = CLK_SET_RATE_PARENT, 1296 .ops = &clk_branch2_ops, 1297 }, 1298 }, 1299 }; 1300 1301 static struct clk_branch camcc_icp_ahb_clk = { 1302 .halt_reg = 0xc094, 1303 .halt_check = BRANCH_HALT, 1304 .clkr = { 1305 .enable_reg = 0xc094, 1306 .enable_mask = BIT(0), 1307 .hw.init = &(const struct clk_init_data) { 1308 .name = "camcc_icp_ahb_clk", 1309 .parent_hws = (const struct clk_hw*[]) { 1310 &camcc_slow_ahb_clk_src.clkr.hw, 1311 }, 1312 .num_parents = 1, 1313 .flags = CLK_SET_RATE_PARENT, 1314 .ops = &clk_branch2_ops, 1315 }, 1316 }, 1317 }; 1318 1319 static struct clk_branch camcc_icp_clk = { 1320 .halt_reg = 0xc08c, 1321 .halt_check = BRANCH_HALT, 1322 .clkr = { 1323 .enable_reg = 0xc08c, 1324 .enable_mask = BIT(0), 1325 .hw.init = &(const struct clk_init_data) { 1326 .name = "camcc_icp_clk", 1327 .parent_hws = (const struct clk_hw*[]) { 1328 &camcc_icp_clk_src.clkr.hw, 1329 }, 1330 .num_parents = 1, 1331 .flags = CLK_SET_RATE_PARENT, 1332 .ops = &clk_branch2_ops, 1333 }, 1334 }, 1335 }; 1336 1337 static struct clk_branch camcc_ife_0_axi_clk = { 1338 .halt_reg = 0xa080, 1339 .halt_check = BRANCH_HALT, 1340 .clkr = { 1341 .enable_reg = 0xa080, 1342 .enable_mask = BIT(0), 1343 .hw.init = &(const struct clk_init_data) { 1344 .name = "camcc_ife_0_axi_clk", 1345 .parent_hws = (const struct clk_hw*[]) { 1346 &camcc_camnoc_axi_clk_src.clkr.hw, 1347 }, 1348 .num_parents = 1, 1349 .flags = CLK_SET_RATE_PARENT, 1350 .ops = &clk_branch2_ops, 1351 }, 1352 }, 1353 }; 1354 1355 static struct clk_branch camcc_ife_0_clk = { 1356 .halt_reg = 0xa028, 1357 .halt_check = BRANCH_HALT, 1358 .clkr = { 1359 .enable_reg = 0xa028, 1360 .enable_mask = BIT(0), 1361 .hw.init = &(const struct clk_init_data) { 1362 .name = "camcc_ife_0_clk", 1363 .parent_hws = (const struct clk_hw*[]) { 1364 &camcc_ife_0_clk_src.clkr.hw, 1365 }, 1366 .num_parents = 1, 1367 .flags = CLK_SET_RATE_PARENT, 1368 .ops = &clk_branch2_ops, 1369 }, 1370 }, 1371 }; 1372 1373 static struct clk_branch camcc_ife_0_cphy_rx_clk = { 1374 .halt_reg = 0xa07c, 1375 .halt_check = BRANCH_HALT, 1376 .clkr = { 1377 .enable_reg = 0xa07c, 1378 .enable_mask = BIT(0), 1379 .hw.init = &(const struct clk_init_data) { 1380 .name = "camcc_ife_0_cphy_rx_clk", 1381 .parent_hws = (const struct clk_hw*[]) { 1382 &camcc_cphy_rx_clk_src.clkr.hw, 1383 }, 1384 .num_parents = 1, 1385 .flags = CLK_SET_RATE_PARENT, 1386 .ops = &clk_branch2_ops, 1387 }, 1388 }, 1389 }; 1390 1391 static struct clk_branch camcc_ife_0_csid_clk = { 1392 .halt_reg = 0xa054, 1393 .halt_check = BRANCH_HALT, 1394 .clkr = { 1395 .enable_reg = 0xa054, 1396 .enable_mask = BIT(0), 1397 .hw.init = &(const struct clk_init_data) { 1398 .name = "camcc_ife_0_csid_clk", 1399 .parent_hws = (const struct clk_hw*[]) { 1400 &camcc_ife_0_csid_clk_src.clkr.hw, 1401 }, 1402 .num_parents = 1, 1403 .flags = CLK_SET_RATE_PARENT, 1404 .ops = &clk_branch2_ops, 1405 }, 1406 }, 1407 }; 1408 1409 static struct clk_branch camcc_ife_0_dsp_clk = { 1410 .halt_reg = 0xa038, 1411 .halt_check = BRANCH_HALT, 1412 .clkr = { 1413 .enable_reg = 0xa038, 1414 .enable_mask = BIT(0), 1415 .hw.init = &(const struct clk_init_data) { 1416 .name = "camcc_ife_0_dsp_clk", 1417 .parent_hws = (const struct clk_hw*[]) { 1418 &camcc_ife_0_clk_src.clkr.hw, 1419 }, 1420 .num_parents = 1, 1421 .flags = CLK_SET_RATE_PARENT, 1422 .ops = &clk_branch2_ops, 1423 }, 1424 }, 1425 }; 1426 1427 static struct clk_branch camcc_ife_1_axi_clk = { 1428 .halt_reg = 0xb058, 1429 .halt_check = BRANCH_HALT, 1430 .clkr = { 1431 .enable_reg = 0xb058, 1432 .enable_mask = BIT(0), 1433 .hw.init = &(const struct clk_init_data) { 1434 .name = "camcc_ife_1_axi_clk", 1435 .parent_hws = (const struct clk_hw*[]) { 1436 &camcc_camnoc_axi_clk_src.clkr.hw, 1437 }, 1438 .num_parents = 1, 1439 .flags = CLK_SET_RATE_PARENT, 1440 .ops = &clk_branch2_ops, 1441 }, 1442 }, 1443 }; 1444 1445 static struct clk_branch camcc_ife_1_clk = { 1446 .halt_reg = 0xb028, 1447 .halt_check = BRANCH_HALT, 1448 .clkr = { 1449 .enable_reg = 0xb028, 1450 .enable_mask = BIT(0), 1451 .hw.init = &(const struct clk_init_data) { 1452 .name = "camcc_ife_1_clk", 1453 .parent_hws = (const struct clk_hw*[]) { 1454 &camcc_ife_1_clk_src.clkr.hw, 1455 }, 1456 .num_parents = 1, 1457 .flags = CLK_SET_RATE_PARENT, 1458 .ops = &clk_branch2_ops, 1459 }, 1460 }, 1461 }; 1462 1463 static struct clk_branch camcc_ife_1_cphy_rx_clk = { 1464 .halt_reg = 0xb054, 1465 .halt_check = BRANCH_HALT, 1466 .clkr = { 1467 .enable_reg = 0xb054, 1468 .enable_mask = BIT(0), 1469 .hw.init = &(const struct clk_init_data) { 1470 .name = "camcc_ife_1_cphy_rx_clk", 1471 .parent_hws = (const struct clk_hw*[]) { 1472 &camcc_cphy_rx_clk_src.clkr.hw, 1473 }, 1474 .num_parents = 1, 1475 .flags = CLK_SET_RATE_PARENT, 1476 .ops = &clk_branch2_ops, 1477 }, 1478 }, 1479 }; 1480 1481 static struct clk_branch camcc_ife_1_csid_clk = { 1482 .halt_reg = 0xb04c, 1483 .halt_check = BRANCH_HALT, 1484 .clkr = { 1485 .enable_reg = 0xb04c, 1486 .enable_mask = BIT(0), 1487 .hw.init = &(const struct clk_init_data) { 1488 .name = "camcc_ife_1_csid_clk", 1489 .parent_hws = (const struct clk_hw*[]) { 1490 &camcc_ife_1_csid_clk_src.clkr.hw, 1491 }, 1492 .num_parents = 1, 1493 .flags = CLK_SET_RATE_PARENT, 1494 .ops = &clk_branch2_ops, 1495 }, 1496 }, 1497 }; 1498 1499 static struct clk_branch camcc_ife_1_dsp_clk = { 1500 .halt_reg = 0xb030, 1501 .halt_check = BRANCH_HALT, 1502 .clkr = { 1503 .enable_reg = 0xb030, 1504 .enable_mask = BIT(0), 1505 .hw.init = &(const struct clk_init_data) { 1506 .name = "camcc_ife_1_dsp_clk", 1507 .parent_hws = (const struct clk_hw*[]) { 1508 &camcc_ife_1_clk_src.clkr.hw, 1509 }, 1510 .num_parents = 1, 1511 .flags = CLK_SET_RATE_PARENT, 1512 .ops = &clk_branch2_ops, 1513 }, 1514 }, 1515 }; 1516 1517 static struct clk_branch camcc_ife_lite_clk = { 1518 .halt_reg = 0xc01c, 1519 .halt_check = BRANCH_HALT, 1520 .clkr = { 1521 .enable_reg = 0xc01c, 1522 .enable_mask = BIT(0), 1523 .hw.init = &(const struct clk_init_data) { 1524 .name = "camcc_ife_lite_clk", 1525 .parent_hws = (const struct clk_hw*[]) { 1526 &camcc_ife_lite_clk_src.clkr.hw, 1527 }, 1528 .num_parents = 1, 1529 .flags = CLK_SET_RATE_PARENT, 1530 .ops = &clk_branch2_ops, 1531 }, 1532 }, 1533 }; 1534 1535 static struct clk_branch camcc_ife_lite_cphy_rx_clk = { 1536 .halt_reg = 0xc040, 1537 .halt_check = BRANCH_HALT, 1538 .clkr = { 1539 .enable_reg = 0xc040, 1540 .enable_mask = BIT(0), 1541 .hw.init = &(const struct clk_init_data) { 1542 .name = "camcc_ife_lite_cphy_rx_clk", 1543 .parent_hws = (const struct clk_hw*[]) { 1544 &camcc_cphy_rx_clk_src.clkr.hw, 1545 }, 1546 .num_parents = 1, 1547 .flags = CLK_SET_RATE_PARENT, 1548 .ops = &clk_branch2_ops, 1549 }, 1550 }, 1551 }; 1552 1553 static struct clk_branch camcc_ife_lite_csid_clk = { 1554 .halt_reg = 0xc038, 1555 .halt_check = BRANCH_HALT, 1556 .clkr = { 1557 .enable_reg = 0xc038, 1558 .enable_mask = BIT(0), 1559 .hw.init = &(const struct clk_init_data) { 1560 .name = "camcc_ife_lite_csid_clk", 1561 .parent_hws = (const struct clk_hw*[]) { 1562 &camcc_ife_lite_csid_clk_src.clkr.hw, 1563 }, 1564 .num_parents = 1, 1565 .flags = CLK_SET_RATE_PARENT, 1566 .ops = &clk_branch2_ops, 1567 }, 1568 }, 1569 }; 1570 1571 static struct clk_branch camcc_ipe_0_ahb_clk = { 1572 .halt_reg = 0x8040, 1573 .halt_check = BRANCH_HALT, 1574 .clkr = { 1575 .enable_reg = 0x8040, 1576 .enable_mask = BIT(0), 1577 .hw.init = &(const struct clk_init_data) { 1578 .name = "camcc_ipe_0_ahb_clk", 1579 .parent_hws = (const struct clk_hw*[]) { 1580 &camcc_slow_ahb_clk_src.clkr.hw, 1581 }, 1582 .num_parents = 1, 1583 .flags = CLK_SET_RATE_PARENT, 1584 .ops = &clk_branch2_ops, 1585 }, 1586 }, 1587 }; 1588 1589 static struct clk_branch camcc_ipe_0_areg_clk = { 1590 .halt_reg = 0x803c, 1591 .halt_check = BRANCH_HALT, 1592 .clkr = { 1593 .enable_reg = 0x803c, 1594 .enable_mask = BIT(0), 1595 .hw.init = &(const struct clk_init_data) { 1596 .name = "camcc_ipe_0_areg_clk", 1597 .parent_hws = (const struct clk_hw*[]) { 1598 &camcc_fast_ahb_clk_src.clkr.hw, 1599 }, 1600 .num_parents = 1, 1601 .flags = CLK_SET_RATE_PARENT, 1602 .ops = &clk_branch2_ops, 1603 }, 1604 }, 1605 }; 1606 1607 static struct clk_branch camcc_ipe_0_axi_clk = { 1608 .halt_reg = 0x8038, 1609 .halt_check = BRANCH_HALT, 1610 .clkr = { 1611 .enable_reg = 0x8038, 1612 .enable_mask = BIT(0), 1613 .hw.init = &(const struct clk_init_data) { 1614 .name = "camcc_ipe_0_axi_clk", 1615 .parent_hws = (const struct clk_hw*[]) { 1616 &camcc_camnoc_axi_clk_src.clkr.hw, 1617 }, 1618 .num_parents = 1, 1619 .flags = CLK_SET_RATE_PARENT, 1620 .ops = &clk_branch2_ops, 1621 }, 1622 }, 1623 }; 1624 1625 static struct clk_branch camcc_ipe_0_clk = { 1626 .halt_reg = 0x8028, 1627 .halt_check = BRANCH_HALT, 1628 .clkr = { 1629 .enable_reg = 0x8028, 1630 .enable_mask = BIT(0), 1631 .hw.init = &(const struct clk_init_data) { 1632 .name = "camcc_ipe_0_clk", 1633 .parent_hws = (const struct clk_hw*[]) { 1634 &camcc_ipe_0_clk_src.clkr.hw, 1635 }, 1636 .num_parents = 1, 1637 .flags = CLK_SET_RATE_PARENT, 1638 .ops = &clk_branch2_ops, 1639 }, 1640 }, 1641 }; 1642 1643 static struct clk_branch camcc_ipe_1_ahb_clk = { 1644 .halt_reg = 0x9028, 1645 .halt_check = BRANCH_HALT, 1646 .clkr = { 1647 .enable_reg = 0x9028, 1648 .enable_mask = BIT(0), 1649 .hw.init = &(const struct clk_init_data) { 1650 .name = "camcc_ipe_1_ahb_clk", 1651 .parent_hws = (const struct clk_hw*[]) { 1652 &camcc_slow_ahb_clk_src.clkr.hw, 1653 }, 1654 .num_parents = 1, 1655 .flags = CLK_SET_RATE_PARENT, 1656 .ops = &clk_branch2_ops, 1657 }, 1658 }, 1659 }; 1660 1661 static struct clk_branch camcc_ipe_1_areg_clk = { 1662 .halt_reg = 0x9024, 1663 .halt_check = BRANCH_HALT, 1664 .clkr = { 1665 .enable_reg = 0x9024, 1666 .enable_mask = BIT(0), 1667 .hw.init = &(const struct clk_init_data) { 1668 .name = "camcc_ipe_1_areg_clk", 1669 .parent_hws = (const struct clk_hw*[]) { 1670 &camcc_fast_ahb_clk_src.clkr.hw, 1671 }, 1672 .num_parents = 1, 1673 .flags = CLK_SET_RATE_PARENT, 1674 .ops = &clk_branch2_ops, 1675 }, 1676 }, 1677 }; 1678 1679 static struct clk_branch camcc_ipe_1_axi_clk = { 1680 .halt_reg = 0x9020, 1681 .halt_check = BRANCH_HALT, 1682 .clkr = { 1683 .enable_reg = 0x9020, 1684 .enable_mask = BIT(0), 1685 .hw.init = &(const struct clk_init_data) { 1686 .name = "camcc_ipe_1_axi_clk", 1687 .parent_hws = (const struct clk_hw*[]) { 1688 &camcc_camnoc_axi_clk_src.clkr.hw, 1689 }, 1690 .num_parents = 1, 1691 .flags = CLK_SET_RATE_PARENT, 1692 .ops = &clk_branch2_ops, 1693 }, 1694 }, 1695 }; 1696 1697 static struct clk_branch camcc_ipe_1_clk = { 1698 .halt_reg = 0x9010, 1699 .halt_check = BRANCH_HALT, 1700 .clkr = { 1701 .enable_reg = 0x9010, 1702 .enable_mask = BIT(0), 1703 .hw.init = &(const struct clk_init_data) { 1704 .name = "camcc_ipe_1_clk", 1705 .parent_hws = (const struct clk_hw*[]) { 1706 &camcc_ipe_0_clk_src.clkr.hw, 1707 }, 1708 .num_parents = 1, 1709 .flags = CLK_SET_RATE_PARENT, 1710 .ops = &clk_branch2_ops, 1711 }, 1712 }, 1713 }; 1714 1715 static struct clk_branch camcc_jpeg_clk = { 1716 .halt_reg = 0xc060, 1717 .halt_check = BRANCH_HALT, 1718 .clkr = { 1719 .enable_reg = 0xc060, 1720 .enable_mask = BIT(0), 1721 .hw.init = &(const struct clk_init_data) { 1722 .name = "camcc_jpeg_clk", 1723 .parent_hws = (const struct clk_hw*[]) { 1724 &camcc_jpeg_clk_src.clkr.hw, 1725 }, 1726 .num_parents = 1, 1727 .flags = CLK_SET_RATE_PARENT, 1728 .ops = &clk_branch2_ops, 1729 }, 1730 }, 1731 }; 1732 1733 static struct clk_branch camcc_lrme_clk = { 1734 .halt_reg = 0xc118, 1735 .halt_check = BRANCH_HALT, 1736 .clkr = { 1737 .enable_reg = 0xc118, 1738 .enable_mask = BIT(0), 1739 .hw.init = &(const struct clk_init_data) { 1740 .name = "camcc_lrme_clk", 1741 .parent_hws = (const struct clk_hw*[]) { 1742 &camcc_lrme_clk_src.clkr.hw, 1743 }, 1744 .num_parents = 1, 1745 .flags = CLK_SET_RATE_PARENT, 1746 .ops = &clk_branch2_ops, 1747 }, 1748 }, 1749 }; 1750 1751 static struct clk_branch camcc_mclk0_clk = { 1752 .halt_reg = 0x501c, 1753 .halt_check = BRANCH_HALT, 1754 .clkr = { 1755 .enable_reg = 0x501c, 1756 .enable_mask = BIT(0), 1757 .hw.init = &(const struct clk_init_data) { 1758 .name = "camcc_mclk0_clk", 1759 .parent_hws = (const struct clk_hw*[]) { 1760 &camcc_mclk0_clk_src.clkr.hw, 1761 }, 1762 .num_parents = 1, 1763 .flags = CLK_SET_RATE_PARENT, 1764 .ops = &clk_branch2_ops, 1765 }, 1766 }, 1767 }; 1768 1769 static struct clk_branch camcc_mclk1_clk = { 1770 .halt_reg = 0x503c, 1771 .halt_check = BRANCH_HALT, 1772 .clkr = { 1773 .enable_reg = 0x503c, 1774 .enable_mask = BIT(0), 1775 .hw.init = &(const struct clk_init_data) { 1776 .name = "camcc_mclk1_clk", 1777 .parent_hws = (const struct clk_hw*[]) { 1778 &camcc_mclk1_clk_src.clkr.hw, 1779 }, 1780 .num_parents = 1, 1781 .flags = CLK_SET_RATE_PARENT, 1782 .ops = &clk_branch2_ops, 1783 }, 1784 }, 1785 }; 1786 1787 static struct clk_branch camcc_mclk2_clk = { 1788 .halt_reg = 0x505c, 1789 .halt_check = BRANCH_HALT, 1790 .clkr = { 1791 .enable_reg = 0x505c, 1792 .enable_mask = BIT(0), 1793 .hw.init = &(const struct clk_init_data) { 1794 .name = "camcc_mclk2_clk", 1795 .parent_hws = (const struct clk_hw*[]) { 1796 &camcc_mclk2_clk_src.clkr.hw, 1797 }, 1798 .num_parents = 1, 1799 .flags = CLK_SET_RATE_PARENT, 1800 .ops = &clk_branch2_ops, 1801 }, 1802 }, 1803 }; 1804 1805 static struct clk_branch camcc_mclk3_clk = { 1806 .halt_reg = 0x507c, 1807 .halt_check = BRANCH_HALT, 1808 .clkr = { 1809 .enable_reg = 0x507c, 1810 .enable_mask = BIT(0), 1811 .hw.init = &(const struct clk_init_data) { 1812 .name = "camcc_mclk3_clk", 1813 .parent_hws = (const struct clk_hw*[]) { 1814 &camcc_mclk3_clk_src.clkr.hw, 1815 }, 1816 .num_parents = 1, 1817 .flags = CLK_SET_RATE_PARENT, 1818 .ops = &clk_branch2_ops, 1819 }, 1820 }, 1821 }; 1822 1823 static struct clk_branch camcc_sleep_clk = { 1824 .halt_reg = 0xc1bc, 1825 .halt_check = BRANCH_HALT, 1826 .clkr = { 1827 .enable_reg = 0xc1bc, 1828 .enable_mask = BIT(0), 1829 .hw.init = &(const struct clk_init_data) { 1830 .name = "camcc_sleep_clk", 1831 .parent_hws = (const struct clk_hw*[]) { 1832 &camcc_sleep_clk_src.clkr.hw, 1833 }, 1834 .num_parents = 1, 1835 .flags = CLK_SET_RATE_PARENT, 1836 .ops = &clk_branch2_ops, 1837 }, 1838 }, 1839 }; 1840 1841 static struct gdsc camcc_titan_top_gdsc; 1842 1843 static struct gdsc camcc_bps_gdsc = { 1844 .gdscr = 0x7004, 1845 .pd = { 1846 .name = "camcc_bps_gdsc", 1847 }, 1848 .flags = HW_CTRL | POLL_CFG_GDSCR, 1849 .pwrsts = PWRSTS_OFF_ON, 1850 }; 1851 1852 static struct gdsc camcc_ife_0_gdsc = { 1853 .gdscr = 0xa004, 1854 .pd = { 1855 .name = "camcc_ife_0_gdsc", 1856 }, 1857 .flags = POLL_CFG_GDSCR, 1858 .parent = &camcc_titan_top_gdsc.pd, 1859 .pwrsts = PWRSTS_OFF_ON, 1860 }; 1861 1862 static struct gdsc camcc_ife_1_gdsc = { 1863 .gdscr = 0xb004, 1864 .pd = { 1865 .name = "camcc_ife_1_gdsc", 1866 }, 1867 .flags = POLL_CFG_GDSCR, 1868 .parent = &camcc_titan_top_gdsc.pd, 1869 .pwrsts = PWRSTS_OFF_ON, 1870 }; 1871 1872 static struct gdsc camcc_ipe_0_gdsc = { 1873 .gdscr = 0x8004, 1874 .pd = { 1875 .name = "camcc_ipe_0_gdsc", 1876 }, 1877 .flags = HW_CTRL | POLL_CFG_GDSCR, 1878 .pwrsts = PWRSTS_OFF_ON, 1879 }; 1880 1881 static struct gdsc camcc_ipe_1_gdsc = { 1882 .gdscr = 0x9004, 1883 .pd = { 1884 .name = "camcc_ipe_1_gdsc", 1885 }, 1886 .flags = HW_CTRL | POLL_CFG_GDSCR, 1887 .pwrsts = PWRSTS_OFF_ON, 1888 }; 1889 1890 static struct gdsc camcc_titan_top_gdsc = { 1891 .gdscr = 0xc1c4, 1892 .pd = { 1893 .name = "camcc_titan_top_gdsc", 1894 }, 1895 .flags = POLL_CFG_GDSCR, 1896 .pwrsts = PWRSTS_OFF_ON, 1897 }; 1898 1899 struct clk_hw *camcc_sm7150_hws[] = { 1900 [CAMCC_PLL0_OUT_EVEN] = &camcc_pll0_out_even.hw, 1901 [CAMCC_PLL0_OUT_ODD] = &camcc_pll0_out_odd.hw, 1902 [CAMCC_PLL1_OUT_EVEN] = &camcc_pll1_out_even.hw, 1903 [CAMCC_PLL2_OUT_EARLY] = &camcc_pll2_out_early.hw, 1904 [CAMCC_PLL3_OUT_EVEN] = &camcc_pll3_out_even.hw, 1905 [CAMCC_PLL4_OUT_EVEN] = &camcc_pll4_out_even.hw, 1906 }; 1907 1908 static struct clk_regmap *camcc_sm7150_clocks[] = { 1909 [CAMCC_BPS_AHB_CLK] = &camcc_bps_ahb_clk.clkr, 1910 [CAMCC_BPS_AREG_CLK] = &camcc_bps_areg_clk.clkr, 1911 [CAMCC_BPS_AXI_CLK] = &camcc_bps_axi_clk.clkr, 1912 [CAMCC_BPS_CLK] = &camcc_bps_clk.clkr, 1913 [CAMCC_BPS_CLK_SRC] = &camcc_bps_clk_src.clkr, 1914 [CAMCC_CAMNOC_AXI_CLK] = &camcc_camnoc_axi_clk.clkr, 1915 [CAMCC_CAMNOC_AXI_CLK_SRC] = &camcc_camnoc_axi_clk_src.clkr, 1916 [CAMCC_CAMNOC_DCD_XO_CLK] = &camcc_camnoc_dcd_xo_clk.clkr, 1917 [CAMCC_CCI_0_CLK] = &camcc_cci_0_clk.clkr, 1918 [CAMCC_CCI_0_CLK_SRC] = &camcc_cci_0_clk_src.clkr, 1919 [CAMCC_CCI_1_CLK] = &camcc_cci_1_clk.clkr, 1920 [CAMCC_CCI_1_CLK_SRC] = &camcc_cci_1_clk_src.clkr, 1921 [CAMCC_CORE_AHB_CLK] = &camcc_core_ahb_clk.clkr, 1922 [CAMCC_CPAS_AHB_CLK] = &camcc_cpas_ahb_clk.clkr, 1923 [CAMCC_CPHY_RX_CLK_SRC] = &camcc_cphy_rx_clk_src.clkr, 1924 [CAMCC_CSI0PHYTIMER_CLK] = &camcc_csi0phytimer_clk.clkr, 1925 [CAMCC_CSI0PHYTIMER_CLK_SRC] = &camcc_csi0phytimer_clk_src.clkr, 1926 [CAMCC_CSI1PHYTIMER_CLK] = &camcc_csi1phytimer_clk.clkr, 1927 [CAMCC_CSI1PHYTIMER_CLK_SRC] = &camcc_csi1phytimer_clk_src.clkr, 1928 [CAMCC_CSI2PHYTIMER_CLK] = &camcc_csi2phytimer_clk.clkr, 1929 [CAMCC_CSI2PHYTIMER_CLK_SRC] = &camcc_csi2phytimer_clk_src.clkr, 1930 [CAMCC_CSI3PHYTIMER_CLK] = &camcc_csi3phytimer_clk.clkr, 1931 [CAMCC_CSI3PHYTIMER_CLK_SRC] = &camcc_csi3phytimer_clk_src.clkr, 1932 [CAMCC_CSIPHY0_CLK] = &camcc_csiphy0_clk.clkr, 1933 [CAMCC_CSIPHY1_CLK] = &camcc_csiphy1_clk.clkr, 1934 [CAMCC_CSIPHY2_CLK] = &camcc_csiphy2_clk.clkr, 1935 [CAMCC_CSIPHY3_CLK] = &camcc_csiphy3_clk.clkr, 1936 [CAMCC_FAST_AHB_CLK_SRC] = &camcc_fast_ahb_clk_src.clkr, 1937 [CAMCC_FD_CORE_CLK] = &camcc_fd_core_clk.clkr, 1938 [CAMCC_FD_CORE_CLK_SRC] = &camcc_fd_core_clk_src.clkr, 1939 [CAMCC_FD_CORE_UAR_CLK] = &camcc_fd_core_uar_clk.clkr, 1940 [CAMCC_ICP_AHB_CLK] = &camcc_icp_ahb_clk.clkr, 1941 [CAMCC_ICP_CLK] = &camcc_icp_clk.clkr, 1942 [CAMCC_ICP_CLK_SRC] = &camcc_icp_clk_src.clkr, 1943 [CAMCC_IFE_0_AXI_CLK] = &camcc_ife_0_axi_clk.clkr, 1944 [CAMCC_IFE_0_CLK] = &camcc_ife_0_clk.clkr, 1945 [CAMCC_IFE_0_CLK_SRC] = &camcc_ife_0_clk_src.clkr, 1946 [CAMCC_IFE_0_CPHY_RX_CLK] = &camcc_ife_0_cphy_rx_clk.clkr, 1947 [CAMCC_IFE_0_CSID_CLK] = &camcc_ife_0_csid_clk.clkr, 1948 [CAMCC_IFE_0_CSID_CLK_SRC] = &camcc_ife_0_csid_clk_src.clkr, 1949 [CAMCC_IFE_0_DSP_CLK] = &camcc_ife_0_dsp_clk.clkr, 1950 [CAMCC_IFE_1_AXI_CLK] = &camcc_ife_1_axi_clk.clkr, 1951 [CAMCC_IFE_1_CLK] = &camcc_ife_1_clk.clkr, 1952 [CAMCC_IFE_1_CLK_SRC] = &camcc_ife_1_clk_src.clkr, 1953 [CAMCC_IFE_1_CPHY_RX_CLK] = &camcc_ife_1_cphy_rx_clk.clkr, 1954 [CAMCC_IFE_1_CSID_CLK] = &camcc_ife_1_csid_clk.clkr, 1955 [CAMCC_IFE_1_CSID_CLK_SRC] = &camcc_ife_1_csid_clk_src.clkr, 1956 [CAMCC_IFE_1_DSP_CLK] = &camcc_ife_1_dsp_clk.clkr, 1957 [CAMCC_IFE_LITE_CLK] = &camcc_ife_lite_clk.clkr, 1958 [CAMCC_IFE_LITE_CLK_SRC] = &camcc_ife_lite_clk_src.clkr, 1959 [CAMCC_IFE_LITE_CPHY_RX_CLK] = &camcc_ife_lite_cphy_rx_clk.clkr, 1960 [CAMCC_IFE_LITE_CSID_CLK] = &camcc_ife_lite_csid_clk.clkr, 1961 [CAMCC_IFE_LITE_CSID_CLK_SRC] = &camcc_ife_lite_csid_clk_src.clkr, 1962 [CAMCC_IPE_0_AHB_CLK] = &camcc_ipe_0_ahb_clk.clkr, 1963 [CAMCC_IPE_0_AREG_CLK] = &camcc_ipe_0_areg_clk.clkr, 1964 [CAMCC_IPE_0_AXI_CLK] = &camcc_ipe_0_axi_clk.clkr, 1965 [CAMCC_IPE_0_CLK] = &camcc_ipe_0_clk.clkr, 1966 [CAMCC_IPE_0_CLK_SRC] = &camcc_ipe_0_clk_src.clkr, 1967 [CAMCC_IPE_1_AHB_CLK] = &camcc_ipe_1_ahb_clk.clkr, 1968 [CAMCC_IPE_1_AREG_CLK] = &camcc_ipe_1_areg_clk.clkr, 1969 [CAMCC_IPE_1_AXI_CLK] = &camcc_ipe_1_axi_clk.clkr, 1970 [CAMCC_IPE_1_CLK] = &camcc_ipe_1_clk.clkr, 1971 [CAMCC_JPEG_CLK] = &camcc_jpeg_clk.clkr, 1972 [CAMCC_JPEG_CLK_SRC] = &camcc_jpeg_clk_src.clkr, 1973 [CAMCC_LRME_CLK] = &camcc_lrme_clk.clkr, 1974 [CAMCC_LRME_CLK_SRC] = &camcc_lrme_clk_src.clkr, 1975 [CAMCC_MCLK0_CLK] = &camcc_mclk0_clk.clkr, 1976 [CAMCC_MCLK0_CLK_SRC] = &camcc_mclk0_clk_src.clkr, 1977 [CAMCC_MCLK1_CLK] = &camcc_mclk1_clk.clkr, 1978 [CAMCC_MCLK1_CLK_SRC] = &camcc_mclk1_clk_src.clkr, 1979 [CAMCC_MCLK2_CLK] = &camcc_mclk2_clk.clkr, 1980 [CAMCC_MCLK2_CLK_SRC] = &camcc_mclk2_clk_src.clkr, 1981 [CAMCC_MCLK3_CLK] = &camcc_mclk3_clk.clkr, 1982 [CAMCC_MCLK3_CLK_SRC] = &camcc_mclk3_clk_src.clkr, 1983 [CAMCC_PLL0] = &camcc_pll0.clkr, 1984 [CAMCC_PLL1] = &camcc_pll1.clkr, 1985 [CAMCC_PLL2] = &camcc_pll2.clkr, 1986 [CAMCC_PLL2_OUT_AUX] = &camcc_pll2_out_aux.clkr, 1987 [CAMCC_PLL2_OUT_MAIN] = &camcc_pll2_out_main.clkr, 1988 [CAMCC_PLL3] = &camcc_pll3.clkr, 1989 [CAMCC_PLL4] = &camcc_pll4.clkr, 1990 [CAMCC_SLEEP_CLK] = &camcc_sleep_clk.clkr, 1991 [CAMCC_SLEEP_CLK_SRC] = &camcc_sleep_clk_src.clkr, 1992 [CAMCC_SLOW_AHB_CLK_SRC] = &camcc_slow_ahb_clk_src.clkr, 1993 [CAMCC_XO_CLK_SRC] = &camcc_xo_clk_src.clkr, 1994 }; 1995 1996 static struct gdsc *camcc_sm7150_gdscs[] = { 1997 [BPS_GDSC] = &camcc_bps_gdsc, 1998 [IFE_0_GDSC] = &camcc_ife_0_gdsc, 1999 [IFE_1_GDSC] = &camcc_ife_1_gdsc, 2000 [IPE_0_GDSC] = &camcc_ipe_0_gdsc, 2001 [IPE_1_GDSC] = &camcc_ipe_1_gdsc, 2002 [TITAN_TOP_GDSC] = &camcc_titan_top_gdsc, 2003 }; 2004 2005 static const struct regmap_config camcc_sm7150_regmap_config = { 2006 .reg_bits = 32, 2007 .reg_stride = 4, 2008 .val_bits = 32, 2009 .max_register = 0xd024, 2010 .fast_io = true, 2011 }; 2012 2013 static const struct qcom_cc_desc camcc_sm7150_desc = { 2014 .config = &camcc_sm7150_regmap_config, 2015 .clk_hws = camcc_sm7150_hws, 2016 .num_clk_hws = ARRAY_SIZE(camcc_sm7150_hws), 2017 .clks = camcc_sm7150_clocks, 2018 .num_clks = ARRAY_SIZE(camcc_sm7150_clocks), 2019 .gdscs = camcc_sm7150_gdscs, 2020 .num_gdscs = ARRAY_SIZE(camcc_sm7150_gdscs), 2021 }; 2022 2023 static const struct of_device_id camcc_sm7150_match_table[] = { 2024 { .compatible = "qcom,sm7150-camcc" }, 2025 { } 2026 }; 2027 MODULE_DEVICE_TABLE(of, camcc_sm7150_match_table); 2028 2029 static int camcc_sm7150_probe(struct platform_device *pdev) 2030 { 2031 struct regmap *regmap; 2032 2033 regmap = qcom_cc_map(pdev, &camcc_sm7150_desc); 2034 if (IS_ERR(regmap)) 2035 return PTR_ERR(regmap); 2036 2037 clk_fabia_pll_configure(&camcc_pll0, regmap, &camcc_pll0_config); 2038 clk_fabia_pll_configure(&camcc_pll1, regmap, &camcc_pll1_config); 2039 clk_agera_pll_configure(&camcc_pll2, regmap, &camcc_pll2_config); 2040 clk_fabia_pll_configure(&camcc_pll3, regmap, &camcc_pll3_config); 2041 clk_fabia_pll_configure(&camcc_pll4, regmap, &camcc_pll3_config); 2042 2043 /* Keep some clocks always-on */ 2044 qcom_branch_set_clk_en(regmap, 0xc1a0); /* CAMCC_GDSC_CLK */ 2045 2046 return qcom_cc_really_probe(&pdev->dev, &camcc_sm7150_desc, regmap); 2047 } 2048 2049 static struct platform_driver camcc_sm7150_driver = { 2050 .probe = camcc_sm7150_probe, 2051 .driver = { 2052 .name = "camcc-sm7150", 2053 .of_match_table = camcc_sm7150_match_table, 2054 }, 2055 }; 2056 2057 module_platform_driver(camcc_sm7150_driver); 2058 2059 MODULE_DESCRIPTION("Qualcomm SM7150 Camera Clock Controller"); 2060 MODULE_LICENSE("GPL"); 2061