1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Limited 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,sm6350-camcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "common.h" 18 #include "gdsc.h" 19 20 enum { 21 DT_BI_TCXO, 22 }; 23 24 enum { 25 P_BI_TCXO, 26 P_CAMCC_PLL0_OUT_EVEN, 27 P_CAMCC_PLL0_OUT_MAIN, 28 P_CAMCC_PLL1_OUT_EVEN, 29 P_CAMCC_PLL1_OUT_MAIN, 30 P_CAMCC_PLL2_OUT_EARLY, 31 P_CAMCC_PLL2_OUT_MAIN, 32 P_CAMCC_PLL3_OUT_MAIN, 33 }; 34 35 static const struct pll_vco fabia_vco[] = { 36 { 249600000, 2000000000, 0 }, 37 }; 38 39 /* 600MHz configuration */ 40 static const struct alpha_pll_config camcc_pll0_config = { 41 .l = 0x1f, 42 .alpha = 0x4000, 43 .config_ctl_val = 0x20485699, 44 .config_ctl_hi_val = 0x00002067, 45 .test_ctl_val = 0x40000000, 46 .test_ctl_hi_val = 0x00000002, 47 .user_ctl_val = 0x00000101, 48 .user_ctl_hi_val = 0x00004805, 49 }; 50 51 static struct clk_alpha_pll camcc_pll0 = { 52 .offset = 0x0, 53 .vco_table = fabia_vco, 54 .num_vco = ARRAY_SIZE(fabia_vco), 55 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 56 .clkr = { 57 .hw.init = &(struct clk_init_data){ 58 .name = "camcc_pll0", 59 .parent_data = &(const struct clk_parent_data){ 60 .index = DT_BI_TCXO, 61 }, 62 .num_parents = 1, 63 .ops = &clk_alpha_pll_fabia_ops, 64 }, 65 }, 66 }; 67 68 static const struct clk_div_table post_div_table_camcc_pll0_out_even[] = { 69 { 0x1, 2 }, 70 { } 71 }; 72 73 static struct clk_alpha_pll_postdiv camcc_pll0_out_even = { 74 .offset = 0x0, 75 .post_div_shift = 8, 76 .post_div_table = post_div_table_camcc_pll0_out_even, 77 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll0_out_even), 78 .width = 4, 79 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 80 .clkr.hw.init = &(struct clk_init_data){ 81 .name = "camcc_pll0_out_even", 82 .parent_hws = (const struct clk_hw*[]){ 83 &camcc_pll0.clkr.hw, 84 }, 85 .num_parents = 1, 86 .flags = CLK_SET_RATE_PARENT, 87 .ops = &clk_alpha_pll_postdiv_fabia_ops, 88 }, 89 }; 90 91 /* 808MHz configuration */ 92 static const struct alpha_pll_config camcc_pll1_config = { 93 .l = 0x2a, 94 .alpha = 0x1555, 95 .config_ctl_val = 0x20485699, 96 .config_ctl_hi_val = 0x00002067, 97 .test_ctl_val = 0x40000000, 98 .test_ctl_hi_val = 0x00000000, 99 .user_ctl_val = 0x00000101, 100 .user_ctl_hi_val = 0x00004805, 101 }; 102 103 static struct clk_alpha_pll camcc_pll1 = { 104 .offset = 0x1000, 105 .vco_table = fabia_vco, 106 .num_vco = ARRAY_SIZE(fabia_vco), 107 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 108 .clkr = { 109 .hw.init = &(struct clk_init_data){ 110 .name = "camcc_pll1", 111 .parent_data = &(const struct clk_parent_data){ 112 .index = DT_BI_TCXO, 113 }, 114 .num_parents = 1, 115 .ops = &clk_alpha_pll_fabia_ops, 116 }, 117 }, 118 }; 119 120 static const struct clk_div_table post_div_table_camcc_pll1_out_even[] = { 121 { 0x1, 2 }, 122 { } 123 }; 124 125 static struct clk_alpha_pll_postdiv camcc_pll1_out_even = { 126 .offset = 0x1000, 127 .post_div_shift = 8, 128 .post_div_table = post_div_table_camcc_pll1_out_even, 129 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll1_out_even), 130 .width = 4, 131 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 132 .clkr.hw.init = &(struct clk_init_data){ 133 .name = "camcc_pll1_out_even", 134 .parent_hws = (const struct clk_hw*[]){ 135 &camcc_pll1.clkr.hw, 136 }, 137 .num_parents = 1, 138 .flags = CLK_SET_RATE_PARENT, 139 .ops = &clk_alpha_pll_postdiv_fabia_ops, 140 }, 141 }; 142 143 /* 1920MHz configuration */ 144 static const struct alpha_pll_config camcc_pll2_config = { 145 .l = 0x64, 146 .alpha = 0x0, 147 .config_ctl_val = 0x20000800, 148 .config_ctl_hi_val = 0x400003d2, 149 .test_ctl_val = 0x04000400, 150 .test_ctl_hi_val = 0x00004000, 151 .user_ctl_val = 0x0000030b, 152 }; 153 154 static struct clk_alpha_pll camcc_pll2 = { 155 .offset = 0x2000, 156 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA], 157 .clkr = { 158 .hw.init = &(struct clk_init_data){ 159 .name = "camcc_pll2", 160 .parent_data = &(const struct clk_parent_data){ 161 .index = DT_BI_TCXO, 162 }, 163 .num_parents = 1, 164 .ops = &clk_alpha_pll_agera_ops, 165 }, 166 }, 167 }; 168 169 static struct clk_fixed_factor camcc_pll2_out_early = { 170 .mult = 1, 171 .div = 2, 172 .hw.init = &(struct clk_init_data){ 173 .name = "camcc_pll2_out_early", 174 .parent_hws = (const struct clk_hw*[]){ 175 &camcc_pll2.clkr.hw, 176 }, 177 .num_parents = 1, 178 .ops = &clk_fixed_factor_ops, 179 }, 180 }; 181 182 static const struct clk_div_table post_div_table_camcc_pll2_out_main[] = { 183 { 0x1, 2 }, 184 { } 185 }; 186 187 static struct clk_alpha_pll_postdiv camcc_pll2_out_main = { 188 .offset = 0x2000, 189 .post_div_shift = 8, 190 .post_div_table = post_div_table_camcc_pll2_out_main, 191 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll2_out_main), 192 .width = 2, 193 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA], 194 .clkr.hw.init = &(struct clk_init_data){ 195 .name = "camcc_pll2_out_main", 196 .parent_hws = (const struct clk_hw*[]){ 197 &camcc_pll2.clkr.hw, 198 }, 199 .num_parents = 1, 200 .flags = CLK_SET_RATE_PARENT, 201 .ops = &clk_alpha_pll_postdiv_ops, 202 }, 203 }; 204 205 /* 384MHz configuration */ 206 static const struct alpha_pll_config camcc_pll3_config = { 207 .l = 0x14, 208 .alpha = 0x0, 209 .config_ctl_val = 0x20485699, 210 .config_ctl_hi_val = 0x00002067, 211 .test_ctl_val = 0x40000000, 212 .test_ctl_hi_val = 0x00000002, 213 .user_ctl_val = 0x00000001, 214 .user_ctl_hi_val = 0x00014805, 215 }; 216 217 static struct clk_alpha_pll camcc_pll3 = { 218 .offset = 0x3000, 219 .vco_table = fabia_vco, 220 .num_vco = ARRAY_SIZE(fabia_vco), 221 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 222 .clkr = { 223 .hw.init = &(struct clk_init_data){ 224 .name = "camcc_pll3", 225 .parent_data = &(const struct clk_parent_data){ 226 .index = DT_BI_TCXO, 227 }, 228 .num_parents = 1, 229 .ops = &clk_alpha_pll_fabia_ops, 230 }, 231 }, 232 }; 233 234 static const struct parent_map camcc_parent_map_0[] = { 235 { P_BI_TCXO, 0 }, 236 { P_CAMCC_PLL0_OUT_EVEN, 6 }, 237 }; 238 239 static const struct clk_parent_data camcc_parent_data_0[] = { 240 { .fw_name = "bi_tcxo" }, 241 { .hw = &camcc_pll0_out_even.clkr.hw }, 242 }; 243 244 static const struct parent_map camcc_parent_map_1[] = { 245 { P_BI_TCXO, 0 }, 246 { P_CAMCC_PLL0_OUT_MAIN, 1 }, 247 { P_CAMCC_PLL1_OUT_EVEN, 3 }, 248 { P_CAMCC_PLL2_OUT_MAIN, 4 }, 249 }; 250 251 static const struct clk_parent_data camcc_parent_data_1[] = { 252 { .fw_name = "bi_tcxo" }, 253 { .hw = &camcc_pll0.clkr.hw }, 254 { .hw = &camcc_pll1_out_even.clkr.hw }, 255 { .hw = &camcc_pll2_out_main.clkr.hw }, 256 }; 257 258 static const struct parent_map camcc_parent_map_2[] = { 259 { P_BI_TCXO, 0 }, 260 { P_CAMCC_PLL0_OUT_MAIN, 1 }, 261 { P_CAMCC_PLL3_OUT_MAIN, 5 }, 262 }; 263 264 static const struct clk_parent_data camcc_parent_data_2[] = { 265 { .fw_name = "bi_tcxo" }, 266 { .hw = &camcc_pll0.clkr.hw }, 267 { .hw = &camcc_pll3.clkr.hw }, 268 }; 269 270 static const struct parent_map camcc_parent_map_3[] = { 271 { P_BI_TCXO, 0 }, 272 { P_CAMCC_PLL2_OUT_EARLY, 3 }, 273 }; 274 275 static const struct clk_parent_data camcc_parent_data_3[] = { 276 { .fw_name = "bi_tcxo" }, 277 { .hw = &camcc_pll2_out_early.hw }, 278 }; 279 280 static const struct parent_map camcc_parent_map_4[] = { 281 { P_BI_TCXO, 0 }, 282 { P_CAMCC_PLL0_OUT_MAIN, 1 }, 283 { P_CAMCC_PLL1_OUT_EVEN, 3 }, 284 }; 285 286 static const struct clk_parent_data camcc_parent_data_4[] = { 287 { .fw_name = "bi_tcxo" }, 288 { .hw = &camcc_pll0.clkr.hw }, 289 { .hw = &camcc_pll1_out_even.clkr.hw }, 290 }; 291 292 static const struct parent_map camcc_parent_map_5[] = { 293 { P_BI_TCXO, 0 }, 294 { P_CAMCC_PLL0_OUT_MAIN, 1 }, 295 { P_CAMCC_PLL1_OUT_EVEN, 3 }, 296 { P_CAMCC_PLL3_OUT_MAIN, 5 }, 297 }; 298 299 static const struct clk_parent_data camcc_parent_data_5[] = { 300 { .fw_name = "bi_tcxo" }, 301 { .hw = &camcc_pll0.clkr.hw }, 302 { .hw = &camcc_pll1_out_even.clkr.hw }, 303 { .hw = &camcc_pll3.clkr.hw }, 304 }; 305 306 static const struct parent_map camcc_parent_map_6[] = { 307 { P_BI_TCXO, 0 }, 308 { P_CAMCC_PLL0_OUT_MAIN, 1 }, 309 { P_CAMCC_PLL2_OUT_MAIN, 4 }, 310 }; 311 312 static const struct clk_parent_data camcc_parent_data_6[] = { 313 { .fw_name = "bi_tcxo" }, 314 { .hw = &camcc_pll0.clkr.hw }, 315 { .hw = &camcc_pll2_out_main.clkr.hw }, 316 }; 317 318 static const struct parent_map camcc_parent_map_7[] = { 319 { P_BI_TCXO, 0 }, 320 { P_CAMCC_PLL0_OUT_MAIN, 1 }, 321 { P_CAMCC_PLL1_OUT_MAIN, 2 }, 322 { P_CAMCC_PLL2_OUT_MAIN, 4 }, 323 }; 324 325 static const struct clk_parent_data camcc_parent_data_7[] = { 326 { .fw_name = "bi_tcxo" }, 327 { .hw = &camcc_pll0.clkr.hw }, 328 { .hw = &camcc_pll1.clkr.hw }, 329 { .hw = &camcc_pll2_out_main.clkr.hw }, 330 }; 331 332 static const struct parent_map camcc_parent_map_8[] = { 333 { P_BI_TCXO, 0 }, 334 { P_CAMCC_PLL0_OUT_MAIN, 1 }, 335 { P_CAMCC_PLL1_OUT_MAIN, 2 }, 336 }; 337 338 static const struct clk_parent_data camcc_parent_data_8[] = { 339 { .fw_name = "bi_tcxo" }, 340 { .hw = &camcc_pll0.clkr.hw }, 341 { .hw = &camcc_pll1.clkr.hw }, 342 }; 343 344 static const struct parent_map camcc_parent_map_9[] = { 345 { P_BI_TCXO, 0 }, 346 { P_CAMCC_PLL2_OUT_MAIN, 4 }, 347 }; 348 349 static const struct clk_parent_data camcc_parent_data_9[] = { 350 { .fw_name = "bi_tcxo" }, 351 { .hw = &camcc_pll2_out_main.clkr.hw }, 352 }; 353 354 static const struct freq_tbl ftbl_camcc_bps_clk_src[] = { 355 F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), 356 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0), 357 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), 358 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0), 359 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0), 360 { } 361 }; 362 363 static struct clk_rcg2 camcc_bps_clk_src = { 364 .cmd_rcgr = 0x6010, 365 .mnd_width = 0, 366 .hid_width = 5, 367 .parent_map = camcc_parent_map_1, 368 .freq_tbl = ftbl_camcc_bps_clk_src, 369 .clkr.hw.init = &(struct clk_init_data){ 370 .name = "camcc_bps_clk_src", 371 .parent_data = camcc_parent_data_1, 372 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 373 .ops = &clk_rcg2_ops, 374 }, 375 }; 376 377 static const struct freq_tbl ftbl_camcc_cci_0_clk_src[] = { 378 F(37500000, P_CAMCC_PLL0_OUT_EVEN, 8, 0, 0), 379 F(50000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0), 380 F(100000000, P_CAMCC_PLL0_OUT_EVEN, 3, 0, 0), 381 { } 382 }; 383 384 static struct clk_rcg2 camcc_cci_0_clk_src = { 385 .cmd_rcgr = 0xf004, 386 .mnd_width = 8, 387 .hid_width = 5, 388 .parent_map = camcc_parent_map_0, 389 .freq_tbl = ftbl_camcc_cci_0_clk_src, 390 .clkr.hw.init = &(struct clk_init_data){ 391 .name = "camcc_cci_0_clk_src", 392 .parent_data = camcc_parent_data_0, 393 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 394 .ops = &clk_rcg2_ops, 395 }, 396 }; 397 398 static struct clk_rcg2 camcc_cci_1_clk_src = { 399 .cmd_rcgr = 0x10004, 400 .mnd_width = 8, 401 .hid_width = 5, 402 .parent_map = camcc_parent_map_0, 403 .freq_tbl = ftbl_camcc_cci_0_clk_src, 404 .clkr.hw.init = &(struct clk_init_data){ 405 .name = "camcc_cci_1_clk_src", 406 .parent_data = camcc_parent_data_0, 407 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 408 .ops = &clk_rcg2_ops, 409 }, 410 }; 411 412 static const struct freq_tbl ftbl_camcc_cphy_rx_clk_src[] = { 413 F(150000000, P_CAMCC_PLL0_OUT_MAIN, 4, 0, 0), 414 F(300000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 415 F(384000000, P_CAMCC_PLL3_OUT_MAIN, 1, 0, 0), 416 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 1.5, 0, 0), 417 { } 418 }; 419 420 static struct clk_rcg2 camcc_cphy_rx_clk_src = { 421 .cmd_rcgr = 0x9064, 422 .mnd_width = 0, 423 .hid_width = 5, 424 .parent_map = camcc_parent_map_2, 425 .freq_tbl = ftbl_camcc_cphy_rx_clk_src, 426 .clkr.hw.init = &(struct clk_init_data){ 427 .name = "camcc_cphy_rx_clk_src", 428 .parent_data = camcc_parent_data_2, 429 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 430 .ops = &clk_rcg2_ops, 431 }, 432 }; 433 434 static const struct freq_tbl ftbl_camcc_csi0phytimer_clk_src[] = { 435 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 1, 0, 0), 436 { } 437 }; 438 439 static struct clk_rcg2 camcc_csi0phytimer_clk_src = { 440 .cmd_rcgr = 0x5004, 441 .mnd_width = 0, 442 .hid_width = 5, 443 .parent_map = camcc_parent_map_0, 444 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, 445 .clkr.hw.init = &(struct clk_init_data){ 446 .name = "camcc_csi0phytimer_clk_src", 447 .parent_data = camcc_parent_data_0, 448 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 449 .ops = &clk_rcg2_ops, 450 }, 451 }; 452 453 static struct clk_rcg2 camcc_csi1phytimer_clk_src = { 454 .cmd_rcgr = 0x5028, 455 .mnd_width = 0, 456 .hid_width = 5, 457 .parent_map = camcc_parent_map_0, 458 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, 459 .clkr.hw.init = &(struct clk_init_data){ 460 .name = "camcc_csi1phytimer_clk_src", 461 .parent_data = camcc_parent_data_0, 462 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 463 .ops = &clk_rcg2_ops, 464 }, 465 }; 466 467 static struct clk_rcg2 camcc_csi2phytimer_clk_src = { 468 .cmd_rcgr = 0x504c, 469 .mnd_width = 0, 470 .hid_width = 5, 471 .parent_map = camcc_parent_map_0, 472 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, 473 .clkr.hw.init = &(struct clk_init_data){ 474 .name = "camcc_csi2phytimer_clk_src", 475 .parent_data = camcc_parent_data_0, 476 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 477 .ops = &clk_rcg2_ops, 478 }, 479 }; 480 481 static struct clk_rcg2 camcc_csi3phytimer_clk_src = { 482 .cmd_rcgr = 0x5070, 483 .mnd_width = 0, 484 .hid_width = 5, 485 .parent_map = camcc_parent_map_0, 486 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, 487 .clkr.hw.init = &(struct clk_init_data){ 488 .name = "camcc_csi3phytimer_clk_src", 489 .parent_data = camcc_parent_data_0, 490 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 491 .ops = &clk_rcg2_ops, 492 }, 493 }; 494 495 static const struct freq_tbl ftbl_camcc_fast_ahb_clk_src[] = { 496 F(100000000, P_CAMCC_PLL0_OUT_MAIN, 6, 0, 0), 497 F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), 498 F(300000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 499 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), 500 { } 501 }; 502 503 static struct clk_rcg2 camcc_fast_ahb_clk_src = { 504 .cmd_rcgr = 0x603c, 505 .mnd_width = 0, 506 .hid_width = 5, 507 .parent_map = camcc_parent_map_4, 508 .freq_tbl = ftbl_camcc_fast_ahb_clk_src, 509 .clkr.hw.init = &(struct clk_init_data){ 510 .name = "camcc_fast_ahb_clk_src", 511 .parent_data = camcc_parent_data_4, 512 .num_parents = ARRAY_SIZE(camcc_parent_data_4), 513 .ops = &clk_rcg2_ops, 514 }, 515 }; 516 517 static const struct freq_tbl ftbl_camcc_icp_clk_src[] = { 518 F(240000000, P_CAMCC_PLL0_OUT_MAIN, 2.5, 0, 0), 519 F(384000000, P_CAMCC_PLL3_OUT_MAIN, 1, 0, 0), 520 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), 521 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0), 522 { } 523 }; 524 525 static struct clk_rcg2 camcc_icp_clk_src = { 526 .cmd_rcgr = 0xe014, 527 .mnd_width = 0, 528 .hid_width = 5, 529 .parent_map = camcc_parent_map_5, 530 .freq_tbl = ftbl_camcc_icp_clk_src, 531 .clkr.hw.init = &(struct clk_init_data){ 532 .name = "camcc_icp_clk_src", 533 .parent_data = camcc_parent_data_5, 534 .num_parents = ARRAY_SIZE(camcc_parent_data_5), 535 .ops = &clk_rcg2_ops, 536 }, 537 }; 538 539 static const struct freq_tbl ftbl_camcc_ife_0_clk_src[] = { 540 F(240000000, P_CAMCC_PLL0_OUT_MAIN, 2.5, 0, 0), 541 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0), 542 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), 543 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0), 544 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0), 545 { } 546 }; 547 548 static struct clk_rcg2 camcc_ife_0_clk_src = { 549 .cmd_rcgr = 0x9010, 550 .mnd_width = 0, 551 .hid_width = 5, 552 .parent_map = camcc_parent_map_1, 553 .freq_tbl = ftbl_camcc_ife_0_clk_src, 554 .clkr.hw.init = &(struct clk_init_data){ 555 .name = "camcc_ife_0_clk_src", 556 .parent_data = camcc_parent_data_1, 557 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 558 .flags = CLK_SET_RATE_PARENT, 559 .ops = &clk_rcg2_ops, 560 }, 561 }; 562 563 static struct clk_rcg2 camcc_ife_0_csid_clk_src = { 564 .cmd_rcgr = 0x903c, 565 .mnd_width = 0, 566 .hid_width = 5, 567 .parent_map = camcc_parent_map_2, 568 .freq_tbl = ftbl_camcc_cphy_rx_clk_src, 569 .clkr.hw.init = &(struct clk_init_data){ 570 .name = "camcc_ife_0_csid_clk_src", 571 .parent_data = camcc_parent_data_2, 572 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 573 .ops = &clk_rcg2_ops, 574 }, 575 }; 576 577 static struct clk_rcg2 camcc_ife_1_clk_src = { 578 .cmd_rcgr = 0xa010, 579 .mnd_width = 0, 580 .hid_width = 5, 581 .parent_map = camcc_parent_map_1, 582 .freq_tbl = ftbl_camcc_ife_0_clk_src, 583 .clkr.hw.init = &(struct clk_init_data){ 584 .name = "camcc_ife_1_clk_src", 585 .parent_data = camcc_parent_data_1, 586 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 587 .flags = CLK_SET_RATE_PARENT, 588 .ops = &clk_rcg2_ops, 589 }, 590 }; 591 592 static struct clk_rcg2 camcc_ife_1_csid_clk_src = { 593 .cmd_rcgr = 0xa034, 594 .mnd_width = 0, 595 .hid_width = 5, 596 .parent_map = camcc_parent_map_2, 597 .freq_tbl = ftbl_camcc_cphy_rx_clk_src, 598 .clkr.hw.init = &(struct clk_init_data){ 599 .name = "camcc_ife_1_csid_clk_src", 600 .parent_data = camcc_parent_data_2, 601 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 602 .ops = &clk_rcg2_ops, 603 }, 604 }; 605 606 static struct clk_rcg2 camcc_ife_2_clk_src = { 607 .cmd_rcgr = 0xb00c, 608 .mnd_width = 0, 609 .hid_width = 5, 610 .parent_map = camcc_parent_map_1, 611 .freq_tbl = ftbl_camcc_ife_0_clk_src, 612 .clkr.hw.init = &(struct clk_init_data){ 613 .name = "camcc_ife_2_clk_src", 614 .parent_data = camcc_parent_data_1, 615 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 616 .ops = &clk_rcg2_ops, 617 }, 618 }; 619 620 static struct clk_rcg2 camcc_ife_2_csid_clk_src = { 621 .cmd_rcgr = 0xb030, 622 .mnd_width = 0, 623 .hid_width = 5, 624 .parent_map = camcc_parent_map_2, 625 .freq_tbl = ftbl_camcc_cphy_rx_clk_src, 626 .clkr.hw.init = &(struct clk_init_data){ 627 .name = "camcc_ife_2_csid_clk_src", 628 .parent_data = camcc_parent_data_2, 629 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 630 .ops = &clk_rcg2_ops, 631 }, 632 }; 633 634 static const struct freq_tbl ftbl_camcc_ife_lite_clk_src[] = { 635 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0), 636 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 1.5, 0, 0), 637 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0), 638 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0), 639 { } 640 }; 641 642 static struct clk_rcg2 camcc_ife_lite_clk_src = { 643 .cmd_rcgr = 0xc004, 644 .mnd_width = 0, 645 .hid_width = 5, 646 .parent_map = camcc_parent_map_6, 647 .freq_tbl = ftbl_camcc_ife_lite_clk_src, 648 .clkr.hw.init = &(struct clk_init_data){ 649 .name = "camcc_ife_lite_clk_src", 650 .parent_data = camcc_parent_data_6, 651 .num_parents = ARRAY_SIZE(camcc_parent_data_6), 652 .ops = &clk_rcg2_ops, 653 }, 654 }; 655 656 static struct clk_rcg2 camcc_ife_lite_csid_clk_src = { 657 .cmd_rcgr = 0xc024, 658 .mnd_width = 0, 659 .hid_width = 5, 660 .parent_map = camcc_parent_map_2, 661 .freq_tbl = ftbl_camcc_cphy_rx_clk_src, 662 .clkr.hw.init = &(struct clk_init_data){ 663 .name = "camcc_ife_lite_csid_clk_src", 664 .parent_data = camcc_parent_data_2, 665 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 666 .ops = &clk_rcg2_ops, 667 }, 668 }; 669 670 static const struct freq_tbl ftbl_camcc_ipe_0_clk_src[] = { 671 F(240000000, P_CAMCC_PLL2_OUT_MAIN, 2, 0, 0), 672 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0), 673 F(404000000, P_CAMCC_PLL1_OUT_MAIN, 2, 0, 0), 674 F(538666667, P_CAMCC_PLL1_OUT_MAIN, 1.5, 0, 0), 675 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0), 676 { } 677 }; 678 679 static struct clk_rcg2 camcc_ipe_0_clk_src = { 680 .cmd_rcgr = 0x7010, 681 .mnd_width = 0, 682 .hid_width = 5, 683 .parent_map = camcc_parent_map_7, 684 .freq_tbl = ftbl_camcc_ipe_0_clk_src, 685 .clkr.hw.init = &(struct clk_init_data){ 686 .name = "camcc_ipe_0_clk_src", 687 .parent_data = camcc_parent_data_7, 688 .num_parents = ARRAY_SIZE(camcc_parent_data_7), 689 .flags = CLK_SET_RATE_PARENT, 690 .ops = &clk_rcg2_ops, 691 }, 692 }; 693 694 static const struct freq_tbl ftbl_camcc_jpeg_clk_src[] = { 695 F(66666667, P_CAMCC_PLL0_OUT_MAIN, 9, 0, 0), 696 F(133333333, P_CAMCC_PLL0_OUT_MAIN, 4.5, 0, 0), 697 F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), 698 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), 699 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0), 700 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0), 701 { } 702 }; 703 704 static struct clk_rcg2 camcc_jpeg_clk_src = { 705 .cmd_rcgr = 0xd004, 706 .mnd_width = 0, 707 .hid_width = 5, 708 .parent_map = camcc_parent_map_1, 709 .freq_tbl = ftbl_camcc_jpeg_clk_src, 710 .clkr.hw.init = &(struct clk_init_data){ 711 .name = "camcc_jpeg_clk_src", 712 .parent_data = camcc_parent_data_1, 713 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 714 .ops = &clk_rcg2_ops, 715 }, 716 }; 717 718 static const struct freq_tbl ftbl_camcc_lrme_clk_src[] = { 719 F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), 720 F(269333333, P_CAMCC_PLL1_OUT_MAIN, 3, 0, 0), 721 F(323200000, P_CAMCC_PLL1_OUT_MAIN, 2.5, 0, 0), 722 F(404000000, P_CAMCC_PLL1_OUT_MAIN, 2, 0, 0), 723 { } 724 }; 725 726 static struct clk_rcg2 camcc_lrme_clk_src = { 727 .cmd_rcgr = 0x11004, 728 .mnd_width = 0, 729 .hid_width = 5, 730 .parent_map = camcc_parent_map_8, 731 .freq_tbl = ftbl_camcc_lrme_clk_src, 732 .clkr.hw.init = &(struct clk_init_data){ 733 .name = "camcc_lrme_clk_src", 734 .parent_data = camcc_parent_data_8, 735 .num_parents = ARRAY_SIZE(camcc_parent_data_8), 736 .ops = &clk_rcg2_ops, 737 }, 738 }; 739 740 static const struct freq_tbl ftbl_camcc_mclk0_clk_src[] = { 741 F(19200000, P_CAMCC_PLL2_OUT_EARLY, 1, 1, 50), 742 F(24000000, P_CAMCC_PLL2_OUT_EARLY, 10, 1, 4), 743 F(64000000, P_CAMCC_PLL2_OUT_EARLY, 15, 0, 0), 744 { } 745 }; 746 747 static struct clk_rcg2 camcc_mclk0_clk_src = { 748 .cmd_rcgr = 0x4004, 749 .mnd_width = 8, 750 .hid_width = 5, 751 .parent_map = camcc_parent_map_3, 752 .freq_tbl = ftbl_camcc_mclk0_clk_src, 753 .clkr.hw.init = &(struct clk_init_data){ 754 .name = "camcc_mclk0_clk_src", 755 .parent_data = camcc_parent_data_3, 756 .num_parents = ARRAY_SIZE(camcc_parent_data_3), 757 .ops = &clk_rcg2_ops, 758 }, 759 }; 760 761 static struct clk_rcg2 camcc_mclk1_clk_src = { 762 .cmd_rcgr = 0x4024, 763 .mnd_width = 8, 764 .hid_width = 5, 765 .parent_map = camcc_parent_map_3, 766 .freq_tbl = ftbl_camcc_mclk0_clk_src, 767 .clkr.hw.init = &(struct clk_init_data){ 768 .name = "camcc_mclk1_clk_src", 769 .parent_data = camcc_parent_data_3, 770 .num_parents = ARRAY_SIZE(camcc_parent_data_3), 771 .ops = &clk_rcg2_ops, 772 }, 773 }; 774 775 static struct clk_rcg2 camcc_mclk2_clk_src = { 776 .cmd_rcgr = 0x4044, 777 .mnd_width = 8, 778 .hid_width = 5, 779 .parent_map = camcc_parent_map_3, 780 .freq_tbl = ftbl_camcc_mclk0_clk_src, 781 .clkr.hw.init = &(struct clk_init_data){ 782 .name = "camcc_mclk2_clk_src", 783 .parent_data = camcc_parent_data_3, 784 .num_parents = ARRAY_SIZE(camcc_parent_data_3), 785 .ops = &clk_rcg2_ops, 786 }, 787 }; 788 789 static struct clk_rcg2 camcc_mclk3_clk_src = { 790 .cmd_rcgr = 0x4064, 791 .mnd_width = 8, 792 .hid_width = 5, 793 .parent_map = camcc_parent_map_3, 794 .freq_tbl = ftbl_camcc_mclk0_clk_src, 795 .clkr.hw.init = &(struct clk_init_data){ 796 .name = "camcc_mclk3_clk_src", 797 .parent_data = camcc_parent_data_3, 798 .num_parents = ARRAY_SIZE(camcc_parent_data_3), 799 .ops = &clk_rcg2_ops, 800 }, 801 }; 802 803 static struct clk_rcg2 camcc_mclk4_clk_src = { 804 .cmd_rcgr = 0x4084, 805 .mnd_width = 8, 806 .hid_width = 5, 807 .parent_map = camcc_parent_map_3, 808 .freq_tbl = ftbl_camcc_mclk0_clk_src, 809 .clkr.hw.init = &(struct clk_init_data){ 810 .name = "camcc_mclk4_clk_src", 811 .parent_data = camcc_parent_data_3, 812 .num_parents = ARRAY_SIZE(camcc_parent_data_3), 813 .ops = &clk_rcg2_ops, 814 }, 815 }; 816 817 static const struct freq_tbl ftbl_camcc_slow_ahb_clk_src[] = { 818 F(80000000, P_CAMCC_PLL2_OUT_MAIN, 6, 0, 0), 819 { } 820 }; 821 822 static struct clk_rcg2 camcc_slow_ahb_clk_src = { 823 .cmd_rcgr = 0x6058, 824 .mnd_width = 0, 825 .hid_width = 5, 826 .parent_map = camcc_parent_map_9, 827 .freq_tbl = ftbl_camcc_slow_ahb_clk_src, 828 .clkr.hw.init = &(struct clk_init_data){ 829 .name = "camcc_slow_ahb_clk_src", 830 .parent_data = camcc_parent_data_9, 831 .num_parents = ARRAY_SIZE(camcc_parent_data_9), 832 .ops = &clk_rcg2_ops, 833 }, 834 }; 835 836 static struct clk_branch camcc_bps_ahb_clk = { 837 .halt_reg = 0x6070, 838 .halt_check = BRANCH_HALT, 839 .clkr = { 840 .enable_reg = 0x6070, 841 .enable_mask = BIT(0), 842 .hw.init = &(struct clk_init_data){ 843 .name = "camcc_bps_ahb_clk", 844 .parent_hws = (const struct clk_hw*[]){ 845 &camcc_slow_ahb_clk_src.clkr.hw 846 }, 847 .num_parents = 1, 848 .flags = CLK_SET_RATE_PARENT, 849 .ops = &clk_branch2_ops, 850 }, 851 }, 852 }; 853 854 static struct clk_branch camcc_bps_areg_clk = { 855 .halt_reg = 0x6054, 856 .halt_check = BRANCH_HALT, 857 .clkr = { 858 .enable_reg = 0x6054, 859 .enable_mask = BIT(0), 860 .hw.init = &(struct clk_init_data){ 861 .name = "camcc_bps_areg_clk", 862 .parent_hws = (const struct clk_hw*[]){ 863 &camcc_fast_ahb_clk_src.clkr.hw 864 }, 865 .num_parents = 1, 866 .flags = CLK_SET_RATE_PARENT, 867 .ops = &clk_branch2_ops, 868 }, 869 }, 870 }; 871 872 static struct clk_branch camcc_bps_axi_clk = { 873 .halt_reg = 0x6038, 874 .halt_check = BRANCH_HALT, 875 .clkr = { 876 .enable_reg = 0x6038, 877 .enable_mask = BIT(0), 878 .hw.init = &(struct clk_init_data){ 879 .name = "camcc_bps_axi_clk", 880 .ops = &clk_branch2_ops, 881 }, 882 }, 883 }; 884 885 static struct clk_branch camcc_bps_clk = { 886 .halt_reg = 0x6028, 887 .halt_check = BRANCH_HALT, 888 .clkr = { 889 .enable_reg = 0x6028, 890 .enable_mask = BIT(0), 891 .hw.init = &(struct clk_init_data){ 892 .name = "camcc_bps_clk", 893 .parent_hws = (const struct clk_hw*[]){ 894 &camcc_bps_clk_src.clkr.hw 895 }, 896 .num_parents = 1, 897 .flags = CLK_SET_RATE_PARENT, 898 .ops = &clk_branch2_ops, 899 }, 900 }, 901 }; 902 903 static struct clk_branch camcc_camnoc_axi_clk = { 904 .halt_reg = 0x13004, 905 .halt_check = BRANCH_HALT, 906 .clkr = { 907 .enable_reg = 0x13004, 908 .enable_mask = BIT(0), 909 .hw.init = &(struct clk_init_data){ 910 .name = "camcc_camnoc_axi_clk", 911 .ops = &clk_branch2_ops, 912 }, 913 }, 914 }; 915 916 static struct clk_branch camcc_cci_0_clk = { 917 .halt_reg = 0xf01c, 918 .halt_check = BRANCH_HALT, 919 .clkr = { 920 .enable_reg = 0xf01c, 921 .enable_mask = BIT(0), 922 .hw.init = &(struct clk_init_data){ 923 .name = "camcc_cci_0_clk", 924 .parent_hws = (const struct clk_hw*[]){ 925 &camcc_cci_0_clk_src.clkr.hw 926 }, 927 .num_parents = 1, 928 .flags = CLK_SET_RATE_PARENT, 929 .ops = &clk_branch2_ops, 930 }, 931 }, 932 }; 933 934 static struct clk_branch camcc_cci_1_clk = { 935 .halt_reg = 0x1001c, 936 .halt_check = BRANCH_HALT, 937 .clkr = { 938 .enable_reg = 0x1001c, 939 .enable_mask = BIT(0), 940 .hw.init = &(struct clk_init_data){ 941 .name = "camcc_cci_1_clk", 942 .parent_hws = (const struct clk_hw*[]){ 943 &camcc_cci_1_clk_src.clkr.hw 944 }, 945 .num_parents = 1, 946 .flags = CLK_SET_RATE_PARENT, 947 .ops = &clk_branch2_ops, 948 }, 949 }, 950 }; 951 952 static struct clk_branch camcc_core_ahb_clk = { 953 .halt_reg = 0x14010, 954 .halt_check = BRANCH_HALT_VOTED, 955 .clkr = { 956 .enable_reg = 0x14010, 957 .enable_mask = BIT(0), 958 .hw.init = &(struct clk_init_data){ 959 .name = "camcc_core_ahb_clk", 960 .parent_hws = (const struct clk_hw*[]){ 961 &camcc_slow_ahb_clk_src.clkr.hw 962 }, 963 .num_parents = 1, 964 .flags = CLK_SET_RATE_PARENT, 965 .ops = &clk_branch2_ops, 966 }, 967 }, 968 }; 969 970 static struct clk_branch camcc_cpas_ahb_clk = { 971 .halt_reg = 0x12004, 972 .halt_check = BRANCH_HALT, 973 .clkr = { 974 .enable_reg = 0x12004, 975 .enable_mask = BIT(0), 976 .hw.init = &(struct clk_init_data){ 977 .name = "camcc_cpas_ahb_clk", 978 .parent_hws = (const struct clk_hw*[]){ 979 &camcc_slow_ahb_clk_src.clkr.hw 980 }, 981 .num_parents = 1, 982 .flags = CLK_SET_RATE_PARENT, 983 .ops = &clk_branch2_ops, 984 }, 985 }, 986 }; 987 988 static struct clk_branch camcc_csi0phytimer_clk = { 989 .halt_reg = 0x501c, 990 .halt_check = BRANCH_HALT, 991 .clkr = { 992 .enable_reg = 0x501c, 993 .enable_mask = BIT(0), 994 .hw.init = &(struct clk_init_data){ 995 .name = "camcc_csi0phytimer_clk", 996 .parent_hws = (const struct clk_hw*[]){ 997 &camcc_csi0phytimer_clk_src.clkr.hw 998 }, 999 .num_parents = 1, 1000 .flags = CLK_SET_RATE_PARENT, 1001 .ops = &clk_branch2_ops, 1002 }, 1003 }, 1004 }; 1005 1006 static struct clk_branch camcc_csi1phytimer_clk = { 1007 .halt_reg = 0x5040, 1008 .halt_check = BRANCH_HALT, 1009 .clkr = { 1010 .enable_reg = 0x5040, 1011 .enable_mask = BIT(0), 1012 .hw.init = &(struct clk_init_data){ 1013 .name = "camcc_csi1phytimer_clk", 1014 .parent_hws = (const struct clk_hw*[]){ 1015 &camcc_csi1phytimer_clk_src.clkr.hw 1016 }, 1017 .num_parents = 1, 1018 .flags = CLK_SET_RATE_PARENT, 1019 .ops = &clk_branch2_ops, 1020 }, 1021 }, 1022 }; 1023 1024 static struct clk_branch camcc_csi2phytimer_clk = { 1025 .halt_reg = 0x5064, 1026 .halt_check = BRANCH_HALT, 1027 .clkr = { 1028 .enable_reg = 0x5064, 1029 .enable_mask = BIT(0), 1030 .hw.init = &(struct clk_init_data){ 1031 .name = "camcc_csi2phytimer_clk", 1032 .parent_hws = (const struct clk_hw*[]){ 1033 &camcc_csi2phytimer_clk_src.clkr.hw 1034 }, 1035 .num_parents = 1, 1036 .flags = CLK_SET_RATE_PARENT, 1037 .ops = &clk_branch2_ops, 1038 }, 1039 }, 1040 }; 1041 1042 static struct clk_branch camcc_csi3phytimer_clk = { 1043 .halt_reg = 0x5088, 1044 .halt_check = BRANCH_HALT, 1045 .clkr = { 1046 .enable_reg = 0x5088, 1047 .enable_mask = BIT(0), 1048 .hw.init = &(struct clk_init_data){ 1049 .name = "camcc_csi3phytimer_clk", 1050 .parent_hws = (const struct clk_hw*[]){ 1051 &camcc_csi3phytimer_clk_src.clkr.hw 1052 }, 1053 .num_parents = 1, 1054 .flags = CLK_SET_RATE_PARENT, 1055 .ops = &clk_branch2_ops, 1056 }, 1057 }, 1058 }; 1059 1060 static struct clk_branch camcc_csiphy0_clk = { 1061 .halt_reg = 0x5020, 1062 .halt_check = BRANCH_HALT, 1063 .clkr = { 1064 .enable_reg = 0x5020, 1065 .enable_mask = BIT(0), 1066 .hw.init = &(struct clk_init_data){ 1067 .name = "camcc_csiphy0_clk", 1068 .parent_hws = (const struct clk_hw*[]){ 1069 &camcc_cphy_rx_clk_src.clkr.hw 1070 }, 1071 .num_parents = 1, 1072 .flags = CLK_SET_RATE_PARENT, 1073 .ops = &clk_branch2_ops, 1074 }, 1075 }, 1076 }; 1077 1078 static struct clk_branch camcc_csiphy1_clk = { 1079 .halt_reg = 0x5044, 1080 .halt_check = BRANCH_HALT, 1081 .clkr = { 1082 .enable_reg = 0x5044, 1083 .enable_mask = BIT(0), 1084 .hw.init = &(struct clk_init_data){ 1085 .name = "camcc_csiphy1_clk", 1086 .parent_hws = (const struct clk_hw*[]){ 1087 &camcc_cphy_rx_clk_src.clkr.hw 1088 }, 1089 .num_parents = 1, 1090 .flags = CLK_SET_RATE_PARENT, 1091 .ops = &clk_branch2_ops, 1092 }, 1093 }, 1094 }; 1095 1096 static struct clk_branch camcc_csiphy2_clk = { 1097 .halt_reg = 0x5068, 1098 .halt_check = BRANCH_HALT, 1099 .clkr = { 1100 .enable_reg = 0x5068, 1101 .enable_mask = BIT(0), 1102 .hw.init = &(struct clk_init_data){ 1103 .name = "camcc_csiphy2_clk", 1104 .parent_hws = (const struct clk_hw*[]){ 1105 &camcc_cphy_rx_clk_src.clkr.hw 1106 }, 1107 .num_parents = 1, 1108 .flags = CLK_SET_RATE_PARENT, 1109 .ops = &clk_branch2_ops, 1110 }, 1111 }, 1112 }; 1113 1114 static struct clk_branch camcc_csiphy3_clk = { 1115 .halt_reg = 0x508c, 1116 .halt_check = BRANCH_HALT, 1117 .clkr = { 1118 .enable_reg = 0x508c, 1119 .enable_mask = BIT(0), 1120 .hw.init = &(struct clk_init_data){ 1121 .name = "camcc_csiphy3_clk", 1122 .parent_hws = (const struct clk_hw*[]){ 1123 &camcc_cphy_rx_clk_src.clkr.hw 1124 }, 1125 .num_parents = 1, 1126 .flags = CLK_SET_RATE_PARENT, 1127 .ops = &clk_branch2_ops, 1128 }, 1129 }, 1130 }; 1131 1132 static struct clk_branch camcc_icp_clk = { 1133 .halt_reg = 0xe02c, 1134 .halt_check = BRANCH_HALT, 1135 .clkr = { 1136 .enable_reg = 0xe02c, 1137 .enable_mask = BIT(0), 1138 .hw.init = &(struct clk_init_data){ 1139 .name = "camcc_icp_clk", 1140 .parent_hws = (const struct clk_hw*[]){ 1141 &camcc_icp_clk_src.clkr.hw 1142 }, 1143 .num_parents = 1, 1144 .flags = CLK_SET_RATE_PARENT, 1145 .ops = &clk_branch2_ops, 1146 }, 1147 }, 1148 }; 1149 1150 static struct clk_branch camcc_icp_ts_clk = { 1151 .halt_reg = 0xe00c, 1152 .halt_check = BRANCH_HALT, 1153 .clkr = { 1154 .enable_reg = 0xe00c, 1155 .enable_mask = BIT(0), 1156 .hw.init = &(struct clk_init_data){ 1157 .name = "camcc_icp_ts_clk", 1158 .ops = &clk_branch2_ops, 1159 }, 1160 }, 1161 }; 1162 1163 static struct clk_branch camcc_ife_0_axi_clk = { 1164 .halt_reg = 0x9080, 1165 .halt_check = BRANCH_HALT, 1166 .clkr = { 1167 .enable_reg = 0x9080, 1168 .enable_mask = BIT(0), 1169 .hw.init = &(struct clk_init_data){ 1170 .name = "camcc_ife_0_axi_clk", 1171 .ops = &clk_branch2_ops, 1172 }, 1173 }, 1174 }; 1175 1176 static struct clk_branch camcc_ife_0_clk = { 1177 .halt_reg = 0x9028, 1178 .halt_check = BRANCH_HALT, 1179 .clkr = { 1180 .enable_reg = 0x9028, 1181 .enable_mask = BIT(0), 1182 .hw.init = &(struct clk_init_data){ 1183 .name = "camcc_ife_0_clk", 1184 .parent_hws = (const struct clk_hw*[]){ 1185 &camcc_ife_0_clk_src.clkr.hw 1186 }, 1187 .num_parents = 1, 1188 .flags = CLK_SET_RATE_PARENT, 1189 .ops = &clk_branch2_ops, 1190 }, 1191 }, 1192 }; 1193 1194 static struct clk_branch camcc_ife_0_cphy_rx_clk = { 1195 .halt_reg = 0x907c, 1196 .halt_check = BRANCH_HALT, 1197 .clkr = { 1198 .enable_reg = 0x907c, 1199 .enable_mask = BIT(0), 1200 .hw.init = &(struct clk_init_data){ 1201 .name = "camcc_ife_0_cphy_rx_clk", 1202 .parent_hws = (const struct clk_hw*[]){ 1203 &camcc_cphy_rx_clk_src.clkr.hw 1204 }, 1205 .num_parents = 1, 1206 .flags = CLK_SET_RATE_PARENT, 1207 .ops = &clk_branch2_ops, 1208 }, 1209 }, 1210 }; 1211 1212 static struct clk_branch camcc_ife_0_csid_clk = { 1213 .halt_reg = 0x9054, 1214 .halt_check = BRANCH_HALT, 1215 .clkr = { 1216 .enable_reg = 0x9054, 1217 .enable_mask = BIT(0), 1218 .hw.init = &(struct clk_init_data){ 1219 .name = "camcc_ife_0_csid_clk", 1220 .parent_hws = (const struct clk_hw*[]){ 1221 &camcc_ife_0_csid_clk_src.clkr.hw 1222 }, 1223 .num_parents = 1, 1224 .flags = CLK_SET_RATE_PARENT, 1225 .ops = &clk_branch2_ops, 1226 }, 1227 }, 1228 }; 1229 1230 static struct clk_branch camcc_ife_0_dsp_clk = { 1231 .halt_reg = 0x9038, 1232 .halt_check = BRANCH_HALT, 1233 .clkr = { 1234 .enable_reg = 0x9038, 1235 .enable_mask = BIT(0), 1236 .hw.init = &(struct clk_init_data){ 1237 .name = "camcc_ife_0_dsp_clk", 1238 .parent_hws = (const struct clk_hw*[]){ 1239 &camcc_ife_0_clk_src.clkr.hw 1240 }, 1241 .num_parents = 1, 1242 .flags = CLK_SET_RATE_PARENT, 1243 .ops = &clk_branch2_ops, 1244 }, 1245 }, 1246 }; 1247 1248 static struct clk_branch camcc_ife_1_axi_clk = { 1249 .halt_reg = 0xa058, 1250 .halt_check = BRANCH_HALT, 1251 .clkr = { 1252 .enable_reg = 0xa058, 1253 .enable_mask = BIT(0), 1254 .hw.init = &(struct clk_init_data){ 1255 .name = "camcc_ife_1_axi_clk", 1256 .ops = &clk_branch2_ops, 1257 }, 1258 }, 1259 }; 1260 1261 static struct clk_branch camcc_ife_1_clk = { 1262 .halt_reg = 0xa028, 1263 .halt_check = BRANCH_HALT, 1264 .clkr = { 1265 .enable_reg = 0xa028, 1266 .enable_mask = BIT(0), 1267 .hw.init = &(struct clk_init_data){ 1268 .name = "camcc_ife_1_clk", 1269 .parent_hws = (const struct clk_hw*[]){ 1270 &camcc_ife_1_clk_src.clkr.hw 1271 }, 1272 .num_parents = 1, 1273 .flags = CLK_SET_RATE_PARENT, 1274 .ops = &clk_branch2_ops, 1275 }, 1276 }, 1277 }; 1278 1279 static struct clk_branch camcc_ife_1_cphy_rx_clk = { 1280 .halt_reg = 0xa054, 1281 .halt_check = BRANCH_HALT, 1282 .clkr = { 1283 .enable_reg = 0xa054, 1284 .enable_mask = BIT(0), 1285 .hw.init = &(struct clk_init_data){ 1286 .name = "camcc_ife_1_cphy_rx_clk", 1287 .parent_hws = (const struct clk_hw*[]){ 1288 &camcc_cphy_rx_clk_src.clkr.hw 1289 }, 1290 .num_parents = 1, 1291 .flags = CLK_SET_RATE_PARENT, 1292 .ops = &clk_branch2_ops, 1293 }, 1294 }, 1295 }; 1296 1297 static struct clk_branch camcc_ife_1_csid_clk = { 1298 .halt_reg = 0xa04c, 1299 .halt_check = BRANCH_HALT, 1300 .clkr = { 1301 .enable_reg = 0xa04c, 1302 .enable_mask = BIT(0), 1303 .hw.init = &(struct clk_init_data){ 1304 .name = "camcc_ife_1_csid_clk", 1305 .parent_hws = (const struct clk_hw*[]){ 1306 &camcc_ife_1_csid_clk_src.clkr.hw 1307 }, 1308 .num_parents = 1, 1309 .flags = CLK_SET_RATE_PARENT, 1310 .ops = &clk_branch2_ops, 1311 }, 1312 }, 1313 }; 1314 1315 static struct clk_branch camcc_ife_1_dsp_clk = { 1316 .halt_reg = 0xa030, 1317 .halt_check = BRANCH_HALT, 1318 .clkr = { 1319 .enable_reg = 0xa030, 1320 .enable_mask = BIT(0), 1321 .hw.init = &(struct clk_init_data){ 1322 .name = "camcc_ife_1_dsp_clk", 1323 .parent_hws = (const struct clk_hw*[]){ 1324 &camcc_ife_1_clk_src.clkr.hw 1325 }, 1326 .num_parents = 1, 1327 .flags = CLK_SET_RATE_PARENT, 1328 .ops = &clk_branch2_ops, 1329 }, 1330 }, 1331 }; 1332 1333 static struct clk_branch camcc_ife_2_axi_clk = { 1334 .halt_reg = 0xb054, 1335 .halt_check = BRANCH_HALT, 1336 .clkr = { 1337 .enable_reg = 0xb054, 1338 .enable_mask = BIT(0), 1339 .hw.init = &(struct clk_init_data){ 1340 .name = "camcc_ife_2_axi_clk", 1341 .ops = &clk_branch2_ops, 1342 }, 1343 }, 1344 }; 1345 1346 static struct clk_branch camcc_ife_2_clk = { 1347 .halt_reg = 0xb024, 1348 .halt_check = BRANCH_HALT, 1349 .clkr = { 1350 .enable_reg = 0xb024, 1351 .enable_mask = BIT(0), 1352 .hw.init = &(struct clk_init_data){ 1353 .name = "camcc_ife_2_clk", 1354 .parent_hws = (const struct clk_hw*[]){ 1355 &camcc_ife_2_clk_src.clkr.hw 1356 }, 1357 .num_parents = 1, 1358 .flags = CLK_SET_RATE_PARENT, 1359 .ops = &clk_branch2_ops, 1360 }, 1361 }, 1362 }; 1363 1364 static struct clk_branch camcc_ife_2_cphy_rx_clk = { 1365 .halt_reg = 0xb050, 1366 .halt_check = BRANCH_HALT, 1367 .clkr = { 1368 .enable_reg = 0xb050, 1369 .enable_mask = BIT(0), 1370 .hw.init = &(struct clk_init_data){ 1371 .name = "camcc_ife_2_cphy_rx_clk", 1372 .parent_hws = (const struct clk_hw*[]){ 1373 &camcc_cphy_rx_clk_src.clkr.hw 1374 }, 1375 .num_parents = 1, 1376 .flags = CLK_SET_RATE_PARENT, 1377 .ops = &clk_branch2_ops, 1378 }, 1379 }, 1380 }; 1381 1382 static struct clk_branch camcc_ife_2_csid_clk = { 1383 .halt_reg = 0xb048, 1384 .halt_check = BRANCH_HALT, 1385 .clkr = { 1386 .enable_reg = 0xb048, 1387 .enable_mask = BIT(0), 1388 .hw.init = &(struct clk_init_data){ 1389 .name = "camcc_ife_2_csid_clk", 1390 .parent_hws = (const struct clk_hw*[]){ 1391 &camcc_ife_2_csid_clk_src.clkr.hw 1392 }, 1393 .num_parents = 1, 1394 .flags = CLK_SET_RATE_PARENT, 1395 .ops = &clk_branch2_ops, 1396 }, 1397 }, 1398 }; 1399 1400 static struct clk_branch camcc_ife_2_dsp_clk = { 1401 .halt_reg = 0xb02c, 1402 .halt_check = BRANCH_HALT, 1403 .clkr = { 1404 .enable_reg = 0xb02c, 1405 .enable_mask = BIT(0), 1406 .hw.init = &(struct clk_init_data){ 1407 .name = "camcc_ife_2_dsp_clk", 1408 .parent_hws = (const struct clk_hw*[]){ 1409 &camcc_ife_2_clk_src.clkr.hw 1410 }, 1411 .num_parents = 1, 1412 .flags = CLK_SET_RATE_PARENT, 1413 .ops = &clk_branch2_ops, 1414 }, 1415 }, 1416 }; 1417 1418 static struct clk_branch camcc_ife_lite_clk = { 1419 .halt_reg = 0xc01c, 1420 .halt_check = BRANCH_HALT, 1421 .clkr = { 1422 .enable_reg = 0xc01c, 1423 .enable_mask = BIT(0), 1424 .hw.init = &(struct clk_init_data){ 1425 .name = "camcc_ife_lite_clk", 1426 .parent_hws = (const struct clk_hw*[]){ 1427 &camcc_ife_lite_clk_src.clkr.hw 1428 }, 1429 .num_parents = 1, 1430 .flags = CLK_SET_RATE_PARENT, 1431 .ops = &clk_branch2_ops, 1432 }, 1433 }, 1434 }; 1435 1436 static struct clk_branch camcc_ife_lite_cphy_rx_clk = { 1437 .halt_reg = 0xc044, 1438 .halt_check = BRANCH_HALT, 1439 .clkr = { 1440 .enable_reg = 0xc044, 1441 .enable_mask = BIT(0), 1442 .hw.init = &(struct clk_init_data){ 1443 .name = "camcc_ife_lite_cphy_rx_clk", 1444 .parent_hws = (const struct clk_hw*[]){ 1445 &camcc_cphy_rx_clk_src.clkr.hw 1446 }, 1447 .num_parents = 1, 1448 .flags = CLK_SET_RATE_PARENT, 1449 .ops = &clk_branch2_ops, 1450 }, 1451 }, 1452 }; 1453 1454 static struct clk_branch camcc_ife_lite_csid_clk = { 1455 .halt_reg = 0xc03c, 1456 .halt_check = BRANCH_HALT, 1457 .clkr = { 1458 .enable_reg = 0xc03c, 1459 .enable_mask = BIT(0), 1460 .hw.init = &(struct clk_init_data){ 1461 .name = "camcc_ife_lite_csid_clk", 1462 .parent_hws = (const struct clk_hw*[]){ 1463 &camcc_ife_lite_csid_clk_src.clkr.hw 1464 }, 1465 .num_parents = 1, 1466 .flags = CLK_SET_RATE_PARENT, 1467 .ops = &clk_branch2_ops, 1468 }, 1469 }, 1470 }; 1471 1472 static struct clk_branch camcc_ipe_0_ahb_clk = { 1473 .halt_reg = 0x7040, 1474 .halt_check = BRANCH_HALT, 1475 .clkr = { 1476 .enable_reg = 0x7040, 1477 .enable_mask = BIT(0), 1478 .hw.init = &(struct clk_init_data){ 1479 .name = "camcc_ipe_0_ahb_clk", 1480 .parent_hws = (const struct clk_hw*[]){ 1481 &camcc_slow_ahb_clk_src.clkr.hw 1482 }, 1483 .num_parents = 1, 1484 .flags = CLK_SET_RATE_PARENT, 1485 .ops = &clk_branch2_ops, 1486 }, 1487 }, 1488 }; 1489 1490 static struct clk_branch camcc_ipe_0_areg_clk = { 1491 .halt_reg = 0x703c, 1492 .halt_check = BRANCH_HALT, 1493 .clkr = { 1494 .enable_reg = 0x703c, 1495 .enable_mask = BIT(0), 1496 .hw.init = &(struct clk_init_data){ 1497 .name = "camcc_ipe_0_areg_clk", 1498 .parent_hws = (const struct clk_hw*[]){ 1499 &camcc_fast_ahb_clk_src.clkr.hw 1500 }, 1501 .num_parents = 1, 1502 .flags = CLK_SET_RATE_PARENT, 1503 .ops = &clk_branch2_ops, 1504 }, 1505 }, 1506 }; 1507 1508 static struct clk_branch camcc_ipe_0_axi_clk = { 1509 .halt_reg = 0x7038, 1510 .halt_check = BRANCH_HALT, 1511 .clkr = { 1512 .enable_reg = 0x7038, 1513 .enable_mask = BIT(0), 1514 .hw.init = &(struct clk_init_data){ 1515 .name = "camcc_ipe_0_axi_clk", 1516 .ops = &clk_branch2_ops, 1517 }, 1518 }, 1519 }; 1520 1521 static struct clk_branch camcc_ipe_0_clk = { 1522 .halt_reg = 0x7028, 1523 .halt_check = BRANCH_HALT, 1524 .clkr = { 1525 .enable_reg = 0x7028, 1526 .enable_mask = BIT(0), 1527 .hw.init = &(struct clk_init_data){ 1528 .name = "camcc_ipe_0_clk", 1529 .parent_hws = (const struct clk_hw*[]){ 1530 &camcc_ipe_0_clk_src.clkr.hw 1531 }, 1532 .num_parents = 1, 1533 .flags = CLK_SET_RATE_PARENT, 1534 .ops = &clk_branch2_ops, 1535 }, 1536 }, 1537 }; 1538 1539 static struct clk_branch camcc_jpeg_clk = { 1540 .halt_reg = 0xd01c, 1541 .halt_check = BRANCH_HALT, 1542 .clkr = { 1543 .enable_reg = 0xd01c, 1544 .enable_mask = BIT(0), 1545 .hw.init = &(struct clk_init_data){ 1546 .name = "camcc_jpeg_clk", 1547 .parent_hws = (const struct clk_hw*[]){ 1548 &camcc_jpeg_clk_src.clkr.hw 1549 }, 1550 .num_parents = 1, 1551 .flags = CLK_SET_RATE_PARENT, 1552 .ops = &clk_branch2_ops, 1553 }, 1554 }, 1555 }; 1556 1557 static struct clk_branch camcc_lrme_clk = { 1558 .halt_reg = 0x1101c, 1559 .halt_check = BRANCH_HALT, 1560 .clkr = { 1561 .enable_reg = 0x1101c, 1562 .enable_mask = BIT(0), 1563 .hw.init = &(struct clk_init_data){ 1564 .name = "camcc_lrme_clk", 1565 .parent_hws = (const struct clk_hw*[]){ 1566 &camcc_lrme_clk_src.clkr.hw 1567 }, 1568 .num_parents = 1, 1569 .flags = CLK_SET_RATE_PARENT, 1570 .ops = &clk_branch2_ops, 1571 }, 1572 }, 1573 }; 1574 1575 static struct clk_branch camcc_mclk0_clk = { 1576 .halt_reg = 0x401c, 1577 .halt_check = BRANCH_HALT, 1578 .clkr = { 1579 .enable_reg = 0x401c, 1580 .enable_mask = BIT(0), 1581 .hw.init = &(struct clk_init_data){ 1582 .name = "camcc_mclk0_clk", 1583 .parent_hws = (const struct clk_hw*[]){ 1584 &camcc_mclk0_clk_src.clkr.hw 1585 }, 1586 .num_parents = 1, 1587 .flags = CLK_SET_RATE_PARENT, 1588 .ops = &clk_branch2_ops, 1589 }, 1590 }, 1591 }; 1592 1593 static struct clk_branch camcc_mclk1_clk = { 1594 .halt_reg = 0x403c, 1595 .halt_check = BRANCH_HALT, 1596 .clkr = { 1597 .enable_reg = 0x403c, 1598 .enable_mask = BIT(0), 1599 .hw.init = &(struct clk_init_data){ 1600 .name = "camcc_mclk1_clk", 1601 .parent_hws = (const struct clk_hw*[]){ 1602 &camcc_mclk1_clk_src.clkr.hw 1603 }, 1604 .num_parents = 1, 1605 .flags = CLK_SET_RATE_PARENT, 1606 .ops = &clk_branch2_ops, 1607 }, 1608 }, 1609 }; 1610 1611 static struct clk_branch camcc_mclk2_clk = { 1612 .halt_reg = 0x405c, 1613 .halt_check = BRANCH_HALT, 1614 .clkr = { 1615 .enable_reg = 0x405c, 1616 .enable_mask = BIT(0), 1617 .hw.init = &(struct clk_init_data){ 1618 .name = "camcc_mclk2_clk", 1619 .parent_hws = (const struct clk_hw*[]){ 1620 &camcc_mclk2_clk_src.clkr.hw 1621 }, 1622 .num_parents = 1, 1623 .flags = CLK_SET_RATE_PARENT, 1624 .ops = &clk_branch2_ops, 1625 }, 1626 }, 1627 }; 1628 1629 static struct clk_branch camcc_mclk3_clk = { 1630 .halt_reg = 0x407c, 1631 .halt_check = BRANCH_HALT, 1632 .clkr = { 1633 .enable_reg = 0x407c, 1634 .enable_mask = BIT(0), 1635 .hw.init = &(struct clk_init_data){ 1636 .name = "camcc_mclk3_clk", 1637 .parent_hws = (const struct clk_hw*[]){ 1638 &camcc_mclk3_clk_src.clkr.hw 1639 }, 1640 .num_parents = 1, 1641 .flags = CLK_SET_RATE_PARENT, 1642 .ops = &clk_branch2_ops, 1643 }, 1644 }, 1645 }; 1646 1647 static struct clk_branch camcc_mclk4_clk = { 1648 .halt_reg = 0x409c, 1649 .halt_check = BRANCH_HALT, 1650 .clkr = { 1651 .enable_reg = 0x409c, 1652 .enable_mask = BIT(0), 1653 .hw.init = &(struct clk_init_data){ 1654 .name = "camcc_mclk4_clk", 1655 .parent_hws = (const struct clk_hw*[]){ 1656 &camcc_mclk4_clk_src.clkr.hw 1657 }, 1658 .num_parents = 1, 1659 .flags = CLK_SET_RATE_PARENT, 1660 .ops = &clk_branch2_ops, 1661 }, 1662 }, 1663 }; 1664 1665 static struct clk_branch camcc_soc_ahb_clk = { 1666 .halt_reg = 0x1400c, 1667 .halt_check = BRANCH_HALT, 1668 .clkr = { 1669 .enable_reg = 0x1400c, 1670 .enable_mask = BIT(0), 1671 .hw.init = &(struct clk_init_data){ 1672 .name = "camcc_soc_ahb_clk", 1673 .ops = &clk_branch2_ops, 1674 }, 1675 }, 1676 }; 1677 1678 static struct clk_branch camcc_sys_tmr_clk = { 1679 .halt_reg = 0xe034, 1680 .halt_check = BRANCH_HALT, 1681 .clkr = { 1682 .enable_reg = 0xe034, 1683 .enable_mask = BIT(0), 1684 .hw.init = &(struct clk_init_data){ 1685 .name = "camcc_sys_tmr_clk", 1686 .ops = &clk_branch2_ops, 1687 }, 1688 }, 1689 }; 1690 1691 static struct gdsc titan_top_gdsc; 1692 1693 static struct gdsc bps_gdsc = { 1694 .gdscr = 0x6004, 1695 .en_rest_wait_val = 0x2, 1696 .en_few_wait_val = 0x2, 1697 .clk_dis_wait_val = 0xf, 1698 .pd = { 1699 .name = "bps_gdsc", 1700 }, 1701 .pwrsts = PWRSTS_OFF_ON, 1702 .parent = &titan_top_gdsc.pd, 1703 .flags = VOTABLE, 1704 }; 1705 1706 static struct gdsc ipe_0_gdsc = { 1707 .gdscr = 0x7004, 1708 .en_rest_wait_val = 0x2, 1709 .en_few_wait_val = 0x2, 1710 .clk_dis_wait_val = 0xf, 1711 .pd = { 1712 .name = "ipe_0_gdsc", 1713 }, 1714 .pwrsts = PWRSTS_OFF_ON, 1715 .parent = &titan_top_gdsc.pd, 1716 .flags = VOTABLE, 1717 }; 1718 1719 static struct gdsc ife_0_gdsc = { 1720 .gdscr = 0x9004, 1721 .en_rest_wait_val = 0x2, 1722 .en_few_wait_val = 0x2, 1723 .clk_dis_wait_val = 0xf, 1724 .pd = { 1725 .name = "ife_0_gdsc", 1726 }, 1727 .pwrsts = PWRSTS_OFF_ON, 1728 .parent = &titan_top_gdsc.pd, 1729 }; 1730 1731 static struct gdsc ife_1_gdsc = { 1732 .gdscr = 0xa004, 1733 .en_rest_wait_val = 0x2, 1734 .en_few_wait_val = 0x2, 1735 .clk_dis_wait_val = 0xf, 1736 .pd = { 1737 .name = "ife_1_gdsc", 1738 }, 1739 .pwrsts = PWRSTS_OFF_ON, 1740 .parent = &titan_top_gdsc.pd, 1741 }; 1742 1743 static struct gdsc ife_2_gdsc = { 1744 .gdscr = 0xb004, 1745 .en_rest_wait_val = 0x2, 1746 .en_few_wait_val = 0x2, 1747 .clk_dis_wait_val = 0xf, 1748 .pd = { 1749 .name = "ife_2_gdsc", 1750 }, 1751 .pwrsts = PWRSTS_OFF_ON, 1752 .parent = &titan_top_gdsc.pd, 1753 }; 1754 1755 static struct gdsc titan_top_gdsc = { 1756 .gdscr = 0x14004, 1757 .en_rest_wait_val = 0x2, 1758 .en_few_wait_val = 0x2, 1759 .clk_dis_wait_val = 0xf, 1760 .pd = { 1761 .name = "titan_top_gdsc", 1762 }, 1763 .pwrsts = PWRSTS_OFF_ON, 1764 }; 1765 1766 static struct clk_hw *camcc_sm6350_hws[] = { 1767 [CAMCC_PLL2_OUT_EARLY] = &camcc_pll2_out_early.hw, 1768 }; 1769 1770 static struct clk_regmap *camcc_sm6350_clocks[] = { 1771 [CAMCC_BPS_AHB_CLK] = &camcc_bps_ahb_clk.clkr, 1772 [CAMCC_BPS_AREG_CLK] = &camcc_bps_areg_clk.clkr, 1773 [CAMCC_BPS_AXI_CLK] = &camcc_bps_axi_clk.clkr, 1774 [CAMCC_BPS_CLK] = &camcc_bps_clk.clkr, 1775 [CAMCC_BPS_CLK_SRC] = &camcc_bps_clk_src.clkr, 1776 [CAMCC_CAMNOC_AXI_CLK] = &camcc_camnoc_axi_clk.clkr, 1777 [CAMCC_CCI_0_CLK] = &camcc_cci_0_clk.clkr, 1778 [CAMCC_CCI_0_CLK_SRC] = &camcc_cci_0_clk_src.clkr, 1779 [CAMCC_CCI_1_CLK] = &camcc_cci_1_clk.clkr, 1780 [CAMCC_CCI_1_CLK_SRC] = &camcc_cci_1_clk_src.clkr, 1781 [CAMCC_CORE_AHB_CLK] = &camcc_core_ahb_clk.clkr, 1782 [CAMCC_CPAS_AHB_CLK] = &camcc_cpas_ahb_clk.clkr, 1783 [CAMCC_CPHY_RX_CLK_SRC] = &camcc_cphy_rx_clk_src.clkr, 1784 [CAMCC_CSI0PHYTIMER_CLK] = &camcc_csi0phytimer_clk.clkr, 1785 [CAMCC_CSI0PHYTIMER_CLK_SRC] = &camcc_csi0phytimer_clk_src.clkr, 1786 [CAMCC_CSI1PHYTIMER_CLK] = &camcc_csi1phytimer_clk.clkr, 1787 [CAMCC_CSI1PHYTIMER_CLK_SRC] = &camcc_csi1phytimer_clk_src.clkr, 1788 [CAMCC_CSI2PHYTIMER_CLK] = &camcc_csi2phytimer_clk.clkr, 1789 [CAMCC_CSI2PHYTIMER_CLK_SRC] = &camcc_csi2phytimer_clk_src.clkr, 1790 [CAMCC_CSI3PHYTIMER_CLK] = &camcc_csi3phytimer_clk.clkr, 1791 [CAMCC_CSI3PHYTIMER_CLK_SRC] = &camcc_csi3phytimer_clk_src.clkr, 1792 [CAMCC_CSIPHY0_CLK] = &camcc_csiphy0_clk.clkr, 1793 [CAMCC_CSIPHY1_CLK] = &camcc_csiphy1_clk.clkr, 1794 [CAMCC_CSIPHY2_CLK] = &camcc_csiphy2_clk.clkr, 1795 [CAMCC_CSIPHY3_CLK] = &camcc_csiphy3_clk.clkr, 1796 [CAMCC_FAST_AHB_CLK_SRC] = &camcc_fast_ahb_clk_src.clkr, 1797 [CAMCC_ICP_CLK] = &camcc_icp_clk.clkr, 1798 [CAMCC_ICP_CLK_SRC] = &camcc_icp_clk_src.clkr, 1799 [CAMCC_ICP_TS_CLK] = &camcc_icp_ts_clk.clkr, 1800 [CAMCC_IFE_0_AXI_CLK] = &camcc_ife_0_axi_clk.clkr, 1801 [CAMCC_IFE_0_CLK] = &camcc_ife_0_clk.clkr, 1802 [CAMCC_IFE_0_CLK_SRC] = &camcc_ife_0_clk_src.clkr, 1803 [CAMCC_IFE_0_CPHY_RX_CLK] = &camcc_ife_0_cphy_rx_clk.clkr, 1804 [CAMCC_IFE_0_CSID_CLK] = &camcc_ife_0_csid_clk.clkr, 1805 [CAMCC_IFE_0_CSID_CLK_SRC] = &camcc_ife_0_csid_clk_src.clkr, 1806 [CAMCC_IFE_0_DSP_CLK] = &camcc_ife_0_dsp_clk.clkr, 1807 [CAMCC_IFE_1_AXI_CLK] = &camcc_ife_1_axi_clk.clkr, 1808 [CAMCC_IFE_1_CLK] = &camcc_ife_1_clk.clkr, 1809 [CAMCC_IFE_1_CLK_SRC] = &camcc_ife_1_clk_src.clkr, 1810 [CAMCC_IFE_1_CPHY_RX_CLK] = &camcc_ife_1_cphy_rx_clk.clkr, 1811 [CAMCC_IFE_1_CSID_CLK] = &camcc_ife_1_csid_clk.clkr, 1812 [CAMCC_IFE_1_CSID_CLK_SRC] = &camcc_ife_1_csid_clk_src.clkr, 1813 [CAMCC_IFE_1_DSP_CLK] = &camcc_ife_1_dsp_clk.clkr, 1814 [CAMCC_IFE_2_AXI_CLK] = &camcc_ife_2_axi_clk.clkr, 1815 [CAMCC_IFE_2_CLK] = &camcc_ife_2_clk.clkr, 1816 [CAMCC_IFE_2_CLK_SRC] = &camcc_ife_2_clk_src.clkr, 1817 [CAMCC_IFE_2_CPHY_RX_CLK] = &camcc_ife_2_cphy_rx_clk.clkr, 1818 [CAMCC_IFE_2_CSID_CLK] = &camcc_ife_2_csid_clk.clkr, 1819 [CAMCC_IFE_2_CSID_CLK_SRC] = &camcc_ife_2_csid_clk_src.clkr, 1820 [CAMCC_IFE_2_DSP_CLK] = &camcc_ife_2_dsp_clk.clkr, 1821 [CAMCC_IFE_LITE_CLK] = &camcc_ife_lite_clk.clkr, 1822 [CAMCC_IFE_LITE_CLK_SRC] = &camcc_ife_lite_clk_src.clkr, 1823 [CAMCC_IFE_LITE_CPHY_RX_CLK] = &camcc_ife_lite_cphy_rx_clk.clkr, 1824 [CAMCC_IFE_LITE_CSID_CLK] = &camcc_ife_lite_csid_clk.clkr, 1825 [CAMCC_IFE_LITE_CSID_CLK_SRC] = &camcc_ife_lite_csid_clk_src.clkr, 1826 [CAMCC_IPE_0_AHB_CLK] = &camcc_ipe_0_ahb_clk.clkr, 1827 [CAMCC_IPE_0_AREG_CLK] = &camcc_ipe_0_areg_clk.clkr, 1828 [CAMCC_IPE_0_AXI_CLK] = &camcc_ipe_0_axi_clk.clkr, 1829 [CAMCC_IPE_0_CLK] = &camcc_ipe_0_clk.clkr, 1830 [CAMCC_IPE_0_CLK_SRC] = &camcc_ipe_0_clk_src.clkr, 1831 [CAMCC_JPEG_CLK] = &camcc_jpeg_clk.clkr, 1832 [CAMCC_JPEG_CLK_SRC] = &camcc_jpeg_clk_src.clkr, 1833 [CAMCC_LRME_CLK] = &camcc_lrme_clk.clkr, 1834 [CAMCC_LRME_CLK_SRC] = &camcc_lrme_clk_src.clkr, 1835 [CAMCC_MCLK0_CLK] = &camcc_mclk0_clk.clkr, 1836 [CAMCC_MCLK0_CLK_SRC] = &camcc_mclk0_clk_src.clkr, 1837 [CAMCC_MCLK1_CLK] = &camcc_mclk1_clk.clkr, 1838 [CAMCC_MCLK1_CLK_SRC] = &camcc_mclk1_clk_src.clkr, 1839 [CAMCC_MCLK2_CLK] = &camcc_mclk2_clk.clkr, 1840 [CAMCC_MCLK2_CLK_SRC] = &camcc_mclk2_clk_src.clkr, 1841 [CAMCC_MCLK3_CLK] = &camcc_mclk3_clk.clkr, 1842 [CAMCC_MCLK3_CLK_SRC] = &camcc_mclk3_clk_src.clkr, 1843 [CAMCC_MCLK4_CLK] = &camcc_mclk4_clk.clkr, 1844 [CAMCC_MCLK4_CLK_SRC] = &camcc_mclk4_clk_src.clkr, 1845 [CAMCC_PLL0] = &camcc_pll0.clkr, 1846 [CAMCC_PLL0_OUT_EVEN] = &camcc_pll0_out_even.clkr, 1847 [CAMCC_PLL1] = &camcc_pll1.clkr, 1848 [CAMCC_PLL1_OUT_EVEN] = &camcc_pll1_out_even.clkr, 1849 [CAMCC_PLL2] = &camcc_pll2.clkr, 1850 [CAMCC_PLL2_OUT_MAIN] = &camcc_pll2_out_main.clkr, 1851 [CAMCC_PLL3] = &camcc_pll3.clkr, 1852 [CAMCC_SLOW_AHB_CLK_SRC] = &camcc_slow_ahb_clk_src.clkr, 1853 [CAMCC_SOC_AHB_CLK] = &camcc_soc_ahb_clk.clkr, 1854 [CAMCC_SYS_TMR_CLK] = &camcc_sys_tmr_clk.clkr, 1855 }; 1856 1857 static struct gdsc *camcc_sm6350_gdscs[] = { 1858 [BPS_GDSC] = &bps_gdsc, 1859 [IPE_0_GDSC] = &ipe_0_gdsc, 1860 [IFE_0_GDSC] = &ife_0_gdsc, 1861 [IFE_1_GDSC] = &ife_1_gdsc, 1862 [IFE_2_GDSC] = &ife_2_gdsc, 1863 [TITAN_TOP_GDSC] = &titan_top_gdsc, 1864 }; 1865 1866 static const struct regmap_config camcc_sm6350_regmap_config = { 1867 .reg_bits = 32, 1868 .reg_stride = 4, 1869 .val_bits = 32, 1870 .max_register = 0x16000, 1871 .fast_io = true, 1872 }; 1873 1874 static const struct qcom_cc_desc camcc_sm6350_desc = { 1875 .config = &camcc_sm6350_regmap_config, 1876 .clk_hws = camcc_sm6350_hws, 1877 .num_clk_hws = ARRAY_SIZE(camcc_sm6350_hws), 1878 .clks = camcc_sm6350_clocks, 1879 .num_clks = ARRAY_SIZE(camcc_sm6350_clocks), 1880 .gdscs = camcc_sm6350_gdscs, 1881 .num_gdscs = ARRAY_SIZE(camcc_sm6350_gdscs), 1882 }; 1883 1884 static const struct of_device_id camcc_sm6350_match_table[] = { 1885 { .compatible = "qcom,sm6350-camcc" }, 1886 { } 1887 }; 1888 MODULE_DEVICE_TABLE(of, camcc_sm6350_match_table); 1889 1890 static int camcc_sm6350_probe(struct platform_device *pdev) 1891 { 1892 struct regmap *regmap; 1893 1894 regmap = qcom_cc_map(pdev, &camcc_sm6350_desc); 1895 if (IS_ERR(regmap)) 1896 return PTR_ERR(regmap); 1897 1898 clk_fabia_pll_configure(&camcc_pll0, regmap, &camcc_pll0_config); 1899 clk_fabia_pll_configure(&camcc_pll1, regmap, &camcc_pll1_config); 1900 clk_agera_pll_configure(&camcc_pll2, regmap, &camcc_pll2_config); 1901 clk_fabia_pll_configure(&camcc_pll3, regmap, &camcc_pll3_config); 1902 1903 return qcom_cc_really_probe(&pdev->dev, &camcc_sm6350_desc, regmap); 1904 } 1905 1906 static struct platform_driver camcc_sm6350_driver = { 1907 .probe = camcc_sm6350_probe, 1908 .driver = { 1909 .name = "sm6350-camcc", 1910 .of_match_table = camcc_sm6350_match_table, 1911 }, 1912 }; 1913 1914 module_platform_driver(camcc_sm6350_driver); 1915 1916 MODULE_DESCRIPTION("QTI CAMCC SM6350 Driver"); 1917 MODULE_LICENSE("GPL"); 1918