1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,sm4450-camcc.h> 12 13 #include "clk-alpha-pll.h" 14 #include "clk-branch.h" 15 #include "clk-pll.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "common.h" 19 #include "gdsc.h" 20 #include "reset.h" 21 22 enum { 23 DT_BI_TCXO, 24 }; 25 26 enum { 27 P_BI_TCXO, 28 P_CAM_CC_PLL0_OUT_EVEN, 29 P_CAM_CC_PLL0_OUT_MAIN, 30 P_CAM_CC_PLL0_OUT_ODD, 31 P_CAM_CC_PLL1_OUT_EVEN, 32 P_CAM_CC_PLL1_OUT_MAIN, 33 P_CAM_CC_PLL2_OUT_EVEN, 34 P_CAM_CC_PLL2_OUT_MAIN, 35 P_CAM_CC_PLL3_OUT_EVEN, 36 P_CAM_CC_PLL4_OUT_EVEN, 37 P_CAM_CC_PLL4_OUT_MAIN, 38 }; 39 40 static const struct pll_vco lucid_evo_vco[] = { 41 { 249600000, 2020000000, 0 }, 42 }; 43 44 static const struct pll_vco rivian_evo_vco[] = { 45 { 864000000, 1056000000, 0 }, 46 }; 47 48 /* 1200.0 MHz Configuration */ 49 static const struct alpha_pll_config cam_cc_pll0_config = { 50 .l = 0x3e, 51 .alpha = 0x8000, 52 .config_ctl_val = 0x20485699, 53 .config_ctl_hi_val = 0x00182261, 54 .config_ctl_hi1_val = 0x32aa299c, 55 .user_ctl_val = 0x00008400, 56 .user_ctl_hi_val = 0x00000805, 57 }; 58 59 static struct clk_alpha_pll cam_cc_pll0 = { 60 .offset = 0x0, 61 .vco_table = lucid_evo_vco, 62 .num_vco = ARRAY_SIZE(lucid_evo_vco), 63 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 64 .clkr = { 65 .hw.init = &(const struct clk_init_data) { 66 .name = "cam_cc_pll0", 67 .parent_data = &(const struct clk_parent_data) { 68 .index = DT_BI_TCXO, 69 }, 70 .num_parents = 1, 71 .ops = &clk_alpha_pll_lucid_evo_ops, 72 }, 73 }, 74 }; 75 76 static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { 77 { 0x1, 2 }, 78 { } 79 }; 80 81 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { 82 .offset = 0x0, 83 .post_div_shift = 10, 84 .post_div_table = post_div_table_cam_cc_pll0_out_even, 85 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), 86 .width = 4, 87 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 88 .clkr.hw.init = &(const struct clk_init_data) { 89 .name = "cam_cc_pll0_out_even", 90 .parent_hws = (const struct clk_hw*[]) { 91 &cam_cc_pll0.clkr.hw, 92 }, 93 .num_parents = 1, 94 .flags = CLK_SET_RATE_PARENT, 95 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 96 }, 97 }; 98 99 static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { 100 { 0x2, 3 }, 101 { } 102 }; 103 104 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { 105 .offset = 0x0, 106 .post_div_shift = 14, 107 .post_div_table = post_div_table_cam_cc_pll0_out_odd, 108 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), 109 .width = 4, 110 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 111 .clkr.hw.init = &(const struct clk_init_data) { 112 .name = "cam_cc_pll0_out_odd", 113 .parent_hws = (const struct clk_hw*[]) { 114 &cam_cc_pll0.clkr.hw, 115 }, 116 .num_parents = 1, 117 .flags = CLK_SET_RATE_PARENT, 118 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 119 }, 120 }; 121 122 /* 600.0 MHz Configuration */ 123 static const struct alpha_pll_config cam_cc_pll1_config = { 124 .l = 0x1f, 125 .alpha = 0x4000, 126 .config_ctl_val = 0x20485699, 127 .config_ctl_hi_val = 0x00182261, 128 .config_ctl_hi1_val = 0x32aa299c, 129 .user_ctl_val = 0x00000400, 130 .user_ctl_hi_val = 0x00000805, 131 }; 132 133 static struct clk_alpha_pll cam_cc_pll1 = { 134 .offset = 0x1000, 135 .vco_table = lucid_evo_vco, 136 .num_vco = ARRAY_SIZE(lucid_evo_vco), 137 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 138 .clkr = { 139 .hw.init = &(const struct clk_init_data) { 140 .name = "cam_cc_pll1", 141 .parent_data = &(const struct clk_parent_data) { 142 .index = DT_BI_TCXO, 143 }, 144 .num_parents = 1, 145 .ops = &clk_alpha_pll_lucid_evo_ops, 146 }, 147 }, 148 }; 149 150 static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { 151 { 0x1, 2 }, 152 { } 153 }; 154 155 static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { 156 .offset = 0x1000, 157 .post_div_shift = 10, 158 .post_div_table = post_div_table_cam_cc_pll1_out_even, 159 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), 160 .width = 4, 161 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 162 .clkr.hw.init = &(const struct clk_init_data) { 163 .name = "cam_cc_pll1_out_even", 164 .parent_hws = (const struct clk_hw*[]) { 165 &cam_cc_pll1.clkr.hw, 166 }, 167 .num_parents = 1, 168 .flags = CLK_SET_RATE_PARENT, 169 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 170 }, 171 }; 172 173 /* 960.0 MHz Configuration */ 174 static const struct alpha_pll_config cam_cc_pll2_config = { 175 .l = 0x32, 176 .alpha = 0x0, 177 .config_ctl_val = 0x90008820, 178 .config_ctl_hi_val = 0x00890263, 179 .config_ctl_hi1_val = 0x00000247, 180 .user_ctl_val = 0x00000400, 181 .user_ctl_hi_val = 0x00400000, 182 }; 183 184 static struct clk_alpha_pll cam_cc_pll2 = { 185 .offset = 0x2000, 186 .vco_table = rivian_evo_vco, 187 .num_vco = ARRAY_SIZE(rivian_evo_vco), 188 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], 189 .clkr = { 190 .hw.init = &(const struct clk_init_data) { 191 .name = "cam_cc_pll2", 192 .parent_data = &(const struct clk_parent_data) { 193 .index = DT_BI_TCXO, 194 }, 195 .num_parents = 1, 196 .ops = &clk_alpha_pll_rivian_evo_ops, 197 }, 198 }, 199 }; 200 201 static const struct clk_div_table post_div_table_cam_cc_pll2_out_even[] = { 202 { 0x1, 2 }, 203 { } 204 }; 205 206 static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even = { 207 .offset = 0x2000, 208 .post_div_shift = 10, 209 .post_div_table = post_div_table_cam_cc_pll2_out_even, 210 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_even), 211 .width = 4, 212 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], 213 .clkr.hw.init = &(const struct clk_init_data) { 214 .name = "cam_cc_pll2_out_even", 215 .parent_hws = (const struct clk_hw*[]) { 216 &cam_cc_pll2.clkr.hw, 217 }, 218 .num_parents = 1, 219 .flags = CLK_SET_RATE_PARENT, 220 .ops = &clk_alpha_pll_postdiv_rivian_evo_ops, 221 }, 222 }; 223 224 /* 600.0 MHz Configuration */ 225 static const struct alpha_pll_config cam_cc_pll3_config = { 226 .l = 0x1f, 227 .alpha = 0x4000, 228 .config_ctl_val = 0x20485699, 229 .config_ctl_hi_val = 0x00182261, 230 .config_ctl_hi1_val = 0x32aa299c, 231 .user_ctl_val = 0x00000400, 232 .user_ctl_hi_val = 0x00000805, 233 }; 234 235 static struct clk_alpha_pll cam_cc_pll3 = { 236 .offset = 0x3000, 237 .vco_table = lucid_evo_vco, 238 .num_vco = ARRAY_SIZE(lucid_evo_vco), 239 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 240 .clkr = { 241 .hw.init = &(const struct clk_init_data) { 242 .name = "cam_cc_pll3", 243 .parent_data = &(const struct clk_parent_data) { 244 .index = DT_BI_TCXO, 245 }, 246 .num_parents = 1, 247 .ops = &clk_alpha_pll_lucid_evo_ops, 248 }, 249 }, 250 }; 251 252 static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { 253 { 0x1, 2 }, 254 { } 255 }; 256 257 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 258 .offset = 0x3000, 259 .post_div_shift = 10, 260 .post_div_table = post_div_table_cam_cc_pll3_out_even, 261 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), 262 .width = 4, 263 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 264 .clkr.hw.init = &(const struct clk_init_data) { 265 .name = "cam_cc_pll3_out_even", 266 .parent_hws = (const struct clk_hw*[]) { 267 &cam_cc_pll3.clkr.hw, 268 }, 269 .num_parents = 1, 270 .flags = CLK_SET_RATE_PARENT, 271 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 272 }, 273 }; 274 275 /* 700.0 MHz Configuration */ 276 static const struct alpha_pll_config cam_cc_pll4_config = { 277 .l = 0x24, 278 .alpha = 0x7555, 279 .config_ctl_val = 0x20485699, 280 .config_ctl_hi_val = 0x00182261, 281 .config_ctl_hi1_val = 0x32aa299c, 282 .user_ctl_val = 0x00000400, 283 .user_ctl_hi_val = 0x00000805, 284 }; 285 286 static struct clk_alpha_pll cam_cc_pll4 = { 287 .offset = 0x4000, 288 .vco_table = lucid_evo_vco, 289 .num_vco = ARRAY_SIZE(lucid_evo_vco), 290 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 291 .clkr = { 292 .hw.init = &(const struct clk_init_data) { 293 .name = "cam_cc_pll4", 294 .parent_data = &(const struct clk_parent_data) { 295 .index = DT_BI_TCXO, 296 }, 297 .num_parents = 1, 298 .ops = &clk_alpha_pll_lucid_evo_ops, 299 }, 300 }, 301 }; 302 303 static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { 304 { 0x1, 2 }, 305 { } 306 }; 307 308 static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { 309 .offset = 0x4000, 310 .post_div_shift = 10, 311 .post_div_table = post_div_table_cam_cc_pll4_out_even, 312 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), 313 .width = 4, 314 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 315 .clkr.hw.init = &(const struct clk_init_data) { 316 .name = "cam_cc_pll4_out_even", 317 .parent_hws = (const struct clk_hw*[]) { 318 &cam_cc_pll4.clkr.hw, 319 }, 320 .num_parents = 1, 321 .flags = CLK_SET_RATE_PARENT, 322 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 323 }, 324 }; 325 326 static const struct parent_map cam_cc_parent_map_0[] = { 327 { P_BI_TCXO, 0 }, 328 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 329 { P_CAM_CC_PLL0_OUT_ODD, 5 }, 330 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 331 }; 332 333 static const struct clk_parent_data cam_cc_parent_data_0[] = { 334 { .index = DT_BI_TCXO }, 335 { .hw = &cam_cc_pll0.clkr.hw }, 336 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 337 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 338 }; 339 340 static const struct parent_map cam_cc_parent_map_1[] = { 341 { P_BI_TCXO, 0 }, 342 { P_CAM_CC_PLL2_OUT_EVEN, 3 }, 343 { P_CAM_CC_PLL2_OUT_MAIN, 4 }, 344 }; 345 346 static const struct clk_parent_data cam_cc_parent_data_1[] = { 347 { .index = DT_BI_TCXO }, 348 { .hw = &cam_cc_pll2_out_even.clkr.hw }, 349 { .hw = &cam_cc_pll2.clkr.hw }, 350 }; 351 352 static const struct parent_map cam_cc_parent_map_2[] = { 353 { P_BI_TCXO, 0 }, 354 { P_CAM_CC_PLL0_OUT_ODD, 5 }, 355 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 356 }; 357 358 static const struct clk_parent_data cam_cc_parent_data_2[] = { 359 { .index = DT_BI_TCXO }, 360 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 361 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 362 }; 363 364 static const struct parent_map cam_cc_parent_map_3[] = { 365 { P_BI_TCXO, 0 }, 366 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 367 { P_CAM_CC_PLL4_OUT_EVEN, 2 }, 368 { P_CAM_CC_PLL4_OUT_MAIN, 3 }, 369 { P_CAM_CC_PLL0_OUT_ODD, 5 }, 370 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 371 }; 372 373 static const struct clk_parent_data cam_cc_parent_data_3[] = { 374 { .index = DT_BI_TCXO }, 375 { .hw = &cam_cc_pll0.clkr.hw }, 376 { .hw = &cam_cc_pll4_out_even.clkr.hw }, 377 { .hw = &cam_cc_pll4.clkr.hw }, 378 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 379 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 380 }; 381 382 static const struct parent_map cam_cc_parent_map_4[] = { 383 { P_BI_TCXO, 0 }, 384 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 385 { P_CAM_CC_PLL1_OUT_MAIN, 2 }, 386 { P_CAM_CC_PLL1_OUT_EVEN, 3 }, 387 { P_CAM_CC_PLL0_OUT_ODD, 5 }, 388 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 389 }; 390 391 static const struct clk_parent_data cam_cc_parent_data_4[] = { 392 { .index = DT_BI_TCXO }, 393 { .hw = &cam_cc_pll0.clkr.hw }, 394 { .hw = &cam_cc_pll1.clkr.hw }, 395 { .hw = &cam_cc_pll1_out_even.clkr.hw }, 396 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 397 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 398 }; 399 400 static const struct parent_map cam_cc_parent_map_5[] = { 401 { P_BI_TCXO, 0 }, 402 { P_CAM_CC_PLL1_OUT_MAIN, 2 }, 403 { P_CAM_CC_PLL1_OUT_EVEN, 3 }, 404 }; 405 406 static const struct clk_parent_data cam_cc_parent_data_5[] = { 407 { .index = DT_BI_TCXO }, 408 { .hw = &cam_cc_pll1.clkr.hw }, 409 { .hw = &cam_cc_pll1_out_even.clkr.hw }, 410 }; 411 412 static const struct parent_map cam_cc_parent_map_6[] = { 413 { P_BI_TCXO, 0 }, 414 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 415 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 416 }; 417 418 static const struct clk_parent_data cam_cc_parent_data_6[] = { 419 { .index = DT_BI_TCXO }, 420 { .hw = &cam_cc_pll0.clkr.hw }, 421 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 422 }; 423 424 static const struct parent_map cam_cc_parent_map_7[] = { 425 { P_BI_TCXO, 0 }, 426 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 427 { P_CAM_CC_PLL3_OUT_EVEN, 5 }, 428 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 429 }; 430 431 static const struct clk_parent_data cam_cc_parent_data_7[] = { 432 { .index = DT_BI_TCXO }, 433 { .hw = &cam_cc_pll0.clkr.hw }, 434 { .hw = &cam_cc_pll3_out_even.clkr.hw }, 435 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 436 }; 437 438 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { 439 F(19200000, P_BI_TCXO, 1, 0, 0), 440 F(300000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 441 F(410000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 442 F(460000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 443 F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 444 F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 445 { } 446 }; 447 448 static struct clk_rcg2 cam_cc_bps_clk_src = { 449 .cmd_rcgr = 0xa004, 450 .mnd_width = 0, 451 .hid_width = 5, 452 .parent_map = cam_cc_parent_map_4, 453 .freq_tbl = ftbl_cam_cc_bps_clk_src, 454 .clkr.hw.init = &(const struct clk_init_data) { 455 .name = "cam_cc_bps_clk_src", 456 .parent_data = cam_cc_parent_data_4, 457 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 458 .flags = CLK_SET_RATE_PARENT, 459 .ops = &clk_rcg2_shared_ops, 460 }, 461 }; 462 463 static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = { 464 F(19200000, P_BI_TCXO, 1, 0, 0), 465 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), 466 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), 467 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 468 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 469 { } 470 }; 471 472 static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = { 473 .cmd_rcgr = 0x13014, 474 .mnd_width = 0, 475 .hid_width = 5, 476 .parent_map = cam_cc_parent_map_0, 477 .freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src, 478 .clkr.hw.init = &(const struct clk_init_data) { 479 .name = "cam_cc_camnoc_axi_clk_src", 480 .parent_data = cam_cc_parent_data_0, 481 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 482 .flags = CLK_SET_RATE_PARENT, 483 .ops = &clk_rcg2_shared_ops, 484 }, 485 }; 486 487 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { 488 F(19200000, P_BI_TCXO, 1, 0, 0), 489 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 490 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0), 491 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 492 { } 493 }; 494 495 static struct clk_rcg2 cam_cc_cci_0_clk_src = { 496 .cmd_rcgr = 0x10004, 497 .mnd_width = 8, 498 .hid_width = 5, 499 .parent_map = cam_cc_parent_map_2, 500 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 501 .clkr.hw.init = &(const struct clk_init_data) { 502 .name = "cam_cc_cci_0_clk_src", 503 .parent_data = cam_cc_parent_data_2, 504 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 505 .flags = CLK_SET_RATE_PARENT, 506 .ops = &clk_rcg2_shared_ops, 507 }, 508 }; 509 510 static struct clk_rcg2 cam_cc_cci_1_clk_src = { 511 .cmd_rcgr = 0x11004, 512 .mnd_width = 8, 513 .hid_width = 5, 514 .parent_map = cam_cc_parent_map_2, 515 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 516 .clkr.hw.init = &(const struct clk_init_data) { 517 .name = "cam_cc_cci_1_clk_src", 518 .parent_data = cam_cc_parent_data_2, 519 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 520 .flags = CLK_SET_RATE_PARENT, 521 .ops = &clk_rcg2_shared_ops, 522 }, 523 }; 524 525 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 526 F(19200000, P_BI_TCXO, 1, 0, 0), 527 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 528 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), 529 { } 530 }; 531 532 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 533 .cmd_rcgr = 0xc054, 534 .mnd_width = 0, 535 .hid_width = 5, 536 .parent_map = cam_cc_parent_map_0, 537 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 538 .clkr.hw.init = &(const struct clk_init_data) { 539 .name = "cam_cc_cphy_rx_clk_src", 540 .parent_data = cam_cc_parent_data_0, 541 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 542 .flags = CLK_SET_RATE_PARENT, 543 .ops = &clk_rcg2_shared_ops, 544 }, 545 }; 546 547 static struct clk_rcg2 cam_cc_cre_clk_src = { 548 .cmd_rcgr = 0x16004, 549 .mnd_width = 0, 550 .hid_width = 5, 551 .parent_map = cam_cc_parent_map_5, 552 .freq_tbl = ftbl_cam_cc_bps_clk_src, 553 .clkr.hw.init = &(const struct clk_init_data) { 554 .name = "cam_cc_cre_clk_src", 555 .parent_data = cam_cc_parent_data_5, 556 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 557 .flags = CLK_SET_RATE_PARENT, 558 .ops = &clk_rcg2_shared_ops, 559 }, 560 }; 561 562 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 563 F(19200000, P_BI_TCXO, 1, 0, 0), 564 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 565 { } 566 }; 567 568 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 569 .cmd_rcgr = 0x9004, 570 .mnd_width = 0, 571 .hid_width = 5, 572 .parent_map = cam_cc_parent_map_0, 573 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 574 .clkr.hw.init = &(const struct clk_init_data) { 575 .name = "cam_cc_csi0phytimer_clk_src", 576 .parent_data = cam_cc_parent_data_0, 577 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 578 .flags = CLK_SET_RATE_PARENT, 579 .ops = &clk_rcg2_shared_ops, 580 }, 581 }; 582 583 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 584 .cmd_rcgr = 0x9028, 585 .mnd_width = 0, 586 .hid_width = 5, 587 .parent_map = cam_cc_parent_map_0, 588 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 589 .clkr.hw.init = &(const struct clk_init_data) { 590 .name = "cam_cc_csi1phytimer_clk_src", 591 .parent_data = cam_cc_parent_data_0, 592 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 593 .flags = CLK_SET_RATE_PARENT, 594 .ops = &clk_rcg2_shared_ops, 595 }, 596 }; 597 598 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 599 .cmd_rcgr = 0x904c, 600 .mnd_width = 0, 601 .hid_width = 5, 602 .parent_map = cam_cc_parent_map_0, 603 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 604 .clkr.hw.init = &(const struct clk_init_data) { 605 .name = "cam_cc_csi2phytimer_clk_src", 606 .parent_data = cam_cc_parent_data_0, 607 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 608 .flags = CLK_SET_RATE_PARENT, 609 .ops = &clk_rcg2_shared_ops, 610 }, 611 }; 612 613 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 614 F(19200000, P_BI_TCXO, 1, 0, 0), 615 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 616 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), 617 F(200000000, P_CAM_CC_PLL0_OUT_MAIN, 6, 0, 0), 618 F(240000000, P_CAM_CC_PLL0_OUT_MAIN, 5, 0, 0), 619 { } 620 }; 621 622 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 623 .cmd_rcgr = 0xa02c, 624 .mnd_width = 0, 625 .hid_width = 5, 626 .parent_map = cam_cc_parent_map_0, 627 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 628 .clkr.hw.init = &(const struct clk_init_data) { 629 .name = "cam_cc_fast_ahb_clk_src", 630 .parent_data = cam_cc_parent_data_0, 631 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 632 .flags = CLK_SET_RATE_PARENT, 633 .ops = &clk_rcg2_shared_ops, 634 }, 635 }; 636 637 static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 638 F(19200000, P_BI_TCXO, 1, 0, 0), 639 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 640 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 641 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 642 { } 643 }; 644 645 static struct clk_rcg2 cam_cc_icp_clk_src = { 646 .cmd_rcgr = 0xf014, 647 .mnd_width = 0, 648 .hid_width = 5, 649 .parent_map = cam_cc_parent_map_6, 650 .freq_tbl = ftbl_cam_cc_icp_clk_src, 651 .clkr.hw.init = &(const struct clk_init_data) { 652 .name = "cam_cc_icp_clk_src", 653 .parent_data = cam_cc_parent_data_6, 654 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), 655 .flags = CLK_SET_RATE_PARENT, 656 .ops = &clk_rcg2_shared_ops, 657 }, 658 }; 659 660 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 661 F(19200000, P_CAM_CC_PLL2_OUT_MAIN, 1, 1, 50), 662 F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4), 663 F(64000000, P_CAM_CC_PLL2_OUT_MAIN, 15, 0, 0), 664 { } 665 }; 666 667 static struct clk_rcg2 cam_cc_mclk0_clk_src = { 668 .cmd_rcgr = 0x8004, 669 .mnd_width = 8, 670 .hid_width = 5, 671 .parent_map = cam_cc_parent_map_1, 672 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 673 .clkr.hw.init = &(const struct clk_init_data) { 674 .name = "cam_cc_mclk0_clk_src", 675 .parent_data = cam_cc_parent_data_1, 676 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 677 .flags = CLK_SET_RATE_PARENT, 678 .ops = &clk_rcg2_shared_ops, 679 }, 680 }; 681 682 static struct clk_rcg2 cam_cc_mclk1_clk_src = { 683 .cmd_rcgr = 0x8024, 684 .mnd_width = 8, 685 .hid_width = 5, 686 .parent_map = cam_cc_parent_map_1, 687 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 688 .clkr.hw.init = &(const struct clk_init_data) { 689 .name = "cam_cc_mclk1_clk_src", 690 .parent_data = cam_cc_parent_data_1, 691 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 692 .flags = CLK_SET_RATE_PARENT, 693 .ops = &clk_rcg2_shared_ops, 694 }, 695 }; 696 697 static struct clk_rcg2 cam_cc_mclk2_clk_src = { 698 .cmd_rcgr = 0x8044, 699 .mnd_width = 8, 700 .hid_width = 5, 701 .parent_map = cam_cc_parent_map_1, 702 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 703 .clkr.hw.init = &(const struct clk_init_data) { 704 .name = "cam_cc_mclk2_clk_src", 705 .parent_data = cam_cc_parent_data_1, 706 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 707 .flags = CLK_SET_RATE_PARENT, 708 .ops = &clk_rcg2_shared_ops, 709 }, 710 }; 711 712 static struct clk_rcg2 cam_cc_mclk3_clk_src = { 713 .cmd_rcgr = 0x8064, 714 .mnd_width = 8, 715 .hid_width = 5, 716 .parent_map = cam_cc_parent_map_1, 717 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 718 .clkr.hw.init = &(const struct clk_init_data) { 719 .name = "cam_cc_mclk3_clk_src", 720 .parent_data = cam_cc_parent_data_1, 721 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 722 .flags = CLK_SET_RATE_PARENT, 723 .ops = &clk_rcg2_shared_ops, 724 }, 725 }; 726 727 static const struct freq_tbl ftbl_cam_cc_ope_0_clk_src[] = { 728 F(19200000, P_BI_TCXO, 1, 0, 0), 729 F(300000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 730 F(410000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 731 F(460000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 732 F(600000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 733 F(700000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 734 { } 735 }; 736 737 static struct clk_rcg2 cam_cc_ope_0_clk_src = { 738 .cmd_rcgr = 0xb004, 739 .mnd_width = 0, 740 .hid_width = 5, 741 .parent_map = cam_cc_parent_map_7, 742 .freq_tbl = ftbl_cam_cc_ope_0_clk_src, 743 .clkr.hw.init = &(const struct clk_init_data) { 744 .name = "cam_cc_ope_0_clk_src", 745 .parent_data = cam_cc_parent_data_7, 746 .num_parents = ARRAY_SIZE(cam_cc_parent_data_7), 747 .flags = CLK_SET_RATE_PARENT, 748 .ops = &clk_rcg2_shared_ops, 749 }, 750 }; 751 752 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 753 F(19200000, P_BI_TCXO, 1, 0, 0), 754 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 755 { } 756 }; 757 758 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 759 .cmd_rcgr = 0xa048, 760 .mnd_width = 0, 761 .hid_width = 5, 762 .parent_map = cam_cc_parent_map_0, 763 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 764 .clkr.hw.init = &(const struct clk_init_data) { 765 .name = "cam_cc_slow_ahb_clk_src", 766 .parent_data = cam_cc_parent_data_0, 767 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 768 .flags = CLK_SET_RATE_PARENT, 769 .ops = &clk_rcg2_shared_ops, 770 }, 771 }; 772 773 static const struct freq_tbl ftbl_cam_cc_tfe_0_clk_src[] = { 774 F(19200000, P_BI_TCXO, 1, 0, 0), 775 F(350000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 776 F(432000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 777 F(548000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 778 F(630000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 779 { } 780 }; 781 782 static struct clk_rcg2 cam_cc_tfe_0_clk_src = { 783 .cmd_rcgr = 0xc004, 784 .mnd_width = 0, 785 .hid_width = 5, 786 .parent_map = cam_cc_parent_map_3, 787 .freq_tbl = ftbl_cam_cc_tfe_0_clk_src, 788 .clkr.hw.init = &(const struct clk_init_data) { 789 .name = "cam_cc_tfe_0_clk_src", 790 .parent_data = cam_cc_parent_data_3, 791 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 792 .flags = CLK_SET_RATE_PARENT, 793 .ops = &clk_rcg2_shared_ops, 794 }, 795 }; 796 797 static struct clk_rcg2 cam_cc_tfe_0_csid_clk_src = { 798 .cmd_rcgr = 0xc02c, 799 .mnd_width = 0, 800 .hid_width = 5, 801 .parent_map = cam_cc_parent_map_0, 802 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 803 .clkr.hw.init = &(const struct clk_init_data) { 804 .name = "cam_cc_tfe_0_csid_clk_src", 805 .parent_data = cam_cc_parent_data_0, 806 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 807 .flags = CLK_SET_RATE_PARENT, 808 .ops = &clk_rcg2_shared_ops, 809 }, 810 }; 811 812 static struct clk_rcg2 cam_cc_tfe_1_clk_src = { 813 .cmd_rcgr = 0xd004, 814 .mnd_width = 0, 815 .hid_width = 5, 816 .parent_map = cam_cc_parent_map_3, 817 .freq_tbl = ftbl_cam_cc_tfe_0_clk_src, 818 .clkr.hw.init = &(const struct clk_init_data) { 819 .name = "cam_cc_tfe_1_clk_src", 820 .parent_data = cam_cc_parent_data_3, 821 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 822 .flags = CLK_SET_RATE_PARENT, 823 .ops = &clk_rcg2_shared_ops, 824 }, 825 }; 826 827 static struct clk_rcg2 cam_cc_tfe_1_csid_clk_src = { 828 .cmd_rcgr = 0xd024, 829 .mnd_width = 0, 830 .hid_width = 5, 831 .parent_map = cam_cc_parent_map_0, 832 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 833 .clkr.hw.init = &(const struct clk_init_data) { 834 .name = "cam_cc_tfe_1_csid_clk_src", 835 .parent_data = cam_cc_parent_data_0, 836 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 837 .flags = CLK_SET_RATE_PARENT, 838 .ops = &clk_rcg2_shared_ops, 839 }, 840 }; 841 842 static struct clk_branch cam_cc_bps_ahb_clk = { 843 .halt_reg = 0xa060, 844 .halt_check = BRANCH_HALT, 845 .clkr = { 846 .enable_reg = 0xa060, 847 .enable_mask = BIT(0), 848 .hw.init = &(const struct clk_init_data) { 849 .name = "cam_cc_bps_ahb_clk", 850 .parent_hws = (const struct clk_hw*[]) { 851 &cam_cc_slow_ahb_clk_src.clkr.hw, 852 }, 853 .num_parents = 1, 854 .flags = CLK_SET_RATE_PARENT, 855 .ops = &clk_branch2_ops, 856 }, 857 }, 858 }; 859 860 static struct clk_branch cam_cc_bps_areg_clk = { 861 .halt_reg = 0xa044, 862 .halt_check = BRANCH_HALT, 863 .clkr = { 864 .enable_reg = 0xa044, 865 .enable_mask = BIT(0), 866 .hw.init = &(const struct clk_init_data) { 867 .name = "cam_cc_bps_areg_clk", 868 .parent_hws = (const struct clk_hw*[]) { 869 &cam_cc_fast_ahb_clk_src.clkr.hw, 870 }, 871 .num_parents = 1, 872 .flags = CLK_SET_RATE_PARENT, 873 .ops = &clk_branch2_ops, 874 }, 875 }, 876 }; 877 878 static struct clk_branch cam_cc_bps_clk = { 879 .halt_reg = 0xa01c, 880 .halt_check = BRANCH_HALT, 881 .clkr = { 882 .enable_reg = 0xa01c, 883 .enable_mask = BIT(0), 884 .hw.init = &(const struct clk_init_data) { 885 .name = "cam_cc_bps_clk", 886 .parent_hws = (const struct clk_hw*[]) { 887 &cam_cc_bps_clk_src.clkr.hw, 888 }, 889 .num_parents = 1, 890 .flags = CLK_SET_RATE_PARENT, 891 .ops = &clk_branch2_ops, 892 }, 893 }, 894 }; 895 896 static struct clk_branch cam_cc_camnoc_atb_clk = { 897 .halt_reg = 0x13034, 898 .halt_check = BRANCH_HALT, 899 .clkr = { 900 .enable_reg = 0x13034, 901 .enable_mask = BIT(0), 902 .hw.init = &(const struct clk_init_data) { 903 .name = "cam_cc_camnoc_atb_clk", 904 .ops = &clk_branch2_ops, 905 }, 906 }, 907 }; 908 909 static struct clk_branch cam_cc_camnoc_axi_clk = { 910 .halt_reg = 0x1302c, 911 .halt_check = BRANCH_HALT, 912 .clkr = { 913 .enable_reg = 0x1302c, 914 .enable_mask = BIT(0), 915 .hw.init = &(const struct clk_init_data) { 916 .name = "cam_cc_camnoc_axi_clk", 917 .parent_hws = (const struct clk_hw*[]) { 918 &cam_cc_camnoc_axi_clk_src.clkr.hw, 919 }, 920 .num_parents = 1, 921 .flags = CLK_SET_RATE_PARENT, 922 .ops = &clk_branch2_ops, 923 }, 924 }, 925 }; 926 927 static struct clk_branch cam_cc_camnoc_axi_hf_clk = { 928 .halt_reg = 0x1300c, 929 .halt_check = BRANCH_HALT, 930 .clkr = { 931 .enable_reg = 0x1300c, 932 .enable_mask = BIT(0), 933 .hw.init = &(const struct clk_init_data) { 934 .name = "cam_cc_camnoc_axi_hf_clk", 935 .ops = &clk_branch2_ops, 936 }, 937 }, 938 }; 939 940 static struct clk_branch cam_cc_camnoc_axi_sf_clk = { 941 .halt_reg = 0x13004, 942 .halt_check = BRANCH_HALT, 943 .clkr = { 944 .enable_reg = 0x13004, 945 .enable_mask = BIT(0), 946 .hw.init = &(const struct clk_init_data) { 947 .name = "cam_cc_camnoc_axi_sf_clk", 948 .ops = &clk_branch2_ops, 949 }, 950 }, 951 }; 952 953 static struct clk_branch cam_cc_cci_0_clk = { 954 .halt_reg = 0x1001c, 955 .halt_check = BRANCH_HALT, 956 .clkr = { 957 .enable_reg = 0x1001c, 958 .enable_mask = BIT(0), 959 .hw.init = &(const struct clk_init_data) { 960 .name = "cam_cc_cci_0_clk", 961 .parent_hws = (const struct clk_hw*[]) { 962 &cam_cc_cci_0_clk_src.clkr.hw, 963 }, 964 .num_parents = 1, 965 .flags = CLK_SET_RATE_PARENT, 966 .ops = &clk_branch2_ops, 967 }, 968 }, 969 }; 970 971 static struct clk_branch cam_cc_cci_1_clk = { 972 .halt_reg = 0x1101c, 973 .halt_check = BRANCH_HALT, 974 .clkr = { 975 .enable_reg = 0x1101c, 976 .enable_mask = BIT(0), 977 .hw.init = &(const struct clk_init_data) { 978 .name = "cam_cc_cci_1_clk", 979 .parent_hws = (const struct clk_hw*[]) { 980 &cam_cc_cci_1_clk_src.clkr.hw, 981 }, 982 .num_parents = 1, 983 .flags = CLK_SET_RATE_PARENT, 984 .ops = &clk_branch2_ops, 985 }, 986 }, 987 }; 988 989 static struct clk_branch cam_cc_core_ahb_clk = { 990 .halt_reg = 0x1401c, 991 .halt_check = BRANCH_HALT_DELAY, 992 .clkr = { 993 .enable_reg = 0x1401c, 994 .enable_mask = BIT(0), 995 .hw.init = &(const struct clk_init_data) { 996 .name = "cam_cc_core_ahb_clk", 997 .parent_hws = (const struct clk_hw*[]) { 998 &cam_cc_slow_ahb_clk_src.clkr.hw, 999 }, 1000 .num_parents = 1, 1001 .flags = CLK_SET_RATE_PARENT, 1002 .ops = &clk_branch2_ops, 1003 }, 1004 }, 1005 }; 1006 1007 static struct clk_branch cam_cc_cpas_ahb_clk = { 1008 .halt_reg = 0x12004, 1009 .halt_check = BRANCH_HALT, 1010 .clkr = { 1011 .enable_reg = 0x12004, 1012 .enable_mask = BIT(0), 1013 .hw.init = &(const struct clk_init_data) { 1014 .name = "cam_cc_cpas_ahb_clk", 1015 .parent_hws = (const struct clk_hw*[]) { 1016 &cam_cc_slow_ahb_clk_src.clkr.hw, 1017 }, 1018 .num_parents = 1, 1019 .flags = CLK_SET_RATE_PARENT, 1020 .ops = &clk_branch2_ops, 1021 }, 1022 }, 1023 }; 1024 1025 static struct clk_branch cam_cc_cre_ahb_clk = { 1026 .halt_reg = 0x16020, 1027 .halt_check = BRANCH_HALT, 1028 .clkr = { 1029 .enable_reg = 0x16020, 1030 .enable_mask = BIT(0), 1031 .hw.init = &(const struct clk_init_data) { 1032 .name = "cam_cc_cre_ahb_clk", 1033 .parent_hws = (const struct clk_hw*[]) { 1034 &cam_cc_slow_ahb_clk_src.clkr.hw, 1035 }, 1036 .num_parents = 1, 1037 .flags = CLK_SET_RATE_PARENT, 1038 .ops = &clk_branch2_ops, 1039 }, 1040 }, 1041 }; 1042 1043 static struct clk_branch cam_cc_cre_clk = { 1044 .halt_reg = 0x1601c, 1045 .halt_check = BRANCH_HALT, 1046 .clkr = { 1047 .enable_reg = 0x1601c, 1048 .enable_mask = BIT(0), 1049 .hw.init = &(const struct clk_init_data) { 1050 .name = "cam_cc_cre_clk", 1051 .parent_hws = (const struct clk_hw*[]) { 1052 &cam_cc_cre_clk_src.clkr.hw, 1053 }, 1054 .num_parents = 1, 1055 .flags = CLK_SET_RATE_PARENT, 1056 .ops = &clk_branch2_ops, 1057 }, 1058 }, 1059 }; 1060 1061 static struct clk_branch cam_cc_csi0phytimer_clk = { 1062 .halt_reg = 0x901c, 1063 .halt_check = BRANCH_HALT, 1064 .clkr = { 1065 .enable_reg = 0x901c, 1066 .enable_mask = BIT(0), 1067 .hw.init = &(const struct clk_init_data) { 1068 .name = "cam_cc_csi0phytimer_clk", 1069 .parent_hws = (const struct clk_hw*[]) { 1070 &cam_cc_csi0phytimer_clk_src.clkr.hw, 1071 }, 1072 .num_parents = 1, 1073 .flags = CLK_SET_RATE_PARENT, 1074 .ops = &clk_branch2_ops, 1075 }, 1076 }, 1077 }; 1078 1079 static struct clk_branch cam_cc_csi1phytimer_clk = { 1080 .halt_reg = 0x9040, 1081 .halt_check = BRANCH_HALT, 1082 .clkr = { 1083 .enable_reg = 0x9040, 1084 .enable_mask = BIT(0), 1085 .hw.init = &(const struct clk_init_data) { 1086 .name = "cam_cc_csi1phytimer_clk", 1087 .parent_hws = (const struct clk_hw*[]) { 1088 &cam_cc_csi1phytimer_clk_src.clkr.hw, 1089 }, 1090 .num_parents = 1, 1091 .flags = CLK_SET_RATE_PARENT, 1092 .ops = &clk_branch2_ops, 1093 }, 1094 }, 1095 }; 1096 1097 static struct clk_branch cam_cc_csi2phytimer_clk = { 1098 .halt_reg = 0x9064, 1099 .halt_check = BRANCH_HALT, 1100 .clkr = { 1101 .enable_reg = 0x9064, 1102 .enable_mask = BIT(0), 1103 .hw.init = &(const struct clk_init_data) { 1104 .name = "cam_cc_csi2phytimer_clk", 1105 .parent_hws = (const struct clk_hw*[]) { 1106 &cam_cc_csi2phytimer_clk_src.clkr.hw, 1107 }, 1108 .num_parents = 1, 1109 .flags = CLK_SET_RATE_PARENT, 1110 .ops = &clk_branch2_ops, 1111 }, 1112 }, 1113 }; 1114 1115 static struct clk_branch cam_cc_csiphy0_clk = { 1116 .halt_reg = 0x9020, 1117 .halt_check = BRANCH_HALT, 1118 .clkr = { 1119 .enable_reg = 0x9020, 1120 .enable_mask = BIT(0), 1121 .hw.init = &(const struct clk_init_data) { 1122 .name = "cam_cc_csiphy0_clk", 1123 .parent_hws = (const struct clk_hw*[]) { 1124 &cam_cc_cphy_rx_clk_src.clkr.hw, 1125 }, 1126 .num_parents = 1, 1127 .flags = CLK_SET_RATE_PARENT, 1128 .ops = &clk_branch2_ops, 1129 }, 1130 }, 1131 }; 1132 1133 static struct clk_branch cam_cc_csiphy1_clk = { 1134 .halt_reg = 0x9044, 1135 .halt_check = BRANCH_HALT, 1136 .clkr = { 1137 .enable_reg = 0x9044, 1138 .enable_mask = BIT(0), 1139 .hw.init = &(const struct clk_init_data) { 1140 .name = "cam_cc_csiphy1_clk", 1141 .parent_hws = (const struct clk_hw*[]) { 1142 &cam_cc_cphy_rx_clk_src.clkr.hw, 1143 }, 1144 .num_parents = 1, 1145 .flags = CLK_SET_RATE_PARENT, 1146 .ops = &clk_branch2_ops, 1147 }, 1148 }, 1149 }; 1150 1151 static struct clk_branch cam_cc_csiphy2_clk = { 1152 .halt_reg = 0x9068, 1153 .halt_check = BRANCH_HALT, 1154 .clkr = { 1155 .enable_reg = 0x9068, 1156 .enable_mask = BIT(0), 1157 .hw.init = &(const struct clk_init_data) { 1158 .name = "cam_cc_csiphy2_clk", 1159 .parent_hws = (const struct clk_hw*[]) { 1160 &cam_cc_cphy_rx_clk_src.clkr.hw, 1161 }, 1162 .num_parents = 1, 1163 .flags = CLK_SET_RATE_PARENT, 1164 .ops = &clk_branch2_ops, 1165 }, 1166 }, 1167 }; 1168 1169 static struct clk_branch cam_cc_icp_atb_clk = { 1170 .halt_reg = 0xf004, 1171 .halt_check = BRANCH_HALT, 1172 .clkr = { 1173 .enable_reg = 0xf004, 1174 .enable_mask = BIT(0), 1175 .hw.init = &(const struct clk_init_data) { 1176 .name = "cam_cc_icp_atb_clk", 1177 .ops = &clk_branch2_ops, 1178 }, 1179 }, 1180 }; 1181 1182 static struct clk_branch cam_cc_icp_clk = { 1183 .halt_reg = 0xf02c, 1184 .halt_check = BRANCH_HALT, 1185 .clkr = { 1186 .enable_reg = 0xf02c, 1187 .enable_mask = BIT(0), 1188 .hw.init = &(const struct clk_init_data) { 1189 .name = "cam_cc_icp_clk", 1190 .parent_hws = (const struct clk_hw*[]) { 1191 &cam_cc_icp_clk_src.clkr.hw, 1192 }, 1193 .num_parents = 1, 1194 .flags = CLK_SET_RATE_PARENT, 1195 .ops = &clk_branch2_ops, 1196 }, 1197 }, 1198 }; 1199 1200 static struct clk_branch cam_cc_icp_cti_clk = { 1201 .halt_reg = 0xf008, 1202 .halt_check = BRANCH_HALT, 1203 .clkr = { 1204 .enable_reg = 0xf008, 1205 .enable_mask = BIT(0), 1206 .hw.init = &(const struct clk_init_data) { 1207 .name = "cam_cc_icp_cti_clk", 1208 .ops = &clk_branch2_ops, 1209 }, 1210 }, 1211 }; 1212 1213 static struct clk_branch cam_cc_icp_ts_clk = { 1214 .halt_reg = 0xf00c, 1215 .halt_check = BRANCH_HALT, 1216 .clkr = { 1217 .enable_reg = 0xf00c, 1218 .enable_mask = BIT(0), 1219 .hw.init = &(const struct clk_init_data) { 1220 .name = "cam_cc_icp_ts_clk", 1221 .ops = &clk_branch2_ops, 1222 }, 1223 }, 1224 }; 1225 1226 static struct clk_branch cam_cc_mclk0_clk = { 1227 .halt_reg = 0x801c, 1228 .halt_check = BRANCH_HALT, 1229 .clkr = { 1230 .enable_reg = 0x801c, 1231 .enable_mask = BIT(0), 1232 .hw.init = &(const struct clk_init_data) { 1233 .name = "cam_cc_mclk0_clk", 1234 .parent_hws = (const struct clk_hw*[]) { 1235 &cam_cc_mclk0_clk_src.clkr.hw, 1236 }, 1237 .num_parents = 1, 1238 .flags = CLK_SET_RATE_PARENT, 1239 .ops = &clk_branch2_ops, 1240 }, 1241 }, 1242 }; 1243 1244 static struct clk_branch cam_cc_mclk1_clk = { 1245 .halt_reg = 0x803c, 1246 .halt_check = BRANCH_HALT, 1247 .clkr = { 1248 .enable_reg = 0x803c, 1249 .enable_mask = BIT(0), 1250 .hw.init = &(const struct clk_init_data) { 1251 .name = "cam_cc_mclk1_clk", 1252 .parent_hws = (const struct clk_hw*[]) { 1253 &cam_cc_mclk1_clk_src.clkr.hw, 1254 }, 1255 .num_parents = 1, 1256 .flags = CLK_SET_RATE_PARENT, 1257 .ops = &clk_branch2_ops, 1258 }, 1259 }, 1260 }; 1261 1262 static struct clk_branch cam_cc_mclk2_clk = { 1263 .halt_reg = 0x805c, 1264 .halt_check = BRANCH_HALT, 1265 .clkr = { 1266 .enable_reg = 0x805c, 1267 .enable_mask = BIT(0), 1268 .hw.init = &(const struct clk_init_data) { 1269 .name = "cam_cc_mclk2_clk", 1270 .parent_hws = (const struct clk_hw*[]) { 1271 &cam_cc_mclk2_clk_src.clkr.hw, 1272 }, 1273 .num_parents = 1, 1274 .flags = CLK_SET_RATE_PARENT, 1275 .ops = &clk_branch2_ops, 1276 }, 1277 }, 1278 }; 1279 1280 static struct clk_branch cam_cc_mclk3_clk = { 1281 .halt_reg = 0x807c, 1282 .halt_check = BRANCH_HALT, 1283 .clkr = { 1284 .enable_reg = 0x807c, 1285 .enable_mask = BIT(0), 1286 .hw.init = &(const struct clk_init_data) { 1287 .name = "cam_cc_mclk3_clk", 1288 .parent_hws = (const struct clk_hw*[]) { 1289 &cam_cc_mclk3_clk_src.clkr.hw, 1290 }, 1291 .num_parents = 1, 1292 .flags = CLK_SET_RATE_PARENT, 1293 .ops = &clk_branch2_ops, 1294 }, 1295 }, 1296 }; 1297 1298 static struct clk_branch cam_cc_ope_0_ahb_clk = { 1299 .halt_reg = 0xb030, 1300 .halt_check = BRANCH_HALT, 1301 .clkr = { 1302 .enable_reg = 0xb030, 1303 .enable_mask = BIT(0), 1304 .hw.init = &(const struct clk_init_data) { 1305 .name = "cam_cc_ope_0_ahb_clk", 1306 .parent_hws = (const struct clk_hw*[]) { 1307 &cam_cc_slow_ahb_clk_src.clkr.hw, 1308 }, 1309 .num_parents = 1, 1310 .flags = CLK_SET_RATE_PARENT, 1311 .ops = &clk_branch2_ops, 1312 }, 1313 }, 1314 }; 1315 1316 static struct clk_branch cam_cc_ope_0_areg_clk = { 1317 .halt_reg = 0xb02c, 1318 .halt_check = BRANCH_HALT, 1319 .clkr = { 1320 .enable_reg = 0xb02c, 1321 .enable_mask = BIT(0), 1322 .hw.init = &(const struct clk_init_data) { 1323 .name = "cam_cc_ope_0_areg_clk", 1324 .parent_hws = (const struct clk_hw*[]) { 1325 &cam_cc_fast_ahb_clk_src.clkr.hw, 1326 }, 1327 .num_parents = 1, 1328 .flags = CLK_SET_RATE_PARENT, 1329 .ops = &clk_branch2_ops, 1330 }, 1331 }, 1332 }; 1333 1334 static struct clk_branch cam_cc_ope_0_clk = { 1335 .halt_reg = 0xb01c, 1336 .halt_check = BRANCH_HALT, 1337 .clkr = { 1338 .enable_reg = 0xb01c, 1339 .enable_mask = BIT(0), 1340 .hw.init = &(const struct clk_init_data) { 1341 .name = "cam_cc_ope_0_clk", 1342 .parent_hws = (const struct clk_hw*[]) { 1343 &cam_cc_ope_0_clk_src.clkr.hw, 1344 }, 1345 .num_parents = 1, 1346 .flags = CLK_SET_RATE_PARENT, 1347 .ops = &clk_branch2_ops, 1348 }, 1349 }, 1350 }; 1351 1352 static struct clk_branch cam_cc_soc_ahb_clk = { 1353 .halt_reg = 0x14018, 1354 .halt_check = BRANCH_HALT, 1355 .clkr = { 1356 .enable_reg = 0x14018, 1357 .enable_mask = BIT(0), 1358 .hw.init = &(const struct clk_init_data) { 1359 .name = "cam_cc_soc_ahb_clk", 1360 .ops = &clk_branch2_ops, 1361 }, 1362 }, 1363 }; 1364 1365 static struct clk_branch cam_cc_sys_tmr_clk = { 1366 .halt_reg = 0xf034, 1367 .halt_check = BRANCH_HALT, 1368 .clkr = { 1369 .enable_reg = 0xf034, 1370 .enable_mask = BIT(0), 1371 .hw.init = &(const struct clk_init_data) { 1372 .name = "cam_cc_sys_tmr_clk", 1373 .ops = &clk_branch2_ops, 1374 }, 1375 }, 1376 }; 1377 1378 static struct clk_branch cam_cc_tfe_0_ahb_clk = { 1379 .halt_reg = 0xc070, 1380 .halt_check = BRANCH_HALT, 1381 .clkr = { 1382 .enable_reg = 0xc070, 1383 .enable_mask = BIT(0), 1384 .hw.init = &(const struct clk_init_data) { 1385 .name = "cam_cc_tfe_0_ahb_clk", 1386 .parent_hws = (const struct clk_hw*[]) { 1387 &cam_cc_slow_ahb_clk_src.clkr.hw, 1388 }, 1389 .num_parents = 1, 1390 .flags = CLK_SET_RATE_PARENT, 1391 .ops = &clk_branch2_ops, 1392 }, 1393 }, 1394 }; 1395 1396 static struct clk_branch cam_cc_tfe_0_clk = { 1397 .halt_reg = 0xc01c, 1398 .halt_check = BRANCH_HALT, 1399 .clkr = { 1400 .enable_reg = 0xc01c, 1401 .enable_mask = BIT(0), 1402 .hw.init = &(const struct clk_init_data) { 1403 .name = "cam_cc_tfe_0_clk", 1404 .parent_hws = (const struct clk_hw*[]) { 1405 &cam_cc_tfe_0_clk_src.clkr.hw, 1406 }, 1407 .num_parents = 1, 1408 .flags = CLK_SET_RATE_PARENT, 1409 .ops = &clk_branch2_ops, 1410 }, 1411 }, 1412 }; 1413 1414 static struct clk_branch cam_cc_tfe_0_cphy_rx_clk = { 1415 .halt_reg = 0xc06c, 1416 .halt_check = BRANCH_HALT, 1417 .clkr = { 1418 .enable_reg = 0xc06c, 1419 .enable_mask = BIT(0), 1420 .hw.init = &(const struct clk_init_data) { 1421 .name = "cam_cc_tfe_0_cphy_rx_clk", 1422 .parent_hws = (const struct clk_hw*[]) { 1423 &cam_cc_cphy_rx_clk_src.clkr.hw, 1424 }, 1425 .num_parents = 1, 1426 .flags = CLK_SET_RATE_PARENT, 1427 .ops = &clk_branch2_ops, 1428 }, 1429 }, 1430 }; 1431 1432 static struct clk_branch cam_cc_tfe_0_csid_clk = { 1433 .halt_reg = 0xc044, 1434 .halt_check = BRANCH_HALT, 1435 .clkr = { 1436 .enable_reg = 0xc044, 1437 .enable_mask = BIT(0), 1438 .hw.init = &(const struct clk_init_data) { 1439 .name = "cam_cc_tfe_0_csid_clk", 1440 .parent_hws = (const struct clk_hw*[]) { 1441 &cam_cc_tfe_0_csid_clk_src.clkr.hw, 1442 }, 1443 .num_parents = 1, 1444 .flags = CLK_SET_RATE_PARENT, 1445 .ops = &clk_branch2_ops, 1446 }, 1447 }, 1448 }; 1449 1450 static struct clk_branch cam_cc_tfe_1_ahb_clk = { 1451 .halt_reg = 0xd048, 1452 .halt_check = BRANCH_HALT, 1453 .clkr = { 1454 .enable_reg = 0xd048, 1455 .enable_mask = BIT(0), 1456 .hw.init = &(const struct clk_init_data) { 1457 .name = "cam_cc_tfe_1_ahb_clk", 1458 .parent_hws = (const struct clk_hw*[]) { 1459 &cam_cc_slow_ahb_clk_src.clkr.hw, 1460 }, 1461 .num_parents = 1, 1462 .flags = CLK_SET_RATE_PARENT, 1463 .ops = &clk_branch2_ops, 1464 }, 1465 }, 1466 }; 1467 1468 static struct clk_branch cam_cc_tfe_1_clk = { 1469 .halt_reg = 0xd01c, 1470 .halt_check = BRANCH_HALT, 1471 .clkr = { 1472 .enable_reg = 0xd01c, 1473 .enable_mask = BIT(0), 1474 .hw.init = &(const struct clk_init_data) { 1475 .name = "cam_cc_tfe_1_clk", 1476 .parent_hws = (const struct clk_hw*[]) { 1477 &cam_cc_tfe_1_clk_src.clkr.hw, 1478 }, 1479 .num_parents = 1, 1480 .flags = CLK_SET_RATE_PARENT, 1481 .ops = &clk_branch2_ops, 1482 }, 1483 }, 1484 }; 1485 1486 static struct clk_branch cam_cc_tfe_1_cphy_rx_clk = { 1487 .halt_reg = 0xd044, 1488 .halt_check = BRANCH_HALT, 1489 .clkr = { 1490 .enable_reg = 0xd044, 1491 .enable_mask = BIT(0), 1492 .hw.init = &(const struct clk_init_data) { 1493 .name = "cam_cc_tfe_1_cphy_rx_clk", 1494 .parent_hws = (const struct clk_hw*[]) { 1495 &cam_cc_cphy_rx_clk_src.clkr.hw, 1496 }, 1497 .num_parents = 1, 1498 .flags = CLK_SET_RATE_PARENT, 1499 .ops = &clk_branch2_ops, 1500 }, 1501 }, 1502 }; 1503 1504 static struct clk_branch cam_cc_tfe_1_csid_clk = { 1505 .halt_reg = 0xd03c, 1506 .halt_check = BRANCH_HALT, 1507 .clkr = { 1508 .enable_reg = 0xd03c, 1509 .enable_mask = BIT(0), 1510 .hw.init = &(const struct clk_init_data) { 1511 .name = "cam_cc_tfe_1_csid_clk", 1512 .parent_hws = (const struct clk_hw*[]) { 1513 &cam_cc_tfe_1_csid_clk_src.clkr.hw, 1514 }, 1515 .num_parents = 1, 1516 .flags = CLK_SET_RATE_PARENT, 1517 .ops = &clk_branch2_ops, 1518 }, 1519 }, 1520 }; 1521 1522 static struct gdsc cam_cc_camss_top_gdsc = { 1523 .gdscr = 0x14004, 1524 .en_rest_wait_val = 0x2, 1525 .en_few_wait_val = 0x2, 1526 .clk_dis_wait_val = 0xf, 1527 .pd = { 1528 .name = "cam_cc_camss_top_gdsc", 1529 }, 1530 .pwrsts = PWRSTS_OFF_ON, 1531 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1532 }; 1533 1534 static struct clk_regmap *cam_cc_sm4450_clocks[] = { 1535 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, 1536 [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr, 1537 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, 1538 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, 1539 [CAM_CC_CAMNOC_ATB_CLK] = &cam_cc_camnoc_atb_clk.clkr, 1540 [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr, 1541 [CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr, 1542 [CAM_CC_CAMNOC_AXI_HF_CLK] = &cam_cc_camnoc_axi_hf_clk.clkr, 1543 [CAM_CC_CAMNOC_AXI_SF_CLK] = &cam_cc_camnoc_axi_sf_clk.clkr, 1544 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, 1545 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, 1546 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, 1547 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, 1548 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 1549 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 1550 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 1551 [CAM_CC_CRE_AHB_CLK] = &cam_cc_cre_ahb_clk.clkr, 1552 [CAM_CC_CRE_CLK] = &cam_cc_cre_clk.clkr, 1553 [CAM_CC_CRE_CLK_SRC] = &cam_cc_cre_clk_src.clkr, 1554 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 1555 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 1556 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 1557 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 1558 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 1559 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 1560 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 1561 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 1562 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 1563 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 1564 [CAM_CC_ICP_ATB_CLK] = &cam_cc_icp_atb_clk.clkr, 1565 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 1566 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 1567 [CAM_CC_ICP_CTI_CLK] = &cam_cc_icp_cti_clk.clkr, 1568 [CAM_CC_ICP_TS_CLK] = &cam_cc_icp_ts_clk.clkr, 1569 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 1570 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 1571 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 1572 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 1573 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 1574 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 1575 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 1576 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 1577 [CAM_CC_OPE_0_AHB_CLK] = &cam_cc_ope_0_ahb_clk.clkr, 1578 [CAM_CC_OPE_0_AREG_CLK] = &cam_cc_ope_0_areg_clk.clkr, 1579 [CAM_CC_OPE_0_CLK] = &cam_cc_ope_0_clk.clkr, 1580 [CAM_CC_OPE_0_CLK_SRC] = &cam_cc_ope_0_clk_src.clkr, 1581 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 1582 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, 1583 [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, 1584 [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 1585 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, 1586 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 1587 [CAM_CC_PLL2_OUT_EVEN] = &cam_cc_pll2_out_even.clkr, 1588 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 1589 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, 1590 [CAM_CC_PLL4] = &cam_cc_pll4.clkr, 1591 [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, 1592 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 1593 [CAM_CC_SOC_AHB_CLK] = &cam_cc_soc_ahb_clk.clkr, 1594 [CAM_CC_SYS_TMR_CLK] = &cam_cc_sys_tmr_clk.clkr, 1595 [CAM_CC_TFE_0_AHB_CLK] = &cam_cc_tfe_0_ahb_clk.clkr, 1596 [CAM_CC_TFE_0_CLK] = &cam_cc_tfe_0_clk.clkr, 1597 [CAM_CC_TFE_0_CLK_SRC] = &cam_cc_tfe_0_clk_src.clkr, 1598 [CAM_CC_TFE_0_CPHY_RX_CLK] = &cam_cc_tfe_0_cphy_rx_clk.clkr, 1599 [CAM_CC_TFE_0_CSID_CLK] = &cam_cc_tfe_0_csid_clk.clkr, 1600 [CAM_CC_TFE_0_CSID_CLK_SRC] = &cam_cc_tfe_0_csid_clk_src.clkr, 1601 [CAM_CC_TFE_1_AHB_CLK] = &cam_cc_tfe_1_ahb_clk.clkr, 1602 [CAM_CC_TFE_1_CLK] = &cam_cc_tfe_1_clk.clkr, 1603 [CAM_CC_TFE_1_CLK_SRC] = &cam_cc_tfe_1_clk_src.clkr, 1604 [CAM_CC_TFE_1_CPHY_RX_CLK] = &cam_cc_tfe_1_cphy_rx_clk.clkr, 1605 [CAM_CC_TFE_1_CSID_CLK] = &cam_cc_tfe_1_csid_clk.clkr, 1606 [CAM_CC_TFE_1_CSID_CLK_SRC] = &cam_cc_tfe_1_csid_clk_src.clkr, 1607 }; 1608 1609 static struct gdsc *cam_cc_sm4450_gdscs[] = { 1610 [CAM_CC_CAMSS_TOP_GDSC] = &cam_cc_camss_top_gdsc, 1611 }; 1612 1613 static const struct qcom_reset_map cam_cc_sm4450_resets[] = { 1614 [CAM_CC_BPS_BCR] = { 0xa000 }, 1615 [CAM_CC_CAMNOC_BCR] = { 0x13000 }, 1616 [CAM_CC_CAMSS_TOP_BCR] = { 0x14000 }, 1617 [CAM_CC_CCI_0_BCR] = { 0x10000 }, 1618 [CAM_CC_CCI_1_BCR] = { 0x11000 }, 1619 [CAM_CC_CPAS_BCR] = { 0x12000 }, 1620 [CAM_CC_CRE_BCR] = { 0x16000 }, 1621 [CAM_CC_CSI0PHY_BCR] = { 0x9000 }, 1622 [CAM_CC_CSI1PHY_BCR] = { 0x9024 }, 1623 [CAM_CC_CSI2PHY_BCR] = { 0x9048 }, 1624 [CAM_CC_ICP_BCR] = { 0xf000 }, 1625 [CAM_CC_MCLK0_BCR] = { 0x8000 }, 1626 [CAM_CC_MCLK1_BCR] = { 0x8020 }, 1627 [CAM_CC_MCLK2_BCR] = { 0x8040 }, 1628 [CAM_CC_MCLK3_BCR] = { 0x8060 }, 1629 [CAM_CC_OPE_0_BCR] = { 0xb000 }, 1630 [CAM_CC_TFE_0_BCR] = { 0xc000 }, 1631 [CAM_CC_TFE_1_BCR] = { 0xd000 }, 1632 }; 1633 1634 static const struct regmap_config cam_cc_sm4450_regmap_config = { 1635 .reg_bits = 32, 1636 .reg_stride = 4, 1637 .val_bits = 32, 1638 .max_register = 0x16024, 1639 .fast_io = true, 1640 }; 1641 1642 static const struct qcom_cc_desc cam_cc_sm4450_desc = { 1643 .config = &cam_cc_sm4450_regmap_config, 1644 .clks = cam_cc_sm4450_clocks, 1645 .num_clks = ARRAY_SIZE(cam_cc_sm4450_clocks), 1646 .resets = cam_cc_sm4450_resets, 1647 .num_resets = ARRAY_SIZE(cam_cc_sm4450_resets), 1648 .gdscs = cam_cc_sm4450_gdscs, 1649 .num_gdscs = ARRAY_SIZE(cam_cc_sm4450_gdscs), 1650 }; 1651 1652 static const struct of_device_id cam_cc_sm4450_match_table[] = { 1653 { .compatible = "qcom,sm4450-camcc" }, 1654 { } 1655 }; 1656 MODULE_DEVICE_TABLE(of, cam_cc_sm4450_match_table); 1657 1658 static int cam_cc_sm4450_probe(struct platform_device *pdev) 1659 { 1660 struct regmap *regmap; 1661 1662 regmap = qcom_cc_map(pdev, &cam_cc_sm4450_desc); 1663 if (IS_ERR(regmap)) 1664 return PTR_ERR(regmap); 1665 1666 clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); 1667 clk_lucid_evo_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); 1668 clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); 1669 clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); 1670 clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); 1671 1672 return qcom_cc_really_probe(&pdev->dev, &cam_cc_sm4450_desc, regmap); 1673 } 1674 1675 static struct platform_driver cam_cc_sm4450_driver = { 1676 .probe = cam_cc_sm4450_probe, 1677 .driver = { 1678 .name = "camcc-sm4450", 1679 .of_match_table = cam_cc_sm4450_match_table, 1680 }, 1681 }; 1682 1683 module_platform_driver(cam_cc_sm4450_driver); 1684 1685 MODULE_DESCRIPTION("QTI CAMCC SM4450 Driver"); 1686 MODULE_LICENSE("GPL"); 1687