1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,camcc-sdm845.h> 13 14 #include "common.h" 15 #include "clk-alpha-pll.h" 16 #include "clk-branch.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "gdsc.h" 20 21 enum { 22 P_BI_TCXO, 23 P_CAM_CC_PLL0_OUT_EVEN, 24 P_CAM_CC_PLL1_OUT_EVEN, 25 P_CAM_CC_PLL2_OUT_EVEN, 26 P_CAM_CC_PLL3_OUT_EVEN, 27 }; 28 29 static struct clk_alpha_pll cam_cc_pll0 = { 30 .offset = 0x0, 31 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 32 .clkr = { 33 .hw.init = &(struct clk_init_data){ 34 .name = "cam_cc_pll0", 35 .parent_data = &(const struct clk_parent_data){ 36 .fw_name = "bi_tcxo", .name = "bi_tcxo", 37 }, 38 .num_parents = 1, 39 .ops = &clk_alpha_pll_fabia_ops, 40 }, 41 }, 42 }; 43 44 static const struct clk_div_table post_div_table_fabia_even[] = { 45 { 0x0, 1 }, 46 { 0x1, 2 }, 47 { } 48 }; 49 50 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { 51 .offset = 0x0, 52 .post_div_shift = 8, 53 .post_div_table = post_div_table_fabia_even, 54 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 55 .width = 4, 56 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 57 .clkr.hw.init = &(struct clk_init_data){ 58 .name = "cam_cc_pll0_out_even", 59 .parent_hws = (const struct clk_hw*[]){ 60 &cam_cc_pll0.clkr.hw, 61 }, 62 .num_parents = 1, 63 .ops = &clk_alpha_pll_postdiv_fabia_ops, 64 }, 65 }; 66 67 static struct clk_alpha_pll cam_cc_pll1 = { 68 .offset = 0x1000, 69 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 70 .clkr = { 71 .hw.init = &(struct clk_init_data){ 72 .name = "cam_cc_pll1", 73 .parent_data = &(const struct clk_parent_data){ 74 .fw_name = "bi_tcxo", .name = "bi_tcxo", 75 }, 76 .num_parents = 1, 77 .ops = &clk_alpha_pll_fabia_ops, 78 }, 79 }, 80 }; 81 82 static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { 83 .offset = 0x1000, 84 .post_div_shift = 8, 85 .post_div_table = post_div_table_fabia_even, 86 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 87 .width = 4, 88 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 89 .clkr.hw.init = &(struct clk_init_data){ 90 .name = "cam_cc_pll1_out_even", 91 .parent_hws = (const struct clk_hw*[]){ 92 &cam_cc_pll1.clkr.hw, 93 }, 94 .num_parents = 1, 95 .ops = &clk_alpha_pll_postdiv_fabia_ops, 96 }, 97 }; 98 99 static struct clk_alpha_pll cam_cc_pll2 = { 100 .offset = 0x2000, 101 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 102 .clkr = { 103 .hw.init = &(struct clk_init_data){ 104 .name = "cam_cc_pll2", 105 .parent_data = &(const struct clk_parent_data){ 106 .fw_name = "bi_tcxo", .name = "bi_tcxo", 107 }, 108 .num_parents = 1, 109 .ops = &clk_alpha_pll_fabia_ops, 110 }, 111 }, 112 }; 113 114 static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even = { 115 .offset = 0x2000, 116 .post_div_shift = 8, 117 .post_div_table = post_div_table_fabia_even, 118 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 119 .width = 4, 120 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 121 .clkr.hw.init = &(struct clk_init_data){ 122 .name = "cam_cc_pll2_out_even", 123 .parent_hws = (const struct clk_hw*[]){ 124 &cam_cc_pll2.clkr.hw, 125 }, 126 .num_parents = 1, 127 .ops = &clk_alpha_pll_postdiv_fabia_ops, 128 }, 129 }; 130 131 static struct clk_alpha_pll cam_cc_pll3 = { 132 .offset = 0x3000, 133 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 134 .clkr = { 135 .hw.init = &(struct clk_init_data){ 136 .name = "cam_cc_pll3", 137 .parent_data = &(const struct clk_parent_data){ 138 .fw_name = "bi_tcxo", .name = "bi_tcxo", 139 }, 140 .num_parents = 1, 141 .ops = &clk_alpha_pll_fabia_ops, 142 }, 143 }, 144 }; 145 146 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 147 .offset = 0x3000, 148 .post_div_shift = 8, 149 .post_div_table = post_div_table_fabia_even, 150 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 151 .width = 4, 152 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 153 .clkr.hw.init = &(struct clk_init_data){ 154 .name = "cam_cc_pll3_out_even", 155 .parent_hws = (const struct clk_hw*[]){ 156 &cam_cc_pll3.clkr.hw, 157 }, 158 .num_parents = 1, 159 .ops = &clk_alpha_pll_postdiv_fabia_ops, 160 }, 161 }; 162 163 static const struct parent_map cam_cc_parent_map_0[] = { 164 { P_BI_TCXO, 0 }, 165 { P_CAM_CC_PLL2_OUT_EVEN, 1 }, 166 { P_CAM_CC_PLL1_OUT_EVEN, 2 }, 167 { P_CAM_CC_PLL3_OUT_EVEN, 5 }, 168 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 169 }; 170 171 static const struct clk_parent_data cam_cc_parent_data_0[] = { 172 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 173 { .hw = &cam_cc_pll2_out_even.clkr.hw }, 174 { .hw = &cam_cc_pll1_out_even.clkr.hw }, 175 { .hw = &cam_cc_pll3_out_even.clkr.hw }, 176 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 177 }; 178 179 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { 180 F(19200000, P_BI_TCXO, 1, 0, 0), 181 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 182 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 183 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0), 184 F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 185 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 186 { } 187 }; 188 189 /* 190 * As per HW design, some of the CAMCC RCGs needs to 191 * move to XO clock during their clock disable so using 192 * clk_rcg2_shared_ops for such RCGs. This is required 193 * to power down the camera memories gracefully. 194 * Also, use CLK_SET_RATE_PARENT flag for the RCGs which 195 * have CAM_CC_PLL2_OUT_EVEN PLL as parent in frequency 196 * table and requires reconfiguration of the PLL frequency. 197 */ 198 static struct clk_rcg2 cam_cc_bps_clk_src = { 199 .cmd_rcgr = 0x600c, 200 .mnd_width = 0, 201 .hid_width = 5, 202 .parent_map = cam_cc_parent_map_0, 203 .freq_tbl = ftbl_cam_cc_bps_clk_src, 204 .clkr.hw.init = &(struct clk_init_data){ 205 .name = "cam_cc_bps_clk_src", 206 .parent_data = cam_cc_parent_data_0, 207 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 208 .flags = CLK_SET_RATE_PARENT, 209 .ops = &clk_rcg2_shared_ops, 210 }, 211 }; 212 213 static const struct freq_tbl ftbl_cam_cc_cci_clk_src[] = { 214 F(19200000, P_BI_TCXO, 1, 0, 0), 215 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 216 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0), 217 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 218 { } 219 }; 220 221 static struct clk_rcg2 cam_cc_cci_clk_src = { 222 .cmd_rcgr = 0xb0d8, 223 .mnd_width = 8, 224 .hid_width = 5, 225 .parent_map = cam_cc_parent_map_0, 226 .freq_tbl = ftbl_cam_cc_cci_clk_src, 227 .clkr.hw.init = &(struct clk_init_data){ 228 .name = "cam_cc_cci_clk_src", 229 .parent_data = cam_cc_parent_data_0, 230 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 231 .ops = &clk_rcg2_ops, 232 }, 233 }; 234 235 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 236 F(19200000, P_BI_TCXO, 1, 0, 0), 237 F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 238 { } 239 }; 240 241 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 242 .cmd_rcgr = 0x9060, 243 .mnd_width = 0, 244 .hid_width = 5, 245 .parent_map = cam_cc_parent_map_0, 246 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 247 .clkr.hw.init = &(struct clk_init_data){ 248 .name = "cam_cc_cphy_rx_clk_src", 249 .parent_data = cam_cc_parent_data_0, 250 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 251 .ops = &clk_rcg2_ops, 252 }, 253 }; 254 255 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 256 F(19200000, P_BI_TCXO, 1, 0, 0), 257 F(240000000, P_CAM_CC_PLL2_OUT_EVEN, 2, 0, 0), 258 F(269333333, P_CAM_CC_PLL1_OUT_EVEN, 3, 0, 0), 259 { } 260 }; 261 262 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 263 .cmd_rcgr = 0x5004, 264 .mnd_width = 0, 265 .hid_width = 5, 266 .parent_map = cam_cc_parent_map_0, 267 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 268 .clkr.hw.init = &(struct clk_init_data){ 269 .name = "cam_cc_csi0phytimer_clk_src", 270 .parent_data = cam_cc_parent_data_0, 271 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 272 .flags = CLK_SET_RATE_PARENT, 273 .ops = &clk_rcg2_ops, 274 }, 275 }; 276 277 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 278 .cmd_rcgr = 0x5028, 279 .mnd_width = 0, 280 .hid_width = 5, 281 .parent_map = cam_cc_parent_map_0, 282 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 283 .clkr.hw.init = &(struct clk_init_data){ 284 .name = "cam_cc_csi1phytimer_clk_src", 285 .parent_data = cam_cc_parent_data_0, 286 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 287 .flags = CLK_SET_RATE_PARENT, 288 .ops = &clk_rcg2_ops, 289 }, 290 }; 291 292 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 293 .cmd_rcgr = 0x504c, 294 .mnd_width = 0, 295 .hid_width = 5, 296 .parent_map = cam_cc_parent_map_0, 297 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 298 .clkr.hw.init = &(struct clk_init_data){ 299 .name = "cam_cc_csi2phytimer_clk_src", 300 .parent_data = cam_cc_parent_data_0, 301 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 302 .flags = CLK_SET_RATE_PARENT, 303 .ops = &clk_rcg2_ops, 304 }, 305 }; 306 307 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 308 .cmd_rcgr = 0x5070, 309 .mnd_width = 0, 310 .hid_width = 5, 311 .parent_map = cam_cc_parent_map_0, 312 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 313 .clkr.hw.init = &(struct clk_init_data){ 314 .name = "cam_cc_csi3phytimer_clk_src", 315 .parent_data = cam_cc_parent_data_0, 316 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 317 .flags = CLK_SET_RATE_PARENT, 318 .ops = &clk_rcg2_ops, 319 }, 320 }; 321 322 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 323 F(19200000, P_BI_TCXO, 1, 0, 0), 324 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0), 325 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 326 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 327 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 328 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), 329 { } 330 }; 331 332 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 333 .cmd_rcgr = 0x6038, 334 .mnd_width = 0, 335 .hid_width = 5, 336 .parent_map = cam_cc_parent_map_0, 337 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 338 .clkr.hw.init = &(struct clk_init_data){ 339 .name = "cam_cc_fast_ahb_clk_src", 340 .parent_data = cam_cc_parent_data_0, 341 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 342 .ops = &clk_rcg2_ops, 343 }, 344 }; 345 346 static const struct freq_tbl ftbl_cam_cc_fd_core_clk_src[] = { 347 F(19200000, P_BI_TCXO, 1, 0, 0), 348 F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 349 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), 350 F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0), 351 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 352 { } 353 }; 354 355 static struct clk_rcg2 cam_cc_fd_core_clk_src = { 356 .cmd_rcgr = 0xb0b0, 357 .mnd_width = 0, 358 .hid_width = 5, 359 .parent_map = cam_cc_parent_map_0, 360 .freq_tbl = ftbl_cam_cc_fd_core_clk_src, 361 .clkr.hw.init = &(struct clk_init_data){ 362 .name = "cam_cc_fd_core_clk_src", 363 .parent_data = cam_cc_parent_data_0, 364 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 365 .ops = &clk_rcg2_shared_ops, 366 }, 367 }; 368 369 static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 370 F(19200000, P_BI_TCXO, 1, 0, 0), 371 F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 372 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), 373 F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0), 374 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 375 { } 376 }; 377 378 static struct clk_rcg2 cam_cc_icp_clk_src = { 379 .cmd_rcgr = 0xb088, 380 .mnd_width = 0, 381 .hid_width = 5, 382 .parent_map = cam_cc_parent_map_0, 383 .freq_tbl = ftbl_cam_cc_icp_clk_src, 384 .clkr.hw.init = &(struct clk_init_data){ 385 .name = "cam_cc_icp_clk_src", 386 .parent_data = cam_cc_parent_data_0, 387 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 388 .ops = &clk_rcg2_shared_ops, 389 }, 390 }; 391 392 static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { 393 F(19200000, P_BI_TCXO, 1, 0, 0), 394 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 395 F(320000000, P_CAM_CC_PLL2_OUT_EVEN, 1.5, 0, 0), 396 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0), 397 F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 398 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 399 { } 400 }; 401 402 static struct clk_rcg2 cam_cc_ife_0_clk_src = { 403 .cmd_rcgr = 0x900c, 404 .mnd_width = 0, 405 .hid_width = 5, 406 .parent_map = cam_cc_parent_map_0, 407 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 408 .clkr.hw.init = &(struct clk_init_data){ 409 .name = "cam_cc_ife_0_clk_src", 410 .parent_data = cam_cc_parent_data_0, 411 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 412 .flags = CLK_SET_RATE_PARENT, 413 .ops = &clk_rcg2_shared_ops, 414 }, 415 }; 416 417 static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = { 418 F(19200000, P_BI_TCXO, 1, 0, 0), 419 F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0), 420 F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 421 F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0), 422 { } 423 }; 424 425 static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { 426 .cmd_rcgr = 0x9038, 427 .mnd_width = 0, 428 .hid_width = 5, 429 .parent_map = cam_cc_parent_map_0, 430 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 431 .clkr.hw.init = &(struct clk_init_data){ 432 .name = "cam_cc_ife_0_csid_clk_src", 433 .parent_data = cam_cc_parent_data_0, 434 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 435 .ops = &clk_rcg2_shared_ops, 436 }, 437 }; 438 439 static struct clk_rcg2 cam_cc_ife_1_clk_src = { 440 .cmd_rcgr = 0xa00c, 441 .mnd_width = 0, 442 .hid_width = 5, 443 .parent_map = cam_cc_parent_map_0, 444 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 445 .clkr.hw.init = &(struct clk_init_data){ 446 .name = "cam_cc_ife_1_clk_src", 447 .parent_data = cam_cc_parent_data_0, 448 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 449 .flags = CLK_SET_RATE_PARENT, 450 .ops = &clk_rcg2_shared_ops, 451 }, 452 }; 453 454 static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { 455 .cmd_rcgr = 0xa030, 456 .mnd_width = 0, 457 .hid_width = 5, 458 .parent_map = cam_cc_parent_map_0, 459 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 460 .clkr.hw.init = &(struct clk_init_data){ 461 .name = "cam_cc_ife_1_csid_clk_src", 462 .parent_data = cam_cc_parent_data_0, 463 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 464 .ops = &clk_rcg2_shared_ops, 465 }, 466 }; 467 468 static struct clk_rcg2 cam_cc_ife_lite_clk_src = { 469 .cmd_rcgr = 0xb004, 470 .mnd_width = 0, 471 .hid_width = 5, 472 .parent_map = cam_cc_parent_map_0, 473 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 474 .clkr.hw.init = &(struct clk_init_data){ 475 .name = "cam_cc_ife_lite_clk_src", 476 .parent_data = cam_cc_parent_data_0, 477 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 478 .flags = CLK_SET_RATE_PARENT, 479 .ops = &clk_rcg2_shared_ops, 480 }, 481 }; 482 483 static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { 484 .cmd_rcgr = 0xb024, 485 .mnd_width = 0, 486 .hid_width = 5, 487 .parent_map = cam_cc_parent_map_0, 488 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 489 .clkr.hw.init = &(struct clk_init_data){ 490 .name = "cam_cc_ife_lite_csid_clk_src", 491 .parent_data = cam_cc_parent_data_0, 492 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 493 .ops = &clk_rcg2_shared_ops, 494 }, 495 }; 496 497 static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = { 498 F(19200000, P_BI_TCXO, 1, 0, 0), 499 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 500 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), 501 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0), 502 F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 503 F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0), 504 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 505 { } 506 }; 507 508 static struct clk_rcg2 cam_cc_ipe_0_clk_src = { 509 .cmd_rcgr = 0x700c, 510 .mnd_width = 0, 511 .hid_width = 5, 512 .parent_map = cam_cc_parent_map_0, 513 .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, 514 .clkr.hw.init = &(struct clk_init_data){ 515 .name = "cam_cc_ipe_0_clk_src", 516 .parent_data = cam_cc_parent_data_0, 517 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 518 .flags = CLK_SET_RATE_PARENT, 519 .ops = &clk_rcg2_shared_ops, 520 }, 521 }; 522 523 static struct clk_rcg2 cam_cc_ipe_1_clk_src = { 524 .cmd_rcgr = 0x800c, 525 .mnd_width = 0, 526 .hid_width = 5, 527 .parent_map = cam_cc_parent_map_0, 528 .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, 529 .clkr.hw.init = &(struct clk_init_data){ 530 .name = "cam_cc_ipe_1_clk_src", 531 .parent_data = cam_cc_parent_data_0, 532 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 533 .flags = CLK_SET_RATE_PARENT, 534 .ops = &clk_rcg2_shared_ops, 535 }, 536 }; 537 538 static struct clk_rcg2 cam_cc_jpeg_clk_src = { 539 .cmd_rcgr = 0xb04c, 540 .mnd_width = 0, 541 .hid_width = 5, 542 .parent_map = cam_cc_parent_map_0, 543 .freq_tbl = ftbl_cam_cc_bps_clk_src, 544 .clkr.hw.init = &(struct clk_init_data){ 545 .name = "cam_cc_jpeg_clk_src", 546 .parent_data = cam_cc_parent_data_0, 547 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 548 .flags = CLK_SET_RATE_PARENT, 549 .ops = &clk_rcg2_shared_ops, 550 }, 551 }; 552 553 static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = { 554 F(19200000, P_BI_TCXO, 1, 0, 0), 555 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 556 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 557 F(269333333, P_CAM_CC_PLL1_OUT_EVEN, 3, 0, 0), 558 F(320000000, P_CAM_CC_PLL2_OUT_EVEN, 1.5, 0, 0), 559 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), 560 { } 561 }; 562 563 static struct clk_rcg2 cam_cc_lrme_clk_src = { 564 .cmd_rcgr = 0xb0f8, 565 .mnd_width = 0, 566 .hid_width = 5, 567 .parent_map = cam_cc_parent_map_0, 568 .freq_tbl = ftbl_cam_cc_lrme_clk_src, 569 .clkr.hw.init = &(struct clk_init_data){ 570 .name = "cam_cc_lrme_clk_src", 571 .parent_data = cam_cc_parent_data_0, 572 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 573 .flags = CLK_SET_RATE_PARENT, 574 .ops = &clk_rcg2_shared_ops, 575 }, 576 }; 577 578 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 579 F(19200000, P_BI_TCXO, 1, 0, 0), 580 F(24000000, P_CAM_CC_PLL2_OUT_EVEN, 10, 1, 2), 581 F(33333333, P_CAM_CC_PLL0_OUT_EVEN, 2, 1, 9), 582 F(34285714, P_CAM_CC_PLL2_OUT_EVEN, 14, 0, 0), 583 { } 584 }; 585 586 static struct clk_rcg2 cam_cc_mclk0_clk_src = { 587 .cmd_rcgr = 0x4004, 588 .mnd_width = 8, 589 .hid_width = 5, 590 .parent_map = cam_cc_parent_map_0, 591 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 592 .clkr.hw.init = &(struct clk_init_data){ 593 .name = "cam_cc_mclk0_clk_src", 594 .parent_data = cam_cc_parent_data_0, 595 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 596 .flags = CLK_SET_RATE_PARENT, 597 .ops = &clk_rcg2_ops, 598 }, 599 }; 600 601 static struct clk_rcg2 cam_cc_mclk1_clk_src = { 602 .cmd_rcgr = 0x4024, 603 .mnd_width = 8, 604 .hid_width = 5, 605 .parent_map = cam_cc_parent_map_0, 606 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 607 .clkr.hw.init = &(struct clk_init_data){ 608 .name = "cam_cc_mclk1_clk_src", 609 .parent_data = cam_cc_parent_data_0, 610 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 611 .flags = CLK_SET_RATE_PARENT, 612 .ops = &clk_rcg2_ops, 613 }, 614 }; 615 616 static struct clk_rcg2 cam_cc_mclk2_clk_src = { 617 .cmd_rcgr = 0x4044, 618 .mnd_width = 8, 619 .hid_width = 5, 620 .parent_map = cam_cc_parent_map_0, 621 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 622 .clkr.hw.init = &(struct clk_init_data){ 623 .name = "cam_cc_mclk2_clk_src", 624 .parent_data = cam_cc_parent_data_0, 625 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 626 .flags = CLK_SET_RATE_PARENT, 627 .ops = &clk_rcg2_ops, 628 }, 629 }; 630 631 static struct clk_rcg2 cam_cc_mclk3_clk_src = { 632 .cmd_rcgr = 0x4064, 633 .mnd_width = 8, 634 .hid_width = 5, 635 .parent_map = cam_cc_parent_map_0, 636 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 637 .clkr.hw.init = &(struct clk_init_data){ 638 .name = "cam_cc_mclk3_clk_src", 639 .parent_data = cam_cc_parent_data_0, 640 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 641 .flags = CLK_SET_RATE_PARENT, 642 .ops = &clk_rcg2_ops, 643 }, 644 }; 645 646 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 647 F(19200000, P_BI_TCXO, 1, 0, 0), 648 F(60000000, P_CAM_CC_PLL0_OUT_EVEN, 10, 0, 0), 649 F(66666667, P_CAM_CC_PLL0_OUT_EVEN, 9, 0, 0), 650 F(73846154, P_CAM_CC_PLL2_OUT_EVEN, 6.5, 0, 0), 651 F(80000000, P_CAM_CC_PLL2_OUT_EVEN, 6, 0, 0), 652 { } 653 }; 654 655 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 656 .cmd_rcgr = 0x6054, 657 .mnd_width = 0, 658 .hid_width = 5, 659 .parent_map = cam_cc_parent_map_0, 660 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 661 .clkr.hw.init = &(struct clk_init_data){ 662 .name = "cam_cc_slow_ahb_clk_src", 663 .parent_data = cam_cc_parent_data_0, 664 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 665 .flags = CLK_SET_RATE_PARENT, 666 .ops = &clk_rcg2_ops, 667 }, 668 }; 669 670 static struct clk_branch cam_cc_bps_ahb_clk = { 671 .halt_reg = 0x606c, 672 .halt_check = BRANCH_HALT, 673 .clkr = { 674 .enable_reg = 0x606c, 675 .enable_mask = BIT(0), 676 .hw.init = &(struct clk_init_data){ 677 .name = "cam_cc_bps_ahb_clk", 678 .parent_hws = (const struct clk_hw*[]){ 679 &cam_cc_slow_ahb_clk_src.clkr.hw, 680 }, 681 .num_parents = 1, 682 .flags = CLK_SET_RATE_PARENT, 683 .ops = &clk_branch2_ops, 684 }, 685 }, 686 }; 687 688 static struct clk_branch cam_cc_bps_areg_clk = { 689 .halt_reg = 0x6050, 690 .halt_check = BRANCH_HALT, 691 .clkr = { 692 .enable_reg = 0x6050, 693 .enable_mask = BIT(0), 694 .hw.init = &(struct clk_init_data){ 695 .name = "cam_cc_bps_areg_clk", 696 .parent_hws = (const struct clk_hw*[]){ 697 &cam_cc_fast_ahb_clk_src.clkr.hw, 698 }, 699 .num_parents = 1, 700 .flags = CLK_SET_RATE_PARENT, 701 .ops = &clk_branch2_ops, 702 }, 703 }, 704 }; 705 706 static struct clk_branch cam_cc_bps_axi_clk = { 707 .halt_reg = 0x6034, 708 .halt_check = BRANCH_HALT, 709 .clkr = { 710 .enable_reg = 0x6034, 711 .enable_mask = BIT(0), 712 .hw.init = &(struct clk_init_data){ 713 .name = "cam_cc_bps_axi_clk", 714 .ops = &clk_branch2_ops, 715 }, 716 }, 717 }; 718 719 static struct clk_branch cam_cc_bps_clk = { 720 .halt_reg = 0x6024, 721 .halt_check = BRANCH_HALT, 722 .clkr = { 723 .enable_reg = 0x6024, 724 .enable_mask = BIT(0), 725 .hw.init = &(struct clk_init_data){ 726 .name = "cam_cc_bps_clk", 727 .parent_hws = (const struct clk_hw*[]){ 728 &cam_cc_bps_clk_src.clkr.hw, 729 }, 730 .num_parents = 1, 731 .flags = CLK_SET_RATE_PARENT, 732 .ops = &clk_branch2_ops, 733 }, 734 }, 735 }; 736 737 static struct clk_branch cam_cc_camnoc_atb_clk = { 738 .halt_reg = 0xb12c, 739 .halt_check = BRANCH_HALT, 740 .clkr = { 741 .enable_reg = 0xb12c, 742 .enable_mask = BIT(0), 743 .hw.init = &(struct clk_init_data){ 744 .name = "cam_cc_camnoc_atb_clk", 745 .ops = &clk_branch2_ops, 746 }, 747 }, 748 }; 749 750 static struct clk_branch cam_cc_camnoc_axi_clk = { 751 .halt_reg = 0xb124, 752 .halt_check = BRANCH_HALT, 753 .clkr = { 754 .enable_reg = 0xb124, 755 .enable_mask = BIT(0), 756 .hw.init = &(struct clk_init_data){ 757 .name = "cam_cc_camnoc_axi_clk", 758 .ops = &clk_branch2_ops, 759 }, 760 }, 761 }; 762 763 static struct clk_branch cam_cc_cci_clk = { 764 .halt_reg = 0xb0f0, 765 .halt_check = BRANCH_HALT, 766 .clkr = { 767 .enable_reg = 0xb0f0, 768 .enable_mask = BIT(0), 769 .hw.init = &(struct clk_init_data){ 770 .name = "cam_cc_cci_clk", 771 .parent_hws = (const struct clk_hw*[]){ 772 &cam_cc_cci_clk_src.clkr.hw, 773 }, 774 .num_parents = 1, 775 .flags = CLK_SET_RATE_PARENT, 776 .ops = &clk_branch2_ops, 777 }, 778 }, 779 }; 780 781 static struct clk_branch cam_cc_cpas_ahb_clk = { 782 .halt_reg = 0xb11c, 783 .halt_check = BRANCH_HALT, 784 .clkr = { 785 .enable_reg = 0xb11c, 786 .enable_mask = BIT(0), 787 .hw.init = &(struct clk_init_data){ 788 .name = "cam_cc_cpas_ahb_clk", 789 .parent_hws = (const struct clk_hw*[]){ 790 &cam_cc_slow_ahb_clk_src.clkr.hw, 791 }, 792 .num_parents = 1, 793 .flags = CLK_SET_RATE_PARENT, 794 .ops = &clk_branch2_ops, 795 }, 796 }, 797 }; 798 799 static struct clk_branch cam_cc_csi0phytimer_clk = { 800 .halt_reg = 0x501c, 801 .halt_check = BRANCH_HALT, 802 .clkr = { 803 .enable_reg = 0x501c, 804 .enable_mask = BIT(0), 805 .hw.init = &(struct clk_init_data){ 806 .name = "cam_cc_csi0phytimer_clk", 807 .parent_hws = (const struct clk_hw*[]){ 808 &cam_cc_csi0phytimer_clk_src.clkr.hw, 809 }, 810 .num_parents = 1, 811 .flags = CLK_SET_RATE_PARENT, 812 .ops = &clk_branch2_ops, 813 }, 814 }, 815 }; 816 817 static struct clk_branch cam_cc_csi1phytimer_clk = { 818 .halt_reg = 0x5040, 819 .halt_check = BRANCH_HALT, 820 .clkr = { 821 .enable_reg = 0x5040, 822 .enable_mask = BIT(0), 823 .hw.init = &(struct clk_init_data){ 824 .name = "cam_cc_csi1phytimer_clk", 825 .parent_hws = (const struct clk_hw*[]){ 826 &cam_cc_csi1phytimer_clk_src.clkr.hw, 827 }, 828 .num_parents = 1, 829 .flags = CLK_SET_RATE_PARENT, 830 .ops = &clk_branch2_ops, 831 }, 832 }, 833 }; 834 835 static struct clk_branch cam_cc_csi2phytimer_clk = { 836 .halt_reg = 0x5064, 837 .halt_check = BRANCH_HALT, 838 .clkr = { 839 .enable_reg = 0x5064, 840 .enable_mask = BIT(0), 841 .hw.init = &(struct clk_init_data){ 842 .name = "cam_cc_csi2phytimer_clk", 843 .parent_hws = (const struct clk_hw*[]){ 844 &cam_cc_csi2phytimer_clk_src.clkr.hw, 845 }, 846 .num_parents = 1, 847 .flags = CLK_SET_RATE_PARENT, 848 .ops = &clk_branch2_ops, 849 }, 850 }, 851 }; 852 853 static struct clk_branch cam_cc_csi3phytimer_clk = { 854 .halt_reg = 0x5088, 855 .halt_check = BRANCH_HALT, 856 .clkr = { 857 .enable_reg = 0x5088, 858 .enable_mask = BIT(0), 859 .hw.init = &(struct clk_init_data){ 860 .name = "cam_cc_csi3phytimer_clk", 861 .parent_hws = (const struct clk_hw*[]){ 862 &cam_cc_csi3phytimer_clk_src.clkr.hw, 863 }, 864 .num_parents = 1, 865 .flags = CLK_SET_RATE_PARENT, 866 .ops = &clk_branch2_ops, 867 }, 868 }, 869 }; 870 871 static struct clk_branch cam_cc_csiphy0_clk = { 872 .halt_reg = 0x5020, 873 .halt_check = BRANCH_HALT, 874 .clkr = { 875 .enable_reg = 0x5020, 876 .enable_mask = BIT(0), 877 .hw.init = &(struct clk_init_data){ 878 .name = "cam_cc_csiphy0_clk", 879 .parent_hws = (const struct clk_hw*[]){ 880 &cam_cc_cphy_rx_clk_src.clkr.hw, 881 }, 882 .num_parents = 1, 883 .flags = CLK_SET_RATE_PARENT, 884 .ops = &clk_branch2_ops, 885 }, 886 }, 887 }; 888 889 static struct clk_branch cam_cc_csiphy1_clk = { 890 .halt_reg = 0x5044, 891 .halt_check = BRANCH_HALT, 892 .clkr = { 893 .enable_reg = 0x5044, 894 .enable_mask = BIT(0), 895 .hw.init = &(struct clk_init_data){ 896 .name = "cam_cc_csiphy1_clk", 897 .parent_hws = (const struct clk_hw*[]){ 898 &cam_cc_cphy_rx_clk_src.clkr.hw, 899 }, 900 .num_parents = 1, 901 .flags = CLK_SET_RATE_PARENT, 902 .ops = &clk_branch2_ops, 903 }, 904 }, 905 }; 906 907 static struct clk_branch cam_cc_csiphy2_clk = { 908 .halt_reg = 0x5068, 909 .halt_check = BRANCH_HALT, 910 .clkr = { 911 .enable_reg = 0x5068, 912 .enable_mask = BIT(0), 913 .hw.init = &(struct clk_init_data){ 914 .name = "cam_cc_csiphy2_clk", 915 .parent_hws = (const struct clk_hw*[]){ 916 &cam_cc_cphy_rx_clk_src.clkr.hw, 917 }, 918 .num_parents = 1, 919 .flags = CLK_SET_RATE_PARENT, 920 .ops = &clk_branch2_ops, 921 }, 922 }, 923 }; 924 925 static struct clk_branch cam_cc_csiphy3_clk = { 926 .halt_reg = 0x508c, 927 .halt_check = BRANCH_HALT, 928 .clkr = { 929 .enable_reg = 0x508c, 930 .enable_mask = BIT(0), 931 .hw.init = &(struct clk_init_data){ 932 .name = "cam_cc_csiphy3_clk", 933 .parent_hws = (const struct clk_hw*[]){ 934 &cam_cc_cphy_rx_clk_src.clkr.hw, 935 }, 936 .num_parents = 1, 937 .flags = CLK_SET_RATE_PARENT, 938 .ops = &clk_branch2_ops, 939 }, 940 }, 941 }; 942 943 static struct clk_branch cam_cc_fd_core_clk = { 944 .halt_reg = 0xb0c8, 945 .halt_check = BRANCH_HALT, 946 .clkr = { 947 .enable_reg = 0xb0c8, 948 .enable_mask = BIT(0), 949 .hw.init = &(struct clk_init_data){ 950 .name = "cam_cc_fd_core_clk", 951 .parent_hws = (const struct clk_hw*[]){ 952 &cam_cc_fd_core_clk_src.clkr.hw, 953 }, 954 .num_parents = 1, 955 .flags = CLK_SET_RATE_PARENT, 956 .ops = &clk_branch2_ops, 957 }, 958 }, 959 }; 960 961 static struct clk_branch cam_cc_fd_core_uar_clk = { 962 .halt_reg = 0xb0d0, 963 .halt_check = BRANCH_HALT, 964 .clkr = { 965 .enable_reg = 0xb0d0, 966 .enable_mask = BIT(0), 967 .hw.init = &(struct clk_init_data){ 968 .name = "cam_cc_fd_core_uar_clk", 969 .parent_hws = (const struct clk_hw*[]){ 970 &cam_cc_fd_core_clk_src.clkr.hw, 971 }, 972 .num_parents = 1, 973 .ops = &clk_branch2_ops, 974 }, 975 }, 976 }; 977 978 static struct clk_branch cam_cc_icp_apb_clk = { 979 .halt_reg = 0xb084, 980 .halt_check = BRANCH_HALT, 981 .clkr = { 982 .enable_reg = 0xb084, 983 .enable_mask = BIT(0), 984 .hw.init = &(struct clk_init_data){ 985 .name = "cam_cc_icp_apb_clk", 986 .ops = &clk_branch2_ops, 987 }, 988 }, 989 }; 990 991 static struct clk_branch cam_cc_icp_atb_clk = { 992 .halt_reg = 0xb078, 993 .halt_check = BRANCH_HALT, 994 .clkr = { 995 .enable_reg = 0xb078, 996 .enable_mask = BIT(0), 997 .hw.init = &(struct clk_init_data){ 998 .name = "cam_cc_icp_atb_clk", 999 .ops = &clk_branch2_ops, 1000 }, 1001 }, 1002 }; 1003 1004 static struct clk_branch cam_cc_icp_clk = { 1005 .halt_reg = 0xb0a0, 1006 .halt_check = BRANCH_HALT, 1007 .clkr = { 1008 .enable_reg = 0xb0a0, 1009 .enable_mask = BIT(0), 1010 .hw.init = &(struct clk_init_data){ 1011 .name = "cam_cc_icp_clk", 1012 .parent_hws = (const struct clk_hw*[]){ 1013 &cam_cc_icp_clk_src.clkr.hw, 1014 }, 1015 .num_parents = 1, 1016 .flags = CLK_SET_RATE_PARENT, 1017 .ops = &clk_branch2_ops, 1018 }, 1019 }, 1020 }; 1021 1022 static struct clk_branch cam_cc_icp_cti_clk = { 1023 .halt_reg = 0xb07c, 1024 .halt_check = BRANCH_HALT, 1025 .clkr = { 1026 .enable_reg = 0xb07c, 1027 .enable_mask = BIT(0), 1028 .hw.init = &(struct clk_init_data){ 1029 .name = "cam_cc_icp_cti_clk", 1030 .ops = &clk_branch2_ops, 1031 }, 1032 }, 1033 }; 1034 1035 static struct clk_branch cam_cc_icp_ts_clk = { 1036 .halt_reg = 0xb080, 1037 .halt_check = BRANCH_HALT, 1038 .clkr = { 1039 .enable_reg = 0xb080, 1040 .enable_mask = BIT(0), 1041 .hw.init = &(struct clk_init_data){ 1042 .name = "cam_cc_icp_ts_clk", 1043 .ops = &clk_branch2_ops, 1044 }, 1045 }, 1046 }; 1047 1048 static struct clk_branch cam_cc_ife_0_axi_clk = { 1049 .halt_reg = 0x907c, 1050 .halt_check = BRANCH_HALT, 1051 .clkr = { 1052 .enable_reg = 0x907c, 1053 .enable_mask = BIT(0), 1054 .hw.init = &(struct clk_init_data){ 1055 .name = "cam_cc_ife_0_axi_clk", 1056 .ops = &clk_branch2_ops, 1057 }, 1058 }, 1059 }; 1060 1061 static struct clk_branch cam_cc_ife_0_clk = { 1062 .halt_reg = 0x9024, 1063 .halt_check = BRANCH_HALT, 1064 .clkr = { 1065 .enable_reg = 0x9024, 1066 .enable_mask = BIT(0), 1067 .hw.init = &(struct clk_init_data){ 1068 .name = "cam_cc_ife_0_clk", 1069 .parent_hws = (const struct clk_hw*[]){ 1070 &cam_cc_ife_0_clk_src.clkr.hw, 1071 }, 1072 .num_parents = 1, 1073 .flags = CLK_SET_RATE_PARENT, 1074 .ops = &clk_branch2_ops, 1075 }, 1076 }, 1077 }; 1078 1079 static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { 1080 .halt_reg = 0x9078, 1081 .halt_check = BRANCH_HALT, 1082 .clkr = { 1083 .enable_reg = 0x9078, 1084 .enable_mask = BIT(0), 1085 .hw.init = &(struct clk_init_data){ 1086 .name = "cam_cc_ife_0_cphy_rx_clk", 1087 .parent_hws = (const struct clk_hw*[]){ 1088 &cam_cc_cphy_rx_clk_src.clkr.hw, 1089 }, 1090 .num_parents = 1, 1091 .flags = CLK_SET_RATE_PARENT, 1092 .ops = &clk_branch2_ops, 1093 }, 1094 }, 1095 }; 1096 1097 static struct clk_branch cam_cc_ife_0_csid_clk = { 1098 .halt_reg = 0x9050, 1099 .halt_check = BRANCH_HALT, 1100 .clkr = { 1101 .enable_reg = 0x9050, 1102 .enable_mask = BIT(0), 1103 .hw.init = &(struct clk_init_data){ 1104 .name = "cam_cc_ife_0_csid_clk", 1105 .parent_hws = (const struct clk_hw*[]){ 1106 &cam_cc_ife_0_csid_clk_src.clkr.hw, 1107 }, 1108 .num_parents = 1, 1109 .flags = CLK_SET_RATE_PARENT, 1110 .ops = &clk_branch2_ops, 1111 }, 1112 }, 1113 }; 1114 1115 static struct clk_branch cam_cc_ife_0_dsp_clk = { 1116 .halt_reg = 0x9034, 1117 .halt_check = BRANCH_HALT, 1118 .clkr = { 1119 .enable_reg = 0x9034, 1120 .enable_mask = BIT(0), 1121 .hw.init = &(struct clk_init_data){ 1122 .name = "cam_cc_ife_0_dsp_clk", 1123 .parent_hws = (const struct clk_hw*[]){ 1124 &cam_cc_ife_0_clk_src.clkr.hw, 1125 }, 1126 .num_parents = 1, 1127 .ops = &clk_branch2_ops, 1128 }, 1129 }, 1130 }; 1131 1132 static struct clk_branch cam_cc_ife_1_axi_clk = { 1133 .halt_reg = 0xa054, 1134 .halt_check = BRANCH_HALT, 1135 .clkr = { 1136 .enable_reg = 0xa054, 1137 .enable_mask = BIT(0), 1138 .hw.init = &(struct clk_init_data){ 1139 .name = "cam_cc_ife_1_axi_clk", 1140 .ops = &clk_branch2_ops, 1141 }, 1142 }, 1143 }; 1144 1145 static struct clk_branch cam_cc_ife_1_clk = { 1146 .halt_reg = 0xa024, 1147 .halt_check = BRANCH_HALT, 1148 .clkr = { 1149 .enable_reg = 0xa024, 1150 .enable_mask = BIT(0), 1151 .hw.init = &(struct clk_init_data){ 1152 .name = "cam_cc_ife_1_clk", 1153 .parent_hws = (const struct clk_hw*[]){ 1154 &cam_cc_ife_1_clk_src.clkr.hw, 1155 }, 1156 .num_parents = 1, 1157 .flags = CLK_SET_RATE_PARENT, 1158 .ops = &clk_branch2_ops, 1159 }, 1160 }, 1161 }; 1162 1163 static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { 1164 .halt_reg = 0xa050, 1165 .halt_check = BRANCH_HALT, 1166 .clkr = { 1167 .enable_reg = 0xa050, 1168 .enable_mask = BIT(0), 1169 .hw.init = &(struct clk_init_data){ 1170 .name = "cam_cc_ife_1_cphy_rx_clk", 1171 .parent_hws = (const struct clk_hw*[]){ 1172 &cam_cc_cphy_rx_clk_src.clkr.hw, 1173 }, 1174 .num_parents = 1, 1175 .flags = CLK_SET_RATE_PARENT, 1176 .ops = &clk_branch2_ops, 1177 }, 1178 }, 1179 }; 1180 1181 static struct clk_branch cam_cc_ife_1_csid_clk = { 1182 .halt_reg = 0xa048, 1183 .halt_check = BRANCH_HALT, 1184 .clkr = { 1185 .enable_reg = 0xa048, 1186 .enable_mask = BIT(0), 1187 .hw.init = &(struct clk_init_data){ 1188 .name = "cam_cc_ife_1_csid_clk", 1189 .parent_hws = (const struct clk_hw*[]){ 1190 &cam_cc_ife_1_csid_clk_src.clkr.hw, 1191 }, 1192 .num_parents = 1, 1193 .flags = CLK_SET_RATE_PARENT, 1194 .ops = &clk_branch2_ops, 1195 }, 1196 }, 1197 }; 1198 1199 static struct clk_branch cam_cc_ife_1_dsp_clk = { 1200 .halt_reg = 0xa02c, 1201 .halt_check = BRANCH_HALT, 1202 .clkr = { 1203 .enable_reg = 0xa02c, 1204 .enable_mask = BIT(0), 1205 .hw.init = &(struct clk_init_data){ 1206 .name = "cam_cc_ife_1_dsp_clk", 1207 .parent_hws = (const struct clk_hw*[]){ 1208 &cam_cc_ife_1_clk_src.clkr.hw, 1209 }, 1210 .num_parents = 1, 1211 .ops = &clk_branch2_ops, 1212 }, 1213 }, 1214 }; 1215 1216 static struct clk_branch cam_cc_ife_lite_clk = { 1217 .halt_reg = 0xb01c, 1218 .halt_check = BRANCH_HALT, 1219 .clkr = { 1220 .enable_reg = 0xb01c, 1221 .enable_mask = BIT(0), 1222 .hw.init = &(struct clk_init_data){ 1223 .name = "cam_cc_ife_lite_clk", 1224 .parent_hws = (const struct clk_hw*[]){ 1225 &cam_cc_ife_lite_clk_src.clkr.hw, 1226 }, 1227 .num_parents = 1, 1228 .flags = CLK_SET_RATE_PARENT, 1229 .ops = &clk_branch2_ops, 1230 }, 1231 }, 1232 }; 1233 1234 static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { 1235 .halt_reg = 0xb044, 1236 .halt_check = BRANCH_HALT, 1237 .clkr = { 1238 .enable_reg = 0xb044, 1239 .enable_mask = BIT(0), 1240 .hw.init = &(struct clk_init_data){ 1241 .name = "cam_cc_ife_lite_cphy_rx_clk", 1242 .parent_hws = (const struct clk_hw*[]){ 1243 &cam_cc_cphy_rx_clk_src.clkr.hw, 1244 }, 1245 .num_parents = 1, 1246 .flags = CLK_SET_RATE_PARENT, 1247 .ops = &clk_branch2_ops, 1248 }, 1249 }, 1250 }; 1251 1252 static struct clk_branch cam_cc_ife_lite_csid_clk = { 1253 .halt_reg = 0xb03c, 1254 .halt_check = BRANCH_HALT, 1255 .clkr = { 1256 .enable_reg = 0xb03c, 1257 .enable_mask = BIT(0), 1258 .hw.init = &(struct clk_init_data){ 1259 .name = "cam_cc_ife_lite_csid_clk", 1260 .parent_hws = (const struct clk_hw*[]){ 1261 &cam_cc_ife_lite_csid_clk_src.clkr.hw, 1262 }, 1263 .num_parents = 1, 1264 .flags = CLK_SET_RATE_PARENT, 1265 .ops = &clk_branch2_ops, 1266 }, 1267 }, 1268 }; 1269 1270 static struct clk_branch cam_cc_ipe_0_ahb_clk = { 1271 .halt_reg = 0x703c, 1272 .halt_check = BRANCH_HALT, 1273 .clkr = { 1274 .enable_reg = 0x703c, 1275 .enable_mask = BIT(0), 1276 .hw.init = &(struct clk_init_data){ 1277 .name = "cam_cc_ipe_0_ahb_clk", 1278 .parent_hws = (const struct clk_hw*[]){ 1279 &cam_cc_slow_ahb_clk_src.clkr.hw, 1280 }, 1281 .num_parents = 1, 1282 .flags = CLK_SET_RATE_PARENT, 1283 .ops = &clk_branch2_ops, 1284 }, 1285 }, 1286 }; 1287 1288 static struct clk_branch cam_cc_ipe_0_areg_clk = { 1289 .halt_reg = 0x7038, 1290 .halt_check = BRANCH_HALT, 1291 .clkr = { 1292 .enable_reg = 0x7038, 1293 .enable_mask = BIT(0), 1294 .hw.init = &(struct clk_init_data){ 1295 .name = "cam_cc_ipe_0_areg_clk", 1296 .parent_hws = (const struct clk_hw*[]){ 1297 &cam_cc_fast_ahb_clk_src.clkr.hw, 1298 }, 1299 .num_parents = 1, 1300 .flags = CLK_SET_RATE_PARENT, 1301 .ops = &clk_branch2_ops, 1302 }, 1303 }, 1304 }; 1305 1306 static struct clk_branch cam_cc_ipe_0_axi_clk = { 1307 .halt_reg = 0x7034, 1308 .halt_check = BRANCH_HALT, 1309 .clkr = { 1310 .enable_reg = 0x7034, 1311 .enable_mask = BIT(0), 1312 .hw.init = &(struct clk_init_data){ 1313 .name = "cam_cc_ipe_0_axi_clk", 1314 .ops = &clk_branch2_ops, 1315 }, 1316 }, 1317 }; 1318 1319 static struct clk_branch cam_cc_ipe_0_clk = { 1320 .halt_reg = 0x7024, 1321 .halt_check = BRANCH_HALT, 1322 .clkr = { 1323 .enable_reg = 0x7024, 1324 .enable_mask = BIT(0), 1325 .hw.init = &(struct clk_init_data){ 1326 .name = "cam_cc_ipe_0_clk", 1327 .parent_hws = (const struct clk_hw*[]){ 1328 &cam_cc_ipe_0_clk_src.clkr.hw, 1329 }, 1330 .num_parents = 1, 1331 .flags = CLK_SET_RATE_PARENT, 1332 .ops = &clk_branch2_ops, 1333 }, 1334 }, 1335 }; 1336 1337 static struct clk_branch cam_cc_ipe_1_ahb_clk = { 1338 .halt_reg = 0x803c, 1339 .halt_check = BRANCH_HALT, 1340 .clkr = { 1341 .enable_reg = 0x803c, 1342 .enable_mask = BIT(0), 1343 .hw.init = &(struct clk_init_data){ 1344 .name = "cam_cc_ipe_1_ahb_clk", 1345 .parent_hws = (const struct clk_hw*[]){ 1346 &cam_cc_slow_ahb_clk_src.clkr.hw, 1347 }, 1348 .num_parents = 1, 1349 .flags = CLK_SET_RATE_PARENT, 1350 .ops = &clk_branch2_ops, 1351 }, 1352 }, 1353 }; 1354 1355 static struct clk_branch cam_cc_ipe_1_areg_clk = { 1356 .halt_reg = 0x8038, 1357 .halt_check = BRANCH_HALT, 1358 .clkr = { 1359 .enable_reg = 0x8038, 1360 .enable_mask = BIT(0), 1361 .hw.init = &(struct clk_init_data){ 1362 .name = "cam_cc_ipe_1_areg_clk", 1363 .parent_hws = (const struct clk_hw*[]){ 1364 &cam_cc_fast_ahb_clk_src.clkr.hw, 1365 }, 1366 .num_parents = 1, 1367 .flags = CLK_SET_RATE_PARENT, 1368 .ops = &clk_branch2_ops, 1369 }, 1370 }, 1371 }; 1372 1373 static struct clk_branch cam_cc_ipe_1_axi_clk = { 1374 .halt_reg = 0x8034, 1375 .halt_check = BRANCH_HALT, 1376 .clkr = { 1377 .enable_reg = 0x8034, 1378 .enable_mask = BIT(0), 1379 .hw.init = &(struct clk_init_data){ 1380 .name = "cam_cc_ipe_1_axi_clk", 1381 .ops = &clk_branch2_ops, 1382 }, 1383 }, 1384 }; 1385 1386 static struct clk_branch cam_cc_ipe_1_clk = { 1387 .halt_reg = 0x8024, 1388 .halt_check = BRANCH_HALT, 1389 .clkr = { 1390 .enable_reg = 0x8024, 1391 .enable_mask = BIT(0), 1392 .hw.init = &(struct clk_init_data){ 1393 .name = "cam_cc_ipe_1_clk", 1394 .parent_hws = (const struct clk_hw*[]){ 1395 &cam_cc_ipe_1_clk_src.clkr.hw, 1396 }, 1397 .num_parents = 1, 1398 .flags = CLK_SET_RATE_PARENT, 1399 .ops = &clk_branch2_ops, 1400 }, 1401 }, 1402 }; 1403 1404 static struct clk_branch cam_cc_jpeg_clk = { 1405 .halt_reg = 0xb064, 1406 .halt_check = BRANCH_HALT, 1407 .clkr = { 1408 .enable_reg = 0xb064, 1409 .enable_mask = BIT(0), 1410 .hw.init = &(struct clk_init_data){ 1411 .name = "cam_cc_jpeg_clk", 1412 .parent_hws = (const struct clk_hw*[]){ 1413 &cam_cc_jpeg_clk_src.clkr.hw, 1414 }, 1415 .num_parents = 1, 1416 .flags = CLK_SET_RATE_PARENT, 1417 .ops = &clk_branch2_ops, 1418 }, 1419 }, 1420 }; 1421 1422 static struct clk_branch cam_cc_lrme_clk = { 1423 .halt_reg = 0xb110, 1424 .halt_check = BRANCH_HALT, 1425 .clkr = { 1426 .enable_reg = 0xb110, 1427 .enable_mask = BIT(0), 1428 .hw.init = &(struct clk_init_data){ 1429 .name = "cam_cc_lrme_clk", 1430 .parent_hws = (const struct clk_hw*[]){ 1431 &cam_cc_lrme_clk_src.clkr.hw, 1432 }, 1433 .num_parents = 1, 1434 .flags = CLK_SET_RATE_PARENT, 1435 .ops = &clk_branch2_ops, 1436 }, 1437 }, 1438 }; 1439 1440 static struct clk_branch cam_cc_mclk0_clk = { 1441 .halt_reg = 0x401c, 1442 .halt_check = BRANCH_HALT, 1443 .clkr = { 1444 .enable_reg = 0x401c, 1445 .enable_mask = BIT(0), 1446 .hw.init = &(struct clk_init_data){ 1447 .name = "cam_cc_mclk0_clk", 1448 .parent_hws = (const struct clk_hw*[]){ 1449 &cam_cc_mclk0_clk_src.clkr.hw, 1450 }, 1451 .num_parents = 1, 1452 .flags = CLK_SET_RATE_PARENT, 1453 .ops = &clk_branch2_ops, 1454 }, 1455 }, 1456 }; 1457 1458 static struct clk_branch cam_cc_mclk1_clk = { 1459 .halt_reg = 0x403c, 1460 .halt_check = BRANCH_HALT, 1461 .clkr = { 1462 .enable_reg = 0x403c, 1463 .enable_mask = BIT(0), 1464 .hw.init = &(struct clk_init_data){ 1465 .name = "cam_cc_mclk1_clk", 1466 .parent_hws = (const struct clk_hw*[]){ 1467 &cam_cc_mclk1_clk_src.clkr.hw, 1468 }, 1469 .num_parents = 1, 1470 .flags = CLK_SET_RATE_PARENT, 1471 .ops = &clk_branch2_ops, 1472 }, 1473 }, 1474 }; 1475 1476 static struct clk_branch cam_cc_mclk2_clk = { 1477 .halt_reg = 0x405c, 1478 .halt_check = BRANCH_HALT, 1479 .clkr = { 1480 .enable_reg = 0x405c, 1481 .enable_mask = BIT(0), 1482 .hw.init = &(struct clk_init_data){ 1483 .name = "cam_cc_mclk2_clk", 1484 .parent_hws = (const struct clk_hw*[]){ 1485 &cam_cc_mclk2_clk_src.clkr.hw, 1486 }, 1487 .num_parents = 1, 1488 .flags = CLK_SET_RATE_PARENT, 1489 .ops = &clk_branch2_ops, 1490 }, 1491 }, 1492 }; 1493 1494 static struct clk_branch cam_cc_mclk3_clk = { 1495 .halt_reg = 0x407c, 1496 .halt_check = BRANCH_HALT, 1497 .clkr = { 1498 .enable_reg = 0x407c, 1499 .enable_mask = BIT(0), 1500 .hw.init = &(struct clk_init_data){ 1501 .name = "cam_cc_mclk3_clk", 1502 .parent_hws = (const struct clk_hw*[]){ 1503 &cam_cc_mclk3_clk_src.clkr.hw, 1504 }, 1505 .num_parents = 1, 1506 .flags = CLK_SET_RATE_PARENT, 1507 .ops = &clk_branch2_ops, 1508 }, 1509 }, 1510 }; 1511 1512 static struct clk_branch cam_cc_soc_ahb_clk = { 1513 .halt_reg = 0xb13c, 1514 .halt_check = BRANCH_HALT, 1515 .clkr = { 1516 .enable_reg = 0xb13c, 1517 .enable_mask = BIT(0), 1518 .hw.init = &(struct clk_init_data){ 1519 .name = "cam_cc_soc_ahb_clk", 1520 .ops = &clk_branch2_ops, 1521 }, 1522 }, 1523 }; 1524 1525 static struct clk_branch cam_cc_sys_tmr_clk = { 1526 .halt_reg = 0xb0a8, 1527 .halt_check = BRANCH_HALT, 1528 .clkr = { 1529 .enable_reg = 0xb0a8, 1530 .enable_mask = BIT(0), 1531 .hw.init = &(struct clk_init_data){ 1532 .name = "cam_cc_sys_tmr_clk", 1533 .ops = &clk_branch2_ops, 1534 }, 1535 }, 1536 }; 1537 1538 static struct gdsc titan_top_gdsc; 1539 1540 static struct gdsc bps_gdsc = { 1541 .gdscr = 0x6004, 1542 .pd = { 1543 .name = "bps_gdsc", 1544 }, 1545 .flags = HW_CTRL | POLL_CFG_GDSCR, 1546 .pwrsts = PWRSTS_OFF_ON, 1547 }; 1548 1549 static struct gdsc ipe_0_gdsc = { 1550 .gdscr = 0x7004, 1551 .pd = { 1552 .name = "ipe_0_gdsc", 1553 }, 1554 .flags = HW_CTRL | POLL_CFG_GDSCR, 1555 .pwrsts = PWRSTS_OFF_ON, 1556 }; 1557 1558 static struct gdsc ipe_1_gdsc = { 1559 .gdscr = 0x8004, 1560 .pd = { 1561 .name = "ipe_1_gdsc", 1562 }, 1563 .flags = HW_CTRL | POLL_CFG_GDSCR, 1564 .pwrsts = PWRSTS_OFF_ON, 1565 }; 1566 1567 static struct gdsc ife_0_gdsc = { 1568 .gdscr = 0x9004, 1569 .pd = { 1570 .name = "ife_0_gdsc", 1571 }, 1572 .flags = POLL_CFG_GDSCR, 1573 .parent = &titan_top_gdsc.pd, 1574 .pwrsts = PWRSTS_OFF_ON, 1575 }; 1576 1577 static struct gdsc ife_1_gdsc = { 1578 .gdscr = 0xa004, 1579 .pd = { 1580 .name = "ife_1_gdsc", 1581 }, 1582 .flags = POLL_CFG_GDSCR, 1583 .parent = &titan_top_gdsc.pd, 1584 .pwrsts = PWRSTS_OFF_ON, 1585 }; 1586 1587 static struct gdsc titan_top_gdsc = { 1588 .gdscr = 0xb134, 1589 .pd = { 1590 .name = "titan_top_gdsc", 1591 }, 1592 .flags = POLL_CFG_GDSCR, 1593 .pwrsts = PWRSTS_OFF_ON, 1594 }; 1595 1596 static struct clk_regmap *cam_cc_sdm845_clocks[] = { 1597 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, 1598 [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr, 1599 [CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr, 1600 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, 1601 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, 1602 [CAM_CC_CAMNOC_ATB_CLK] = &cam_cc_camnoc_atb_clk.clkr, 1603 [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr, 1604 [CAM_CC_CCI_CLK] = &cam_cc_cci_clk.clkr, 1605 [CAM_CC_CCI_CLK_SRC] = &cam_cc_cci_clk_src.clkr, 1606 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 1607 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 1608 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 1609 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 1610 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 1611 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 1612 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 1613 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 1614 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 1615 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 1616 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 1617 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 1618 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 1619 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 1620 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 1621 [CAM_CC_FD_CORE_CLK] = &cam_cc_fd_core_clk.clkr, 1622 [CAM_CC_FD_CORE_CLK_SRC] = &cam_cc_fd_core_clk_src.clkr, 1623 [CAM_CC_FD_CORE_UAR_CLK] = &cam_cc_fd_core_uar_clk.clkr, 1624 [CAM_CC_ICP_APB_CLK] = &cam_cc_icp_apb_clk.clkr, 1625 [CAM_CC_ICP_ATB_CLK] = &cam_cc_icp_atb_clk.clkr, 1626 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 1627 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 1628 [CAM_CC_ICP_CTI_CLK] = &cam_cc_icp_cti_clk.clkr, 1629 [CAM_CC_ICP_TS_CLK] = &cam_cc_icp_ts_clk.clkr, 1630 [CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr, 1631 [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, 1632 [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, 1633 [CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr, 1634 [CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr, 1635 [CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr, 1636 [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, 1637 [CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr, 1638 [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, 1639 [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, 1640 [CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr, 1641 [CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr, 1642 [CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr, 1643 [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, 1644 [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, 1645 [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, 1646 [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, 1647 [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, 1648 [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, 1649 [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr, 1650 [CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr, 1651 [CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr, 1652 [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr, 1653 [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr, 1654 [CAM_CC_IPE_1_AHB_CLK] = &cam_cc_ipe_1_ahb_clk.clkr, 1655 [CAM_CC_IPE_1_AREG_CLK] = &cam_cc_ipe_1_areg_clk.clkr, 1656 [CAM_CC_IPE_1_AXI_CLK] = &cam_cc_ipe_1_axi_clk.clkr, 1657 [CAM_CC_IPE_1_CLK] = &cam_cc_ipe_1_clk.clkr, 1658 [CAM_CC_IPE_1_CLK_SRC] = &cam_cc_ipe_1_clk_src.clkr, 1659 [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, 1660 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, 1661 [CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr, 1662 [CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr, 1663 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 1664 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 1665 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 1666 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 1667 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 1668 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 1669 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 1670 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 1671 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 1672 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, 1673 [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 1674 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, 1675 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 1676 [CAM_CC_PLL2_OUT_EVEN] = &cam_cc_pll2_out_even.clkr, 1677 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 1678 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, 1679 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 1680 [CAM_CC_SOC_AHB_CLK] = &cam_cc_soc_ahb_clk.clkr, 1681 [CAM_CC_SYS_TMR_CLK] = &cam_cc_sys_tmr_clk.clkr, 1682 }; 1683 1684 static struct gdsc *cam_cc_sdm845_gdscs[] = { 1685 [BPS_GDSC] = &bps_gdsc, 1686 [IPE_0_GDSC] = &ipe_0_gdsc, 1687 [IPE_1_GDSC] = &ipe_1_gdsc, 1688 [IFE_0_GDSC] = &ife_0_gdsc, 1689 [IFE_1_GDSC] = &ife_1_gdsc, 1690 [TITAN_TOP_GDSC] = &titan_top_gdsc, 1691 }; 1692 1693 static const struct regmap_config cam_cc_sdm845_regmap_config = { 1694 .reg_bits = 32, 1695 .reg_stride = 4, 1696 .val_bits = 32, 1697 .max_register = 0xd004, 1698 .fast_io = true, 1699 }; 1700 1701 static const struct qcom_cc_desc cam_cc_sdm845_desc = { 1702 .config = &cam_cc_sdm845_regmap_config, 1703 .clks = cam_cc_sdm845_clocks, 1704 .num_clks = ARRAY_SIZE(cam_cc_sdm845_clocks), 1705 .gdscs = cam_cc_sdm845_gdscs, 1706 .num_gdscs = ARRAY_SIZE(cam_cc_sdm845_gdscs), 1707 }; 1708 1709 static const struct of_device_id cam_cc_sdm845_match_table[] = { 1710 { .compatible = "qcom,sdm845-camcc" }, 1711 { } 1712 }; 1713 MODULE_DEVICE_TABLE(of, cam_cc_sdm845_match_table); 1714 1715 static int cam_cc_sdm845_probe(struct platform_device *pdev) 1716 { 1717 struct regmap *regmap; 1718 struct alpha_pll_config cam_cc_pll_config = { }; 1719 1720 regmap = qcom_cc_map(pdev, &cam_cc_sdm845_desc); 1721 if (IS_ERR(regmap)) 1722 return PTR_ERR(regmap); 1723 1724 cam_cc_pll_config.l = 0x1f; 1725 cam_cc_pll_config.alpha = 0x4000; 1726 clk_fabia_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll_config); 1727 1728 cam_cc_pll_config.l = 0x2a; 1729 cam_cc_pll_config.alpha = 0x1556; 1730 clk_fabia_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll_config); 1731 1732 cam_cc_pll_config.l = 0x32; 1733 cam_cc_pll_config.alpha = 0x0; 1734 clk_fabia_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll_config); 1735 1736 cam_cc_pll_config.l = 0x14; 1737 clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll_config); 1738 1739 return qcom_cc_really_probe(&pdev->dev, &cam_cc_sdm845_desc, regmap); 1740 } 1741 1742 static struct platform_driver cam_cc_sdm845_driver = { 1743 .probe = cam_cc_sdm845_probe, 1744 .driver = { 1745 .name = "sdm845-camcc", 1746 .of_match_table = cam_cc_sdm845_match_table, 1747 }, 1748 }; 1749 1750 module_platform_driver(cam_cc_sdm845_driver); 1751 1752 MODULE_DESCRIPTION("QTI CAM_CC SDM845 Driver"); 1753 MODULE_LICENSE("GPL v2"); 1754