1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2023, Linaro Ltd. 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/mod_devicetable.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/regmap.h> 13 14 #include <dt-bindings/clock/qcom,sc8280xp-camcc.h> 15 16 #include "clk-alpha-pll.h" 17 #include "clk-branch.h" 18 #include "clk-rcg.h" 19 #include "clk-regmap.h" 20 #include "common.h" 21 #include "gdsc.h" 22 #include "reset.h" 23 24 enum { 25 DT_IFACE, 26 DT_BI_TCXO, 27 DT_BI_TCXO_AO, 28 DT_SLEEP_CLK, 29 }; 30 31 enum { 32 P_BI_TCXO, 33 P_CAMCC_PLL0_OUT_EVEN, 34 P_CAMCC_PLL0_OUT_MAIN, 35 P_CAMCC_PLL0_OUT_ODD, 36 P_CAMCC_PLL1_OUT_EVEN, 37 P_CAMCC_PLL2_OUT_AUX, 38 P_CAMCC_PLL2_OUT_EARLY, 39 P_CAMCC_PLL3_OUT_EVEN, 40 P_CAMCC_PLL4_OUT_EVEN, 41 P_CAMCC_PLL5_OUT_EVEN, 42 P_CAMCC_PLL6_OUT_EVEN, 43 P_CAMCC_PLL7_OUT_EVEN, 44 P_CAMCC_PLL7_OUT_ODD, 45 P_SLEEP_CLK, 46 }; 47 48 static struct pll_vco lucid_vco[] = { 49 { 249600000, 1800000000, 0 }, 50 }; 51 52 static struct pll_vco zonda_vco[] = { 53 { 595200000, 3600000000, 0 }, 54 }; 55 56 static struct alpha_pll_config camcc_pll0_config = { 57 .l = 0x3e, 58 .alpha = 0x8000, 59 .config_ctl_val = 0x20485699, 60 .config_ctl_hi_val = 0x00002261, 61 .config_ctl_hi1_val = 0x2a9a699c, 62 .test_ctl_val = 0x00000000, 63 .test_ctl_hi_val = 0x00000000, 64 .test_ctl_hi1_val = 0x01800000, 65 .user_ctl_val = 0x00003100, 66 .user_ctl_hi_val = 0x00000805, 67 .user_ctl_hi1_val = 0x00000000, 68 }; 69 70 static struct clk_alpha_pll camcc_pll0 = { 71 .offset = 0x0, 72 .vco_table = lucid_vco, 73 .num_vco = ARRAY_SIZE(lucid_vco), 74 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 75 .clkr = { 76 .hw.init = &(struct clk_init_data){ 77 .name = "camcc_pll0", 78 .parent_data = &(const struct clk_parent_data){ 79 .index = DT_BI_TCXO, 80 }, 81 .num_parents = 1, 82 .ops = &clk_alpha_pll_lucid_5lpe_ops, 83 }, 84 }, 85 }; 86 87 static const struct clk_div_table post_div_table_camcc_pll0_out_even[] = { 88 { 0x1, 2 }, 89 }; 90 91 static struct clk_alpha_pll_postdiv camcc_pll0_out_even = { 92 .offset = 0x0, 93 .post_div_shift = 8, 94 .post_div_table = post_div_table_camcc_pll0_out_even, 95 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll0_out_even), 96 .width = 4, 97 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 98 .clkr.hw.init = &(struct clk_init_data){ 99 .name = "camcc_pll0_out_even", 100 .parent_hws = (const struct clk_hw*[]){ 101 &camcc_pll0.clkr.hw, 102 }, 103 .num_parents = 1, 104 .flags = CLK_SET_RATE_PARENT, 105 .ops = &clk_alpha_pll_postdiv_lucid_ops, 106 }, 107 }; 108 109 static const struct clk_div_table post_div_table_camcc_pll0_out_odd[] = { 110 { 0x3, 3 }, 111 }; 112 113 static struct clk_alpha_pll_postdiv camcc_pll0_out_odd = { 114 .offset = 0x0, 115 .post_div_shift = 12, 116 .post_div_table = post_div_table_camcc_pll0_out_odd, 117 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll0_out_odd), 118 .width = 4, 119 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 120 .clkr.hw.init = &(struct clk_init_data){ 121 .name = "camcc_pll0_out_odd", 122 .parent_hws = (const struct clk_hw*[]){ 123 &camcc_pll0.clkr.hw, 124 }, 125 .num_parents = 1, 126 .flags = CLK_SET_RATE_PARENT, 127 .ops = &clk_alpha_pll_postdiv_lucid_ops, 128 }, 129 }; 130 131 static struct alpha_pll_config camcc_pll1_config = { 132 .l = 0x21, 133 .alpha = 0x5555, 134 .config_ctl_val = 0x20485699, 135 .config_ctl_hi_val = 0x00002261, 136 .config_ctl_hi1_val = 0x2a9a699c, 137 .test_ctl_val = 0x00000000, 138 .test_ctl_hi_val = 0x00000000, 139 .test_ctl_hi1_val = 0x01800000, 140 .user_ctl_val = 0x00000100, 141 .user_ctl_hi_val = 0x00000805, 142 .user_ctl_hi1_val = 0x00000000, 143 }; 144 145 static struct clk_alpha_pll camcc_pll1 = { 146 .offset = 0x1000, 147 .vco_table = lucid_vco, 148 .num_vco = ARRAY_SIZE(lucid_vco), 149 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 150 .clkr = { 151 .hw.init = &(struct clk_init_data){ 152 .name = "camcc_pll1", 153 .parent_data = &(const struct clk_parent_data){ 154 .index = DT_BI_TCXO, 155 }, 156 .num_parents = 1, 157 .ops = &clk_alpha_pll_lucid_5lpe_ops, 158 }, 159 }, 160 }; 161 162 static const struct clk_div_table post_div_table_camcc_pll1_out_even[] = { 163 { 0x1, 2 }, 164 }; 165 166 static struct clk_alpha_pll_postdiv camcc_pll1_out_even = { 167 .offset = 0x1000, 168 .post_div_shift = 8, 169 .post_div_table = post_div_table_camcc_pll1_out_even, 170 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll1_out_even), 171 .width = 4, 172 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 173 .clkr.hw.init = &(struct clk_init_data){ 174 .name = "camcc_pll1_out_even", 175 .parent_hws = (const struct clk_hw*[]){ 176 &camcc_pll1.clkr.hw, 177 }, 178 .num_parents = 1, 179 .flags = CLK_SET_RATE_PARENT, 180 .ops = &clk_alpha_pll_postdiv_lucid_ops, 181 }, 182 }; 183 184 static struct alpha_pll_config camcc_pll2_config = { 185 .l = 0x32, 186 .alpha = 0x0, 187 .config_ctl_val = 0x08200800, 188 .config_ctl_hi_val = 0x05028011, 189 .config_ctl_hi1_val = 0x08000000, 190 }; 191 192 static struct clk_alpha_pll camcc_pll2 = { 193 .offset = 0x2000, 194 .vco_table = zonda_vco, 195 .num_vco = ARRAY_SIZE(zonda_vco), 196 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], 197 .clkr = { 198 .hw.init = &(struct clk_init_data){ 199 .name = "camcc_pll2", 200 .parent_data = &(const struct clk_parent_data){ 201 .index = DT_BI_TCXO, 202 }, 203 .num_parents = 1, 204 .ops = &clk_alpha_pll_zonda_ops, 205 }, 206 }, 207 }; 208 209 static struct alpha_pll_config camcc_pll3_config = { 210 .l = 0x29, 211 .alpha = 0xaaaa, 212 .config_ctl_val = 0x20485699, 213 .config_ctl_hi_val = 0x00002261, 214 .config_ctl_hi1_val = 0x2a9a699c, 215 .test_ctl_val = 0x00000000, 216 .test_ctl_hi_val = 0x00000000, 217 .test_ctl_hi1_val = 0x01800000, 218 .user_ctl_val = 0x00000100, 219 .user_ctl_hi_val = 0x00000805, 220 .user_ctl_hi1_val = 0x00000000, 221 }; 222 223 static struct clk_alpha_pll camcc_pll3 = { 224 .offset = 0x3000, 225 .vco_table = lucid_vco, 226 .num_vco = ARRAY_SIZE(lucid_vco), 227 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 228 .clkr = { 229 .hw.init = &(struct clk_init_data){ 230 .name = "camcc_pll3", 231 .parent_data = &(const struct clk_parent_data){ 232 .index = DT_BI_TCXO, 233 }, 234 .num_parents = 1, 235 .ops = &clk_alpha_pll_lucid_5lpe_ops, 236 }, 237 }, 238 }; 239 240 static const struct clk_div_table post_div_table_camcc_pll3_out_even[] = { 241 { 0x1, 2 }, 242 }; 243 244 static struct clk_alpha_pll_postdiv camcc_pll3_out_even = { 245 .offset = 0x3000, 246 .post_div_shift = 8, 247 .post_div_table = post_div_table_camcc_pll3_out_even, 248 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll3_out_even), 249 .width = 4, 250 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 251 .clkr.hw.init = &(struct clk_init_data){ 252 .name = "camcc_pll3_out_even", 253 .parent_hws = (const struct clk_hw*[]){ 254 &camcc_pll3.clkr.hw, 255 }, 256 .num_parents = 1, 257 .flags = CLK_SET_RATE_PARENT, 258 .ops = &clk_alpha_pll_postdiv_lucid_ops, 259 }, 260 }; 261 262 static struct alpha_pll_config camcc_pll4_config = { 263 .l = 0x29, 264 .alpha = 0xaaaa, 265 .config_ctl_val = 0x20485699, 266 .config_ctl_hi_val = 0x00002261, 267 .config_ctl_hi1_val = 0x2a9a699c, 268 .test_ctl_val = 0x00000000, 269 .test_ctl_hi_val = 0x00000000, 270 .test_ctl_hi1_val = 0x01800000, 271 .user_ctl_val = 0x00000100, 272 .user_ctl_hi_val = 0x00000805, 273 .user_ctl_hi1_val = 0x00000000, 274 }; 275 276 static struct clk_alpha_pll camcc_pll4 = { 277 .offset = 0x4000, 278 .vco_table = lucid_vco, 279 .num_vco = ARRAY_SIZE(lucid_vco), 280 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 281 .clkr = { 282 .hw.init = &(struct clk_init_data){ 283 .name = "camcc_pll4", 284 .parent_data = &(const struct clk_parent_data){ 285 .index = DT_BI_TCXO, 286 }, 287 .num_parents = 1, 288 .ops = &clk_alpha_pll_lucid_5lpe_ops, 289 }, 290 }, 291 }; 292 293 static const struct clk_div_table post_div_table_camcc_pll4_out_even[] = { 294 { 0x1, 2 }, 295 }; 296 297 static struct clk_alpha_pll_postdiv camcc_pll4_out_even = { 298 .offset = 0x4000, 299 .post_div_shift = 8, 300 .post_div_table = post_div_table_camcc_pll4_out_even, 301 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll4_out_even), 302 .width = 4, 303 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 304 .clkr.hw.init = &(struct clk_init_data){ 305 .name = "camcc_pll4_out_even", 306 .parent_hws = (const struct clk_hw*[]){ 307 &camcc_pll4.clkr.hw, 308 }, 309 .num_parents = 1, 310 .flags = CLK_SET_RATE_PARENT, 311 .ops = &clk_alpha_pll_postdiv_lucid_ops, 312 }, 313 }; 314 315 static struct alpha_pll_config camcc_pll5_config = { 316 .l = 0x29, 317 .alpha = 0xaaaa, 318 .config_ctl_val = 0x20485699, 319 .config_ctl_hi_val = 0x00002261, 320 .config_ctl_hi1_val = 0x2a9a699c, 321 .test_ctl_val = 0x00000000, 322 .test_ctl_hi_val = 0x00000000, 323 .test_ctl_hi1_val = 0x01800000, 324 .user_ctl_val = 0x00000100, 325 .user_ctl_hi_val = 0x00000805, 326 .user_ctl_hi1_val = 0x00000000, 327 }; 328 329 static struct clk_alpha_pll camcc_pll5 = { 330 .offset = 0x10000, 331 .vco_table = lucid_vco, 332 .num_vco = ARRAY_SIZE(lucid_vco), 333 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 334 .clkr = { 335 .hw.init = &(struct clk_init_data){ 336 .name = "camcc_pll5", 337 .parent_data = &(const struct clk_parent_data){ 338 .index = DT_BI_TCXO, 339 }, 340 .num_parents = 1, 341 .ops = &clk_alpha_pll_lucid_5lpe_ops, 342 }, 343 }, 344 }; 345 346 static const struct clk_div_table post_div_table_camcc_pll5_out_even[] = { 347 { 0x1, 2 }, 348 }; 349 350 static struct clk_alpha_pll_postdiv camcc_pll5_out_even = { 351 .offset = 0x10000, 352 .post_div_shift = 8, 353 .post_div_table = post_div_table_camcc_pll5_out_even, 354 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll5_out_even), 355 .width = 4, 356 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 357 .clkr.hw.init = &(struct clk_init_data){ 358 .name = "camcc_pll5_out_even", 359 .parent_hws = (const struct clk_hw*[]){ 360 &camcc_pll5.clkr.hw, 361 }, 362 .num_parents = 1, 363 .flags = CLK_SET_RATE_PARENT, 364 .ops = &clk_alpha_pll_postdiv_lucid_ops, 365 }, 366 }; 367 368 static struct alpha_pll_config camcc_pll6_config = { 369 .l = 0x29, 370 .alpha = 0xaaaa, 371 .config_ctl_val = 0x20486699, 372 .config_ctl_hi_val = 0x00002261, 373 .config_ctl_hi1_val = 0x2a9a699c, 374 .test_ctl_val = 0x00000000, 375 .test_ctl_hi_val = 0x00000000, 376 .test_ctl_hi1_val = 0x01800000, 377 .user_ctl_val = 0x00000100, 378 .user_ctl_hi_val = 0x00000805, 379 .user_ctl_hi1_val = 0x00000000, 380 }; 381 382 static struct clk_alpha_pll camcc_pll6 = { 383 .offset = 0x11000, 384 .vco_table = lucid_vco, 385 .num_vco = ARRAY_SIZE(lucid_vco), 386 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 387 .clkr = { 388 .hw.init = &(struct clk_init_data){ 389 .name = "camcc_pll6", 390 .parent_data = &(const struct clk_parent_data){ 391 .index = DT_BI_TCXO, 392 }, 393 .num_parents = 1, 394 .ops = &clk_alpha_pll_lucid_5lpe_ops, 395 }, 396 }, 397 }; 398 399 static const struct clk_div_table post_div_table_camcc_pll6_out_even[] = { 400 { 0x1, 2 }, 401 }; 402 403 static struct clk_alpha_pll_postdiv camcc_pll6_out_even = { 404 .offset = 0x11000, 405 .post_div_shift = 8, 406 .post_div_table = post_div_table_camcc_pll6_out_even, 407 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll6_out_even), 408 .width = 4, 409 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 410 .clkr.hw.init = &(struct clk_init_data){ 411 .name = "camcc_pll6_out_even", 412 .parent_hws = (const struct clk_hw*[]){ 413 &camcc_pll6.clkr.hw, 414 }, 415 .num_parents = 1, 416 .flags = CLK_SET_RATE_PARENT, 417 .ops = &clk_alpha_pll_postdiv_lucid_ops, 418 }, 419 }; 420 421 static struct alpha_pll_config camcc_pll7_config = { 422 .l = 0x32, 423 .alpha = 0x0, 424 .config_ctl_val = 0x20485699, 425 .config_ctl_hi_val = 0x00002261, 426 .config_ctl_hi1_val = 0x2a9a699c, 427 .test_ctl_val = 0x00000000, 428 .test_ctl_hi_val = 0x00000000, 429 .test_ctl_hi1_val = 0x01800000, 430 .user_ctl_val = 0x00003100, 431 .user_ctl_hi_val = 0x00000805, 432 .user_ctl_hi1_val = 0x00000000, 433 }; 434 435 static struct clk_alpha_pll camcc_pll7 = { 436 .offset = 0x12000, 437 .vco_table = lucid_vco, 438 .num_vco = ARRAY_SIZE(lucid_vco), 439 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 440 .clkr = { 441 .hw.init = &(struct clk_init_data){ 442 .name = "camcc_pll7", 443 .parent_data = &(const struct clk_parent_data){ 444 .index = DT_BI_TCXO, 445 }, 446 .num_parents = 1, 447 .ops = &clk_alpha_pll_lucid_5lpe_ops, 448 }, 449 }, 450 }; 451 452 static const struct clk_div_table post_div_table_camcc_pll7_out_even[] = { 453 { 0x1, 2 }, 454 }; 455 456 static struct clk_alpha_pll_postdiv camcc_pll7_out_even = { 457 .offset = 0x12000, 458 .post_div_shift = 8, 459 .post_div_table = post_div_table_camcc_pll7_out_even, 460 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll7_out_even), 461 .width = 4, 462 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 463 .clkr.hw.init = &(struct clk_init_data){ 464 .name = "camcc_pll7_out_even", 465 .parent_hws = (const struct clk_hw*[]){ 466 &camcc_pll7.clkr.hw, 467 }, 468 .num_parents = 1, 469 .flags = CLK_SET_RATE_PARENT, 470 .ops = &clk_alpha_pll_postdiv_lucid_ops, 471 }, 472 }; 473 474 static const struct clk_div_table post_div_table_camcc_pll7_out_odd[] = { 475 { 0x3, 3 }, 476 }; 477 478 static struct clk_alpha_pll_postdiv camcc_pll7_out_odd = { 479 .offset = 0x12000, 480 .post_div_shift = 12, 481 .post_div_table = post_div_table_camcc_pll7_out_odd, 482 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll7_out_odd), 483 .width = 4, 484 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 485 .clkr.hw.init = &(struct clk_init_data){ 486 .name = "camcc_pll7_out_odd", 487 .parent_hws = (const struct clk_hw*[]){ 488 &camcc_pll7.clkr.hw, 489 }, 490 .num_parents = 1, 491 .flags = CLK_SET_RATE_PARENT, 492 .ops = &clk_alpha_pll_postdiv_lucid_ops, 493 }, 494 }; 495 496 static const struct parent_map camcc_parent_map_0[] = { 497 { P_BI_TCXO, 0 }, 498 { P_CAMCC_PLL0_OUT_MAIN, 1 }, 499 { P_CAMCC_PLL0_OUT_EVEN, 2 }, 500 { P_CAMCC_PLL0_OUT_ODD, 3 }, 501 { P_CAMCC_PLL7_OUT_EVEN, 5 }, 502 }; 503 504 static const struct clk_parent_data camcc_parent_data_0[] = { 505 { .index = DT_BI_TCXO }, 506 { .hw = &camcc_pll0.clkr.hw }, 507 { .hw = &camcc_pll0_out_even.clkr.hw }, 508 { .hw = &camcc_pll0_out_odd.clkr.hw }, 509 { .hw = &camcc_pll7_out_even.clkr.hw }, 510 }; 511 512 static const struct parent_map camcc_parent_map_1[] = { 513 { P_BI_TCXO, 0 }, 514 { P_CAMCC_PLL2_OUT_AUX, 2 }, 515 { P_CAMCC_PLL2_OUT_EARLY, 5 }, 516 }; 517 518 static const struct clk_parent_data camcc_parent_data_1[] = { 519 { .index = DT_BI_TCXO }, 520 { .hw = &camcc_pll2.clkr.hw }, 521 { .hw = &camcc_pll2.clkr.hw }, 522 }; 523 524 static const struct parent_map camcc_parent_map_2[] = { 525 { P_BI_TCXO, 0 }, 526 { P_CAMCC_PLL0_OUT_MAIN, 1 }, 527 { P_CAMCC_PLL0_OUT_EVEN, 2 }, 528 { P_CAMCC_PLL0_OUT_ODD, 3 }, 529 { P_CAMCC_PLL7_OUT_ODD, 4 }, 530 { P_CAMCC_PLL7_OUT_EVEN, 5 }, 531 }; 532 533 static const struct clk_parent_data camcc_parent_data_2[] = { 534 { .index = DT_BI_TCXO }, 535 { .hw = &camcc_pll0.clkr.hw }, 536 { .hw = &camcc_pll0_out_even.clkr.hw }, 537 { .hw = &camcc_pll0_out_odd.clkr.hw }, 538 { .hw = &camcc_pll7_out_odd.clkr.hw }, 539 { .hw = &camcc_pll7_out_even.clkr.hw }, 540 }; 541 542 static const struct parent_map camcc_parent_map_3[] = { 543 { P_BI_TCXO, 0 }, 544 { P_CAMCC_PLL0_OUT_MAIN, 1 }, 545 { P_CAMCC_PLL0_OUT_EVEN, 2 }, 546 { P_CAMCC_PLL0_OUT_ODD, 3 }, 547 { P_CAMCC_PLL7_OUT_EVEN, 5 }, 548 { P_CAMCC_PLL3_OUT_EVEN, 6 }, 549 }; 550 551 static const struct clk_parent_data camcc_parent_data_3[] = { 552 { .index = DT_BI_TCXO }, 553 { .hw = &camcc_pll0.clkr.hw }, 554 { .hw = &camcc_pll0_out_even.clkr.hw }, 555 { .hw = &camcc_pll0_out_odd.clkr.hw }, 556 { .hw = &camcc_pll7_out_even.clkr.hw }, 557 { .hw = &camcc_pll3_out_even.clkr.hw }, 558 }; 559 560 static const struct parent_map camcc_parent_map_4[] = { 561 { P_BI_TCXO, 0 }, 562 { P_CAMCC_PLL3_OUT_EVEN, 6 }, 563 }; 564 565 static const struct clk_parent_data camcc_parent_data_4[] = { 566 { .index = DT_BI_TCXO }, 567 { .hw = &camcc_pll3_out_even.clkr.hw }, 568 }; 569 570 static const struct parent_map camcc_parent_map_5[] = { 571 { P_BI_TCXO, 0 }, 572 { P_CAMCC_PLL4_OUT_EVEN, 6 }, 573 }; 574 575 static const struct clk_parent_data camcc_parent_data_5[] = { 576 { .index = DT_BI_TCXO }, 577 { .hw = &camcc_pll4_out_even.clkr.hw }, 578 }; 579 580 static const struct parent_map camcc_parent_map_6[] = { 581 { P_BI_TCXO, 0 }, 582 { P_CAMCC_PLL5_OUT_EVEN, 6 }, 583 }; 584 585 static const struct clk_parent_data camcc_parent_data_6[] = { 586 { .index = DT_BI_TCXO }, 587 { .hw = &camcc_pll5_out_even.clkr.hw }, 588 }; 589 590 static const struct parent_map camcc_parent_map_7[] = { 591 { P_BI_TCXO, 0 }, 592 { P_CAMCC_PLL6_OUT_EVEN, 6 }, 593 }; 594 595 static const struct clk_parent_data camcc_parent_data_7[] = { 596 { .index = DT_BI_TCXO }, 597 { .hw = &camcc_pll6_out_even.clkr.hw }, 598 }; 599 600 static const struct parent_map camcc_parent_map_8[] = { 601 { P_BI_TCXO, 0 }, 602 { P_CAMCC_PLL1_OUT_EVEN, 4 }, 603 }; 604 605 static const struct clk_parent_data camcc_parent_data_8[] = { 606 { .index = DT_BI_TCXO }, 607 { .hw = &camcc_pll1_out_even.clkr.hw }, 608 }; 609 610 static const struct parent_map camcc_parent_map_9[] = { 611 { P_SLEEP_CLK, 0 }, 612 }; 613 614 static const struct clk_parent_data camcc_parent_data_9[] = { 615 { .fw_name = "sleep_clk" }, 616 }; 617 618 static const struct parent_map camcc_parent_map_10[] = { 619 { P_BI_TCXO, 0 }, 620 }; 621 622 static const struct clk_parent_data camcc_parent_data_10_ao[] = { 623 { .fw_name = "bi_tcxo_ao" }, 624 }; 625 626 static const struct freq_tbl ftbl_camcc_bps_clk_src[] = { 627 F(19200000, P_BI_TCXO, 1, 0, 0), 628 F(200000000, P_CAMCC_PLL0_OUT_ODD, 2, 0, 0), 629 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 630 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0), 631 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 632 F(760000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), 633 { } 634 }; 635 636 static struct clk_rcg2 camcc_bps_clk_src = { 637 .cmd_rcgr = 0x7010, 638 .mnd_width = 0, 639 .hid_width = 5, 640 .parent_map = camcc_parent_map_3, 641 .freq_tbl = ftbl_camcc_bps_clk_src, 642 .clkr.hw.init = &(struct clk_init_data){ 643 .name = "camcc_bps_clk_src", 644 .parent_data = camcc_parent_data_3, 645 .num_parents = ARRAY_SIZE(camcc_parent_data_3), 646 .flags = CLK_SET_RATE_PARENT, 647 .ops = &clk_rcg2_shared_ops, 648 }, 649 }; 650 651 static const struct freq_tbl ftbl_camcc_camnoc_axi_clk_src[] = { 652 F(19200000, P_BI_TCXO, 1, 0, 0), 653 F(150000000, P_CAMCC_PLL0_OUT_EVEN, 4, 0, 0), 654 F(266666667, P_CAMCC_PLL0_OUT_ODD, 1.5, 0, 0), 655 F(320000000, P_CAMCC_PLL7_OUT_ODD, 1, 0, 0), 656 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 657 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0), 658 { } 659 }; 660 661 static struct clk_rcg2 camcc_camnoc_axi_clk_src = { 662 .cmd_rcgr = 0xc170, 663 .mnd_width = 0, 664 .hid_width = 5, 665 .parent_map = camcc_parent_map_2, 666 .freq_tbl = ftbl_camcc_camnoc_axi_clk_src, 667 .clkr.hw.init = &(struct clk_init_data){ 668 .name = "camcc_camnoc_axi_clk_src", 669 .parent_data = camcc_parent_data_2, 670 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 671 .ops = &clk_rcg2_ops, 672 }, 673 }; 674 675 static const struct freq_tbl ftbl_camcc_cci_0_clk_src[] = { 676 F(19200000, P_BI_TCXO, 1, 0, 0), 677 F(37500000, P_CAMCC_PLL0_OUT_EVEN, 16, 0, 0), 678 { } 679 }; 680 681 static struct clk_rcg2 camcc_cci_0_clk_src = { 682 .cmd_rcgr = 0xc108, 683 .mnd_width = 8, 684 .hid_width = 5, 685 .parent_map = camcc_parent_map_0, 686 .freq_tbl = ftbl_camcc_cci_0_clk_src, 687 .clkr.hw.init = &(struct clk_init_data){ 688 .name = "camcc_cci_0_clk_src", 689 .parent_data = camcc_parent_data_0, 690 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 691 .ops = &clk_rcg2_ops, 692 }, 693 }; 694 695 static struct clk_rcg2 camcc_cci_1_clk_src = { 696 .cmd_rcgr = 0xc124, 697 .mnd_width = 8, 698 .hid_width = 5, 699 .parent_map = camcc_parent_map_0, 700 .freq_tbl = ftbl_camcc_cci_0_clk_src, 701 .clkr.hw.init = &(struct clk_init_data){ 702 .name = "camcc_cci_1_clk_src", 703 .parent_data = camcc_parent_data_0, 704 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 705 .ops = &clk_rcg2_ops, 706 }, 707 }; 708 709 static struct clk_rcg2 camcc_cci_2_clk_src = { 710 .cmd_rcgr = 0xc204, 711 .mnd_width = 8, 712 .hid_width = 5, 713 .parent_map = camcc_parent_map_0, 714 .freq_tbl = ftbl_camcc_cci_0_clk_src, 715 .clkr.hw.init = &(struct clk_init_data){ 716 .name = "camcc_cci_2_clk_src", 717 .parent_data = camcc_parent_data_0, 718 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 719 .ops = &clk_rcg2_ops, 720 }, 721 }; 722 723 static struct clk_rcg2 camcc_cci_3_clk_src = { 724 .cmd_rcgr = 0xc220, 725 .mnd_width = 8, 726 .hid_width = 5, 727 .parent_map = camcc_parent_map_0, 728 .freq_tbl = ftbl_camcc_cci_0_clk_src, 729 .clkr.hw.init = &(struct clk_init_data){ 730 .name = "camcc_cci_3_clk_src", 731 .parent_data = camcc_parent_data_0, 732 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 733 .ops = &clk_rcg2_ops, 734 }, 735 }; 736 737 static const struct freq_tbl ftbl_camcc_cphy_rx_clk_src[] = { 738 F(19200000, P_BI_TCXO, 1, 0, 0), 739 F(240000000, P_CAMCC_PLL0_OUT_EVEN, 2.5, 0, 0), 740 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 741 { } 742 }; 743 744 static struct clk_rcg2 camcc_cphy_rx_clk_src = { 745 .cmd_rcgr = 0xa064, 746 .mnd_width = 0, 747 .hid_width = 5, 748 .parent_map = camcc_parent_map_0, 749 .freq_tbl = ftbl_camcc_cphy_rx_clk_src, 750 .clkr.hw.init = &(struct clk_init_data){ 751 .name = "camcc_cphy_rx_clk_src", 752 .parent_data = camcc_parent_data_0, 753 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 754 .ops = &clk_rcg2_ops, 755 }, 756 }; 757 758 static const struct freq_tbl ftbl_camcc_csi0phytimer_clk_src[] = { 759 F(19200000, P_BI_TCXO, 1, 0, 0), 760 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0), 761 { } 762 }; 763 764 static struct clk_rcg2 camcc_csi0phytimer_clk_src = { 765 .cmd_rcgr = 0x6004, 766 .mnd_width = 0, 767 .hid_width = 5, 768 .parent_map = camcc_parent_map_0, 769 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, 770 .clkr.hw.init = &(struct clk_init_data){ 771 .name = "camcc_csi0phytimer_clk_src", 772 .parent_data = camcc_parent_data_0, 773 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 774 .ops = &clk_rcg2_ops, 775 }, 776 }; 777 778 static struct clk_rcg2 camcc_csi1phytimer_clk_src = { 779 .cmd_rcgr = 0x6028, 780 .mnd_width = 0, 781 .hid_width = 5, 782 .parent_map = camcc_parent_map_0, 783 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, 784 .clkr.hw.init = &(struct clk_init_data){ 785 .name = "camcc_csi1phytimer_clk_src", 786 .parent_data = camcc_parent_data_0, 787 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 788 .ops = &clk_rcg2_ops, 789 }, 790 }; 791 792 static struct clk_rcg2 camcc_csi2phytimer_clk_src = { 793 .cmd_rcgr = 0x604c, 794 .mnd_width = 0, 795 .hid_width = 5, 796 .parent_map = camcc_parent_map_0, 797 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, 798 .clkr.hw.init = &(struct clk_init_data){ 799 .name = "camcc_csi2phytimer_clk_src", 800 .parent_data = camcc_parent_data_0, 801 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 802 .ops = &clk_rcg2_ops, 803 }, 804 }; 805 806 static struct clk_rcg2 camcc_csi3phytimer_clk_src = { 807 .cmd_rcgr = 0x6074, 808 .mnd_width = 0, 809 .hid_width = 5, 810 .parent_map = camcc_parent_map_0, 811 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, 812 .clkr.hw.init = &(struct clk_init_data){ 813 .name = "camcc_csi3phytimer_clk_src", 814 .parent_data = camcc_parent_data_0, 815 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 816 .ops = &clk_rcg2_ops, 817 }, 818 }; 819 820 static const struct freq_tbl ftbl_camcc_fast_ahb_clk_src[] = { 821 F(19200000, P_BI_TCXO, 1, 0, 0), 822 F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0), 823 F(200000000, P_CAMCC_PLL0_OUT_EVEN, 3, 0, 0), 824 F(300000000, P_CAMCC_PLL0_OUT_MAIN, 4, 0, 0), 825 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), 826 { } 827 }; 828 829 static struct clk_rcg2 camcc_fast_ahb_clk_src = { 830 .cmd_rcgr = 0x703c, 831 .mnd_width = 0, 832 .hid_width = 5, 833 .parent_map = camcc_parent_map_0, 834 .freq_tbl = ftbl_camcc_fast_ahb_clk_src, 835 .clkr.hw.init = &(struct clk_init_data){ 836 .name = "camcc_fast_ahb_clk_src", 837 .parent_data = camcc_parent_data_0, 838 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 839 .ops = &clk_rcg2_ops, 840 }, 841 }; 842 843 static const struct freq_tbl ftbl_camcc_icp_clk_src[] = { 844 F(19200000, P_BI_TCXO, 1, 0, 0), 845 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 846 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 847 { } 848 }; 849 850 static struct clk_rcg2 camcc_icp_clk_src = { 851 .cmd_rcgr = 0xc0b8, 852 .mnd_width = 0, 853 .hid_width = 5, 854 .parent_map = camcc_parent_map_0, 855 .freq_tbl = ftbl_camcc_icp_clk_src, 856 .clkr.hw.init = &(struct clk_init_data){ 857 .name = "camcc_icp_clk_src", 858 .parent_data = camcc_parent_data_0, 859 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 860 .ops = &clk_rcg2_shared_ops, 861 }, 862 }; 863 864 static const struct freq_tbl ftbl_camcc_ife_0_clk_src[] = { 865 F(19200000, P_BI_TCXO, 1, 0, 0), 866 F(400000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), 867 F(558000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), 868 F(637000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), 869 F(760000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), 870 { } 871 }; 872 873 static struct clk_rcg2 camcc_ife_0_clk_src = { 874 .cmd_rcgr = 0xa010, 875 .mnd_width = 0, 876 .hid_width = 5, 877 .parent_map = camcc_parent_map_4, 878 .freq_tbl = ftbl_camcc_ife_0_clk_src, 879 .clkr.hw.init = &(struct clk_init_data){ 880 .name = "camcc_ife_0_clk_src", 881 .parent_data = camcc_parent_data_4, 882 .num_parents = ARRAY_SIZE(camcc_parent_data_4), 883 .flags = CLK_SET_RATE_PARENT, 884 .ops = &clk_rcg2_shared_ops, 885 }, 886 }; 887 888 static const struct freq_tbl ftbl_camcc_ife_0_csid_clk_src[] = { 889 F(19200000, P_BI_TCXO, 1, 0, 0), 890 F(75000000, P_CAMCC_PLL0_OUT_EVEN, 8, 0, 0), 891 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 892 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0), 893 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 894 { } 895 }; 896 897 static struct clk_rcg2 camcc_ife_0_csid_clk_src = { 898 .cmd_rcgr = 0xa03c, 899 .mnd_width = 0, 900 .hid_width = 5, 901 .parent_map = camcc_parent_map_0, 902 .freq_tbl = ftbl_camcc_ife_0_csid_clk_src, 903 .clkr.hw.init = &(struct clk_init_data){ 904 .name = "camcc_ife_0_csid_clk_src", 905 .parent_data = camcc_parent_data_0, 906 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 907 .ops = &clk_rcg2_shared_ops, 908 }, 909 }; 910 911 static const struct freq_tbl ftbl_camcc_ife_1_clk_src[] = { 912 F(19200000, P_BI_TCXO, 1, 0, 0), 913 F(400000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), 914 F(558000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), 915 F(637000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), 916 F(760000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), 917 { } 918 }; 919 920 static struct clk_rcg2 camcc_ife_1_clk_src = { 921 .cmd_rcgr = 0xb010, 922 .mnd_width = 0, 923 .hid_width = 5, 924 .parent_map = camcc_parent_map_5, 925 .freq_tbl = ftbl_camcc_ife_1_clk_src, 926 .clkr.hw.init = &(struct clk_init_data){ 927 .name = "camcc_ife_1_clk_src", 928 .parent_data = camcc_parent_data_5, 929 .num_parents = ARRAY_SIZE(camcc_parent_data_5), 930 .flags = CLK_SET_RATE_PARENT, 931 .ops = &clk_rcg2_shared_ops, 932 }, 933 }; 934 935 static struct clk_rcg2 camcc_ife_1_csid_clk_src = { 936 .cmd_rcgr = 0xb03c, 937 .mnd_width = 0, 938 .hid_width = 5, 939 .parent_map = camcc_parent_map_0, 940 .freq_tbl = ftbl_camcc_ife_0_csid_clk_src, 941 .clkr.hw.init = &(struct clk_init_data){ 942 .name = "camcc_ife_1_csid_clk_src", 943 .parent_data = camcc_parent_data_0, 944 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 945 .ops = &clk_rcg2_shared_ops, 946 }, 947 }; 948 949 static const struct freq_tbl ftbl_camcc_ife_2_clk_src[] = { 950 F(400000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0), 951 F(558000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0), 952 F(637000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0), 953 F(760000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0), 954 { } 955 }; 956 957 static struct clk_rcg2 camcc_ife_2_clk_src = { 958 .cmd_rcgr = 0xf010, 959 .mnd_width = 0, 960 .hid_width = 5, 961 .parent_map = camcc_parent_map_6, 962 .freq_tbl = ftbl_camcc_ife_2_clk_src, 963 .clkr.hw.init = &(struct clk_init_data){ 964 .name = "camcc_ife_2_clk_src", 965 .parent_data = camcc_parent_data_6, 966 .num_parents = ARRAY_SIZE(camcc_parent_data_6), 967 .flags = CLK_SET_RATE_PARENT, 968 .ops = &clk_rcg2_shared_ops, 969 }, 970 }; 971 972 static const struct freq_tbl ftbl_camcc_ife_2_csid_clk_src[] = { 973 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 974 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0), 975 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 976 { } 977 }; 978 979 static struct clk_rcg2 camcc_ife_2_csid_clk_src = { 980 .cmd_rcgr = 0xf03c, 981 .mnd_width = 0, 982 .hid_width = 5, 983 .parent_map = camcc_parent_map_0, 984 .freq_tbl = ftbl_camcc_ife_2_csid_clk_src, 985 .clkr.hw.init = &(struct clk_init_data){ 986 .name = "camcc_ife_2_csid_clk_src", 987 .parent_data = camcc_parent_data_0, 988 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 989 .ops = &clk_rcg2_shared_ops, 990 }, 991 }; 992 993 static const struct freq_tbl ftbl_camcc_ife_3_clk_src[] = { 994 F(19200000, P_BI_TCXO, 1, 0, 0), 995 F(400000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0), 996 F(558000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0), 997 F(637000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0), 998 F(760000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0), 999 { } 1000 }; 1001 1002 static struct clk_rcg2 camcc_ife_3_clk_src = { 1003 .cmd_rcgr = 0xf07c, 1004 .mnd_width = 0, 1005 .hid_width = 5, 1006 .parent_map = camcc_parent_map_7, 1007 .freq_tbl = ftbl_camcc_ife_3_clk_src, 1008 .clkr.hw.init = &(struct clk_init_data){ 1009 .name = "camcc_ife_3_clk_src", 1010 .parent_data = camcc_parent_data_7, 1011 .num_parents = ARRAY_SIZE(camcc_parent_data_7), 1012 .flags = CLK_SET_RATE_PARENT, 1013 .ops = &clk_rcg2_shared_ops, 1014 }, 1015 }; 1016 1017 static struct clk_rcg2 camcc_ife_3_csid_clk_src = { 1018 .cmd_rcgr = 0xf0a8, 1019 .mnd_width = 0, 1020 .hid_width = 5, 1021 .parent_map = camcc_parent_map_0, 1022 .freq_tbl = ftbl_camcc_ife_2_csid_clk_src, 1023 .clkr.hw.init = &(struct clk_init_data){ 1024 .name = "camcc_ife_3_csid_clk_src", 1025 .parent_data = camcc_parent_data_0, 1026 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 1027 .ops = &clk_rcg2_shared_ops, 1028 }, 1029 }; 1030 1031 static const struct freq_tbl ftbl_camcc_ife_lite_0_clk_src[] = { 1032 F(320000000, P_CAMCC_PLL7_OUT_ODD, 1, 0, 0), 1033 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 1034 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0), 1035 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 1036 { } 1037 }; 1038 1039 static struct clk_rcg2 camcc_ife_lite_0_clk_src = { 1040 .cmd_rcgr = 0xc004, 1041 .mnd_width = 0, 1042 .hid_width = 5, 1043 .parent_map = camcc_parent_map_2, 1044 .freq_tbl = ftbl_camcc_ife_lite_0_clk_src, 1045 .clkr.hw.init = &(struct clk_init_data){ 1046 .name = "camcc_ife_lite_0_clk_src", 1047 .parent_data = camcc_parent_data_2, 1048 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 1049 .ops = &clk_rcg2_shared_ops, 1050 }, 1051 }; 1052 1053 static struct clk_rcg2 camcc_ife_lite_0_csid_clk_src = { 1054 .cmd_rcgr = 0xc020, 1055 .mnd_width = 0, 1056 .hid_width = 5, 1057 .parent_map = camcc_parent_map_0, 1058 .freq_tbl = ftbl_camcc_ife_2_csid_clk_src, 1059 .clkr.hw.init = &(struct clk_init_data){ 1060 .name = "camcc_ife_lite_0_csid_clk_src", 1061 .parent_data = camcc_parent_data_0, 1062 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 1063 .ops = &clk_rcg2_shared_ops, 1064 }, 1065 }; 1066 1067 static struct clk_rcg2 camcc_ife_lite_1_clk_src = { 1068 .cmd_rcgr = 0xc048, 1069 .mnd_width = 0, 1070 .hid_width = 5, 1071 .parent_map = camcc_parent_map_2, 1072 .freq_tbl = ftbl_camcc_ife_lite_0_clk_src, 1073 .clkr.hw.init = &(struct clk_init_data){ 1074 .name = "camcc_ife_lite_1_clk_src", 1075 .parent_data = camcc_parent_data_2, 1076 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 1077 .ops = &clk_rcg2_shared_ops, 1078 }, 1079 }; 1080 1081 static struct clk_rcg2 camcc_ife_lite_1_csid_clk_src = { 1082 .cmd_rcgr = 0xc064, 1083 .mnd_width = 0, 1084 .hid_width = 5, 1085 .parent_map = camcc_parent_map_0, 1086 .freq_tbl = ftbl_camcc_ife_2_csid_clk_src, 1087 .clkr.hw.init = &(struct clk_init_data){ 1088 .name = "camcc_ife_lite_1_csid_clk_src", 1089 .parent_data = camcc_parent_data_0, 1090 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 1091 .ops = &clk_rcg2_shared_ops, 1092 }, 1093 }; 1094 1095 static struct clk_rcg2 camcc_ife_lite_2_clk_src = { 1096 .cmd_rcgr = 0xc240, 1097 .mnd_width = 0, 1098 .hid_width = 5, 1099 .parent_map = camcc_parent_map_2, 1100 .freq_tbl = ftbl_camcc_ife_lite_0_clk_src, 1101 .clkr.hw.init = &(struct clk_init_data){ 1102 .name = "camcc_ife_lite_2_clk_src", 1103 .parent_data = camcc_parent_data_2, 1104 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 1105 .ops = &clk_rcg2_shared_ops, 1106 }, 1107 }; 1108 1109 static struct clk_rcg2 camcc_ife_lite_2_csid_clk_src = { 1110 .cmd_rcgr = 0xc25c, 1111 .mnd_width = 0, 1112 .hid_width = 5, 1113 .parent_map = camcc_parent_map_0, 1114 .freq_tbl = ftbl_camcc_ife_2_csid_clk_src, 1115 .clkr.hw.init = &(struct clk_init_data){ 1116 .name = "camcc_ife_lite_2_csid_clk_src", 1117 .parent_data = camcc_parent_data_0, 1118 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 1119 .ops = &clk_rcg2_shared_ops, 1120 }, 1121 }; 1122 1123 static struct clk_rcg2 camcc_ife_lite_3_clk_src = { 1124 .cmd_rcgr = 0xc284, 1125 .mnd_width = 0, 1126 .hid_width = 5, 1127 .parent_map = camcc_parent_map_2, 1128 .freq_tbl = ftbl_camcc_ife_lite_0_clk_src, 1129 .clkr.hw.init = &(struct clk_init_data){ 1130 .name = "camcc_ife_lite_3_clk_src", 1131 .parent_data = camcc_parent_data_2, 1132 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 1133 .ops = &clk_rcg2_shared_ops, 1134 }, 1135 }; 1136 1137 static struct clk_rcg2 camcc_ife_lite_3_csid_clk_src = { 1138 .cmd_rcgr = 0xc2a0, 1139 .mnd_width = 0, 1140 .hid_width = 5, 1141 .parent_map = camcc_parent_map_0, 1142 .freq_tbl = ftbl_camcc_ife_2_csid_clk_src, 1143 .clkr.hw.init = &(struct clk_init_data){ 1144 .name = "camcc_ife_lite_3_csid_clk_src", 1145 .parent_data = camcc_parent_data_0, 1146 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 1147 .ops = &clk_rcg2_shared_ops, 1148 }, 1149 }; 1150 1151 static const struct freq_tbl ftbl_camcc_ipe_0_clk_src[] = { 1152 F(19200000, P_BI_TCXO, 1, 0, 0), 1153 F(320000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), 1154 F(475000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), 1155 F(520000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), 1156 F(600000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), 1157 { } 1158 }; 1159 1160 static struct clk_rcg2 camcc_ipe_0_clk_src = { 1161 .cmd_rcgr = 0x8010, 1162 .mnd_width = 0, 1163 .hid_width = 5, 1164 .parent_map = camcc_parent_map_8, 1165 .freq_tbl = ftbl_camcc_ipe_0_clk_src, 1166 .clkr.hw.init = &(struct clk_init_data){ 1167 .name = "camcc_ipe_0_clk_src", 1168 .parent_data = camcc_parent_data_8, 1169 .num_parents = ARRAY_SIZE(camcc_parent_data_8), 1170 .flags = CLK_SET_RATE_PARENT, 1171 .ops = &clk_rcg2_shared_ops, 1172 }, 1173 }; 1174 1175 static const struct freq_tbl ftbl_camcc_jpeg_clk_src[] = { 1176 F(19200000, P_BI_TCXO, 1, 0, 0), 1177 F(200000000, P_CAMCC_PLL0_OUT_ODD, 2, 0, 0), 1178 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 1179 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0), 1180 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 1181 { } 1182 }; 1183 1184 static struct clk_rcg2 camcc_jpeg_clk_src = { 1185 .cmd_rcgr = 0xc08c, 1186 .mnd_width = 0, 1187 .hid_width = 5, 1188 .parent_map = camcc_parent_map_0, 1189 .freq_tbl = ftbl_camcc_jpeg_clk_src, 1190 .clkr.hw.init = &(struct clk_init_data){ 1191 .name = "camcc_jpeg_clk_src", 1192 .parent_data = camcc_parent_data_0, 1193 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 1194 .ops = &clk_rcg2_shared_ops, 1195 }, 1196 }; 1197 1198 static const struct freq_tbl ftbl_camcc_lrme_clk_src[] = { 1199 F(240000000, P_CAMCC_PLL7_OUT_EVEN, 2, 0, 0), 1200 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0), 1201 F(320000000, P_CAMCC_PLL7_OUT_ODD, 1, 0, 0), 1202 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), 1203 { } 1204 }; 1205 1206 static struct clk_rcg2 camcc_lrme_clk_src = { 1207 .cmd_rcgr = 0xc144, 1208 .mnd_width = 0, 1209 .hid_width = 5, 1210 .parent_map = camcc_parent_map_2, 1211 .freq_tbl = ftbl_camcc_lrme_clk_src, 1212 .clkr.hw.init = &(struct clk_init_data){ 1213 .name = "camcc_lrme_clk_src", 1214 .parent_data = camcc_parent_data_2, 1215 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 1216 .ops = &clk_rcg2_shared_ops, 1217 }, 1218 }; 1219 1220 static const struct freq_tbl ftbl_camcc_mclk0_clk_src[] = { 1221 F(19200000, P_BI_TCXO, 1, 0, 0), 1222 F(24000000, P_CAMCC_PLL2_OUT_EARLY, 10, 1, 4), 1223 F(64000000, P_CAMCC_PLL2_OUT_EARLY, 15, 0, 0), 1224 { } 1225 }; 1226 1227 static struct clk_rcg2 camcc_mclk0_clk_src = { 1228 .cmd_rcgr = 0x5004, 1229 .mnd_width = 8, 1230 .hid_width = 5, 1231 .parent_map = camcc_parent_map_1, 1232 .freq_tbl = ftbl_camcc_mclk0_clk_src, 1233 .clkr.hw.init = &(struct clk_init_data){ 1234 .name = "camcc_mclk0_clk_src", 1235 .parent_data = camcc_parent_data_1, 1236 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 1237 .ops = &clk_rcg2_ops, 1238 }, 1239 }; 1240 1241 static struct clk_rcg2 camcc_mclk1_clk_src = { 1242 .cmd_rcgr = 0x5024, 1243 .mnd_width = 8, 1244 .hid_width = 5, 1245 .parent_map = camcc_parent_map_1, 1246 .freq_tbl = ftbl_camcc_mclk0_clk_src, 1247 .clkr.hw.init = &(struct clk_init_data){ 1248 .name = "camcc_mclk1_clk_src", 1249 .parent_data = camcc_parent_data_1, 1250 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 1251 .ops = &clk_rcg2_ops, 1252 }, 1253 }; 1254 1255 static struct clk_rcg2 camcc_mclk2_clk_src = { 1256 .cmd_rcgr = 0x5044, 1257 .mnd_width = 8, 1258 .hid_width = 5, 1259 .parent_map = camcc_parent_map_1, 1260 .freq_tbl = ftbl_camcc_mclk0_clk_src, 1261 .clkr.hw.init = &(struct clk_init_data){ 1262 .name = "camcc_mclk2_clk_src", 1263 .parent_data = camcc_parent_data_1, 1264 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 1265 .ops = &clk_rcg2_ops, 1266 }, 1267 }; 1268 1269 static struct clk_rcg2 camcc_mclk3_clk_src = { 1270 .cmd_rcgr = 0x5064, 1271 .mnd_width = 8, 1272 .hid_width = 5, 1273 .parent_map = camcc_parent_map_1, 1274 .freq_tbl = ftbl_camcc_mclk0_clk_src, 1275 .clkr.hw.init = &(struct clk_init_data){ 1276 .name = "camcc_mclk3_clk_src", 1277 .parent_data = camcc_parent_data_1, 1278 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 1279 .ops = &clk_rcg2_ops, 1280 }, 1281 }; 1282 1283 static struct clk_rcg2 camcc_mclk4_clk_src = { 1284 .cmd_rcgr = 0x5084, 1285 .mnd_width = 8, 1286 .hid_width = 5, 1287 .parent_map = camcc_parent_map_1, 1288 .freq_tbl = ftbl_camcc_mclk0_clk_src, 1289 .clkr.hw.init = &(struct clk_init_data){ 1290 .name = "camcc_mclk4_clk_src", 1291 .parent_data = camcc_parent_data_1, 1292 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 1293 .ops = &clk_rcg2_ops, 1294 }, 1295 }; 1296 1297 static struct clk_rcg2 camcc_mclk5_clk_src = { 1298 .cmd_rcgr = 0x50a4, 1299 .mnd_width = 8, 1300 .hid_width = 5, 1301 .parent_map = camcc_parent_map_1, 1302 .freq_tbl = ftbl_camcc_mclk0_clk_src, 1303 .clkr.hw.init = &(struct clk_init_data){ 1304 .name = "camcc_mclk5_clk_src", 1305 .parent_data = camcc_parent_data_1, 1306 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 1307 .ops = &clk_rcg2_ops, 1308 }, 1309 }; 1310 1311 static struct clk_rcg2 camcc_mclk6_clk_src = { 1312 .cmd_rcgr = 0x50c4, 1313 .mnd_width = 8, 1314 .hid_width = 5, 1315 .parent_map = camcc_parent_map_1, 1316 .freq_tbl = ftbl_camcc_mclk0_clk_src, 1317 .clkr.hw.init = &(struct clk_init_data){ 1318 .name = "camcc_mclk6_clk_src", 1319 .parent_data = camcc_parent_data_1, 1320 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 1321 .ops = &clk_rcg2_ops, 1322 }, 1323 }; 1324 1325 static struct clk_rcg2 camcc_mclk7_clk_src = { 1326 .cmd_rcgr = 0x50e4, 1327 .mnd_width = 8, 1328 .hid_width = 5, 1329 .parent_map = camcc_parent_map_1, 1330 .freq_tbl = ftbl_camcc_mclk0_clk_src, 1331 .clkr.hw.init = &(struct clk_init_data){ 1332 .name = "camcc_mclk7_clk_src", 1333 .parent_data = camcc_parent_data_1, 1334 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 1335 .ops = &clk_rcg2_ops, 1336 }, 1337 }; 1338 1339 static const struct freq_tbl ftbl_camcc_sleep_clk_src[] = { 1340 F(32000, P_SLEEP_CLK, 1, 0, 0), 1341 { } 1342 }; 1343 1344 static struct clk_rcg2 camcc_sleep_clk_src = { 1345 .cmd_rcgr = 0xc1e8, 1346 .mnd_width = 0, 1347 .hid_width = 5, 1348 .parent_map = camcc_parent_map_9, 1349 .freq_tbl = ftbl_camcc_sleep_clk_src, 1350 .clkr.hw.init = &(struct clk_init_data){ 1351 .name = "camcc_sleep_clk_src", 1352 .parent_data = camcc_parent_data_9, 1353 .num_parents = ARRAY_SIZE(camcc_parent_data_9), 1354 .ops = &clk_rcg2_ops, 1355 }, 1356 }; 1357 1358 static const struct freq_tbl ftbl_camcc_slow_ahb_clk_src[] = { 1359 F(19200000, P_BI_TCXO, 1, 0, 0), 1360 F(80000000, P_CAMCC_PLL7_OUT_EVEN, 6, 0, 0), 1361 { } 1362 }; 1363 1364 static struct clk_rcg2 camcc_slow_ahb_clk_src = { 1365 .cmd_rcgr = 0x7058, 1366 .mnd_width = 8, 1367 .hid_width = 5, 1368 .parent_map = camcc_parent_map_0, 1369 .freq_tbl = ftbl_camcc_slow_ahb_clk_src, 1370 .clkr.hw.init = &(struct clk_init_data){ 1371 .name = "camcc_slow_ahb_clk_src", 1372 .parent_data = camcc_parent_data_0, 1373 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 1374 .ops = &clk_rcg2_ops, 1375 }, 1376 }; 1377 1378 static const struct freq_tbl ftbl_camcc_xo_clk_src[] = { 1379 F(19200000, P_BI_TCXO, 1, 0, 0), 1380 { } 1381 }; 1382 1383 static struct clk_rcg2 camcc_xo_clk_src = { 1384 .cmd_rcgr = 0xc1cc, 1385 .mnd_width = 0, 1386 .hid_width = 5, 1387 .parent_map = camcc_parent_map_10, 1388 .freq_tbl = ftbl_camcc_xo_clk_src, 1389 .clkr.hw.init = &(struct clk_init_data){ 1390 .name = "camcc_xo_clk_src", 1391 .parent_data = camcc_parent_data_10_ao, 1392 .num_parents = ARRAY_SIZE(camcc_parent_data_10_ao), 1393 .ops = &clk_rcg2_ops, 1394 }, 1395 }; 1396 1397 static struct clk_branch camcc_bps_ahb_clk = { 1398 .halt_reg = 0x7070, 1399 .halt_check = BRANCH_HALT, 1400 .clkr = { 1401 .enable_reg = 0x7070, 1402 .enable_mask = BIT(0), 1403 .hw.init = &(struct clk_init_data){ 1404 .name = "camcc_bps_ahb_clk", 1405 .parent_hws = (const struct clk_hw*[]){ 1406 &camcc_slow_ahb_clk_src.clkr.hw, 1407 }, 1408 .num_parents = 1, 1409 .flags = CLK_SET_RATE_PARENT, 1410 .ops = &clk_branch2_ops, 1411 }, 1412 }, 1413 }; 1414 1415 static struct clk_branch camcc_bps_areg_clk = { 1416 .halt_reg = 0x7054, 1417 .halt_check = BRANCH_HALT, 1418 .clkr = { 1419 .enable_reg = 0x7054, 1420 .enable_mask = BIT(0), 1421 .hw.init = &(struct clk_init_data){ 1422 .name = "camcc_bps_areg_clk", 1423 .parent_hws = (const struct clk_hw*[]){ 1424 &camcc_fast_ahb_clk_src.clkr.hw, 1425 }, 1426 .num_parents = 1, 1427 .flags = CLK_SET_RATE_PARENT, 1428 .ops = &clk_branch2_ops, 1429 }, 1430 }, 1431 }; 1432 1433 static struct clk_branch camcc_bps_axi_clk = { 1434 .halt_reg = 0x7038, 1435 .halt_check = BRANCH_HALT, 1436 .clkr = { 1437 .enable_reg = 0x7038, 1438 .enable_mask = BIT(0), 1439 .hw.init = &(struct clk_init_data){ 1440 .name = "camcc_bps_axi_clk", 1441 .parent_hws = (const struct clk_hw*[]){ 1442 &camcc_camnoc_axi_clk_src.clkr.hw, 1443 }, 1444 .num_parents = 1, 1445 .flags = CLK_SET_RATE_PARENT, 1446 .ops = &clk_branch2_ops, 1447 }, 1448 }, 1449 }; 1450 1451 static struct clk_branch camcc_bps_clk = { 1452 .halt_reg = 0x7028, 1453 .halt_check = BRANCH_HALT, 1454 .clkr = { 1455 .enable_reg = 0x7028, 1456 .enable_mask = BIT(0), 1457 .hw.init = &(struct clk_init_data){ 1458 .name = "camcc_bps_clk", 1459 .parent_hws = (const struct clk_hw*[]){ 1460 &camcc_bps_clk_src.clkr.hw, 1461 }, 1462 .num_parents = 1, 1463 .flags = CLK_SET_RATE_PARENT, 1464 .ops = &clk_branch2_ops, 1465 }, 1466 }, 1467 }; 1468 1469 static struct clk_branch camcc_camnoc_axi_clk = { 1470 .halt_reg = 0xc18c, 1471 .halt_check = BRANCH_HALT, 1472 .clkr = { 1473 .enable_reg = 0xc18c, 1474 .enable_mask = BIT(0), 1475 .hw.init = &(struct clk_init_data){ 1476 .name = "camcc_camnoc_axi_clk", 1477 .parent_hws = (const struct clk_hw*[]){ 1478 &camcc_camnoc_axi_clk_src.clkr.hw, 1479 }, 1480 .num_parents = 1, 1481 .flags = CLK_SET_RATE_PARENT, 1482 .ops = &clk_branch2_ops, 1483 }, 1484 }, 1485 }; 1486 1487 static struct clk_branch camcc_camnoc_dcd_xo_clk = { 1488 .halt_reg = 0xc194, 1489 .halt_check = BRANCH_HALT, 1490 .clkr = { 1491 .enable_reg = 0xc194, 1492 .enable_mask = BIT(0), 1493 .hw.init = &(struct clk_init_data){ 1494 .name = "camcc_camnoc_dcd_xo_clk", 1495 .parent_hws = (const struct clk_hw*[]){ 1496 &camcc_xo_clk_src.clkr.hw, 1497 }, 1498 .num_parents = 1, 1499 .flags = CLK_SET_RATE_PARENT, 1500 .ops = &clk_branch2_ops, 1501 }, 1502 }, 1503 }; 1504 1505 static struct clk_branch camcc_cci_0_clk = { 1506 .halt_reg = 0xc120, 1507 .halt_check = BRANCH_HALT, 1508 .clkr = { 1509 .enable_reg = 0xc120, 1510 .enable_mask = BIT(0), 1511 .hw.init = &(struct clk_init_data){ 1512 .name = "camcc_cci_0_clk", 1513 .parent_hws = (const struct clk_hw*[]){ 1514 &camcc_cci_0_clk_src.clkr.hw, 1515 }, 1516 .num_parents = 1, 1517 .flags = CLK_SET_RATE_PARENT, 1518 .ops = &clk_branch2_ops, 1519 }, 1520 }, 1521 }; 1522 1523 static struct clk_branch camcc_cci_1_clk = { 1524 .halt_reg = 0xc13c, 1525 .halt_check = BRANCH_HALT, 1526 .clkr = { 1527 .enable_reg = 0xc13c, 1528 .enable_mask = BIT(0), 1529 .hw.init = &(struct clk_init_data){ 1530 .name = "camcc_cci_1_clk", 1531 .parent_hws = (const struct clk_hw*[]){ 1532 &camcc_cci_1_clk_src.clkr.hw, 1533 }, 1534 .num_parents = 1, 1535 .flags = CLK_SET_RATE_PARENT, 1536 .ops = &clk_branch2_ops, 1537 }, 1538 }, 1539 }; 1540 1541 static struct clk_branch camcc_cci_2_clk = { 1542 .halt_reg = 0xc21c, 1543 .halt_check = BRANCH_HALT, 1544 .clkr = { 1545 .enable_reg = 0xc21c, 1546 .enable_mask = BIT(0), 1547 .hw.init = &(struct clk_init_data){ 1548 .name = "camcc_cci_2_clk", 1549 .parent_hws = (const struct clk_hw*[]){ 1550 &camcc_cci_2_clk_src.clkr.hw, 1551 }, 1552 .num_parents = 1, 1553 .flags = CLK_SET_RATE_PARENT, 1554 .ops = &clk_branch2_ops, 1555 }, 1556 }, 1557 }; 1558 1559 static struct clk_branch camcc_cci_3_clk = { 1560 .halt_reg = 0xc238, 1561 .halt_check = BRANCH_HALT, 1562 .clkr = { 1563 .enable_reg = 0xc238, 1564 .enable_mask = BIT(0), 1565 .hw.init = &(struct clk_init_data){ 1566 .name = "camcc_cci_3_clk", 1567 .parent_hws = (const struct clk_hw*[]){ 1568 &camcc_cci_3_clk_src.clkr.hw, 1569 }, 1570 .num_parents = 1, 1571 .flags = CLK_SET_RATE_PARENT, 1572 .ops = &clk_branch2_ops, 1573 }, 1574 }, 1575 }; 1576 1577 static struct clk_branch camcc_core_ahb_clk = { 1578 .halt_reg = 0xc1c8, 1579 .halt_check = BRANCH_HALT_DELAY, 1580 .clkr = { 1581 .enable_reg = 0xc1c8, 1582 .enable_mask = BIT(0), 1583 .hw.init = &(struct clk_init_data){ 1584 .name = "camcc_core_ahb_clk", 1585 .parent_hws = (const struct clk_hw*[]){ 1586 &camcc_slow_ahb_clk_src.clkr.hw, 1587 }, 1588 .num_parents = 1, 1589 .flags = CLK_SET_RATE_PARENT, 1590 .ops = &clk_branch2_ops, 1591 }, 1592 }, 1593 }; 1594 1595 static struct clk_branch camcc_cpas_ahb_clk = { 1596 .halt_reg = 0xc168, 1597 .halt_check = BRANCH_HALT, 1598 .clkr = { 1599 .enable_reg = 0xc168, 1600 .enable_mask = BIT(0), 1601 .hw.init = &(struct clk_init_data){ 1602 .name = "camcc_cpas_ahb_clk", 1603 .parent_hws = (const struct clk_hw*[]){ 1604 &camcc_slow_ahb_clk_src.clkr.hw, 1605 }, 1606 .num_parents = 1, 1607 .flags = CLK_SET_RATE_PARENT, 1608 .ops = &clk_branch2_ops, 1609 }, 1610 }, 1611 }; 1612 1613 static struct clk_branch camcc_csi0phytimer_clk = { 1614 .halt_reg = 0x601c, 1615 .halt_check = BRANCH_HALT, 1616 .clkr = { 1617 .enable_reg = 0x601c, 1618 .enable_mask = BIT(0), 1619 .hw.init = &(struct clk_init_data){ 1620 .name = "camcc_csi0phytimer_clk", 1621 .parent_hws = (const struct clk_hw*[]){ 1622 &camcc_csi0phytimer_clk_src.clkr.hw, 1623 }, 1624 .num_parents = 1, 1625 .flags = CLK_SET_RATE_PARENT, 1626 .ops = &clk_branch2_ops, 1627 }, 1628 }, 1629 }; 1630 1631 static struct clk_branch camcc_csi1phytimer_clk = { 1632 .halt_reg = 0x6040, 1633 .halt_check = BRANCH_HALT, 1634 .clkr = { 1635 .enable_reg = 0x6040, 1636 .enable_mask = BIT(0), 1637 .hw.init = &(struct clk_init_data){ 1638 .name = "camcc_csi1phytimer_clk", 1639 .parent_hws = (const struct clk_hw*[]){ 1640 &camcc_csi1phytimer_clk_src.clkr.hw, 1641 }, 1642 .num_parents = 1, 1643 .flags = CLK_SET_RATE_PARENT, 1644 .ops = &clk_branch2_ops, 1645 }, 1646 }, 1647 }; 1648 1649 static struct clk_branch camcc_csi2phytimer_clk = { 1650 .halt_reg = 0x6064, 1651 .halt_check = BRANCH_HALT, 1652 .clkr = { 1653 .enable_reg = 0x6064, 1654 .enable_mask = BIT(0), 1655 .hw.init = &(struct clk_init_data){ 1656 .name = "camcc_csi2phytimer_clk", 1657 .parent_hws = (const struct clk_hw*[]){ 1658 &camcc_csi2phytimer_clk_src.clkr.hw, 1659 }, 1660 .num_parents = 1, 1661 .flags = CLK_SET_RATE_PARENT, 1662 .ops = &clk_branch2_ops, 1663 }, 1664 }, 1665 }; 1666 1667 static struct clk_branch camcc_csi3phytimer_clk = { 1668 .halt_reg = 0x608c, 1669 .halt_check = BRANCH_HALT, 1670 .clkr = { 1671 .enable_reg = 0x608c, 1672 .enable_mask = BIT(0), 1673 .hw.init = &(struct clk_init_data){ 1674 .name = "camcc_csi3phytimer_clk", 1675 .parent_hws = (const struct clk_hw*[]){ 1676 &camcc_csi3phytimer_clk_src.clkr.hw, 1677 }, 1678 .num_parents = 1, 1679 .flags = CLK_SET_RATE_PARENT, 1680 .ops = &clk_branch2_ops, 1681 }, 1682 }, 1683 }; 1684 1685 static struct clk_branch camcc_csiphy0_clk = { 1686 .halt_reg = 0x6020, 1687 .halt_check = BRANCH_HALT, 1688 .clkr = { 1689 .enable_reg = 0x6020, 1690 .enable_mask = BIT(0), 1691 .hw.init = &(struct clk_init_data){ 1692 .name = "camcc_csiphy0_clk", 1693 .parent_hws = (const struct clk_hw*[]){ 1694 &camcc_cphy_rx_clk_src.clkr.hw, 1695 }, 1696 .num_parents = 1, 1697 .flags = CLK_SET_RATE_PARENT, 1698 .ops = &clk_branch2_ops, 1699 }, 1700 }, 1701 }; 1702 1703 static struct clk_branch camcc_csiphy1_clk = { 1704 .halt_reg = 0x6044, 1705 .halt_check = BRANCH_HALT, 1706 .clkr = { 1707 .enable_reg = 0x6044, 1708 .enable_mask = BIT(0), 1709 .hw.init = &(struct clk_init_data){ 1710 .name = "camcc_csiphy1_clk", 1711 .parent_hws = (const struct clk_hw*[]){ 1712 &camcc_cphy_rx_clk_src.clkr.hw, 1713 }, 1714 .num_parents = 1, 1715 .flags = CLK_SET_RATE_PARENT, 1716 .ops = &clk_branch2_ops, 1717 }, 1718 }, 1719 }; 1720 1721 static struct clk_branch camcc_csiphy2_clk = { 1722 .halt_reg = 0x6068, 1723 .halt_check = BRANCH_HALT, 1724 .clkr = { 1725 .enable_reg = 0x6068, 1726 .enable_mask = BIT(0), 1727 .hw.init = &(struct clk_init_data){ 1728 .name = "camcc_csiphy2_clk", 1729 .parent_hws = (const struct clk_hw*[]){ 1730 &camcc_cphy_rx_clk_src.clkr.hw, 1731 }, 1732 .num_parents = 1, 1733 .flags = CLK_SET_RATE_PARENT, 1734 .ops = &clk_branch2_ops, 1735 }, 1736 }, 1737 }; 1738 1739 static struct clk_branch camcc_csiphy3_clk = { 1740 .halt_reg = 0x6090, 1741 .halt_check = BRANCH_HALT, 1742 .clkr = { 1743 .enable_reg = 0x6090, 1744 .enable_mask = BIT(0), 1745 .hw.init = &(struct clk_init_data){ 1746 .name = "camcc_csiphy3_clk", 1747 .parent_hws = (const struct clk_hw*[]){ 1748 &camcc_cphy_rx_clk_src.clkr.hw, 1749 }, 1750 .num_parents = 1, 1751 .flags = CLK_SET_RATE_PARENT, 1752 .ops = &clk_branch2_ops, 1753 }, 1754 }, 1755 }; 1756 1757 static struct clk_branch camcc_gdsc_clk = { 1758 .halt_reg = 0xc1e4, 1759 .halt_check = BRANCH_HALT, 1760 .clkr = { 1761 .enable_reg = 0xc1e4, 1762 .enable_mask = BIT(0), 1763 .hw.init = &(struct clk_init_data){ 1764 .name = "camcc_gdsc_clk", 1765 .parent_hws = (const struct clk_hw*[]){ 1766 &camcc_xo_clk_src.clkr.hw, 1767 }, 1768 .num_parents = 1, 1769 .flags = CLK_SET_RATE_PARENT, 1770 .ops = &clk_branch2_ops, 1771 }, 1772 }, 1773 }; 1774 1775 static struct clk_branch camcc_icp_ahb_clk = { 1776 .halt_reg = 0xc0d8, 1777 .halt_check = BRANCH_HALT, 1778 .clkr = { 1779 .enable_reg = 0xc0d8, 1780 .enable_mask = BIT(0), 1781 .hw.init = &(struct clk_init_data){ 1782 .name = "camcc_icp_ahb_clk", 1783 .parent_hws = (const struct clk_hw*[]){ 1784 &camcc_slow_ahb_clk_src.clkr.hw, 1785 }, 1786 .num_parents = 1, 1787 .flags = CLK_SET_RATE_PARENT, 1788 .ops = &clk_branch2_ops, 1789 }, 1790 }, 1791 }; 1792 1793 static struct clk_branch camcc_icp_clk = { 1794 .halt_reg = 0xc0d0, 1795 .halt_check = BRANCH_HALT, 1796 .clkr = { 1797 .enable_reg = 0xc0d0, 1798 .enable_mask = BIT(0), 1799 .hw.init = &(struct clk_init_data){ 1800 .name = "camcc_icp_clk", 1801 .parent_hws = (const struct clk_hw*[]){ 1802 &camcc_icp_clk_src.clkr.hw, 1803 }, 1804 .num_parents = 1, 1805 .flags = CLK_SET_RATE_PARENT, 1806 .ops = &clk_branch2_ops, 1807 }, 1808 }, 1809 }; 1810 1811 static struct clk_branch camcc_ife_0_axi_clk = { 1812 .halt_reg = 0xa080, 1813 .halt_check = BRANCH_HALT, 1814 .clkr = { 1815 .enable_reg = 0xa080, 1816 .enable_mask = BIT(0), 1817 .hw.init = &(struct clk_init_data){ 1818 .name = "camcc_ife_0_axi_clk", 1819 .parent_hws = (const struct clk_hw*[]){ 1820 &camcc_camnoc_axi_clk_src.clkr.hw, 1821 }, 1822 .num_parents = 1, 1823 .flags = CLK_SET_RATE_PARENT, 1824 .ops = &clk_branch2_ops, 1825 }, 1826 }, 1827 }; 1828 1829 static struct clk_branch camcc_ife_0_clk = { 1830 .halt_reg = 0xa028, 1831 .halt_check = BRANCH_HALT, 1832 .clkr = { 1833 .enable_reg = 0xa028, 1834 .enable_mask = BIT(0), 1835 .hw.init = &(struct clk_init_data){ 1836 .name = "camcc_ife_0_clk", 1837 .parent_hws = (const struct clk_hw*[]){ 1838 &camcc_ife_0_clk_src.clkr.hw, 1839 }, 1840 .num_parents = 1, 1841 .flags = CLK_SET_RATE_PARENT, 1842 .ops = &clk_branch2_ops, 1843 }, 1844 }, 1845 }; 1846 1847 static struct clk_branch camcc_ife_0_cphy_rx_clk = { 1848 .halt_reg = 0xa07c, 1849 .halt_check = BRANCH_HALT, 1850 .clkr = { 1851 .enable_reg = 0xa07c, 1852 .enable_mask = BIT(0), 1853 .hw.init = &(struct clk_init_data){ 1854 .name = "camcc_ife_0_cphy_rx_clk", 1855 .parent_hws = (const struct clk_hw*[]){ 1856 &camcc_cphy_rx_clk_src.clkr.hw, 1857 }, 1858 .num_parents = 1, 1859 .flags = CLK_SET_RATE_PARENT, 1860 .ops = &clk_branch2_ops, 1861 }, 1862 }, 1863 }; 1864 1865 static struct clk_branch camcc_ife_0_csid_clk = { 1866 .halt_reg = 0xa054, 1867 .halt_check = BRANCH_HALT, 1868 .clkr = { 1869 .enable_reg = 0xa054, 1870 .enable_mask = BIT(0), 1871 .hw.init = &(struct clk_init_data){ 1872 .name = "camcc_ife_0_csid_clk", 1873 .parent_hws = (const struct clk_hw*[]){ 1874 &camcc_ife_0_csid_clk_src.clkr.hw, 1875 }, 1876 .num_parents = 1, 1877 .flags = CLK_SET_RATE_PARENT, 1878 .ops = &clk_branch2_ops, 1879 }, 1880 }, 1881 }; 1882 1883 static struct clk_branch camcc_ife_0_dsp_clk = { 1884 .halt_reg = 0xa038, 1885 .halt_check = BRANCH_HALT, 1886 .clkr = { 1887 .enable_reg = 0xa038, 1888 .enable_mask = BIT(0), 1889 .hw.init = &(struct clk_init_data){ 1890 .name = "camcc_ife_0_dsp_clk", 1891 .parent_hws = (const struct clk_hw*[]){ 1892 &camcc_ife_0_clk_src.clkr.hw, 1893 }, 1894 .num_parents = 1, 1895 .flags = CLK_SET_RATE_PARENT, 1896 .ops = &clk_branch2_ops, 1897 }, 1898 }, 1899 }; 1900 1901 static struct clk_branch camcc_ife_1_axi_clk = { 1902 .halt_reg = 0xb068, 1903 .halt_check = BRANCH_HALT, 1904 .clkr = { 1905 .enable_reg = 0xb068, 1906 .enable_mask = BIT(0), 1907 .hw.init = &(struct clk_init_data){ 1908 .name = "camcc_ife_1_axi_clk", 1909 .parent_hws = (const struct clk_hw*[]){ 1910 &camcc_camnoc_axi_clk_src.clkr.hw, 1911 }, 1912 .num_parents = 1, 1913 .flags = CLK_SET_RATE_PARENT, 1914 .ops = &clk_branch2_ops, 1915 }, 1916 }, 1917 }; 1918 1919 static struct clk_branch camcc_ife_1_clk = { 1920 .halt_reg = 0xb028, 1921 .halt_check = BRANCH_HALT, 1922 .clkr = { 1923 .enable_reg = 0xb028, 1924 .enable_mask = BIT(0), 1925 .hw.init = &(struct clk_init_data){ 1926 .name = "camcc_ife_1_clk", 1927 .parent_hws = (const struct clk_hw*[]){ 1928 &camcc_ife_1_clk_src.clkr.hw, 1929 }, 1930 .num_parents = 1, 1931 .flags = CLK_SET_RATE_PARENT, 1932 .ops = &clk_branch2_ops, 1933 }, 1934 }, 1935 }; 1936 1937 static struct clk_branch camcc_ife_1_cphy_rx_clk = { 1938 .halt_reg = 0xb064, 1939 .halt_check = BRANCH_HALT, 1940 .clkr = { 1941 .enable_reg = 0xb064, 1942 .enable_mask = BIT(0), 1943 .hw.init = &(struct clk_init_data){ 1944 .name = "camcc_ife_1_cphy_rx_clk", 1945 .parent_hws = (const struct clk_hw*[]){ 1946 &camcc_cphy_rx_clk_src.clkr.hw, 1947 }, 1948 .num_parents = 1, 1949 .flags = CLK_SET_RATE_PARENT, 1950 .ops = &clk_branch2_ops, 1951 }, 1952 }, 1953 }; 1954 1955 static struct clk_branch camcc_ife_1_csid_clk = { 1956 .halt_reg = 0xb054, 1957 .halt_check = BRANCH_HALT, 1958 .clkr = { 1959 .enable_reg = 0xb054, 1960 .enable_mask = BIT(0), 1961 .hw.init = &(struct clk_init_data){ 1962 .name = "camcc_ife_1_csid_clk", 1963 .parent_hws = (const struct clk_hw*[]){ 1964 &camcc_ife_1_csid_clk_src.clkr.hw, 1965 }, 1966 .num_parents = 1, 1967 .flags = CLK_SET_RATE_PARENT, 1968 .ops = &clk_branch2_ops, 1969 }, 1970 }, 1971 }; 1972 1973 static struct clk_branch camcc_ife_1_dsp_clk = { 1974 .halt_reg = 0xb038, 1975 .halt_check = BRANCH_HALT, 1976 .clkr = { 1977 .enable_reg = 0xb038, 1978 .enable_mask = BIT(0), 1979 .hw.init = &(struct clk_init_data){ 1980 .name = "camcc_ife_1_dsp_clk", 1981 .parent_hws = (const struct clk_hw*[]){ 1982 &camcc_ife_1_clk_src.clkr.hw, 1983 }, 1984 .num_parents = 1, 1985 .flags = CLK_SET_RATE_PARENT, 1986 .ops = &clk_branch2_ops, 1987 }, 1988 }, 1989 }; 1990 1991 static struct clk_branch camcc_ife_2_axi_clk = { 1992 .halt_reg = 0xf068, 1993 .halt_check = BRANCH_HALT, 1994 .clkr = { 1995 .enable_reg = 0xf068, 1996 .enable_mask = BIT(0), 1997 .hw.init = &(struct clk_init_data){ 1998 .name = "camcc_ife_2_axi_clk", 1999 .parent_hws = (const struct clk_hw*[]){ 2000 &camcc_camnoc_axi_clk_src.clkr.hw, 2001 }, 2002 .num_parents = 1, 2003 .flags = CLK_SET_RATE_PARENT, 2004 .ops = &clk_branch2_ops, 2005 }, 2006 }, 2007 }; 2008 2009 static struct clk_branch camcc_ife_2_clk = { 2010 .halt_reg = 0xf028, 2011 .halt_check = BRANCH_HALT, 2012 .clkr = { 2013 .enable_reg = 0xf028, 2014 .enable_mask = BIT(0), 2015 .hw.init = &(struct clk_init_data){ 2016 .name = "camcc_ife_2_clk", 2017 .parent_hws = (const struct clk_hw*[]){ 2018 &camcc_ife_2_clk_src.clkr.hw, 2019 }, 2020 .num_parents = 1, 2021 .flags = CLK_SET_RATE_PARENT, 2022 .ops = &clk_branch2_ops, 2023 }, 2024 }, 2025 }; 2026 2027 static struct clk_branch camcc_ife_2_cphy_rx_clk = { 2028 .halt_reg = 0xf064, 2029 .halt_check = BRANCH_HALT, 2030 .clkr = { 2031 .enable_reg = 0xf064, 2032 .enable_mask = BIT(0), 2033 .hw.init = &(struct clk_init_data){ 2034 .name = "camcc_ife_2_cphy_rx_clk", 2035 .parent_hws = (const struct clk_hw*[]){ 2036 &camcc_cphy_rx_clk_src.clkr.hw, 2037 }, 2038 .num_parents = 1, 2039 .flags = CLK_SET_RATE_PARENT, 2040 .ops = &clk_branch2_ops, 2041 }, 2042 }, 2043 }; 2044 2045 static struct clk_branch camcc_ife_2_csid_clk = { 2046 .halt_reg = 0xf054, 2047 .halt_check = BRANCH_HALT, 2048 .clkr = { 2049 .enable_reg = 0xf054, 2050 .enable_mask = BIT(0), 2051 .hw.init = &(struct clk_init_data){ 2052 .name = "camcc_ife_2_csid_clk", 2053 .parent_hws = (const struct clk_hw*[]){ 2054 &camcc_ife_2_csid_clk_src.clkr.hw, 2055 }, 2056 .num_parents = 1, 2057 .flags = CLK_SET_RATE_PARENT, 2058 .ops = &clk_branch2_ops, 2059 }, 2060 }, 2061 }; 2062 2063 static struct clk_branch camcc_ife_2_dsp_clk = { 2064 .halt_reg = 0xf038, 2065 .halt_check = BRANCH_HALT, 2066 .clkr = { 2067 .enable_reg = 0xf038, 2068 .enable_mask = BIT(0), 2069 .hw.init = &(struct clk_init_data){ 2070 .name = "camcc_ife_2_dsp_clk", 2071 .parent_hws = (const struct clk_hw*[]){ 2072 &camcc_ife_2_clk_src.clkr.hw, 2073 }, 2074 .num_parents = 1, 2075 .flags = CLK_SET_RATE_PARENT, 2076 .ops = &clk_branch2_ops, 2077 }, 2078 }, 2079 }; 2080 2081 static struct clk_branch camcc_ife_3_axi_clk = { 2082 .halt_reg = 0xf0d4, 2083 .halt_check = BRANCH_HALT, 2084 .clkr = { 2085 .enable_reg = 0xf0d4, 2086 .enable_mask = BIT(0), 2087 .hw.init = &(struct clk_init_data){ 2088 .name = "camcc_ife_3_axi_clk", 2089 .parent_hws = (const struct clk_hw*[]){ 2090 &camcc_camnoc_axi_clk_src.clkr.hw, 2091 }, 2092 .num_parents = 1, 2093 .flags = CLK_SET_RATE_PARENT, 2094 .ops = &clk_branch2_ops, 2095 }, 2096 }, 2097 }; 2098 2099 static struct clk_branch camcc_ife_3_clk = { 2100 .halt_reg = 0xf094, 2101 .halt_check = BRANCH_HALT, 2102 .clkr = { 2103 .enable_reg = 0xf094, 2104 .enable_mask = BIT(0), 2105 .hw.init = &(struct clk_init_data){ 2106 .name = "camcc_ife_3_clk", 2107 .parent_hws = (const struct clk_hw*[]){ 2108 &camcc_ife_3_clk_src.clkr.hw, 2109 }, 2110 .num_parents = 1, 2111 .flags = CLK_SET_RATE_PARENT, 2112 .ops = &clk_branch2_ops, 2113 }, 2114 }, 2115 }; 2116 2117 static struct clk_branch camcc_ife_3_cphy_rx_clk = { 2118 .halt_reg = 0xf0d0, 2119 .halt_check = BRANCH_HALT, 2120 .clkr = { 2121 .enable_reg = 0xf0d0, 2122 .enable_mask = BIT(0), 2123 .hw.init = &(struct clk_init_data){ 2124 .name = "camcc_ife_3_cphy_rx_clk", 2125 .parent_hws = (const struct clk_hw*[]){ 2126 &camcc_cphy_rx_clk_src.clkr.hw, 2127 }, 2128 .num_parents = 1, 2129 .flags = CLK_SET_RATE_PARENT, 2130 .ops = &clk_branch2_ops, 2131 }, 2132 }, 2133 }; 2134 2135 static struct clk_branch camcc_ife_3_csid_clk = { 2136 .halt_reg = 0xf0c0, 2137 .halt_check = BRANCH_HALT, 2138 .clkr = { 2139 .enable_reg = 0xf0c0, 2140 .enable_mask = BIT(0), 2141 .hw.init = &(struct clk_init_data){ 2142 .name = "camcc_ife_3_csid_clk", 2143 .parent_hws = (const struct clk_hw*[]){ 2144 &camcc_ife_3_csid_clk_src.clkr.hw, 2145 }, 2146 .num_parents = 1, 2147 .flags = CLK_SET_RATE_PARENT, 2148 .ops = &clk_branch2_ops, 2149 }, 2150 }, 2151 }; 2152 2153 static struct clk_branch camcc_ife_3_dsp_clk = { 2154 .halt_reg = 0xf0a4, 2155 .halt_check = BRANCH_HALT, 2156 .clkr = { 2157 .enable_reg = 0xf0a4, 2158 .enable_mask = BIT(0), 2159 .hw.init = &(struct clk_init_data){ 2160 .name = "camcc_ife_3_dsp_clk", 2161 .parent_hws = (const struct clk_hw*[]){ 2162 &camcc_ife_3_clk_src.clkr.hw, 2163 }, 2164 .num_parents = 1, 2165 .flags = CLK_SET_RATE_PARENT, 2166 .ops = &clk_branch2_ops, 2167 }, 2168 }, 2169 }; 2170 2171 static struct clk_branch camcc_ife_lite_0_clk = { 2172 .halt_reg = 0xc01c, 2173 .halt_check = BRANCH_HALT, 2174 .clkr = { 2175 .enable_reg = 0xc01c, 2176 .enable_mask = BIT(0), 2177 .hw.init = &(struct clk_init_data){ 2178 .name = "camcc_ife_lite_0_clk", 2179 .parent_hws = (const struct clk_hw*[]){ 2180 &camcc_ife_lite_0_clk_src.clkr.hw, 2181 }, 2182 .num_parents = 1, 2183 .flags = CLK_SET_RATE_PARENT, 2184 .ops = &clk_branch2_ops, 2185 }, 2186 }, 2187 }; 2188 2189 static struct clk_branch camcc_ife_lite_0_cphy_rx_clk = { 2190 .halt_reg = 0xc040, 2191 .halt_check = BRANCH_HALT, 2192 .clkr = { 2193 .enable_reg = 0xc040, 2194 .enable_mask = BIT(0), 2195 .hw.init = &(struct clk_init_data){ 2196 .name = "camcc_ife_lite_0_cphy_rx_clk", 2197 .parent_hws = (const struct clk_hw*[]){ 2198 &camcc_cphy_rx_clk_src.clkr.hw, 2199 }, 2200 .num_parents = 1, 2201 .flags = CLK_SET_RATE_PARENT, 2202 .ops = &clk_branch2_ops, 2203 }, 2204 }, 2205 }; 2206 2207 static struct clk_branch camcc_ife_lite_0_csid_clk = { 2208 .halt_reg = 0xc038, 2209 .halt_check = BRANCH_HALT, 2210 .clkr = { 2211 .enable_reg = 0xc038, 2212 .enable_mask = BIT(0), 2213 .hw.init = &(struct clk_init_data){ 2214 .name = "camcc_ife_lite_0_csid_clk", 2215 .parent_hws = (const struct clk_hw*[]){ 2216 &camcc_ife_lite_0_csid_clk_src.clkr.hw, 2217 }, 2218 .num_parents = 1, 2219 .flags = CLK_SET_RATE_PARENT, 2220 .ops = &clk_branch2_ops, 2221 }, 2222 }, 2223 }; 2224 2225 static struct clk_branch camcc_ife_lite_1_clk = { 2226 .halt_reg = 0xc060, 2227 .halt_check = BRANCH_HALT, 2228 .clkr = { 2229 .enable_reg = 0xc060, 2230 .enable_mask = BIT(0), 2231 .hw.init = &(struct clk_init_data){ 2232 .name = "camcc_ife_lite_1_clk", 2233 .parent_hws = (const struct clk_hw*[]){ 2234 &camcc_ife_lite_1_clk_src.clkr.hw, 2235 }, 2236 .num_parents = 1, 2237 .flags = CLK_SET_RATE_PARENT, 2238 .ops = &clk_branch2_ops, 2239 }, 2240 }, 2241 }; 2242 2243 static struct clk_branch camcc_ife_lite_1_cphy_rx_clk = { 2244 .halt_reg = 0xc084, 2245 .halt_check = BRANCH_HALT, 2246 .clkr = { 2247 .enable_reg = 0xc084, 2248 .enable_mask = BIT(0), 2249 .hw.init = &(struct clk_init_data){ 2250 .name = "camcc_ife_lite_1_cphy_rx_clk", 2251 .parent_hws = (const struct clk_hw*[]){ 2252 &camcc_cphy_rx_clk_src.clkr.hw, 2253 }, 2254 .num_parents = 1, 2255 .flags = CLK_SET_RATE_PARENT, 2256 .ops = &clk_branch2_ops, 2257 }, 2258 }, 2259 }; 2260 2261 static struct clk_branch camcc_ife_lite_1_csid_clk = { 2262 .halt_reg = 0xc07c, 2263 .halt_check = BRANCH_HALT, 2264 .clkr = { 2265 .enable_reg = 0xc07c, 2266 .enable_mask = BIT(0), 2267 .hw.init = &(struct clk_init_data){ 2268 .name = "camcc_ife_lite_1_csid_clk", 2269 .parent_hws = (const struct clk_hw*[]){ 2270 &camcc_ife_lite_1_csid_clk_src.clkr.hw, 2271 }, 2272 .num_parents = 1, 2273 .flags = CLK_SET_RATE_PARENT, 2274 .ops = &clk_branch2_ops, 2275 }, 2276 }, 2277 }; 2278 2279 static struct clk_branch camcc_ife_lite_2_clk = { 2280 .halt_reg = 0xc258, 2281 .halt_check = BRANCH_HALT, 2282 .clkr = { 2283 .enable_reg = 0xc258, 2284 .enable_mask = BIT(0), 2285 .hw.init = &(struct clk_init_data){ 2286 .name = "camcc_ife_lite_2_clk", 2287 .parent_hws = (const struct clk_hw*[]){ 2288 &camcc_ife_lite_2_clk_src.clkr.hw, 2289 }, 2290 .num_parents = 1, 2291 .flags = CLK_SET_RATE_PARENT, 2292 .ops = &clk_branch2_ops, 2293 }, 2294 }, 2295 }; 2296 2297 static struct clk_branch camcc_ife_lite_2_cphy_rx_clk = { 2298 .halt_reg = 0xc27c, 2299 .halt_check = BRANCH_HALT, 2300 .clkr = { 2301 .enable_reg = 0xc27c, 2302 .enable_mask = BIT(0), 2303 .hw.init = &(struct clk_init_data){ 2304 .name = "camcc_ife_lite_2_cphy_rx_clk", 2305 .parent_hws = (const struct clk_hw*[]){ 2306 &camcc_cphy_rx_clk_src.clkr.hw, 2307 }, 2308 .num_parents = 1, 2309 .flags = CLK_SET_RATE_PARENT, 2310 .ops = &clk_branch2_ops, 2311 }, 2312 }, 2313 }; 2314 2315 static struct clk_branch camcc_ife_lite_2_csid_clk = { 2316 .halt_reg = 0xc274, 2317 .halt_check = BRANCH_HALT, 2318 .clkr = { 2319 .enable_reg = 0xc274, 2320 .enable_mask = BIT(0), 2321 .hw.init = &(struct clk_init_data){ 2322 .name = "camcc_ife_lite_2_csid_clk", 2323 .parent_hws = (const struct clk_hw*[]){ 2324 &camcc_ife_lite_2_csid_clk_src.clkr.hw, 2325 }, 2326 .num_parents = 1, 2327 .flags = CLK_SET_RATE_PARENT, 2328 .ops = &clk_branch2_ops, 2329 }, 2330 }, 2331 }; 2332 2333 static struct clk_branch camcc_ife_lite_3_clk = { 2334 .halt_reg = 0xc29c, 2335 .halt_check = BRANCH_HALT, 2336 .clkr = { 2337 .enable_reg = 0xc29c, 2338 .enable_mask = BIT(0), 2339 .hw.init = &(struct clk_init_data){ 2340 .name = "camcc_ife_lite_3_clk", 2341 .parent_hws = (const struct clk_hw*[]){ 2342 &camcc_ife_lite_3_clk_src.clkr.hw, 2343 }, 2344 .num_parents = 1, 2345 .flags = CLK_SET_RATE_PARENT, 2346 .ops = &clk_branch2_ops, 2347 }, 2348 }, 2349 }; 2350 2351 static struct clk_branch camcc_ife_lite_3_cphy_rx_clk = { 2352 .halt_reg = 0xc2c0, 2353 .halt_check = BRANCH_HALT, 2354 .clkr = { 2355 .enable_reg = 0xc2c0, 2356 .enable_mask = BIT(0), 2357 .hw.init = &(struct clk_init_data){ 2358 .name = "camcc_ife_lite_3_cphy_rx_clk", 2359 .parent_hws = (const struct clk_hw*[]){ 2360 &camcc_cphy_rx_clk_src.clkr.hw, 2361 }, 2362 .num_parents = 1, 2363 .flags = CLK_SET_RATE_PARENT, 2364 .ops = &clk_branch2_ops, 2365 }, 2366 }, 2367 }; 2368 2369 static struct clk_branch camcc_ife_lite_3_csid_clk = { 2370 .halt_reg = 0xc2b8, 2371 .halt_check = BRANCH_HALT, 2372 .clkr = { 2373 .enable_reg = 0xc2b8, 2374 .enable_mask = BIT(0), 2375 .hw.init = &(struct clk_init_data){ 2376 .name = "camcc_ife_lite_3_csid_clk", 2377 .parent_hws = (const struct clk_hw*[]){ 2378 &camcc_ife_lite_3_csid_clk_src.clkr.hw, 2379 }, 2380 .num_parents = 1, 2381 .flags = CLK_SET_RATE_PARENT, 2382 .ops = &clk_branch2_ops, 2383 }, 2384 }, 2385 }; 2386 2387 static struct clk_branch camcc_ipe_0_ahb_clk = { 2388 .halt_reg = 0x8040, 2389 .halt_check = BRANCH_HALT, 2390 .clkr = { 2391 .enable_reg = 0x8040, 2392 .enable_mask = BIT(0), 2393 .hw.init = &(struct clk_init_data){ 2394 .name = "camcc_ipe_0_ahb_clk", 2395 .parent_hws = (const struct clk_hw*[]){ 2396 &camcc_slow_ahb_clk_src.clkr.hw, 2397 }, 2398 .num_parents = 1, 2399 .flags = CLK_SET_RATE_PARENT, 2400 .ops = &clk_branch2_ops, 2401 }, 2402 }, 2403 }; 2404 2405 static struct clk_branch camcc_ipe_0_areg_clk = { 2406 .halt_reg = 0x803c, 2407 .halt_check = BRANCH_HALT, 2408 .clkr = { 2409 .enable_reg = 0x803c, 2410 .enable_mask = BIT(0), 2411 .hw.init = &(struct clk_init_data){ 2412 .name = "camcc_ipe_0_areg_clk", 2413 .parent_hws = (const struct clk_hw*[]){ 2414 &camcc_fast_ahb_clk_src.clkr.hw, 2415 }, 2416 .num_parents = 1, 2417 .flags = CLK_SET_RATE_PARENT, 2418 .ops = &clk_branch2_ops, 2419 }, 2420 }, 2421 }; 2422 2423 static struct clk_branch camcc_ipe_0_axi_clk = { 2424 .halt_reg = 0x8038, 2425 .halt_check = BRANCH_HALT, 2426 .clkr = { 2427 .enable_reg = 0x8038, 2428 .enable_mask = BIT(0), 2429 .hw.init = &(struct clk_init_data){ 2430 .name = "camcc_ipe_0_axi_clk", 2431 .parent_hws = (const struct clk_hw*[]){ 2432 &camcc_camnoc_axi_clk_src.clkr.hw, 2433 }, 2434 .num_parents = 1, 2435 .flags = CLK_SET_RATE_PARENT, 2436 .ops = &clk_branch2_ops, 2437 }, 2438 }, 2439 }; 2440 2441 static struct clk_branch camcc_ipe_0_clk = { 2442 .halt_reg = 0x8028, 2443 .halt_check = BRANCH_HALT, 2444 .clkr = { 2445 .enable_reg = 0x8028, 2446 .enable_mask = BIT(0), 2447 .hw.init = &(struct clk_init_data){ 2448 .name = "camcc_ipe_0_clk", 2449 .parent_hws = (const struct clk_hw*[]){ 2450 &camcc_ipe_0_clk_src.clkr.hw, 2451 }, 2452 .num_parents = 1, 2453 .flags = CLK_SET_RATE_PARENT, 2454 .ops = &clk_branch2_ops, 2455 }, 2456 }, 2457 }; 2458 2459 static struct clk_branch camcc_ipe_1_ahb_clk = { 2460 .halt_reg = 0x9028, 2461 .halt_check = BRANCH_HALT, 2462 .clkr = { 2463 .enable_reg = 0x9028, 2464 .enable_mask = BIT(0), 2465 .hw.init = &(struct clk_init_data){ 2466 .name = "camcc_ipe_1_ahb_clk", 2467 .parent_hws = (const struct clk_hw*[]){ 2468 &camcc_slow_ahb_clk_src.clkr.hw, 2469 }, 2470 .num_parents = 1, 2471 .flags = CLK_SET_RATE_PARENT, 2472 .ops = &clk_branch2_ops, 2473 }, 2474 }, 2475 }; 2476 2477 static struct clk_branch camcc_ipe_1_areg_clk = { 2478 .halt_reg = 0x9024, 2479 .halt_check = BRANCH_HALT, 2480 .clkr = { 2481 .enable_reg = 0x9024, 2482 .enable_mask = BIT(0), 2483 .hw.init = &(struct clk_init_data){ 2484 .name = "camcc_ipe_1_areg_clk", 2485 .parent_hws = (const struct clk_hw*[]){ 2486 &camcc_fast_ahb_clk_src.clkr.hw, 2487 }, 2488 .num_parents = 1, 2489 .flags = CLK_SET_RATE_PARENT, 2490 .ops = &clk_branch2_ops, 2491 }, 2492 }, 2493 }; 2494 2495 static struct clk_branch camcc_ipe_1_axi_clk = { 2496 .halt_reg = 0x9020, 2497 .halt_check = BRANCH_HALT, 2498 .clkr = { 2499 .enable_reg = 0x9020, 2500 .enable_mask = BIT(0), 2501 .hw.init = &(struct clk_init_data){ 2502 .name = "camcc_ipe_1_axi_clk", 2503 .parent_hws = (const struct clk_hw*[]){ 2504 &camcc_camnoc_axi_clk_src.clkr.hw, 2505 }, 2506 .num_parents = 1, 2507 .flags = CLK_SET_RATE_PARENT, 2508 .ops = &clk_branch2_ops, 2509 }, 2510 }, 2511 }; 2512 2513 static struct clk_branch camcc_ipe_1_clk = { 2514 .halt_reg = 0x9010, 2515 .halt_check = BRANCH_HALT, 2516 .clkr = { 2517 .enable_reg = 0x9010, 2518 .enable_mask = BIT(0), 2519 .hw.init = &(struct clk_init_data){ 2520 .name = "camcc_ipe_1_clk", 2521 .parent_hws = (const struct clk_hw*[]){ 2522 &camcc_ipe_0_clk_src.clkr.hw, 2523 }, 2524 .num_parents = 1, 2525 .flags = CLK_SET_RATE_PARENT, 2526 .ops = &clk_branch2_ops, 2527 }, 2528 }, 2529 }; 2530 2531 static struct clk_branch camcc_jpeg_clk = { 2532 .halt_reg = 0xc0a4, 2533 .halt_check = BRANCH_HALT, 2534 .clkr = { 2535 .enable_reg = 0xc0a4, 2536 .enable_mask = BIT(0), 2537 .hw.init = &(struct clk_init_data){ 2538 .name = "camcc_jpeg_clk", 2539 .parent_hws = (const struct clk_hw*[]){ 2540 &camcc_jpeg_clk_src.clkr.hw, 2541 }, 2542 .num_parents = 1, 2543 .flags = CLK_SET_RATE_PARENT, 2544 .ops = &clk_branch2_ops, 2545 }, 2546 }, 2547 }; 2548 2549 static struct clk_branch camcc_lrme_clk = { 2550 .halt_reg = 0xc15c, 2551 .halt_check = BRANCH_HALT, 2552 .clkr = { 2553 .enable_reg = 0xc15c, 2554 .enable_mask = BIT(0), 2555 .hw.init = &(struct clk_init_data){ 2556 .name = "camcc_lrme_clk", 2557 .parent_hws = (const struct clk_hw*[]){ 2558 &camcc_lrme_clk_src.clkr.hw, 2559 }, 2560 .num_parents = 1, 2561 .flags = CLK_SET_RATE_PARENT, 2562 .ops = &clk_branch2_ops, 2563 }, 2564 }, 2565 }; 2566 2567 static struct clk_branch camcc_mclk0_clk = { 2568 .halt_reg = 0x501c, 2569 .halt_check = BRANCH_HALT, 2570 .clkr = { 2571 .enable_reg = 0x501c, 2572 .enable_mask = BIT(0), 2573 .hw.init = &(struct clk_init_data){ 2574 .name = "camcc_mclk0_clk", 2575 .parent_hws = (const struct clk_hw*[]){ 2576 &camcc_mclk0_clk_src.clkr.hw, 2577 }, 2578 .num_parents = 1, 2579 .flags = CLK_SET_RATE_PARENT, 2580 .ops = &clk_branch2_ops, 2581 }, 2582 }, 2583 }; 2584 2585 static struct clk_branch camcc_mclk1_clk = { 2586 .halt_reg = 0x503c, 2587 .halt_check = BRANCH_HALT, 2588 .clkr = { 2589 .enable_reg = 0x503c, 2590 .enable_mask = BIT(0), 2591 .hw.init = &(struct clk_init_data){ 2592 .name = "camcc_mclk1_clk", 2593 .parent_hws = (const struct clk_hw*[]){ 2594 &camcc_mclk1_clk_src.clkr.hw, 2595 }, 2596 .num_parents = 1, 2597 .flags = CLK_SET_RATE_PARENT, 2598 .ops = &clk_branch2_ops, 2599 }, 2600 }, 2601 }; 2602 2603 static struct clk_branch camcc_mclk2_clk = { 2604 .halt_reg = 0x505c, 2605 .halt_check = BRANCH_HALT, 2606 .clkr = { 2607 .enable_reg = 0x505c, 2608 .enable_mask = BIT(0), 2609 .hw.init = &(struct clk_init_data){ 2610 .name = "camcc_mclk2_clk", 2611 .parent_hws = (const struct clk_hw*[]){ 2612 &camcc_mclk2_clk_src.clkr.hw, 2613 }, 2614 .num_parents = 1, 2615 .flags = CLK_SET_RATE_PARENT, 2616 .ops = &clk_branch2_ops, 2617 }, 2618 }, 2619 }; 2620 2621 static struct clk_branch camcc_mclk3_clk = { 2622 .halt_reg = 0x507c, 2623 .halt_check = BRANCH_HALT, 2624 .clkr = { 2625 .enable_reg = 0x507c, 2626 .enable_mask = BIT(0), 2627 .hw.init = &(struct clk_init_data){ 2628 .name = "camcc_mclk3_clk", 2629 .parent_hws = (const struct clk_hw*[]){ 2630 &camcc_mclk3_clk_src.clkr.hw, 2631 }, 2632 .num_parents = 1, 2633 .flags = CLK_SET_RATE_PARENT, 2634 .ops = &clk_branch2_ops, 2635 }, 2636 }, 2637 }; 2638 2639 static struct clk_branch camcc_mclk4_clk = { 2640 .halt_reg = 0x509c, 2641 .halt_check = BRANCH_HALT, 2642 .clkr = { 2643 .enable_reg = 0x509c, 2644 .enable_mask = BIT(0), 2645 .hw.init = &(struct clk_init_data){ 2646 .name = "camcc_mclk4_clk", 2647 .parent_hws = (const struct clk_hw*[]){ 2648 &camcc_mclk4_clk_src.clkr.hw, 2649 }, 2650 .num_parents = 1, 2651 .flags = CLK_SET_RATE_PARENT, 2652 .ops = &clk_branch2_ops, 2653 }, 2654 }, 2655 }; 2656 2657 static struct clk_branch camcc_mclk5_clk = { 2658 .halt_reg = 0x50bc, 2659 .halt_check = BRANCH_HALT, 2660 .clkr = { 2661 .enable_reg = 0x50bc, 2662 .enable_mask = BIT(0), 2663 .hw.init = &(struct clk_init_data){ 2664 .name = "camcc_mclk5_clk", 2665 .parent_hws = (const struct clk_hw*[]){ 2666 &camcc_mclk5_clk_src.clkr.hw, 2667 }, 2668 .num_parents = 1, 2669 .flags = CLK_SET_RATE_PARENT, 2670 .ops = &clk_branch2_ops, 2671 }, 2672 }, 2673 }; 2674 2675 static struct clk_branch camcc_mclk6_clk = { 2676 .halt_reg = 0x50dc, 2677 .halt_check = BRANCH_HALT, 2678 .clkr = { 2679 .enable_reg = 0x50dc, 2680 .enable_mask = BIT(0), 2681 .hw.init = &(struct clk_init_data){ 2682 .name = "camcc_mclk6_clk", 2683 .parent_hws = (const struct clk_hw*[]){ 2684 &camcc_mclk6_clk_src.clkr.hw, 2685 }, 2686 .num_parents = 1, 2687 .flags = CLK_SET_RATE_PARENT, 2688 .ops = &clk_branch2_ops, 2689 }, 2690 }, 2691 }; 2692 2693 static struct clk_branch camcc_mclk7_clk = { 2694 .halt_reg = 0x50fc, 2695 .halt_check = BRANCH_HALT, 2696 .clkr = { 2697 .enable_reg = 0x50fc, 2698 .enable_mask = BIT(0), 2699 .hw.init = &(struct clk_init_data){ 2700 .name = "camcc_mclk7_clk", 2701 .parent_hws = (const struct clk_hw*[]){ 2702 &camcc_mclk7_clk_src.clkr.hw, 2703 }, 2704 .num_parents = 1, 2705 .flags = CLK_SET_RATE_PARENT, 2706 .ops = &clk_branch2_ops, 2707 }, 2708 }, 2709 }; 2710 2711 static struct clk_branch camcc_sleep_clk = { 2712 .halt_reg = 0xc200, 2713 .halt_check = BRANCH_HALT, 2714 .clkr = { 2715 .enable_reg = 0xc200, 2716 .enable_mask = BIT(0), 2717 .hw.init = &(struct clk_init_data){ 2718 .name = "camcc_sleep_clk", 2719 .parent_hws = (const struct clk_hw*[]){ 2720 &camcc_sleep_clk_src.clkr.hw, 2721 }, 2722 .num_parents = 1, 2723 .flags = CLK_SET_RATE_PARENT, 2724 .ops = &clk_branch2_ops, 2725 }, 2726 }, 2727 }; 2728 2729 static struct gdsc titan_top_gdsc; 2730 2731 static struct gdsc bps_gdsc = { 2732 .gdscr = 0x7004, 2733 .pd = { 2734 .name = "bps_gdsc", 2735 }, 2736 .flags = HW_CTRL | RETAIN_FF_ENABLE, 2737 .parent = &titan_top_gdsc.pd, 2738 .pwrsts = PWRSTS_OFF_ON, 2739 }; 2740 2741 static struct gdsc ife_0_gdsc = { 2742 .gdscr = 0xa004, 2743 .pd = { 2744 .name = "ife_0_gdsc", 2745 }, 2746 .flags = RETAIN_FF_ENABLE, 2747 .parent = &titan_top_gdsc.pd, 2748 .pwrsts = PWRSTS_OFF_ON, 2749 }; 2750 2751 static struct gdsc ife_1_gdsc = { 2752 .gdscr = 0xb004, 2753 .pd = { 2754 .name = "ife_1_gdsc", 2755 }, 2756 .flags = RETAIN_FF_ENABLE, 2757 .parent = &titan_top_gdsc.pd, 2758 .pwrsts = PWRSTS_OFF_ON, 2759 }; 2760 2761 static struct gdsc ife_2_gdsc = { 2762 .gdscr = 0xf004, 2763 .pd = { 2764 .name = "ife_2_gdsc", 2765 }, 2766 .flags = RETAIN_FF_ENABLE, 2767 .parent = &titan_top_gdsc.pd, 2768 .pwrsts = PWRSTS_OFF_ON, 2769 }; 2770 2771 static struct gdsc ife_3_gdsc = { 2772 .gdscr = 0xf070, 2773 .pd = { 2774 .name = "ife_3_gdsc", 2775 }, 2776 .flags = RETAIN_FF_ENABLE, 2777 .parent = &titan_top_gdsc.pd, 2778 .pwrsts = PWRSTS_OFF_ON, 2779 }; 2780 2781 static struct gdsc ipe_0_gdsc = { 2782 .gdscr = 0x8004, 2783 .pd = { 2784 .name = "ipe_0_gdsc", 2785 }, 2786 .flags = HW_CTRL | RETAIN_FF_ENABLE, 2787 .parent = &titan_top_gdsc.pd, 2788 .pwrsts = PWRSTS_OFF_ON, 2789 }; 2790 2791 static struct gdsc ipe_1_gdsc = { 2792 .gdscr = 0x9004, 2793 .pd = { 2794 .name = "ipe_1_gdsc", 2795 }, 2796 .flags = HW_CTRL | RETAIN_FF_ENABLE, 2797 .parent = &titan_top_gdsc.pd, 2798 .pwrsts = PWRSTS_OFF_ON, 2799 }; 2800 2801 static struct gdsc titan_top_gdsc = { 2802 .gdscr = 0xc1bc, 2803 .pd = { 2804 .name = "titan_top_gdsc", 2805 }, 2806 .flags = RETAIN_FF_ENABLE, 2807 .pwrsts = PWRSTS_OFF_ON, 2808 }; 2809 2810 static struct clk_regmap *camcc_sc8280xp_clocks[] = { 2811 [CAMCC_BPS_AHB_CLK] = &camcc_bps_ahb_clk.clkr, 2812 [CAMCC_BPS_AREG_CLK] = &camcc_bps_areg_clk.clkr, 2813 [CAMCC_BPS_AXI_CLK] = &camcc_bps_axi_clk.clkr, 2814 [CAMCC_BPS_CLK] = &camcc_bps_clk.clkr, 2815 [CAMCC_BPS_CLK_SRC] = &camcc_bps_clk_src.clkr, 2816 [CAMCC_CAMNOC_AXI_CLK] = &camcc_camnoc_axi_clk.clkr, 2817 [CAMCC_CAMNOC_AXI_CLK_SRC] = &camcc_camnoc_axi_clk_src.clkr, 2818 [CAMCC_CAMNOC_DCD_XO_CLK] = &camcc_camnoc_dcd_xo_clk.clkr, 2819 [CAMCC_CCI_0_CLK] = &camcc_cci_0_clk.clkr, 2820 [CAMCC_CCI_0_CLK_SRC] = &camcc_cci_0_clk_src.clkr, 2821 [CAMCC_CCI_1_CLK] = &camcc_cci_1_clk.clkr, 2822 [CAMCC_CCI_1_CLK_SRC] = &camcc_cci_1_clk_src.clkr, 2823 [CAMCC_CCI_2_CLK] = &camcc_cci_2_clk.clkr, 2824 [CAMCC_CCI_2_CLK_SRC] = &camcc_cci_2_clk_src.clkr, 2825 [CAMCC_CCI_3_CLK] = &camcc_cci_3_clk.clkr, 2826 [CAMCC_CCI_3_CLK_SRC] = &camcc_cci_3_clk_src.clkr, 2827 [CAMCC_CORE_AHB_CLK] = &camcc_core_ahb_clk.clkr, 2828 [CAMCC_CPAS_AHB_CLK] = &camcc_cpas_ahb_clk.clkr, 2829 [CAMCC_CPHY_RX_CLK_SRC] = &camcc_cphy_rx_clk_src.clkr, 2830 [CAMCC_CSI0PHYTIMER_CLK] = &camcc_csi0phytimer_clk.clkr, 2831 [CAMCC_CSI0PHYTIMER_CLK_SRC] = &camcc_csi0phytimer_clk_src.clkr, 2832 [CAMCC_CSI1PHYTIMER_CLK] = &camcc_csi1phytimer_clk.clkr, 2833 [CAMCC_CSI1PHYTIMER_CLK_SRC] = &camcc_csi1phytimer_clk_src.clkr, 2834 [CAMCC_CSI2PHYTIMER_CLK] = &camcc_csi2phytimer_clk.clkr, 2835 [CAMCC_CSI2PHYTIMER_CLK_SRC] = &camcc_csi2phytimer_clk_src.clkr, 2836 [CAMCC_CSI3PHYTIMER_CLK] = &camcc_csi3phytimer_clk.clkr, 2837 [CAMCC_CSI3PHYTIMER_CLK_SRC] = &camcc_csi3phytimer_clk_src.clkr, 2838 [CAMCC_CSIPHY0_CLK] = &camcc_csiphy0_clk.clkr, 2839 [CAMCC_CSIPHY1_CLK] = &camcc_csiphy1_clk.clkr, 2840 [CAMCC_CSIPHY2_CLK] = &camcc_csiphy2_clk.clkr, 2841 [CAMCC_CSIPHY3_CLK] = &camcc_csiphy3_clk.clkr, 2842 [CAMCC_FAST_AHB_CLK_SRC] = &camcc_fast_ahb_clk_src.clkr, 2843 [CAMCC_GDSC_CLK] = &camcc_gdsc_clk.clkr, 2844 [CAMCC_ICP_AHB_CLK] = &camcc_icp_ahb_clk.clkr, 2845 [CAMCC_ICP_CLK] = &camcc_icp_clk.clkr, 2846 [CAMCC_ICP_CLK_SRC] = &camcc_icp_clk_src.clkr, 2847 [CAMCC_IFE_0_AXI_CLK] = &camcc_ife_0_axi_clk.clkr, 2848 [CAMCC_IFE_0_CLK] = &camcc_ife_0_clk.clkr, 2849 [CAMCC_IFE_0_CLK_SRC] = &camcc_ife_0_clk_src.clkr, 2850 [CAMCC_IFE_0_CPHY_RX_CLK] = &camcc_ife_0_cphy_rx_clk.clkr, 2851 [CAMCC_IFE_0_CSID_CLK] = &camcc_ife_0_csid_clk.clkr, 2852 [CAMCC_IFE_0_CSID_CLK_SRC] = &camcc_ife_0_csid_clk_src.clkr, 2853 [CAMCC_IFE_0_DSP_CLK] = &camcc_ife_0_dsp_clk.clkr, 2854 [CAMCC_IFE_1_AXI_CLK] = &camcc_ife_1_axi_clk.clkr, 2855 [CAMCC_IFE_1_CLK] = &camcc_ife_1_clk.clkr, 2856 [CAMCC_IFE_1_CLK_SRC] = &camcc_ife_1_clk_src.clkr, 2857 [CAMCC_IFE_1_CPHY_RX_CLK] = &camcc_ife_1_cphy_rx_clk.clkr, 2858 [CAMCC_IFE_1_CSID_CLK] = &camcc_ife_1_csid_clk.clkr, 2859 [CAMCC_IFE_1_CSID_CLK_SRC] = &camcc_ife_1_csid_clk_src.clkr, 2860 [CAMCC_IFE_1_DSP_CLK] = &camcc_ife_1_dsp_clk.clkr, 2861 [CAMCC_IFE_2_AXI_CLK] = &camcc_ife_2_axi_clk.clkr, 2862 [CAMCC_IFE_2_CLK] = &camcc_ife_2_clk.clkr, 2863 [CAMCC_IFE_2_CLK_SRC] = &camcc_ife_2_clk_src.clkr, 2864 [CAMCC_IFE_2_CPHY_RX_CLK] = &camcc_ife_2_cphy_rx_clk.clkr, 2865 [CAMCC_IFE_2_CSID_CLK] = &camcc_ife_2_csid_clk.clkr, 2866 [CAMCC_IFE_2_CSID_CLK_SRC] = &camcc_ife_2_csid_clk_src.clkr, 2867 [CAMCC_IFE_2_DSP_CLK] = &camcc_ife_2_dsp_clk.clkr, 2868 [CAMCC_IFE_3_AXI_CLK] = &camcc_ife_3_axi_clk.clkr, 2869 [CAMCC_IFE_3_CLK] = &camcc_ife_3_clk.clkr, 2870 [CAMCC_IFE_3_CLK_SRC] = &camcc_ife_3_clk_src.clkr, 2871 [CAMCC_IFE_3_CPHY_RX_CLK] = &camcc_ife_3_cphy_rx_clk.clkr, 2872 [CAMCC_IFE_3_CSID_CLK] = &camcc_ife_3_csid_clk.clkr, 2873 [CAMCC_IFE_3_CSID_CLK_SRC] = &camcc_ife_3_csid_clk_src.clkr, 2874 [CAMCC_IFE_3_DSP_CLK] = &camcc_ife_3_dsp_clk.clkr, 2875 [CAMCC_IFE_LITE_0_CLK] = &camcc_ife_lite_0_clk.clkr, 2876 [CAMCC_IFE_LITE_0_CLK_SRC] = &camcc_ife_lite_0_clk_src.clkr, 2877 [CAMCC_IFE_LITE_0_CPHY_RX_CLK] = &camcc_ife_lite_0_cphy_rx_clk.clkr, 2878 [CAMCC_IFE_LITE_0_CSID_CLK] = &camcc_ife_lite_0_csid_clk.clkr, 2879 [CAMCC_IFE_LITE_0_CSID_CLK_SRC] = &camcc_ife_lite_0_csid_clk_src.clkr, 2880 [CAMCC_IFE_LITE_1_CLK] = &camcc_ife_lite_1_clk.clkr, 2881 [CAMCC_IFE_LITE_1_CLK_SRC] = &camcc_ife_lite_1_clk_src.clkr, 2882 [CAMCC_IFE_LITE_1_CPHY_RX_CLK] = &camcc_ife_lite_1_cphy_rx_clk.clkr, 2883 [CAMCC_IFE_LITE_1_CSID_CLK] = &camcc_ife_lite_1_csid_clk.clkr, 2884 [CAMCC_IFE_LITE_1_CSID_CLK_SRC] = &camcc_ife_lite_1_csid_clk_src.clkr, 2885 [CAMCC_IFE_LITE_2_CLK] = &camcc_ife_lite_2_clk.clkr, 2886 [CAMCC_IFE_LITE_2_CLK_SRC] = &camcc_ife_lite_2_clk_src.clkr, 2887 [CAMCC_IFE_LITE_2_CPHY_RX_CLK] = &camcc_ife_lite_2_cphy_rx_clk.clkr, 2888 [CAMCC_IFE_LITE_2_CSID_CLK] = &camcc_ife_lite_2_csid_clk.clkr, 2889 [CAMCC_IFE_LITE_2_CSID_CLK_SRC] = &camcc_ife_lite_2_csid_clk_src.clkr, 2890 [CAMCC_IFE_LITE_3_CLK] = &camcc_ife_lite_3_clk.clkr, 2891 [CAMCC_IFE_LITE_3_CLK_SRC] = &camcc_ife_lite_3_clk_src.clkr, 2892 [CAMCC_IFE_LITE_3_CPHY_RX_CLK] = &camcc_ife_lite_3_cphy_rx_clk.clkr, 2893 [CAMCC_IFE_LITE_3_CSID_CLK] = &camcc_ife_lite_3_csid_clk.clkr, 2894 [CAMCC_IFE_LITE_3_CSID_CLK_SRC] = &camcc_ife_lite_3_csid_clk_src.clkr, 2895 [CAMCC_IPE_0_AHB_CLK] = &camcc_ipe_0_ahb_clk.clkr, 2896 [CAMCC_IPE_0_AREG_CLK] = &camcc_ipe_0_areg_clk.clkr, 2897 [CAMCC_IPE_0_AXI_CLK] = &camcc_ipe_0_axi_clk.clkr, 2898 [CAMCC_IPE_0_CLK] = &camcc_ipe_0_clk.clkr, 2899 [CAMCC_IPE_0_CLK_SRC] = &camcc_ipe_0_clk_src.clkr, 2900 [CAMCC_IPE_1_AHB_CLK] = &camcc_ipe_1_ahb_clk.clkr, 2901 [CAMCC_IPE_1_AREG_CLK] = &camcc_ipe_1_areg_clk.clkr, 2902 [CAMCC_IPE_1_AXI_CLK] = &camcc_ipe_1_axi_clk.clkr, 2903 [CAMCC_IPE_1_CLK] = &camcc_ipe_1_clk.clkr, 2904 [CAMCC_JPEG_CLK] = &camcc_jpeg_clk.clkr, 2905 [CAMCC_JPEG_CLK_SRC] = &camcc_jpeg_clk_src.clkr, 2906 [CAMCC_LRME_CLK] = &camcc_lrme_clk.clkr, 2907 [CAMCC_LRME_CLK_SRC] = &camcc_lrme_clk_src.clkr, 2908 [CAMCC_MCLK0_CLK] = &camcc_mclk0_clk.clkr, 2909 [CAMCC_MCLK0_CLK_SRC] = &camcc_mclk0_clk_src.clkr, 2910 [CAMCC_MCLK1_CLK] = &camcc_mclk1_clk.clkr, 2911 [CAMCC_MCLK1_CLK_SRC] = &camcc_mclk1_clk_src.clkr, 2912 [CAMCC_MCLK2_CLK] = &camcc_mclk2_clk.clkr, 2913 [CAMCC_MCLK2_CLK_SRC] = &camcc_mclk2_clk_src.clkr, 2914 [CAMCC_MCLK3_CLK] = &camcc_mclk3_clk.clkr, 2915 [CAMCC_MCLK3_CLK_SRC] = &camcc_mclk3_clk_src.clkr, 2916 [CAMCC_MCLK4_CLK] = &camcc_mclk4_clk.clkr, 2917 [CAMCC_MCLK4_CLK_SRC] = &camcc_mclk4_clk_src.clkr, 2918 [CAMCC_MCLK5_CLK] = &camcc_mclk5_clk.clkr, 2919 [CAMCC_MCLK5_CLK_SRC] = &camcc_mclk5_clk_src.clkr, 2920 [CAMCC_MCLK6_CLK] = &camcc_mclk6_clk.clkr, 2921 [CAMCC_MCLK6_CLK_SRC] = &camcc_mclk6_clk_src.clkr, 2922 [CAMCC_MCLK7_CLK] = &camcc_mclk7_clk.clkr, 2923 [CAMCC_MCLK7_CLK_SRC] = &camcc_mclk7_clk_src.clkr, 2924 [CAMCC_PLL0] = &camcc_pll0.clkr, 2925 [CAMCC_PLL0_OUT_EVEN] = &camcc_pll0_out_even.clkr, 2926 [CAMCC_PLL0_OUT_ODD] = &camcc_pll0_out_odd.clkr, 2927 [CAMCC_PLL1] = &camcc_pll1.clkr, 2928 [CAMCC_PLL1_OUT_EVEN] = &camcc_pll1_out_even.clkr, 2929 [CAMCC_PLL2] = &camcc_pll2.clkr, 2930 [CAMCC_PLL3] = &camcc_pll3.clkr, 2931 [CAMCC_PLL3_OUT_EVEN] = &camcc_pll3_out_even.clkr, 2932 [CAMCC_PLL4] = &camcc_pll4.clkr, 2933 [CAMCC_PLL4_OUT_EVEN] = &camcc_pll4_out_even.clkr, 2934 [CAMCC_PLL5] = &camcc_pll5.clkr, 2935 [CAMCC_PLL5_OUT_EVEN] = &camcc_pll5_out_even.clkr, 2936 [CAMCC_PLL6] = &camcc_pll6.clkr, 2937 [CAMCC_PLL6_OUT_EVEN] = &camcc_pll6_out_even.clkr, 2938 [CAMCC_PLL7] = &camcc_pll7.clkr, 2939 [CAMCC_PLL7_OUT_EVEN] = &camcc_pll7_out_even.clkr, 2940 [CAMCC_PLL7_OUT_ODD] = &camcc_pll7_out_odd.clkr, 2941 [CAMCC_SLEEP_CLK] = &camcc_sleep_clk.clkr, 2942 [CAMCC_SLEEP_CLK_SRC] = &camcc_sleep_clk_src.clkr, 2943 [CAMCC_SLOW_AHB_CLK_SRC] = &camcc_slow_ahb_clk_src.clkr, 2944 [CAMCC_XO_CLK_SRC] = &camcc_xo_clk_src.clkr, 2945 }; 2946 2947 static struct gdsc *camcc_sc8280xp_gdscs[] = { 2948 [BPS_GDSC] = &bps_gdsc, 2949 [IFE_0_GDSC] = &ife_0_gdsc, 2950 [IFE_1_GDSC] = &ife_1_gdsc, 2951 [IFE_2_GDSC] = &ife_2_gdsc, 2952 [IFE_3_GDSC] = &ife_3_gdsc, 2953 [IPE_0_GDSC] = &ipe_0_gdsc, 2954 [IPE_1_GDSC] = &ipe_1_gdsc, 2955 [TITAN_TOP_GDSC] = &titan_top_gdsc, 2956 }; 2957 2958 static const struct qcom_reset_map camcc_sc8280xp_resets[] = { 2959 [CAMCC_BPS_BCR] = { 0x7000 }, 2960 [CAMCC_CAMNOC_BCR] = { 0xc16c }, 2961 [CAMCC_CCI_BCR] = { 0xc104 }, 2962 [CAMCC_CPAS_BCR] = { 0xc164 }, 2963 [CAMCC_CSI0PHY_BCR] = { 0x6000 }, 2964 [CAMCC_CSI1PHY_BCR] = { 0x6024 }, 2965 [CAMCC_CSI2PHY_BCR] = { 0x6048 }, 2966 [CAMCC_CSI3PHY_BCR] = { 0x6070 }, 2967 [CAMCC_ICP_BCR] = { 0xc0b4 }, 2968 [CAMCC_IFE_0_BCR] = { 0xa000 }, 2969 [CAMCC_IFE_1_BCR] = { 0xb000 }, 2970 [CAMCC_IFE_2_BCR] = { 0xf000 }, 2971 [CAMCC_IFE_3_BCR] = { 0xf06c }, 2972 [CAMCC_IFE_LITE_0_BCR] = { 0xc000 }, 2973 [CAMCC_IFE_LITE_1_BCR] = { 0xc044 }, 2974 [CAMCC_IFE_LITE_2_BCR] = { 0xc23c }, 2975 [CAMCC_IFE_LITE_3_BCR] = { 0xc280 }, 2976 [CAMCC_IPE_0_BCR] = { 0x8000 }, 2977 [CAMCC_IPE_1_BCR] = { 0x9000 }, 2978 [CAMCC_JPEG_BCR] = { 0xc088 }, 2979 [CAMCC_LRME_BCR] = { 0xc140 }, 2980 }; 2981 2982 static const struct regmap_config camcc_sc8280xp_regmap_config = { 2983 .reg_bits = 32, 2984 .reg_stride = 4, 2985 .val_bits = 32, 2986 .max_register = 0x13020, 2987 .fast_io = true, 2988 }; 2989 2990 static struct qcom_cc_desc camcc_sc8280xp_desc = { 2991 .config = &camcc_sc8280xp_regmap_config, 2992 .clks = camcc_sc8280xp_clocks, 2993 .num_clks = ARRAY_SIZE(camcc_sc8280xp_clocks), 2994 .resets = camcc_sc8280xp_resets, 2995 .num_resets = ARRAY_SIZE(camcc_sc8280xp_resets), 2996 .gdscs = camcc_sc8280xp_gdscs, 2997 .num_gdscs = ARRAY_SIZE(camcc_sc8280xp_gdscs), 2998 }; 2999 3000 static const struct of_device_id camcc_sc8280xp_match_table[] = { 3001 { .compatible = "qcom,sc8280xp-camcc" }, 3002 { } 3003 }; 3004 MODULE_DEVICE_TABLE(of, camcc_sc8280xp_match_table); 3005 3006 static int camcc_sc8280xp_probe(struct platform_device *pdev) 3007 { 3008 struct regmap *regmap; 3009 int ret; 3010 3011 ret = devm_pm_runtime_enable(&pdev->dev); 3012 if (ret) 3013 return ret; 3014 3015 ret = pm_runtime_resume_and_get(&pdev->dev); 3016 if (ret) 3017 return ret; 3018 3019 regmap = qcom_cc_map(pdev, &camcc_sc8280xp_desc); 3020 if (IS_ERR(regmap)) { 3021 ret = PTR_ERR(regmap); 3022 goto err_put_rpm; 3023 } 3024 3025 clk_lucid_pll_configure(&camcc_pll0, regmap, &camcc_pll0_config); 3026 clk_lucid_pll_configure(&camcc_pll1, regmap, &camcc_pll1_config); 3027 clk_zonda_pll_configure(&camcc_pll2, regmap, &camcc_pll2_config); 3028 clk_lucid_pll_configure(&camcc_pll3, regmap, &camcc_pll3_config); 3029 clk_lucid_pll_configure(&camcc_pll4, regmap, &camcc_pll4_config); 3030 clk_lucid_pll_configure(&camcc_pll5, regmap, &camcc_pll5_config); 3031 clk_lucid_pll_configure(&camcc_pll6, regmap, &camcc_pll6_config); 3032 clk_lucid_pll_configure(&camcc_pll7, regmap, &camcc_pll7_config); 3033 3034 /* Keep some clocks always-on */ 3035 qcom_branch_set_clk_en(regmap, 0xc1e4); /* CAMCC_GDSC_CLK */ 3036 3037 ret = qcom_cc_really_probe(pdev, &camcc_sc8280xp_desc, regmap); 3038 if (ret) 3039 goto err_disable; 3040 3041 pm_runtime_put(&pdev->dev); 3042 3043 return 0; 3044 3045 err_disable: 3046 regmap_update_bits(regmap, 0xc1e4, BIT(0), 0); 3047 err_put_rpm: 3048 pm_runtime_put_sync(&pdev->dev); 3049 3050 return ret; 3051 } 3052 3053 static struct platform_driver camcc_sc8280xp_driver = { 3054 .probe = camcc_sc8280xp_probe, 3055 .driver = { 3056 .name = "camcc-sc8280xp", 3057 .of_match_table = camcc_sc8280xp_match_table, 3058 }, 3059 }; 3060 3061 module_platform_driver(camcc_sc8280xp_driver); 3062 3063 MODULE_DESCRIPTION("QCOM CAMCC SC8280XP Driver"); 3064 MODULE_LICENSE("GPL"); 3065