1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2023, Linaro Ltd. 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/regmap.h> 12 13 #include <dt-bindings/clock/qcom,sc8280xp-camcc.h> 14 15 #include "clk-alpha-pll.h" 16 #include "clk-branch.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "common.h" 20 #include "gdsc.h" 21 #include "reset.h" 22 23 enum { 24 DT_IFACE, 25 DT_BI_TCXO, 26 DT_BI_TCXO_AO, 27 DT_SLEEP_CLK, 28 }; 29 30 enum { 31 P_BI_TCXO, 32 P_CAMCC_PLL0_OUT_EVEN, 33 P_CAMCC_PLL0_OUT_MAIN, 34 P_CAMCC_PLL0_OUT_ODD, 35 P_CAMCC_PLL1_OUT_EVEN, 36 P_CAMCC_PLL2_OUT_AUX, 37 P_CAMCC_PLL2_OUT_EARLY, 38 P_CAMCC_PLL3_OUT_EVEN, 39 P_CAMCC_PLL4_OUT_EVEN, 40 P_CAMCC_PLL5_OUT_EVEN, 41 P_CAMCC_PLL6_OUT_EVEN, 42 P_CAMCC_PLL7_OUT_EVEN, 43 P_CAMCC_PLL7_OUT_ODD, 44 P_SLEEP_CLK, 45 }; 46 47 static const struct pll_vco lucid_vco[] = { 48 { 249600000, 1800000000, 0 }, 49 }; 50 51 static const struct pll_vco zonda_vco[] = { 52 { 595200000, 3600000000, 0 }, 53 }; 54 55 static struct alpha_pll_config camcc_pll0_config = { 56 .l = 0x3e, 57 .alpha = 0x8000, 58 .config_ctl_val = 0x20485699, 59 .config_ctl_hi_val = 0x00002261, 60 .config_ctl_hi1_val = 0x2a9a699c, 61 .test_ctl_val = 0x00000000, 62 .test_ctl_hi_val = 0x00000000, 63 .test_ctl_hi1_val = 0x01800000, 64 .user_ctl_val = 0x00003100, 65 .user_ctl_hi_val = 0x00000805, 66 .user_ctl_hi1_val = 0x00000000, 67 }; 68 69 static struct clk_alpha_pll camcc_pll0 = { 70 .offset = 0x0, 71 .vco_table = lucid_vco, 72 .num_vco = ARRAY_SIZE(lucid_vco), 73 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 74 .clkr = { 75 .hw.init = &(struct clk_init_data){ 76 .name = "camcc_pll0", 77 .parent_data = &(const struct clk_parent_data){ 78 .index = DT_BI_TCXO, 79 }, 80 .num_parents = 1, 81 .ops = &clk_alpha_pll_lucid_5lpe_ops, 82 }, 83 }, 84 }; 85 86 static const struct clk_div_table post_div_table_camcc_pll0_out_even[] = { 87 { 0x1, 2 }, 88 }; 89 90 static struct clk_alpha_pll_postdiv camcc_pll0_out_even = { 91 .offset = 0x0, 92 .post_div_shift = 8, 93 .post_div_table = post_div_table_camcc_pll0_out_even, 94 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll0_out_even), 95 .width = 4, 96 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 97 .clkr.hw.init = &(struct clk_init_data){ 98 .name = "camcc_pll0_out_even", 99 .parent_hws = (const struct clk_hw*[]){ 100 &camcc_pll0.clkr.hw, 101 }, 102 .num_parents = 1, 103 .flags = CLK_SET_RATE_PARENT, 104 .ops = &clk_alpha_pll_postdiv_lucid_ops, 105 }, 106 }; 107 108 static const struct clk_div_table post_div_table_camcc_pll0_out_odd[] = { 109 { 0x3, 3 }, 110 }; 111 112 static struct clk_alpha_pll_postdiv camcc_pll0_out_odd = { 113 .offset = 0x0, 114 .post_div_shift = 12, 115 .post_div_table = post_div_table_camcc_pll0_out_odd, 116 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll0_out_odd), 117 .width = 4, 118 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 119 .clkr.hw.init = &(struct clk_init_data){ 120 .name = "camcc_pll0_out_odd", 121 .parent_hws = (const struct clk_hw*[]){ 122 &camcc_pll0.clkr.hw, 123 }, 124 .num_parents = 1, 125 .flags = CLK_SET_RATE_PARENT, 126 .ops = &clk_alpha_pll_postdiv_lucid_ops, 127 }, 128 }; 129 130 static struct alpha_pll_config camcc_pll1_config = { 131 .l = 0x21, 132 .alpha = 0x5555, 133 .config_ctl_val = 0x20485699, 134 .config_ctl_hi_val = 0x00002261, 135 .config_ctl_hi1_val = 0x2a9a699c, 136 .test_ctl_val = 0x00000000, 137 .test_ctl_hi_val = 0x00000000, 138 .test_ctl_hi1_val = 0x01800000, 139 .user_ctl_val = 0x00000100, 140 .user_ctl_hi_val = 0x00000805, 141 .user_ctl_hi1_val = 0x00000000, 142 }; 143 144 static struct clk_alpha_pll camcc_pll1 = { 145 .offset = 0x1000, 146 .vco_table = lucid_vco, 147 .num_vco = ARRAY_SIZE(lucid_vco), 148 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 149 .clkr = { 150 .hw.init = &(struct clk_init_data){ 151 .name = "camcc_pll1", 152 .parent_data = &(const struct clk_parent_data){ 153 .index = DT_BI_TCXO, 154 }, 155 .num_parents = 1, 156 .ops = &clk_alpha_pll_lucid_5lpe_ops, 157 }, 158 }, 159 }; 160 161 static const struct clk_div_table post_div_table_camcc_pll1_out_even[] = { 162 { 0x1, 2 }, 163 }; 164 165 static struct clk_alpha_pll_postdiv camcc_pll1_out_even = { 166 .offset = 0x1000, 167 .post_div_shift = 8, 168 .post_div_table = post_div_table_camcc_pll1_out_even, 169 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll1_out_even), 170 .width = 4, 171 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 172 .clkr.hw.init = &(struct clk_init_data){ 173 .name = "camcc_pll1_out_even", 174 .parent_hws = (const struct clk_hw*[]){ 175 &camcc_pll1.clkr.hw, 176 }, 177 .num_parents = 1, 178 .flags = CLK_SET_RATE_PARENT, 179 .ops = &clk_alpha_pll_postdiv_lucid_ops, 180 }, 181 }; 182 183 static struct alpha_pll_config camcc_pll2_config = { 184 .l = 0x32, 185 .alpha = 0x0, 186 .config_ctl_val = 0x08200800, 187 .config_ctl_hi_val = 0x05028011, 188 .config_ctl_hi1_val = 0x08000000, 189 }; 190 191 static struct clk_alpha_pll camcc_pll2 = { 192 .offset = 0x2000, 193 .vco_table = zonda_vco, 194 .num_vco = ARRAY_SIZE(zonda_vco), 195 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], 196 .clkr = { 197 .hw.init = &(struct clk_init_data){ 198 .name = "camcc_pll2", 199 .parent_data = &(const struct clk_parent_data){ 200 .index = DT_BI_TCXO, 201 }, 202 .num_parents = 1, 203 .ops = &clk_alpha_pll_zonda_ops, 204 }, 205 }, 206 }; 207 208 static struct alpha_pll_config camcc_pll3_config = { 209 .l = 0x29, 210 .alpha = 0xaaaa, 211 .config_ctl_val = 0x20485699, 212 .config_ctl_hi_val = 0x00002261, 213 .config_ctl_hi1_val = 0x2a9a699c, 214 .test_ctl_val = 0x00000000, 215 .test_ctl_hi_val = 0x00000000, 216 .test_ctl_hi1_val = 0x01800000, 217 .user_ctl_val = 0x00000100, 218 .user_ctl_hi_val = 0x00000805, 219 .user_ctl_hi1_val = 0x00000000, 220 }; 221 222 static struct clk_alpha_pll camcc_pll3 = { 223 .offset = 0x3000, 224 .vco_table = lucid_vco, 225 .num_vco = ARRAY_SIZE(lucid_vco), 226 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 227 .clkr = { 228 .hw.init = &(struct clk_init_data){ 229 .name = "camcc_pll3", 230 .parent_data = &(const struct clk_parent_data){ 231 .index = DT_BI_TCXO, 232 }, 233 .num_parents = 1, 234 .ops = &clk_alpha_pll_lucid_5lpe_ops, 235 }, 236 }, 237 }; 238 239 static const struct clk_div_table post_div_table_camcc_pll3_out_even[] = { 240 { 0x1, 2 }, 241 }; 242 243 static struct clk_alpha_pll_postdiv camcc_pll3_out_even = { 244 .offset = 0x3000, 245 .post_div_shift = 8, 246 .post_div_table = post_div_table_camcc_pll3_out_even, 247 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll3_out_even), 248 .width = 4, 249 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 250 .clkr.hw.init = &(struct clk_init_data){ 251 .name = "camcc_pll3_out_even", 252 .parent_hws = (const struct clk_hw*[]){ 253 &camcc_pll3.clkr.hw, 254 }, 255 .num_parents = 1, 256 .flags = CLK_SET_RATE_PARENT, 257 .ops = &clk_alpha_pll_postdiv_lucid_ops, 258 }, 259 }; 260 261 static struct alpha_pll_config camcc_pll4_config = { 262 .l = 0x29, 263 .alpha = 0xaaaa, 264 .config_ctl_val = 0x20485699, 265 .config_ctl_hi_val = 0x00002261, 266 .config_ctl_hi1_val = 0x2a9a699c, 267 .test_ctl_val = 0x00000000, 268 .test_ctl_hi_val = 0x00000000, 269 .test_ctl_hi1_val = 0x01800000, 270 .user_ctl_val = 0x00000100, 271 .user_ctl_hi_val = 0x00000805, 272 .user_ctl_hi1_val = 0x00000000, 273 }; 274 275 static struct clk_alpha_pll camcc_pll4 = { 276 .offset = 0x4000, 277 .vco_table = lucid_vco, 278 .num_vco = ARRAY_SIZE(lucid_vco), 279 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 280 .clkr = { 281 .hw.init = &(struct clk_init_data){ 282 .name = "camcc_pll4", 283 .parent_data = &(const struct clk_parent_data){ 284 .index = DT_BI_TCXO, 285 }, 286 .num_parents = 1, 287 .ops = &clk_alpha_pll_lucid_5lpe_ops, 288 }, 289 }, 290 }; 291 292 static const struct clk_div_table post_div_table_camcc_pll4_out_even[] = { 293 { 0x1, 2 }, 294 }; 295 296 static struct clk_alpha_pll_postdiv camcc_pll4_out_even = { 297 .offset = 0x4000, 298 .post_div_shift = 8, 299 .post_div_table = post_div_table_camcc_pll4_out_even, 300 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll4_out_even), 301 .width = 4, 302 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 303 .clkr.hw.init = &(struct clk_init_data){ 304 .name = "camcc_pll4_out_even", 305 .parent_hws = (const struct clk_hw*[]){ 306 &camcc_pll4.clkr.hw, 307 }, 308 .num_parents = 1, 309 .flags = CLK_SET_RATE_PARENT, 310 .ops = &clk_alpha_pll_postdiv_lucid_ops, 311 }, 312 }; 313 314 static struct alpha_pll_config camcc_pll5_config = { 315 .l = 0x29, 316 .alpha = 0xaaaa, 317 .config_ctl_val = 0x20485699, 318 .config_ctl_hi_val = 0x00002261, 319 .config_ctl_hi1_val = 0x2a9a699c, 320 .test_ctl_val = 0x00000000, 321 .test_ctl_hi_val = 0x00000000, 322 .test_ctl_hi1_val = 0x01800000, 323 .user_ctl_val = 0x00000100, 324 .user_ctl_hi_val = 0x00000805, 325 .user_ctl_hi1_val = 0x00000000, 326 }; 327 328 static struct clk_alpha_pll camcc_pll5 = { 329 .offset = 0x10000, 330 .vco_table = lucid_vco, 331 .num_vco = ARRAY_SIZE(lucid_vco), 332 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 333 .clkr = { 334 .hw.init = &(struct clk_init_data){ 335 .name = "camcc_pll5", 336 .parent_data = &(const struct clk_parent_data){ 337 .index = DT_BI_TCXO, 338 }, 339 .num_parents = 1, 340 .ops = &clk_alpha_pll_lucid_5lpe_ops, 341 }, 342 }, 343 }; 344 345 static const struct clk_div_table post_div_table_camcc_pll5_out_even[] = { 346 { 0x1, 2 }, 347 }; 348 349 static struct clk_alpha_pll_postdiv camcc_pll5_out_even = { 350 .offset = 0x10000, 351 .post_div_shift = 8, 352 .post_div_table = post_div_table_camcc_pll5_out_even, 353 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll5_out_even), 354 .width = 4, 355 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 356 .clkr.hw.init = &(struct clk_init_data){ 357 .name = "camcc_pll5_out_even", 358 .parent_hws = (const struct clk_hw*[]){ 359 &camcc_pll5.clkr.hw, 360 }, 361 .num_parents = 1, 362 .flags = CLK_SET_RATE_PARENT, 363 .ops = &clk_alpha_pll_postdiv_lucid_ops, 364 }, 365 }; 366 367 static struct alpha_pll_config camcc_pll6_config = { 368 .l = 0x29, 369 .alpha = 0xaaaa, 370 .config_ctl_val = 0x20486699, 371 .config_ctl_hi_val = 0x00002261, 372 .config_ctl_hi1_val = 0x2a9a699c, 373 .test_ctl_val = 0x00000000, 374 .test_ctl_hi_val = 0x00000000, 375 .test_ctl_hi1_val = 0x01800000, 376 .user_ctl_val = 0x00000100, 377 .user_ctl_hi_val = 0x00000805, 378 .user_ctl_hi1_val = 0x00000000, 379 }; 380 381 static struct clk_alpha_pll camcc_pll6 = { 382 .offset = 0x11000, 383 .vco_table = lucid_vco, 384 .num_vco = ARRAY_SIZE(lucid_vco), 385 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 386 .clkr = { 387 .hw.init = &(struct clk_init_data){ 388 .name = "camcc_pll6", 389 .parent_data = &(const struct clk_parent_data){ 390 .index = DT_BI_TCXO, 391 }, 392 .num_parents = 1, 393 .ops = &clk_alpha_pll_lucid_5lpe_ops, 394 }, 395 }, 396 }; 397 398 static const struct clk_div_table post_div_table_camcc_pll6_out_even[] = { 399 { 0x1, 2 }, 400 }; 401 402 static struct clk_alpha_pll_postdiv camcc_pll6_out_even = { 403 .offset = 0x11000, 404 .post_div_shift = 8, 405 .post_div_table = post_div_table_camcc_pll6_out_even, 406 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll6_out_even), 407 .width = 4, 408 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 409 .clkr.hw.init = &(struct clk_init_data){ 410 .name = "camcc_pll6_out_even", 411 .parent_hws = (const struct clk_hw*[]){ 412 &camcc_pll6.clkr.hw, 413 }, 414 .num_parents = 1, 415 .flags = CLK_SET_RATE_PARENT, 416 .ops = &clk_alpha_pll_postdiv_lucid_ops, 417 }, 418 }; 419 420 static struct alpha_pll_config camcc_pll7_config = { 421 .l = 0x32, 422 .alpha = 0x0, 423 .config_ctl_val = 0x20485699, 424 .config_ctl_hi_val = 0x00002261, 425 .config_ctl_hi1_val = 0x2a9a699c, 426 .test_ctl_val = 0x00000000, 427 .test_ctl_hi_val = 0x00000000, 428 .test_ctl_hi1_val = 0x01800000, 429 .user_ctl_val = 0x00003100, 430 .user_ctl_hi_val = 0x00000805, 431 .user_ctl_hi1_val = 0x00000000, 432 }; 433 434 static struct clk_alpha_pll camcc_pll7 = { 435 .offset = 0x12000, 436 .vco_table = lucid_vco, 437 .num_vco = ARRAY_SIZE(lucid_vco), 438 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 439 .clkr = { 440 .hw.init = &(struct clk_init_data){ 441 .name = "camcc_pll7", 442 .parent_data = &(const struct clk_parent_data){ 443 .index = DT_BI_TCXO, 444 }, 445 .num_parents = 1, 446 .ops = &clk_alpha_pll_lucid_5lpe_ops, 447 }, 448 }, 449 }; 450 451 static const struct clk_div_table post_div_table_camcc_pll7_out_even[] = { 452 { 0x1, 2 }, 453 }; 454 455 static struct clk_alpha_pll_postdiv camcc_pll7_out_even = { 456 .offset = 0x12000, 457 .post_div_shift = 8, 458 .post_div_table = post_div_table_camcc_pll7_out_even, 459 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll7_out_even), 460 .width = 4, 461 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 462 .clkr.hw.init = &(struct clk_init_data){ 463 .name = "camcc_pll7_out_even", 464 .parent_hws = (const struct clk_hw*[]){ 465 &camcc_pll7.clkr.hw, 466 }, 467 .num_parents = 1, 468 .flags = CLK_SET_RATE_PARENT, 469 .ops = &clk_alpha_pll_postdiv_lucid_ops, 470 }, 471 }; 472 473 static const struct clk_div_table post_div_table_camcc_pll7_out_odd[] = { 474 { 0x3, 3 }, 475 }; 476 477 static struct clk_alpha_pll_postdiv camcc_pll7_out_odd = { 478 .offset = 0x12000, 479 .post_div_shift = 12, 480 .post_div_table = post_div_table_camcc_pll7_out_odd, 481 .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll7_out_odd), 482 .width = 4, 483 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 484 .clkr.hw.init = &(struct clk_init_data){ 485 .name = "camcc_pll7_out_odd", 486 .parent_hws = (const struct clk_hw*[]){ 487 &camcc_pll7.clkr.hw, 488 }, 489 .num_parents = 1, 490 .flags = CLK_SET_RATE_PARENT, 491 .ops = &clk_alpha_pll_postdiv_lucid_ops, 492 }, 493 }; 494 495 static const struct parent_map camcc_parent_map_0[] = { 496 { P_BI_TCXO, 0 }, 497 { P_CAMCC_PLL0_OUT_MAIN, 1 }, 498 { P_CAMCC_PLL0_OUT_EVEN, 2 }, 499 { P_CAMCC_PLL0_OUT_ODD, 3 }, 500 { P_CAMCC_PLL7_OUT_EVEN, 5 }, 501 }; 502 503 static const struct clk_parent_data camcc_parent_data_0[] = { 504 { .index = DT_BI_TCXO }, 505 { .hw = &camcc_pll0.clkr.hw }, 506 { .hw = &camcc_pll0_out_even.clkr.hw }, 507 { .hw = &camcc_pll0_out_odd.clkr.hw }, 508 { .hw = &camcc_pll7_out_even.clkr.hw }, 509 }; 510 511 static const struct parent_map camcc_parent_map_1[] = { 512 { P_BI_TCXO, 0 }, 513 { P_CAMCC_PLL2_OUT_AUX, 2 }, 514 { P_CAMCC_PLL2_OUT_EARLY, 5 }, 515 }; 516 517 static const struct clk_parent_data camcc_parent_data_1[] = { 518 { .index = DT_BI_TCXO }, 519 { .hw = &camcc_pll2.clkr.hw }, 520 { .hw = &camcc_pll2.clkr.hw }, 521 }; 522 523 static const struct parent_map camcc_parent_map_2[] = { 524 { P_BI_TCXO, 0 }, 525 { P_CAMCC_PLL0_OUT_MAIN, 1 }, 526 { P_CAMCC_PLL0_OUT_EVEN, 2 }, 527 { P_CAMCC_PLL0_OUT_ODD, 3 }, 528 { P_CAMCC_PLL7_OUT_ODD, 4 }, 529 { P_CAMCC_PLL7_OUT_EVEN, 5 }, 530 }; 531 532 static const struct clk_parent_data camcc_parent_data_2[] = { 533 { .index = DT_BI_TCXO }, 534 { .hw = &camcc_pll0.clkr.hw }, 535 { .hw = &camcc_pll0_out_even.clkr.hw }, 536 { .hw = &camcc_pll0_out_odd.clkr.hw }, 537 { .hw = &camcc_pll7_out_odd.clkr.hw }, 538 { .hw = &camcc_pll7_out_even.clkr.hw }, 539 }; 540 541 static const struct parent_map camcc_parent_map_3[] = { 542 { P_BI_TCXO, 0 }, 543 { P_CAMCC_PLL0_OUT_MAIN, 1 }, 544 { P_CAMCC_PLL0_OUT_EVEN, 2 }, 545 { P_CAMCC_PLL0_OUT_ODD, 3 }, 546 { P_CAMCC_PLL7_OUT_EVEN, 5 }, 547 { P_CAMCC_PLL3_OUT_EVEN, 6 }, 548 }; 549 550 static const struct clk_parent_data camcc_parent_data_3[] = { 551 { .index = DT_BI_TCXO }, 552 { .hw = &camcc_pll0.clkr.hw }, 553 { .hw = &camcc_pll0_out_even.clkr.hw }, 554 { .hw = &camcc_pll0_out_odd.clkr.hw }, 555 { .hw = &camcc_pll7_out_even.clkr.hw }, 556 { .hw = &camcc_pll3_out_even.clkr.hw }, 557 }; 558 559 static const struct parent_map camcc_parent_map_4[] = { 560 { P_BI_TCXO, 0 }, 561 { P_CAMCC_PLL3_OUT_EVEN, 6 }, 562 }; 563 564 static const struct clk_parent_data camcc_parent_data_4[] = { 565 { .index = DT_BI_TCXO }, 566 { .hw = &camcc_pll3_out_even.clkr.hw }, 567 }; 568 569 static const struct parent_map camcc_parent_map_5[] = { 570 { P_BI_TCXO, 0 }, 571 { P_CAMCC_PLL4_OUT_EVEN, 6 }, 572 }; 573 574 static const struct clk_parent_data camcc_parent_data_5[] = { 575 { .index = DT_BI_TCXO }, 576 { .hw = &camcc_pll4_out_even.clkr.hw }, 577 }; 578 579 static const struct parent_map camcc_parent_map_6[] = { 580 { P_BI_TCXO, 0 }, 581 { P_CAMCC_PLL5_OUT_EVEN, 6 }, 582 }; 583 584 static const struct clk_parent_data camcc_parent_data_6[] = { 585 { .index = DT_BI_TCXO }, 586 { .hw = &camcc_pll5_out_even.clkr.hw }, 587 }; 588 589 static const struct parent_map camcc_parent_map_7[] = { 590 { P_BI_TCXO, 0 }, 591 { P_CAMCC_PLL6_OUT_EVEN, 6 }, 592 }; 593 594 static const struct clk_parent_data camcc_parent_data_7[] = { 595 { .index = DT_BI_TCXO }, 596 { .hw = &camcc_pll6_out_even.clkr.hw }, 597 }; 598 599 static const struct parent_map camcc_parent_map_8[] = { 600 { P_BI_TCXO, 0 }, 601 { P_CAMCC_PLL1_OUT_EVEN, 4 }, 602 }; 603 604 static const struct clk_parent_data camcc_parent_data_8[] = { 605 { .index = DT_BI_TCXO }, 606 { .hw = &camcc_pll1_out_even.clkr.hw }, 607 }; 608 609 static const struct parent_map camcc_parent_map_9[] = { 610 { P_SLEEP_CLK, 0 }, 611 }; 612 613 static const struct clk_parent_data camcc_parent_data_9[] = { 614 { .fw_name = "sleep_clk" }, 615 }; 616 617 static const struct parent_map camcc_parent_map_10[] = { 618 { P_BI_TCXO, 0 }, 619 }; 620 621 static const struct clk_parent_data camcc_parent_data_10_ao[] = { 622 { .fw_name = "bi_tcxo_ao" }, 623 }; 624 625 static const struct freq_tbl ftbl_camcc_bps_clk_src[] = { 626 F(19200000, P_BI_TCXO, 1, 0, 0), 627 F(200000000, P_CAMCC_PLL0_OUT_ODD, 2, 0, 0), 628 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 629 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0), 630 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 631 F(760000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), 632 { } 633 }; 634 635 static struct clk_rcg2 camcc_bps_clk_src = { 636 .cmd_rcgr = 0x7010, 637 .mnd_width = 0, 638 .hid_width = 5, 639 .parent_map = camcc_parent_map_3, 640 .freq_tbl = ftbl_camcc_bps_clk_src, 641 .clkr.hw.init = &(struct clk_init_data){ 642 .name = "camcc_bps_clk_src", 643 .parent_data = camcc_parent_data_3, 644 .num_parents = ARRAY_SIZE(camcc_parent_data_3), 645 .flags = CLK_SET_RATE_PARENT, 646 .ops = &clk_rcg2_shared_ops, 647 }, 648 }; 649 650 static const struct freq_tbl ftbl_camcc_camnoc_axi_clk_src[] = { 651 F(19200000, P_BI_TCXO, 1, 0, 0), 652 F(150000000, P_CAMCC_PLL0_OUT_EVEN, 4, 0, 0), 653 F(266666667, P_CAMCC_PLL0_OUT_ODD, 1.5, 0, 0), 654 F(320000000, P_CAMCC_PLL7_OUT_ODD, 1, 0, 0), 655 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 656 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0), 657 { } 658 }; 659 660 static struct clk_rcg2 camcc_camnoc_axi_clk_src = { 661 .cmd_rcgr = 0xc170, 662 .mnd_width = 0, 663 .hid_width = 5, 664 .parent_map = camcc_parent_map_2, 665 .freq_tbl = ftbl_camcc_camnoc_axi_clk_src, 666 .clkr.hw.init = &(struct clk_init_data){ 667 .name = "camcc_camnoc_axi_clk_src", 668 .parent_data = camcc_parent_data_2, 669 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 670 .ops = &clk_rcg2_ops, 671 }, 672 }; 673 674 static const struct freq_tbl ftbl_camcc_cci_0_clk_src[] = { 675 F(19200000, P_BI_TCXO, 1, 0, 0), 676 F(37500000, P_CAMCC_PLL0_OUT_EVEN, 16, 0, 0), 677 { } 678 }; 679 680 static struct clk_rcg2 camcc_cci_0_clk_src = { 681 .cmd_rcgr = 0xc108, 682 .mnd_width = 8, 683 .hid_width = 5, 684 .parent_map = camcc_parent_map_0, 685 .freq_tbl = ftbl_camcc_cci_0_clk_src, 686 .clkr.hw.init = &(struct clk_init_data){ 687 .name = "camcc_cci_0_clk_src", 688 .parent_data = camcc_parent_data_0, 689 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 690 .ops = &clk_rcg2_ops, 691 }, 692 }; 693 694 static struct clk_rcg2 camcc_cci_1_clk_src = { 695 .cmd_rcgr = 0xc124, 696 .mnd_width = 8, 697 .hid_width = 5, 698 .parent_map = camcc_parent_map_0, 699 .freq_tbl = ftbl_camcc_cci_0_clk_src, 700 .clkr.hw.init = &(struct clk_init_data){ 701 .name = "camcc_cci_1_clk_src", 702 .parent_data = camcc_parent_data_0, 703 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 704 .ops = &clk_rcg2_ops, 705 }, 706 }; 707 708 static struct clk_rcg2 camcc_cci_2_clk_src = { 709 .cmd_rcgr = 0xc204, 710 .mnd_width = 8, 711 .hid_width = 5, 712 .parent_map = camcc_parent_map_0, 713 .freq_tbl = ftbl_camcc_cci_0_clk_src, 714 .clkr.hw.init = &(struct clk_init_data){ 715 .name = "camcc_cci_2_clk_src", 716 .parent_data = camcc_parent_data_0, 717 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 718 .ops = &clk_rcg2_ops, 719 }, 720 }; 721 722 static struct clk_rcg2 camcc_cci_3_clk_src = { 723 .cmd_rcgr = 0xc220, 724 .mnd_width = 8, 725 .hid_width = 5, 726 .parent_map = camcc_parent_map_0, 727 .freq_tbl = ftbl_camcc_cci_0_clk_src, 728 .clkr.hw.init = &(struct clk_init_data){ 729 .name = "camcc_cci_3_clk_src", 730 .parent_data = camcc_parent_data_0, 731 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 732 .ops = &clk_rcg2_ops, 733 }, 734 }; 735 736 static const struct freq_tbl ftbl_camcc_cphy_rx_clk_src[] = { 737 F(19200000, P_BI_TCXO, 1, 0, 0), 738 F(240000000, P_CAMCC_PLL0_OUT_EVEN, 2.5, 0, 0), 739 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 740 { } 741 }; 742 743 static struct clk_rcg2 camcc_cphy_rx_clk_src = { 744 .cmd_rcgr = 0xa064, 745 .mnd_width = 0, 746 .hid_width = 5, 747 .parent_map = camcc_parent_map_0, 748 .freq_tbl = ftbl_camcc_cphy_rx_clk_src, 749 .clkr.hw.init = &(struct clk_init_data){ 750 .name = "camcc_cphy_rx_clk_src", 751 .parent_data = camcc_parent_data_0, 752 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 753 .ops = &clk_rcg2_ops, 754 }, 755 }; 756 757 static const struct freq_tbl ftbl_camcc_csi0phytimer_clk_src[] = { 758 F(19200000, P_BI_TCXO, 1, 0, 0), 759 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0), 760 { } 761 }; 762 763 static struct clk_rcg2 camcc_csi0phytimer_clk_src = { 764 .cmd_rcgr = 0x6004, 765 .mnd_width = 0, 766 .hid_width = 5, 767 .parent_map = camcc_parent_map_0, 768 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, 769 .clkr.hw.init = &(struct clk_init_data){ 770 .name = "camcc_csi0phytimer_clk_src", 771 .parent_data = camcc_parent_data_0, 772 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 773 .ops = &clk_rcg2_ops, 774 }, 775 }; 776 777 static struct clk_rcg2 camcc_csi1phytimer_clk_src = { 778 .cmd_rcgr = 0x6028, 779 .mnd_width = 0, 780 .hid_width = 5, 781 .parent_map = camcc_parent_map_0, 782 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, 783 .clkr.hw.init = &(struct clk_init_data){ 784 .name = "camcc_csi1phytimer_clk_src", 785 .parent_data = camcc_parent_data_0, 786 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 787 .ops = &clk_rcg2_ops, 788 }, 789 }; 790 791 static struct clk_rcg2 camcc_csi2phytimer_clk_src = { 792 .cmd_rcgr = 0x604c, 793 .mnd_width = 0, 794 .hid_width = 5, 795 .parent_map = camcc_parent_map_0, 796 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, 797 .clkr.hw.init = &(struct clk_init_data){ 798 .name = "camcc_csi2phytimer_clk_src", 799 .parent_data = camcc_parent_data_0, 800 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 801 .ops = &clk_rcg2_ops, 802 }, 803 }; 804 805 static struct clk_rcg2 camcc_csi3phytimer_clk_src = { 806 .cmd_rcgr = 0x6074, 807 .mnd_width = 0, 808 .hid_width = 5, 809 .parent_map = camcc_parent_map_0, 810 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, 811 .clkr.hw.init = &(struct clk_init_data){ 812 .name = "camcc_csi3phytimer_clk_src", 813 .parent_data = camcc_parent_data_0, 814 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 815 .ops = &clk_rcg2_ops, 816 }, 817 }; 818 819 static const struct freq_tbl ftbl_camcc_fast_ahb_clk_src[] = { 820 F(19200000, P_BI_TCXO, 1, 0, 0), 821 F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0), 822 F(200000000, P_CAMCC_PLL0_OUT_EVEN, 3, 0, 0), 823 F(300000000, P_CAMCC_PLL0_OUT_MAIN, 4, 0, 0), 824 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), 825 { } 826 }; 827 828 static struct clk_rcg2 camcc_fast_ahb_clk_src = { 829 .cmd_rcgr = 0x703c, 830 .mnd_width = 0, 831 .hid_width = 5, 832 .parent_map = camcc_parent_map_0, 833 .freq_tbl = ftbl_camcc_fast_ahb_clk_src, 834 .clkr.hw.init = &(struct clk_init_data){ 835 .name = "camcc_fast_ahb_clk_src", 836 .parent_data = camcc_parent_data_0, 837 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 838 .ops = &clk_rcg2_ops, 839 }, 840 }; 841 842 static const struct freq_tbl ftbl_camcc_icp_clk_src[] = { 843 F(19200000, P_BI_TCXO, 1, 0, 0), 844 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 845 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 846 { } 847 }; 848 849 static struct clk_rcg2 camcc_icp_clk_src = { 850 .cmd_rcgr = 0xc0b8, 851 .mnd_width = 0, 852 .hid_width = 5, 853 .parent_map = camcc_parent_map_0, 854 .freq_tbl = ftbl_camcc_icp_clk_src, 855 .clkr.hw.init = &(struct clk_init_data){ 856 .name = "camcc_icp_clk_src", 857 .parent_data = camcc_parent_data_0, 858 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 859 .ops = &clk_rcg2_shared_ops, 860 }, 861 }; 862 863 static const struct freq_tbl ftbl_camcc_ife_0_clk_src[] = { 864 F(19200000, P_BI_TCXO, 1, 0, 0), 865 F(400000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), 866 F(558000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), 867 F(637000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), 868 F(760000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), 869 { } 870 }; 871 872 static struct clk_rcg2 camcc_ife_0_clk_src = { 873 .cmd_rcgr = 0xa010, 874 .mnd_width = 0, 875 .hid_width = 5, 876 .parent_map = camcc_parent_map_4, 877 .freq_tbl = ftbl_camcc_ife_0_clk_src, 878 .clkr.hw.init = &(struct clk_init_data){ 879 .name = "camcc_ife_0_clk_src", 880 .parent_data = camcc_parent_data_4, 881 .num_parents = ARRAY_SIZE(camcc_parent_data_4), 882 .flags = CLK_SET_RATE_PARENT, 883 .ops = &clk_rcg2_shared_ops, 884 }, 885 }; 886 887 static const struct freq_tbl ftbl_camcc_ife_0_csid_clk_src[] = { 888 F(19200000, P_BI_TCXO, 1, 0, 0), 889 F(75000000, P_CAMCC_PLL0_OUT_EVEN, 8, 0, 0), 890 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 891 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0), 892 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 893 { } 894 }; 895 896 static struct clk_rcg2 camcc_ife_0_csid_clk_src = { 897 .cmd_rcgr = 0xa03c, 898 .mnd_width = 0, 899 .hid_width = 5, 900 .parent_map = camcc_parent_map_0, 901 .freq_tbl = ftbl_camcc_ife_0_csid_clk_src, 902 .clkr.hw.init = &(struct clk_init_data){ 903 .name = "camcc_ife_0_csid_clk_src", 904 .parent_data = camcc_parent_data_0, 905 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 906 .ops = &clk_rcg2_shared_ops, 907 }, 908 }; 909 910 static const struct freq_tbl ftbl_camcc_ife_1_clk_src[] = { 911 F(19200000, P_BI_TCXO, 1, 0, 0), 912 F(400000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), 913 F(558000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), 914 F(637000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), 915 F(760000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), 916 { } 917 }; 918 919 static struct clk_rcg2 camcc_ife_1_clk_src = { 920 .cmd_rcgr = 0xb010, 921 .mnd_width = 0, 922 .hid_width = 5, 923 .parent_map = camcc_parent_map_5, 924 .freq_tbl = ftbl_camcc_ife_1_clk_src, 925 .clkr.hw.init = &(struct clk_init_data){ 926 .name = "camcc_ife_1_clk_src", 927 .parent_data = camcc_parent_data_5, 928 .num_parents = ARRAY_SIZE(camcc_parent_data_5), 929 .flags = CLK_SET_RATE_PARENT, 930 .ops = &clk_rcg2_shared_ops, 931 }, 932 }; 933 934 static struct clk_rcg2 camcc_ife_1_csid_clk_src = { 935 .cmd_rcgr = 0xb03c, 936 .mnd_width = 0, 937 .hid_width = 5, 938 .parent_map = camcc_parent_map_0, 939 .freq_tbl = ftbl_camcc_ife_0_csid_clk_src, 940 .clkr.hw.init = &(struct clk_init_data){ 941 .name = "camcc_ife_1_csid_clk_src", 942 .parent_data = camcc_parent_data_0, 943 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 944 .ops = &clk_rcg2_shared_ops, 945 }, 946 }; 947 948 static const struct freq_tbl ftbl_camcc_ife_2_clk_src[] = { 949 F(400000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0), 950 F(558000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0), 951 F(637000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0), 952 F(760000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0), 953 { } 954 }; 955 956 static struct clk_rcg2 camcc_ife_2_clk_src = { 957 .cmd_rcgr = 0xf010, 958 .mnd_width = 0, 959 .hid_width = 5, 960 .parent_map = camcc_parent_map_6, 961 .freq_tbl = ftbl_camcc_ife_2_clk_src, 962 .clkr.hw.init = &(struct clk_init_data){ 963 .name = "camcc_ife_2_clk_src", 964 .parent_data = camcc_parent_data_6, 965 .num_parents = ARRAY_SIZE(camcc_parent_data_6), 966 .flags = CLK_SET_RATE_PARENT, 967 .ops = &clk_rcg2_shared_ops, 968 }, 969 }; 970 971 static const struct freq_tbl ftbl_camcc_ife_2_csid_clk_src[] = { 972 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 973 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0), 974 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 975 { } 976 }; 977 978 static struct clk_rcg2 camcc_ife_2_csid_clk_src = { 979 .cmd_rcgr = 0xf03c, 980 .mnd_width = 0, 981 .hid_width = 5, 982 .parent_map = camcc_parent_map_0, 983 .freq_tbl = ftbl_camcc_ife_2_csid_clk_src, 984 .clkr.hw.init = &(struct clk_init_data){ 985 .name = "camcc_ife_2_csid_clk_src", 986 .parent_data = camcc_parent_data_0, 987 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 988 .ops = &clk_rcg2_shared_ops, 989 }, 990 }; 991 992 static const struct freq_tbl ftbl_camcc_ife_3_clk_src[] = { 993 F(19200000, P_BI_TCXO, 1, 0, 0), 994 F(400000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0), 995 F(558000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0), 996 F(637000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0), 997 F(760000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0), 998 { } 999 }; 1000 1001 static struct clk_rcg2 camcc_ife_3_clk_src = { 1002 .cmd_rcgr = 0xf07c, 1003 .mnd_width = 0, 1004 .hid_width = 5, 1005 .parent_map = camcc_parent_map_7, 1006 .freq_tbl = ftbl_camcc_ife_3_clk_src, 1007 .clkr.hw.init = &(struct clk_init_data){ 1008 .name = "camcc_ife_3_clk_src", 1009 .parent_data = camcc_parent_data_7, 1010 .num_parents = ARRAY_SIZE(camcc_parent_data_7), 1011 .flags = CLK_SET_RATE_PARENT, 1012 .ops = &clk_rcg2_shared_ops, 1013 }, 1014 }; 1015 1016 static struct clk_rcg2 camcc_ife_3_csid_clk_src = { 1017 .cmd_rcgr = 0xf0a8, 1018 .mnd_width = 0, 1019 .hid_width = 5, 1020 .parent_map = camcc_parent_map_0, 1021 .freq_tbl = ftbl_camcc_ife_2_csid_clk_src, 1022 .clkr.hw.init = &(struct clk_init_data){ 1023 .name = "camcc_ife_3_csid_clk_src", 1024 .parent_data = camcc_parent_data_0, 1025 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 1026 .ops = &clk_rcg2_shared_ops, 1027 }, 1028 }; 1029 1030 static const struct freq_tbl ftbl_camcc_ife_lite_0_clk_src[] = { 1031 F(320000000, P_CAMCC_PLL7_OUT_ODD, 1, 0, 0), 1032 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 1033 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0), 1034 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 1035 { } 1036 }; 1037 1038 static struct clk_rcg2 camcc_ife_lite_0_clk_src = { 1039 .cmd_rcgr = 0xc004, 1040 .mnd_width = 0, 1041 .hid_width = 5, 1042 .parent_map = camcc_parent_map_2, 1043 .freq_tbl = ftbl_camcc_ife_lite_0_clk_src, 1044 .clkr.hw.init = &(struct clk_init_data){ 1045 .name = "camcc_ife_lite_0_clk_src", 1046 .parent_data = camcc_parent_data_2, 1047 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 1048 .ops = &clk_rcg2_shared_ops, 1049 }, 1050 }; 1051 1052 static struct clk_rcg2 camcc_ife_lite_0_csid_clk_src = { 1053 .cmd_rcgr = 0xc020, 1054 .mnd_width = 0, 1055 .hid_width = 5, 1056 .parent_map = camcc_parent_map_0, 1057 .freq_tbl = ftbl_camcc_ife_2_csid_clk_src, 1058 .clkr.hw.init = &(struct clk_init_data){ 1059 .name = "camcc_ife_lite_0_csid_clk_src", 1060 .parent_data = camcc_parent_data_0, 1061 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 1062 .ops = &clk_rcg2_shared_ops, 1063 }, 1064 }; 1065 1066 static struct clk_rcg2 camcc_ife_lite_1_clk_src = { 1067 .cmd_rcgr = 0xc048, 1068 .mnd_width = 0, 1069 .hid_width = 5, 1070 .parent_map = camcc_parent_map_2, 1071 .freq_tbl = ftbl_camcc_ife_lite_0_clk_src, 1072 .clkr.hw.init = &(struct clk_init_data){ 1073 .name = "camcc_ife_lite_1_clk_src", 1074 .parent_data = camcc_parent_data_2, 1075 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 1076 .ops = &clk_rcg2_shared_ops, 1077 }, 1078 }; 1079 1080 static struct clk_rcg2 camcc_ife_lite_1_csid_clk_src = { 1081 .cmd_rcgr = 0xc064, 1082 .mnd_width = 0, 1083 .hid_width = 5, 1084 .parent_map = camcc_parent_map_0, 1085 .freq_tbl = ftbl_camcc_ife_2_csid_clk_src, 1086 .clkr.hw.init = &(struct clk_init_data){ 1087 .name = "camcc_ife_lite_1_csid_clk_src", 1088 .parent_data = camcc_parent_data_0, 1089 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 1090 .ops = &clk_rcg2_shared_ops, 1091 }, 1092 }; 1093 1094 static struct clk_rcg2 camcc_ife_lite_2_clk_src = { 1095 .cmd_rcgr = 0xc240, 1096 .mnd_width = 0, 1097 .hid_width = 5, 1098 .parent_map = camcc_parent_map_2, 1099 .freq_tbl = ftbl_camcc_ife_lite_0_clk_src, 1100 .clkr.hw.init = &(struct clk_init_data){ 1101 .name = "camcc_ife_lite_2_clk_src", 1102 .parent_data = camcc_parent_data_2, 1103 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 1104 .ops = &clk_rcg2_shared_ops, 1105 }, 1106 }; 1107 1108 static struct clk_rcg2 camcc_ife_lite_2_csid_clk_src = { 1109 .cmd_rcgr = 0xc25c, 1110 .mnd_width = 0, 1111 .hid_width = 5, 1112 .parent_map = camcc_parent_map_0, 1113 .freq_tbl = ftbl_camcc_ife_2_csid_clk_src, 1114 .clkr.hw.init = &(struct clk_init_data){ 1115 .name = "camcc_ife_lite_2_csid_clk_src", 1116 .parent_data = camcc_parent_data_0, 1117 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 1118 .ops = &clk_rcg2_shared_ops, 1119 }, 1120 }; 1121 1122 static struct clk_rcg2 camcc_ife_lite_3_clk_src = { 1123 .cmd_rcgr = 0xc284, 1124 .mnd_width = 0, 1125 .hid_width = 5, 1126 .parent_map = camcc_parent_map_2, 1127 .freq_tbl = ftbl_camcc_ife_lite_0_clk_src, 1128 .clkr.hw.init = &(struct clk_init_data){ 1129 .name = "camcc_ife_lite_3_clk_src", 1130 .parent_data = camcc_parent_data_2, 1131 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 1132 .ops = &clk_rcg2_shared_ops, 1133 }, 1134 }; 1135 1136 static struct clk_rcg2 camcc_ife_lite_3_csid_clk_src = { 1137 .cmd_rcgr = 0xc2a0, 1138 .mnd_width = 0, 1139 .hid_width = 5, 1140 .parent_map = camcc_parent_map_0, 1141 .freq_tbl = ftbl_camcc_ife_2_csid_clk_src, 1142 .clkr.hw.init = &(struct clk_init_data){ 1143 .name = "camcc_ife_lite_3_csid_clk_src", 1144 .parent_data = camcc_parent_data_0, 1145 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 1146 .ops = &clk_rcg2_shared_ops, 1147 }, 1148 }; 1149 1150 static const struct freq_tbl ftbl_camcc_ipe_0_clk_src[] = { 1151 F(19200000, P_BI_TCXO, 1, 0, 0), 1152 F(320000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), 1153 F(475000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), 1154 F(520000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), 1155 F(600000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), 1156 { } 1157 }; 1158 1159 static struct clk_rcg2 camcc_ipe_0_clk_src = { 1160 .cmd_rcgr = 0x8010, 1161 .mnd_width = 0, 1162 .hid_width = 5, 1163 .parent_map = camcc_parent_map_8, 1164 .freq_tbl = ftbl_camcc_ipe_0_clk_src, 1165 .clkr.hw.init = &(struct clk_init_data){ 1166 .name = "camcc_ipe_0_clk_src", 1167 .parent_data = camcc_parent_data_8, 1168 .num_parents = ARRAY_SIZE(camcc_parent_data_8), 1169 .flags = CLK_SET_RATE_PARENT, 1170 .ops = &clk_rcg2_shared_ops, 1171 }, 1172 }; 1173 1174 static const struct freq_tbl ftbl_camcc_jpeg_clk_src[] = { 1175 F(19200000, P_BI_TCXO, 1, 0, 0), 1176 F(200000000, P_CAMCC_PLL0_OUT_ODD, 2, 0, 0), 1177 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), 1178 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0), 1179 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), 1180 { } 1181 }; 1182 1183 static struct clk_rcg2 camcc_jpeg_clk_src = { 1184 .cmd_rcgr = 0xc08c, 1185 .mnd_width = 0, 1186 .hid_width = 5, 1187 .parent_map = camcc_parent_map_0, 1188 .freq_tbl = ftbl_camcc_jpeg_clk_src, 1189 .clkr.hw.init = &(struct clk_init_data){ 1190 .name = "camcc_jpeg_clk_src", 1191 .parent_data = camcc_parent_data_0, 1192 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 1193 .ops = &clk_rcg2_shared_ops, 1194 }, 1195 }; 1196 1197 static const struct freq_tbl ftbl_camcc_lrme_clk_src[] = { 1198 F(240000000, P_CAMCC_PLL7_OUT_EVEN, 2, 0, 0), 1199 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0), 1200 F(320000000, P_CAMCC_PLL7_OUT_ODD, 1, 0, 0), 1201 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), 1202 { } 1203 }; 1204 1205 static struct clk_rcg2 camcc_lrme_clk_src = { 1206 .cmd_rcgr = 0xc144, 1207 .mnd_width = 0, 1208 .hid_width = 5, 1209 .parent_map = camcc_parent_map_2, 1210 .freq_tbl = ftbl_camcc_lrme_clk_src, 1211 .clkr.hw.init = &(struct clk_init_data){ 1212 .name = "camcc_lrme_clk_src", 1213 .parent_data = camcc_parent_data_2, 1214 .num_parents = ARRAY_SIZE(camcc_parent_data_2), 1215 .ops = &clk_rcg2_shared_ops, 1216 }, 1217 }; 1218 1219 static const struct freq_tbl ftbl_camcc_mclk0_clk_src[] = { 1220 F(19200000, P_BI_TCXO, 1, 0, 0), 1221 F(24000000, P_CAMCC_PLL2_OUT_EARLY, 10, 1, 4), 1222 F(64000000, P_CAMCC_PLL2_OUT_EARLY, 15, 0, 0), 1223 { } 1224 }; 1225 1226 static struct clk_rcg2 camcc_mclk0_clk_src = { 1227 .cmd_rcgr = 0x5004, 1228 .mnd_width = 8, 1229 .hid_width = 5, 1230 .parent_map = camcc_parent_map_1, 1231 .freq_tbl = ftbl_camcc_mclk0_clk_src, 1232 .clkr.hw.init = &(struct clk_init_data){ 1233 .name = "camcc_mclk0_clk_src", 1234 .parent_data = camcc_parent_data_1, 1235 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 1236 .ops = &clk_rcg2_ops, 1237 }, 1238 }; 1239 1240 static struct clk_rcg2 camcc_mclk1_clk_src = { 1241 .cmd_rcgr = 0x5024, 1242 .mnd_width = 8, 1243 .hid_width = 5, 1244 .parent_map = camcc_parent_map_1, 1245 .freq_tbl = ftbl_camcc_mclk0_clk_src, 1246 .clkr.hw.init = &(struct clk_init_data){ 1247 .name = "camcc_mclk1_clk_src", 1248 .parent_data = camcc_parent_data_1, 1249 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 1250 .ops = &clk_rcg2_ops, 1251 }, 1252 }; 1253 1254 static struct clk_rcg2 camcc_mclk2_clk_src = { 1255 .cmd_rcgr = 0x5044, 1256 .mnd_width = 8, 1257 .hid_width = 5, 1258 .parent_map = camcc_parent_map_1, 1259 .freq_tbl = ftbl_camcc_mclk0_clk_src, 1260 .clkr.hw.init = &(struct clk_init_data){ 1261 .name = "camcc_mclk2_clk_src", 1262 .parent_data = camcc_parent_data_1, 1263 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 1264 .ops = &clk_rcg2_ops, 1265 }, 1266 }; 1267 1268 static struct clk_rcg2 camcc_mclk3_clk_src = { 1269 .cmd_rcgr = 0x5064, 1270 .mnd_width = 8, 1271 .hid_width = 5, 1272 .parent_map = camcc_parent_map_1, 1273 .freq_tbl = ftbl_camcc_mclk0_clk_src, 1274 .clkr.hw.init = &(struct clk_init_data){ 1275 .name = "camcc_mclk3_clk_src", 1276 .parent_data = camcc_parent_data_1, 1277 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 1278 .ops = &clk_rcg2_ops, 1279 }, 1280 }; 1281 1282 static struct clk_rcg2 camcc_mclk4_clk_src = { 1283 .cmd_rcgr = 0x5084, 1284 .mnd_width = 8, 1285 .hid_width = 5, 1286 .parent_map = camcc_parent_map_1, 1287 .freq_tbl = ftbl_camcc_mclk0_clk_src, 1288 .clkr.hw.init = &(struct clk_init_data){ 1289 .name = "camcc_mclk4_clk_src", 1290 .parent_data = camcc_parent_data_1, 1291 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 1292 .ops = &clk_rcg2_ops, 1293 }, 1294 }; 1295 1296 static struct clk_rcg2 camcc_mclk5_clk_src = { 1297 .cmd_rcgr = 0x50a4, 1298 .mnd_width = 8, 1299 .hid_width = 5, 1300 .parent_map = camcc_parent_map_1, 1301 .freq_tbl = ftbl_camcc_mclk0_clk_src, 1302 .clkr.hw.init = &(struct clk_init_data){ 1303 .name = "camcc_mclk5_clk_src", 1304 .parent_data = camcc_parent_data_1, 1305 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 1306 .ops = &clk_rcg2_ops, 1307 }, 1308 }; 1309 1310 static struct clk_rcg2 camcc_mclk6_clk_src = { 1311 .cmd_rcgr = 0x50c4, 1312 .mnd_width = 8, 1313 .hid_width = 5, 1314 .parent_map = camcc_parent_map_1, 1315 .freq_tbl = ftbl_camcc_mclk0_clk_src, 1316 .clkr.hw.init = &(struct clk_init_data){ 1317 .name = "camcc_mclk6_clk_src", 1318 .parent_data = camcc_parent_data_1, 1319 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 1320 .ops = &clk_rcg2_ops, 1321 }, 1322 }; 1323 1324 static struct clk_rcg2 camcc_mclk7_clk_src = { 1325 .cmd_rcgr = 0x50e4, 1326 .mnd_width = 8, 1327 .hid_width = 5, 1328 .parent_map = camcc_parent_map_1, 1329 .freq_tbl = ftbl_camcc_mclk0_clk_src, 1330 .clkr.hw.init = &(struct clk_init_data){ 1331 .name = "camcc_mclk7_clk_src", 1332 .parent_data = camcc_parent_data_1, 1333 .num_parents = ARRAY_SIZE(camcc_parent_data_1), 1334 .ops = &clk_rcg2_ops, 1335 }, 1336 }; 1337 1338 static const struct freq_tbl ftbl_camcc_sleep_clk_src[] = { 1339 F(32000, P_SLEEP_CLK, 1, 0, 0), 1340 { } 1341 }; 1342 1343 static struct clk_rcg2 camcc_sleep_clk_src = { 1344 .cmd_rcgr = 0xc1e8, 1345 .mnd_width = 0, 1346 .hid_width = 5, 1347 .parent_map = camcc_parent_map_9, 1348 .freq_tbl = ftbl_camcc_sleep_clk_src, 1349 .clkr.hw.init = &(struct clk_init_data){ 1350 .name = "camcc_sleep_clk_src", 1351 .parent_data = camcc_parent_data_9, 1352 .num_parents = ARRAY_SIZE(camcc_parent_data_9), 1353 .ops = &clk_rcg2_ops, 1354 }, 1355 }; 1356 1357 static const struct freq_tbl ftbl_camcc_slow_ahb_clk_src[] = { 1358 F(19200000, P_BI_TCXO, 1, 0, 0), 1359 F(80000000, P_CAMCC_PLL7_OUT_EVEN, 6, 0, 0), 1360 { } 1361 }; 1362 1363 static struct clk_rcg2 camcc_slow_ahb_clk_src = { 1364 .cmd_rcgr = 0x7058, 1365 .mnd_width = 8, 1366 .hid_width = 5, 1367 .parent_map = camcc_parent_map_0, 1368 .freq_tbl = ftbl_camcc_slow_ahb_clk_src, 1369 .clkr.hw.init = &(struct clk_init_data){ 1370 .name = "camcc_slow_ahb_clk_src", 1371 .parent_data = camcc_parent_data_0, 1372 .num_parents = ARRAY_SIZE(camcc_parent_data_0), 1373 .ops = &clk_rcg2_ops, 1374 }, 1375 }; 1376 1377 static const struct freq_tbl ftbl_camcc_xo_clk_src[] = { 1378 F(19200000, P_BI_TCXO, 1, 0, 0), 1379 { } 1380 }; 1381 1382 static struct clk_rcg2 camcc_xo_clk_src = { 1383 .cmd_rcgr = 0xc1cc, 1384 .mnd_width = 0, 1385 .hid_width = 5, 1386 .parent_map = camcc_parent_map_10, 1387 .freq_tbl = ftbl_camcc_xo_clk_src, 1388 .clkr.hw.init = &(struct clk_init_data){ 1389 .name = "camcc_xo_clk_src", 1390 .parent_data = camcc_parent_data_10_ao, 1391 .num_parents = ARRAY_SIZE(camcc_parent_data_10_ao), 1392 .ops = &clk_rcg2_ops, 1393 }, 1394 }; 1395 1396 static struct clk_branch camcc_bps_ahb_clk = { 1397 .halt_reg = 0x7070, 1398 .halt_check = BRANCH_HALT, 1399 .clkr = { 1400 .enable_reg = 0x7070, 1401 .enable_mask = BIT(0), 1402 .hw.init = &(struct clk_init_data){ 1403 .name = "camcc_bps_ahb_clk", 1404 .parent_hws = (const struct clk_hw*[]){ 1405 &camcc_slow_ahb_clk_src.clkr.hw, 1406 }, 1407 .num_parents = 1, 1408 .flags = CLK_SET_RATE_PARENT, 1409 .ops = &clk_branch2_ops, 1410 }, 1411 }, 1412 }; 1413 1414 static struct clk_branch camcc_bps_areg_clk = { 1415 .halt_reg = 0x7054, 1416 .halt_check = BRANCH_HALT, 1417 .clkr = { 1418 .enable_reg = 0x7054, 1419 .enable_mask = BIT(0), 1420 .hw.init = &(struct clk_init_data){ 1421 .name = "camcc_bps_areg_clk", 1422 .parent_hws = (const struct clk_hw*[]){ 1423 &camcc_fast_ahb_clk_src.clkr.hw, 1424 }, 1425 .num_parents = 1, 1426 .flags = CLK_SET_RATE_PARENT, 1427 .ops = &clk_branch2_ops, 1428 }, 1429 }, 1430 }; 1431 1432 static struct clk_branch camcc_bps_axi_clk = { 1433 .halt_reg = 0x7038, 1434 .halt_check = BRANCH_HALT, 1435 .clkr = { 1436 .enable_reg = 0x7038, 1437 .enable_mask = BIT(0), 1438 .hw.init = &(struct clk_init_data){ 1439 .name = "camcc_bps_axi_clk", 1440 .parent_hws = (const struct clk_hw*[]){ 1441 &camcc_camnoc_axi_clk_src.clkr.hw, 1442 }, 1443 .num_parents = 1, 1444 .flags = CLK_SET_RATE_PARENT, 1445 .ops = &clk_branch2_ops, 1446 }, 1447 }, 1448 }; 1449 1450 static struct clk_branch camcc_bps_clk = { 1451 .halt_reg = 0x7028, 1452 .halt_check = BRANCH_HALT, 1453 .clkr = { 1454 .enable_reg = 0x7028, 1455 .enable_mask = BIT(0), 1456 .hw.init = &(struct clk_init_data){ 1457 .name = "camcc_bps_clk", 1458 .parent_hws = (const struct clk_hw*[]){ 1459 &camcc_bps_clk_src.clkr.hw, 1460 }, 1461 .num_parents = 1, 1462 .flags = CLK_SET_RATE_PARENT, 1463 .ops = &clk_branch2_ops, 1464 }, 1465 }, 1466 }; 1467 1468 static struct clk_branch camcc_camnoc_axi_clk = { 1469 .halt_reg = 0xc18c, 1470 .halt_check = BRANCH_HALT, 1471 .clkr = { 1472 .enable_reg = 0xc18c, 1473 .enable_mask = BIT(0), 1474 .hw.init = &(struct clk_init_data){ 1475 .name = "camcc_camnoc_axi_clk", 1476 .parent_hws = (const struct clk_hw*[]){ 1477 &camcc_camnoc_axi_clk_src.clkr.hw, 1478 }, 1479 .num_parents = 1, 1480 .flags = CLK_SET_RATE_PARENT, 1481 .ops = &clk_branch2_ops, 1482 }, 1483 }, 1484 }; 1485 1486 static struct clk_branch camcc_camnoc_dcd_xo_clk = { 1487 .halt_reg = 0xc194, 1488 .halt_check = BRANCH_HALT, 1489 .clkr = { 1490 .enable_reg = 0xc194, 1491 .enable_mask = BIT(0), 1492 .hw.init = &(struct clk_init_data){ 1493 .name = "camcc_camnoc_dcd_xo_clk", 1494 .parent_hws = (const struct clk_hw*[]){ 1495 &camcc_xo_clk_src.clkr.hw, 1496 }, 1497 .num_parents = 1, 1498 .flags = CLK_SET_RATE_PARENT, 1499 .ops = &clk_branch2_ops, 1500 }, 1501 }, 1502 }; 1503 1504 static struct clk_branch camcc_cci_0_clk = { 1505 .halt_reg = 0xc120, 1506 .halt_check = BRANCH_HALT, 1507 .clkr = { 1508 .enable_reg = 0xc120, 1509 .enable_mask = BIT(0), 1510 .hw.init = &(struct clk_init_data){ 1511 .name = "camcc_cci_0_clk", 1512 .parent_hws = (const struct clk_hw*[]){ 1513 &camcc_cci_0_clk_src.clkr.hw, 1514 }, 1515 .num_parents = 1, 1516 .flags = CLK_SET_RATE_PARENT, 1517 .ops = &clk_branch2_ops, 1518 }, 1519 }, 1520 }; 1521 1522 static struct clk_branch camcc_cci_1_clk = { 1523 .halt_reg = 0xc13c, 1524 .halt_check = BRANCH_HALT, 1525 .clkr = { 1526 .enable_reg = 0xc13c, 1527 .enable_mask = BIT(0), 1528 .hw.init = &(struct clk_init_data){ 1529 .name = "camcc_cci_1_clk", 1530 .parent_hws = (const struct clk_hw*[]){ 1531 &camcc_cci_1_clk_src.clkr.hw, 1532 }, 1533 .num_parents = 1, 1534 .flags = CLK_SET_RATE_PARENT, 1535 .ops = &clk_branch2_ops, 1536 }, 1537 }, 1538 }; 1539 1540 static struct clk_branch camcc_cci_2_clk = { 1541 .halt_reg = 0xc21c, 1542 .halt_check = BRANCH_HALT, 1543 .clkr = { 1544 .enable_reg = 0xc21c, 1545 .enable_mask = BIT(0), 1546 .hw.init = &(struct clk_init_data){ 1547 .name = "camcc_cci_2_clk", 1548 .parent_hws = (const struct clk_hw*[]){ 1549 &camcc_cci_2_clk_src.clkr.hw, 1550 }, 1551 .num_parents = 1, 1552 .flags = CLK_SET_RATE_PARENT, 1553 .ops = &clk_branch2_ops, 1554 }, 1555 }, 1556 }; 1557 1558 static struct clk_branch camcc_cci_3_clk = { 1559 .halt_reg = 0xc238, 1560 .halt_check = BRANCH_HALT, 1561 .clkr = { 1562 .enable_reg = 0xc238, 1563 .enable_mask = BIT(0), 1564 .hw.init = &(struct clk_init_data){ 1565 .name = "camcc_cci_3_clk", 1566 .parent_hws = (const struct clk_hw*[]){ 1567 &camcc_cci_3_clk_src.clkr.hw, 1568 }, 1569 .num_parents = 1, 1570 .flags = CLK_SET_RATE_PARENT, 1571 .ops = &clk_branch2_ops, 1572 }, 1573 }, 1574 }; 1575 1576 static struct clk_branch camcc_core_ahb_clk = { 1577 .halt_reg = 0xc1c8, 1578 .halt_check = BRANCH_HALT_DELAY, 1579 .clkr = { 1580 .enable_reg = 0xc1c8, 1581 .enable_mask = BIT(0), 1582 .hw.init = &(struct clk_init_data){ 1583 .name = "camcc_core_ahb_clk", 1584 .parent_hws = (const struct clk_hw*[]){ 1585 &camcc_slow_ahb_clk_src.clkr.hw, 1586 }, 1587 .num_parents = 1, 1588 .flags = CLK_SET_RATE_PARENT, 1589 .ops = &clk_branch2_ops, 1590 }, 1591 }, 1592 }; 1593 1594 static struct clk_branch camcc_cpas_ahb_clk = { 1595 .halt_reg = 0xc168, 1596 .halt_check = BRANCH_HALT, 1597 .clkr = { 1598 .enable_reg = 0xc168, 1599 .enable_mask = BIT(0), 1600 .hw.init = &(struct clk_init_data){ 1601 .name = "camcc_cpas_ahb_clk", 1602 .parent_hws = (const struct clk_hw*[]){ 1603 &camcc_slow_ahb_clk_src.clkr.hw, 1604 }, 1605 .num_parents = 1, 1606 .flags = CLK_SET_RATE_PARENT, 1607 .ops = &clk_branch2_ops, 1608 }, 1609 }, 1610 }; 1611 1612 static struct clk_branch camcc_csi0phytimer_clk = { 1613 .halt_reg = 0x601c, 1614 .halt_check = BRANCH_HALT, 1615 .clkr = { 1616 .enable_reg = 0x601c, 1617 .enable_mask = BIT(0), 1618 .hw.init = &(struct clk_init_data){ 1619 .name = "camcc_csi0phytimer_clk", 1620 .parent_hws = (const struct clk_hw*[]){ 1621 &camcc_csi0phytimer_clk_src.clkr.hw, 1622 }, 1623 .num_parents = 1, 1624 .flags = CLK_SET_RATE_PARENT, 1625 .ops = &clk_branch2_ops, 1626 }, 1627 }, 1628 }; 1629 1630 static struct clk_branch camcc_csi1phytimer_clk = { 1631 .halt_reg = 0x6040, 1632 .halt_check = BRANCH_HALT, 1633 .clkr = { 1634 .enable_reg = 0x6040, 1635 .enable_mask = BIT(0), 1636 .hw.init = &(struct clk_init_data){ 1637 .name = "camcc_csi1phytimer_clk", 1638 .parent_hws = (const struct clk_hw*[]){ 1639 &camcc_csi1phytimer_clk_src.clkr.hw, 1640 }, 1641 .num_parents = 1, 1642 .flags = CLK_SET_RATE_PARENT, 1643 .ops = &clk_branch2_ops, 1644 }, 1645 }, 1646 }; 1647 1648 static struct clk_branch camcc_csi2phytimer_clk = { 1649 .halt_reg = 0x6064, 1650 .halt_check = BRANCH_HALT, 1651 .clkr = { 1652 .enable_reg = 0x6064, 1653 .enable_mask = BIT(0), 1654 .hw.init = &(struct clk_init_data){ 1655 .name = "camcc_csi2phytimer_clk", 1656 .parent_hws = (const struct clk_hw*[]){ 1657 &camcc_csi2phytimer_clk_src.clkr.hw, 1658 }, 1659 .num_parents = 1, 1660 .flags = CLK_SET_RATE_PARENT, 1661 .ops = &clk_branch2_ops, 1662 }, 1663 }, 1664 }; 1665 1666 static struct clk_branch camcc_csi3phytimer_clk = { 1667 .halt_reg = 0x608c, 1668 .halt_check = BRANCH_HALT, 1669 .clkr = { 1670 .enable_reg = 0x608c, 1671 .enable_mask = BIT(0), 1672 .hw.init = &(struct clk_init_data){ 1673 .name = "camcc_csi3phytimer_clk", 1674 .parent_hws = (const struct clk_hw*[]){ 1675 &camcc_csi3phytimer_clk_src.clkr.hw, 1676 }, 1677 .num_parents = 1, 1678 .flags = CLK_SET_RATE_PARENT, 1679 .ops = &clk_branch2_ops, 1680 }, 1681 }, 1682 }; 1683 1684 static struct clk_branch camcc_csiphy0_clk = { 1685 .halt_reg = 0x6020, 1686 .halt_check = BRANCH_HALT, 1687 .clkr = { 1688 .enable_reg = 0x6020, 1689 .enable_mask = BIT(0), 1690 .hw.init = &(struct clk_init_data){ 1691 .name = "camcc_csiphy0_clk", 1692 .parent_hws = (const struct clk_hw*[]){ 1693 &camcc_cphy_rx_clk_src.clkr.hw, 1694 }, 1695 .num_parents = 1, 1696 .flags = CLK_SET_RATE_PARENT, 1697 .ops = &clk_branch2_ops, 1698 }, 1699 }, 1700 }; 1701 1702 static struct clk_branch camcc_csiphy1_clk = { 1703 .halt_reg = 0x6044, 1704 .halt_check = BRANCH_HALT, 1705 .clkr = { 1706 .enable_reg = 0x6044, 1707 .enable_mask = BIT(0), 1708 .hw.init = &(struct clk_init_data){ 1709 .name = "camcc_csiphy1_clk", 1710 .parent_hws = (const struct clk_hw*[]){ 1711 &camcc_cphy_rx_clk_src.clkr.hw, 1712 }, 1713 .num_parents = 1, 1714 .flags = CLK_SET_RATE_PARENT, 1715 .ops = &clk_branch2_ops, 1716 }, 1717 }, 1718 }; 1719 1720 static struct clk_branch camcc_csiphy2_clk = { 1721 .halt_reg = 0x6068, 1722 .halt_check = BRANCH_HALT, 1723 .clkr = { 1724 .enable_reg = 0x6068, 1725 .enable_mask = BIT(0), 1726 .hw.init = &(struct clk_init_data){ 1727 .name = "camcc_csiphy2_clk", 1728 .parent_hws = (const struct clk_hw*[]){ 1729 &camcc_cphy_rx_clk_src.clkr.hw, 1730 }, 1731 .num_parents = 1, 1732 .flags = CLK_SET_RATE_PARENT, 1733 .ops = &clk_branch2_ops, 1734 }, 1735 }, 1736 }; 1737 1738 static struct clk_branch camcc_csiphy3_clk = { 1739 .halt_reg = 0x6090, 1740 .halt_check = BRANCH_HALT, 1741 .clkr = { 1742 .enable_reg = 0x6090, 1743 .enable_mask = BIT(0), 1744 .hw.init = &(struct clk_init_data){ 1745 .name = "camcc_csiphy3_clk", 1746 .parent_hws = (const struct clk_hw*[]){ 1747 &camcc_cphy_rx_clk_src.clkr.hw, 1748 }, 1749 .num_parents = 1, 1750 .flags = CLK_SET_RATE_PARENT, 1751 .ops = &clk_branch2_ops, 1752 }, 1753 }, 1754 }; 1755 1756 static struct clk_branch camcc_icp_ahb_clk = { 1757 .halt_reg = 0xc0d8, 1758 .halt_check = BRANCH_HALT, 1759 .clkr = { 1760 .enable_reg = 0xc0d8, 1761 .enable_mask = BIT(0), 1762 .hw.init = &(struct clk_init_data){ 1763 .name = "camcc_icp_ahb_clk", 1764 .parent_hws = (const struct clk_hw*[]){ 1765 &camcc_slow_ahb_clk_src.clkr.hw, 1766 }, 1767 .num_parents = 1, 1768 .flags = CLK_SET_RATE_PARENT, 1769 .ops = &clk_branch2_ops, 1770 }, 1771 }, 1772 }; 1773 1774 static struct clk_branch camcc_icp_clk = { 1775 .halt_reg = 0xc0d0, 1776 .halt_check = BRANCH_HALT, 1777 .clkr = { 1778 .enable_reg = 0xc0d0, 1779 .enable_mask = BIT(0), 1780 .hw.init = &(struct clk_init_data){ 1781 .name = "camcc_icp_clk", 1782 .parent_hws = (const struct clk_hw*[]){ 1783 &camcc_icp_clk_src.clkr.hw, 1784 }, 1785 .num_parents = 1, 1786 .flags = CLK_SET_RATE_PARENT, 1787 .ops = &clk_branch2_ops, 1788 }, 1789 }, 1790 }; 1791 1792 static struct clk_branch camcc_ife_0_axi_clk = { 1793 .halt_reg = 0xa080, 1794 .halt_check = BRANCH_HALT, 1795 .clkr = { 1796 .enable_reg = 0xa080, 1797 .enable_mask = BIT(0), 1798 .hw.init = &(struct clk_init_data){ 1799 .name = "camcc_ife_0_axi_clk", 1800 .parent_hws = (const struct clk_hw*[]){ 1801 &camcc_camnoc_axi_clk_src.clkr.hw, 1802 }, 1803 .num_parents = 1, 1804 .flags = CLK_SET_RATE_PARENT, 1805 .ops = &clk_branch2_ops, 1806 }, 1807 }, 1808 }; 1809 1810 static struct clk_branch camcc_ife_0_clk = { 1811 .halt_reg = 0xa028, 1812 .halt_check = BRANCH_HALT, 1813 .clkr = { 1814 .enable_reg = 0xa028, 1815 .enable_mask = BIT(0), 1816 .hw.init = &(struct clk_init_data){ 1817 .name = "camcc_ife_0_clk", 1818 .parent_hws = (const struct clk_hw*[]){ 1819 &camcc_ife_0_clk_src.clkr.hw, 1820 }, 1821 .num_parents = 1, 1822 .flags = CLK_SET_RATE_PARENT, 1823 .ops = &clk_branch2_ops, 1824 }, 1825 }, 1826 }; 1827 1828 static struct clk_branch camcc_ife_0_cphy_rx_clk = { 1829 .halt_reg = 0xa07c, 1830 .halt_check = BRANCH_HALT, 1831 .clkr = { 1832 .enable_reg = 0xa07c, 1833 .enable_mask = BIT(0), 1834 .hw.init = &(struct clk_init_data){ 1835 .name = "camcc_ife_0_cphy_rx_clk", 1836 .parent_hws = (const struct clk_hw*[]){ 1837 &camcc_cphy_rx_clk_src.clkr.hw, 1838 }, 1839 .num_parents = 1, 1840 .flags = CLK_SET_RATE_PARENT, 1841 .ops = &clk_branch2_ops, 1842 }, 1843 }, 1844 }; 1845 1846 static struct clk_branch camcc_ife_0_csid_clk = { 1847 .halt_reg = 0xa054, 1848 .halt_check = BRANCH_HALT, 1849 .clkr = { 1850 .enable_reg = 0xa054, 1851 .enable_mask = BIT(0), 1852 .hw.init = &(struct clk_init_data){ 1853 .name = "camcc_ife_0_csid_clk", 1854 .parent_hws = (const struct clk_hw*[]){ 1855 &camcc_ife_0_csid_clk_src.clkr.hw, 1856 }, 1857 .num_parents = 1, 1858 .flags = CLK_SET_RATE_PARENT, 1859 .ops = &clk_branch2_ops, 1860 }, 1861 }, 1862 }; 1863 1864 static struct clk_branch camcc_ife_0_dsp_clk = { 1865 .halt_reg = 0xa038, 1866 .halt_check = BRANCH_HALT, 1867 .clkr = { 1868 .enable_reg = 0xa038, 1869 .enable_mask = BIT(0), 1870 .hw.init = &(struct clk_init_data){ 1871 .name = "camcc_ife_0_dsp_clk", 1872 .parent_hws = (const struct clk_hw*[]){ 1873 &camcc_ife_0_clk_src.clkr.hw, 1874 }, 1875 .num_parents = 1, 1876 .flags = CLK_SET_RATE_PARENT, 1877 .ops = &clk_branch2_ops, 1878 }, 1879 }, 1880 }; 1881 1882 static struct clk_branch camcc_ife_1_axi_clk = { 1883 .halt_reg = 0xb068, 1884 .halt_check = BRANCH_HALT, 1885 .clkr = { 1886 .enable_reg = 0xb068, 1887 .enable_mask = BIT(0), 1888 .hw.init = &(struct clk_init_data){ 1889 .name = "camcc_ife_1_axi_clk", 1890 .parent_hws = (const struct clk_hw*[]){ 1891 &camcc_camnoc_axi_clk_src.clkr.hw, 1892 }, 1893 .num_parents = 1, 1894 .flags = CLK_SET_RATE_PARENT, 1895 .ops = &clk_branch2_ops, 1896 }, 1897 }, 1898 }; 1899 1900 static struct clk_branch camcc_ife_1_clk = { 1901 .halt_reg = 0xb028, 1902 .halt_check = BRANCH_HALT, 1903 .clkr = { 1904 .enable_reg = 0xb028, 1905 .enable_mask = BIT(0), 1906 .hw.init = &(struct clk_init_data){ 1907 .name = "camcc_ife_1_clk", 1908 .parent_hws = (const struct clk_hw*[]){ 1909 &camcc_ife_1_clk_src.clkr.hw, 1910 }, 1911 .num_parents = 1, 1912 .flags = CLK_SET_RATE_PARENT, 1913 .ops = &clk_branch2_ops, 1914 }, 1915 }, 1916 }; 1917 1918 static struct clk_branch camcc_ife_1_cphy_rx_clk = { 1919 .halt_reg = 0xb064, 1920 .halt_check = BRANCH_HALT, 1921 .clkr = { 1922 .enable_reg = 0xb064, 1923 .enable_mask = BIT(0), 1924 .hw.init = &(struct clk_init_data){ 1925 .name = "camcc_ife_1_cphy_rx_clk", 1926 .parent_hws = (const struct clk_hw*[]){ 1927 &camcc_cphy_rx_clk_src.clkr.hw, 1928 }, 1929 .num_parents = 1, 1930 .flags = CLK_SET_RATE_PARENT, 1931 .ops = &clk_branch2_ops, 1932 }, 1933 }, 1934 }; 1935 1936 static struct clk_branch camcc_ife_1_csid_clk = { 1937 .halt_reg = 0xb054, 1938 .halt_check = BRANCH_HALT, 1939 .clkr = { 1940 .enable_reg = 0xb054, 1941 .enable_mask = BIT(0), 1942 .hw.init = &(struct clk_init_data){ 1943 .name = "camcc_ife_1_csid_clk", 1944 .parent_hws = (const struct clk_hw*[]){ 1945 &camcc_ife_1_csid_clk_src.clkr.hw, 1946 }, 1947 .num_parents = 1, 1948 .flags = CLK_SET_RATE_PARENT, 1949 .ops = &clk_branch2_ops, 1950 }, 1951 }, 1952 }; 1953 1954 static struct clk_branch camcc_ife_1_dsp_clk = { 1955 .halt_reg = 0xb038, 1956 .halt_check = BRANCH_HALT, 1957 .clkr = { 1958 .enable_reg = 0xb038, 1959 .enable_mask = BIT(0), 1960 .hw.init = &(struct clk_init_data){ 1961 .name = "camcc_ife_1_dsp_clk", 1962 .parent_hws = (const struct clk_hw*[]){ 1963 &camcc_ife_1_clk_src.clkr.hw, 1964 }, 1965 .num_parents = 1, 1966 .flags = CLK_SET_RATE_PARENT, 1967 .ops = &clk_branch2_ops, 1968 }, 1969 }, 1970 }; 1971 1972 static struct clk_branch camcc_ife_2_axi_clk = { 1973 .halt_reg = 0xf068, 1974 .halt_check = BRANCH_HALT, 1975 .clkr = { 1976 .enable_reg = 0xf068, 1977 .enable_mask = BIT(0), 1978 .hw.init = &(struct clk_init_data){ 1979 .name = "camcc_ife_2_axi_clk", 1980 .parent_hws = (const struct clk_hw*[]){ 1981 &camcc_camnoc_axi_clk_src.clkr.hw, 1982 }, 1983 .num_parents = 1, 1984 .flags = CLK_SET_RATE_PARENT, 1985 .ops = &clk_branch2_ops, 1986 }, 1987 }, 1988 }; 1989 1990 static struct clk_branch camcc_ife_2_clk = { 1991 .halt_reg = 0xf028, 1992 .halt_check = BRANCH_HALT, 1993 .clkr = { 1994 .enable_reg = 0xf028, 1995 .enable_mask = BIT(0), 1996 .hw.init = &(struct clk_init_data){ 1997 .name = "camcc_ife_2_clk", 1998 .parent_hws = (const struct clk_hw*[]){ 1999 &camcc_ife_2_clk_src.clkr.hw, 2000 }, 2001 .num_parents = 1, 2002 .flags = CLK_SET_RATE_PARENT, 2003 .ops = &clk_branch2_ops, 2004 }, 2005 }, 2006 }; 2007 2008 static struct clk_branch camcc_ife_2_cphy_rx_clk = { 2009 .halt_reg = 0xf064, 2010 .halt_check = BRANCH_HALT, 2011 .clkr = { 2012 .enable_reg = 0xf064, 2013 .enable_mask = BIT(0), 2014 .hw.init = &(struct clk_init_data){ 2015 .name = "camcc_ife_2_cphy_rx_clk", 2016 .parent_hws = (const struct clk_hw*[]){ 2017 &camcc_cphy_rx_clk_src.clkr.hw, 2018 }, 2019 .num_parents = 1, 2020 .flags = CLK_SET_RATE_PARENT, 2021 .ops = &clk_branch2_ops, 2022 }, 2023 }, 2024 }; 2025 2026 static struct clk_branch camcc_ife_2_csid_clk = { 2027 .halt_reg = 0xf054, 2028 .halt_check = BRANCH_HALT, 2029 .clkr = { 2030 .enable_reg = 0xf054, 2031 .enable_mask = BIT(0), 2032 .hw.init = &(struct clk_init_data){ 2033 .name = "camcc_ife_2_csid_clk", 2034 .parent_hws = (const struct clk_hw*[]){ 2035 &camcc_ife_2_csid_clk_src.clkr.hw, 2036 }, 2037 .num_parents = 1, 2038 .flags = CLK_SET_RATE_PARENT, 2039 .ops = &clk_branch2_ops, 2040 }, 2041 }, 2042 }; 2043 2044 static struct clk_branch camcc_ife_2_dsp_clk = { 2045 .halt_reg = 0xf038, 2046 .halt_check = BRANCH_HALT, 2047 .clkr = { 2048 .enable_reg = 0xf038, 2049 .enable_mask = BIT(0), 2050 .hw.init = &(struct clk_init_data){ 2051 .name = "camcc_ife_2_dsp_clk", 2052 .parent_hws = (const struct clk_hw*[]){ 2053 &camcc_ife_2_clk_src.clkr.hw, 2054 }, 2055 .num_parents = 1, 2056 .flags = CLK_SET_RATE_PARENT, 2057 .ops = &clk_branch2_ops, 2058 }, 2059 }, 2060 }; 2061 2062 static struct clk_branch camcc_ife_3_axi_clk = { 2063 .halt_reg = 0xf0d4, 2064 .halt_check = BRANCH_HALT, 2065 .clkr = { 2066 .enable_reg = 0xf0d4, 2067 .enable_mask = BIT(0), 2068 .hw.init = &(struct clk_init_data){ 2069 .name = "camcc_ife_3_axi_clk", 2070 .parent_hws = (const struct clk_hw*[]){ 2071 &camcc_camnoc_axi_clk_src.clkr.hw, 2072 }, 2073 .num_parents = 1, 2074 .flags = CLK_SET_RATE_PARENT, 2075 .ops = &clk_branch2_ops, 2076 }, 2077 }, 2078 }; 2079 2080 static struct clk_branch camcc_ife_3_clk = { 2081 .halt_reg = 0xf094, 2082 .halt_check = BRANCH_HALT, 2083 .clkr = { 2084 .enable_reg = 0xf094, 2085 .enable_mask = BIT(0), 2086 .hw.init = &(struct clk_init_data){ 2087 .name = "camcc_ife_3_clk", 2088 .parent_hws = (const struct clk_hw*[]){ 2089 &camcc_ife_3_clk_src.clkr.hw, 2090 }, 2091 .num_parents = 1, 2092 .flags = CLK_SET_RATE_PARENT, 2093 .ops = &clk_branch2_ops, 2094 }, 2095 }, 2096 }; 2097 2098 static struct clk_branch camcc_ife_3_cphy_rx_clk = { 2099 .halt_reg = 0xf0d0, 2100 .halt_check = BRANCH_HALT, 2101 .clkr = { 2102 .enable_reg = 0xf0d0, 2103 .enable_mask = BIT(0), 2104 .hw.init = &(struct clk_init_data){ 2105 .name = "camcc_ife_3_cphy_rx_clk", 2106 .parent_hws = (const struct clk_hw*[]){ 2107 &camcc_cphy_rx_clk_src.clkr.hw, 2108 }, 2109 .num_parents = 1, 2110 .flags = CLK_SET_RATE_PARENT, 2111 .ops = &clk_branch2_ops, 2112 }, 2113 }, 2114 }; 2115 2116 static struct clk_branch camcc_ife_3_csid_clk = { 2117 .halt_reg = 0xf0c0, 2118 .halt_check = BRANCH_HALT, 2119 .clkr = { 2120 .enable_reg = 0xf0c0, 2121 .enable_mask = BIT(0), 2122 .hw.init = &(struct clk_init_data){ 2123 .name = "camcc_ife_3_csid_clk", 2124 .parent_hws = (const struct clk_hw*[]){ 2125 &camcc_ife_3_csid_clk_src.clkr.hw, 2126 }, 2127 .num_parents = 1, 2128 .flags = CLK_SET_RATE_PARENT, 2129 .ops = &clk_branch2_ops, 2130 }, 2131 }, 2132 }; 2133 2134 static struct clk_branch camcc_ife_3_dsp_clk = { 2135 .halt_reg = 0xf0a4, 2136 .halt_check = BRANCH_HALT, 2137 .clkr = { 2138 .enable_reg = 0xf0a4, 2139 .enable_mask = BIT(0), 2140 .hw.init = &(struct clk_init_data){ 2141 .name = "camcc_ife_3_dsp_clk", 2142 .parent_hws = (const struct clk_hw*[]){ 2143 &camcc_ife_3_clk_src.clkr.hw, 2144 }, 2145 .num_parents = 1, 2146 .flags = CLK_SET_RATE_PARENT, 2147 .ops = &clk_branch2_ops, 2148 }, 2149 }, 2150 }; 2151 2152 static struct clk_branch camcc_ife_lite_0_clk = { 2153 .halt_reg = 0xc01c, 2154 .halt_check = BRANCH_HALT, 2155 .clkr = { 2156 .enable_reg = 0xc01c, 2157 .enable_mask = BIT(0), 2158 .hw.init = &(struct clk_init_data){ 2159 .name = "camcc_ife_lite_0_clk", 2160 .parent_hws = (const struct clk_hw*[]){ 2161 &camcc_ife_lite_0_clk_src.clkr.hw, 2162 }, 2163 .num_parents = 1, 2164 .flags = CLK_SET_RATE_PARENT, 2165 .ops = &clk_branch2_ops, 2166 }, 2167 }, 2168 }; 2169 2170 static struct clk_branch camcc_ife_lite_0_cphy_rx_clk = { 2171 .halt_reg = 0xc040, 2172 .halt_check = BRANCH_HALT, 2173 .clkr = { 2174 .enable_reg = 0xc040, 2175 .enable_mask = BIT(0), 2176 .hw.init = &(struct clk_init_data){ 2177 .name = "camcc_ife_lite_0_cphy_rx_clk", 2178 .parent_hws = (const struct clk_hw*[]){ 2179 &camcc_cphy_rx_clk_src.clkr.hw, 2180 }, 2181 .num_parents = 1, 2182 .flags = CLK_SET_RATE_PARENT, 2183 .ops = &clk_branch2_ops, 2184 }, 2185 }, 2186 }; 2187 2188 static struct clk_branch camcc_ife_lite_0_csid_clk = { 2189 .halt_reg = 0xc038, 2190 .halt_check = BRANCH_HALT, 2191 .clkr = { 2192 .enable_reg = 0xc038, 2193 .enable_mask = BIT(0), 2194 .hw.init = &(struct clk_init_data){ 2195 .name = "camcc_ife_lite_0_csid_clk", 2196 .parent_hws = (const struct clk_hw*[]){ 2197 &camcc_ife_lite_0_csid_clk_src.clkr.hw, 2198 }, 2199 .num_parents = 1, 2200 .flags = CLK_SET_RATE_PARENT, 2201 .ops = &clk_branch2_ops, 2202 }, 2203 }, 2204 }; 2205 2206 static struct clk_branch camcc_ife_lite_1_clk = { 2207 .halt_reg = 0xc060, 2208 .halt_check = BRANCH_HALT, 2209 .clkr = { 2210 .enable_reg = 0xc060, 2211 .enable_mask = BIT(0), 2212 .hw.init = &(struct clk_init_data){ 2213 .name = "camcc_ife_lite_1_clk", 2214 .parent_hws = (const struct clk_hw*[]){ 2215 &camcc_ife_lite_1_clk_src.clkr.hw, 2216 }, 2217 .num_parents = 1, 2218 .flags = CLK_SET_RATE_PARENT, 2219 .ops = &clk_branch2_ops, 2220 }, 2221 }, 2222 }; 2223 2224 static struct clk_branch camcc_ife_lite_1_cphy_rx_clk = { 2225 .halt_reg = 0xc084, 2226 .halt_check = BRANCH_HALT, 2227 .clkr = { 2228 .enable_reg = 0xc084, 2229 .enable_mask = BIT(0), 2230 .hw.init = &(struct clk_init_data){ 2231 .name = "camcc_ife_lite_1_cphy_rx_clk", 2232 .parent_hws = (const struct clk_hw*[]){ 2233 &camcc_cphy_rx_clk_src.clkr.hw, 2234 }, 2235 .num_parents = 1, 2236 .flags = CLK_SET_RATE_PARENT, 2237 .ops = &clk_branch2_ops, 2238 }, 2239 }, 2240 }; 2241 2242 static struct clk_branch camcc_ife_lite_1_csid_clk = { 2243 .halt_reg = 0xc07c, 2244 .halt_check = BRANCH_HALT, 2245 .clkr = { 2246 .enable_reg = 0xc07c, 2247 .enable_mask = BIT(0), 2248 .hw.init = &(struct clk_init_data){ 2249 .name = "camcc_ife_lite_1_csid_clk", 2250 .parent_hws = (const struct clk_hw*[]){ 2251 &camcc_ife_lite_1_csid_clk_src.clkr.hw, 2252 }, 2253 .num_parents = 1, 2254 .flags = CLK_SET_RATE_PARENT, 2255 .ops = &clk_branch2_ops, 2256 }, 2257 }, 2258 }; 2259 2260 static struct clk_branch camcc_ife_lite_2_clk = { 2261 .halt_reg = 0xc258, 2262 .halt_check = BRANCH_HALT, 2263 .clkr = { 2264 .enable_reg = 0xc258, 2265 .enable_mask = BIT(0), 2266 .hw.init = &(struct clk_init_data){ 2267 .name = "camcc_ife_lite_2_clk", 2268 .parent_hws = (const struct clk_hw*[]){ 2269 &camcc_ife_lite_2_clk_src.clkr.hw, 2270 }, 2271 .num_parents = 1, 2272 .flags = CLK_SET_RATE_PARENT, 2273 .ops = &clk_branch2_ops, 2274 }, 2275 }, 2276 }; 2277 2278 static struct clk_branch camcc_ife_lite_2_cphy_rx_clk = { 2279 .halt_reg = 0xc27c, 2280 .halt_check = BRANCH_HALT, 2281 .clkr = { 2282 .enable_reg = 0xc27c, 2283 .enable_mask = BIT(0), 2284 .hw.init = &(struct clk_init_data){ 2285 .name = "camcc_ife_lite_2_cphy_rx_clk", 2286 .parent_hws = (const struct clk_hw*[]){ 2287 &camcc_cphy_rx_clk_src.clkr.hw, 2288 }, 2289 .num_parents = 1, 2290 .flags = CLK_SET_RATE_PARENT, 2291 .ops = &clk_branch2_ops, 2292 }, 2293 }, 2294 }; 2295 2296 static struct clk_branch camcc_ife_lite_2_csid_clk = { 2297 .halt_reg = 0xc274, 2298 .halt_check = BRANCH_HALT, 2299 .clkr = { 2300 .enable_reg = 0xc274, 2301 .enable_mask = BIT(0), 2302 .hw.init = &(struct clk_init_data){ 2303 .name = "camcc_ife_lite_2_csid_clk", 2304 .parent_hws = (const struct clk_hw*[]){ 2305 &camcc_ife_lite_2_csid_clk_src.clkr.hw, 2306 }, 2307 .num_parents = 1, 2308 .flags = CLK_SET_RATE_PARENT, 2309 .ops = &clk_branch2_ops, 2310 }, 2311 }, 2312 }; 2313 2314 static struct clk_branch camcc_ife_lite_3_clk = { 2315 .halt_reg = 0xc29c, 2316 .halt_check = BRANCH_HALT, 2317 .clkr = { 2318 .enable_reg = 0xc29c, 2319 .enable_mask = BIT(0), 2320 .hw.init = &(struct clk_init_data){ 2321 .name = "camcc_ife_lite_3_clk", 2322 .parent_hws = (const struct clk_hw*[]){ 2323 &camcc_ife_lite_3_clk_src.clkr.hw, 2324 }, 2325 .num_parents = 1, 2326 .flags = CLK_SET_RATE_PARENT, 2327 .ops = &clk_branch2_ops, 2328 }, 2329 }, 2330 }; 2331 2332 static struct clk_branch camcc_ife_lite_3_cphy_rx_clk = { 2333 .halt_reg = 0xc2c0, 2334 .halt_check = BRANCH_HALT, 2335 .clkr = { 2336 .enable_reg = 0xc2c0, 2337 .enable_mask = BIT(0), 2338 .hw.init = &(struct clk_init_data){ 2339 .name = "camcc_ife_lite_3_cphy_rx_clk", 2340 .parent_hws = (const struct clk_hw*[]){ 2341 &camcc_cphy_rx_clk_src.clkr.hw, 2342 }, 2343 .num_parents = 1, 2344 .flags = CLK_SET_RATE_PARENT, 2345 .ops = &clk_branch2_ops, 2346 }, 2347 }, 2348 }; 2349 2350 static struct clk_branch camcc_ife_lite_3_csid_clk = { 2351 .halt_reg = 0xc2b8, 2352 .halt_check = BRANCH_HALT, 2353 .clkr = { 2354 .enable_reg = 0xc2b8, 2355 .enable_mask = BIT(0), 2356 .hw.init = &(struct clk_init_data){ 2357 .name = "camcc_ife_lite_3_csid_clk", 2358 .parent_hws = (const struct clk_hw*[]){ 2359 &camcc_ife_lite_3_csid_clk_src.clkr.hw, 2360 }, 2361 .num_parents = 1, 2362 .flags = CLK_SET_RATE_PARENT, 2363 .ops = &clk_branch2_ops, 2364 }, 2365 }, 2366 }; 2367 2368 static struct clk_branch camcc_ipe_0_ahb_clk = { 2369 .halt_reg = 0x8040, 2370 .halt_check = BRANCH_HALT, 2371 .clkr = { 2372 .enable_reg = 0x8040, 2373 .enable_mask = BIT(0), 2374 .hw.init = &(struct clk_init_data){ 2375 .name = "camcc_ipe_0_ahb_clk", 2376 .parent_hws = (const struct clk_hw*[]){ 2377 &camcc_slow_ahb_clk_src.clkr.hw, 2378 }, 2379 .num_parents = 1, 2380 .flags = CLK_SET_RATE_PARENT, 2381 .ops = &clk_branch2_ops, 2382 }, 2383 }, 2384 }; 2385 2386 static struct clk_branch camcc_ipe_0_areg_clk = { 2387 .halt_reg = 0x803c, 2388 .halt_check = BRANCH_HALT, 2389 .clkr = { 2390 .enable_reg = 0x803c, 2391 .enable_mask = BIT(0), 2392 .hw.init = &(struct clk_init_data){ 2393 .name = "camcc_ipe_0_areg_clk", 2394 .parent_hws = (const struct clk_hw*[]){ 2395 &camcc_fast_ahb_clk_src.clkr.hw, 2396 }, 2397 .num_parents = 1, 2398 .flags = CLK_SET_RATE_PARENT, 2399 .ops = &clk_branch2_ops, 2400 }, 2401 }, 2402 }; 2403 2404 static struct clk_branch camcc_ipe_0_axi_clk = { 2405 .halt_reg = 0x8038, 2406 .halt_check = BRANCH_HALT, 2407 .clkr = { 2408 .enable_reg = 0x8038, 2409 .enable_mask = BIT(0), 2410 .hw.init = &(struct clk_init_data){ 2411 .name = "camcc_ipe_0_axi_clk", 2412 .parent_hws = (const struct clk_hw*[]){ 2413 &camcc_camnoc_axi_clk_src.clkr.hw, 2414 }, 2415 .num_parents = 1, 2416 .flags = CLK_SET_RATE_PARENT, 2417 .ops = &clk_branch2_ops, 2418 }, 2419 }, 2420 }; 2421 2422 static struct clk_branch camcc_ipe_0_clk = { 2423 .halt_reg = 0x8028, 2424 .halt_check = BRANCH_HALT, 2425 .clkr = { 2426 .enable_reg = 0x8028, 2427 .enable_mask = BIT(0), 2428 .hw.init = &(struct clk_init_data){ 2429 .name = "camcc_ipe_0_clk", 2430 .parent_hws = (const struct clk_hw*[]){ 2431 &camcc_ipe_0_clk_src.clkr.hw, 2432 }, 2433 .num_parents = 1, 2434 .flags = CLK_SET_RATE_PARENT, 2435 .ops = &clk_branch2_ops, 2436 }, 2437 }, 2438 }; 2439 2440 static struct clk_branch camcc_ipe_1_ahb_clk = { 2441 .halt_reg = 0x9028, 2442 .halt_check = BRANCH_HALT, 2443 .clkr = { 2444 .enable_reg = 0x9028, 2445 .enable_mask = BIT(0), 2446 .hw.init = &(struct clk_init_data){ 2447 .name = "camcc_ipe_1_ahb_clk", 2448 .parent_hws = (const struct clk_hw*[]){ 2449 &camcc_slow_ahb_clk_src.clkr.hw, 2450 }, 2451 .num_parents = 1, 2452 .flags = CLK_SET_RATE_PARENT, 2453 .ops = &clk_branch2_ops, 2454 }, 2455 }, 2456 }; 2457 2458 static struct clk_branch camcc_ipe_1_areg_clk = { 2459 .halt_reg = 0x9024, 2460 .halt_check = BRANCH_HALT, 2461 .clkr = { 2462 .enable_reg = 0x9024, 2463 .enable_mask = BIT(0), 2464 .hw.init = &(struct clk_init_data){ 2465 .name = "camcc_ipe_1_areg_clk", 2466 .parent_hws = (const struct clk_hw*[]){ 2467 &camcc_fast_ahb_clk_src.clkr.hw, 2468 }, 2469 .num_parents = 1, 2470 .flags = CLK_SET_RATE_PARENT, 2471 .ops = &clk_branch2_ops, 2472 }, 2473 }, 2474 }; 2475 2476 static struct clk_branch camcc_ipe_1_axi_clk = { 2477 .halt_reg = 0x9020, 2478 .halt_check = BRANCH_HALT, 2479 .clkr = { 2480 .enable_reg = 0x9020, 2481 .enable_mask = BIT(0), 2482 .hw.init = &(struct clk_init_data){ 2483 .name = "camcc_ipe_1_axi_clk", 2484 .parent_hws = (const struct clk_hw*[]){ 2485 &camcc_camnoc_axi_clk_src.clkr.hw, 2486 }, 2487 .num_parents = 1, 2488 .flags = CLK_SET_RATE_PARENT, 2489 .ops = &clk_branch2_ops, 2490 }, 2491 }, 2492 }; 2493 2494 static struct clk_branch camcc_ipe_1_clk = { 2495 .halt_reg = 0x9010, 2496 .halt_check = BRANCH_HALT, 2497 .clkr = { 2498 .enable_reg = 0x9010, 2499 .enable_mask = BIT(0), 2500 .hw.init = &(struct clk_init_data){ 2501 .name = "camcc_ipe_1_clk", 2502 .parent_hws = (const struct clk_hw*[]){ 2503 &camcc_ipe_0_clk_src.clkr.hw, 2504 }, 2505 .num_parents = 1, 2506 .flags = CLK_SET_RATE_PARENT, 2507 .ops = &clk_branch2_ops, 2508 }, 2509 }, 2510 }; 2511 2512 static struct clk_branch camcc_jpeg_clk = { 2513 .halt_reg = 0xc0a4, 2514 .halt_check = BRANCH_HALT, 2515 .clkr = { 2516 .enable_reg = 0xc0a4, 2517 .enable_mask = BIT(0), 2518 .hw.init = &(struct clk_init_data){ 2519 .name = "camcc_jpeg_clk", 2520 .parent_hws = (const struct clk_hw*[]){ 2521 &camcc_jpeg_clk_src.clkr.hw, 2522 }, 2523 .num_parents = 1, 2524 .flags = CLK_SET_RATE_PARENT, 2525 .ops = &clk_branch2_ops, 2526 }, 2527 }, 2528 }; 2529 2530 static struct clk_branch camcc_lrme_clk = { 2531 .halt_reg = 0xc15c, 2532 .halt_check = BRANCH_HALT, 2533 .clkr = { 2534 .enable_reg = 0xc15c, 2535 .enable_mask = BIT(0), 2536 .hw.init = &(struct clk_init_data){ 2537 .name = "camcc_lrme_clk", 2538 .parent_hws = (const struct clk_hw*[]){ 2539 &camcc_lrme_clk_src.clkr.hw, 2540 }, 2541 .num_parents = 1, 2542 .flags = CLK_SET_RATE_PARENT, 2543 .ops = &clk_branch2_ops, 2544 }, 2545 }, 2546 }; 2547 2548 static struct clk_branch camcc_mclk0_clk = { 2549 .halt_reg = 0x501c, 2550 .halt_check = BRANCH_HALT, 2551 .clkr = { 2552 .enable_reg = 0x501c, 2553 .enable_mask = BIT(0), 2554 .hw.init = &(struct clk_init_data){ 2555 .name = "camcc_mclk0_clk", 2556 .parent_hws = (const struct clk_hw*[]){ 2557 &camcc_mclk0_clk_src.clkr.hw, 2558 }, 2559 .num_parents = 1, 2560 .flags = CLK_SET_RATE_PARENT, 2561 .ops = &clk_branch2_ops, 2562 }, 2563 }, 2564 }; 2565 2566 static struct clk_branch camcc_mclk1_clk = { 2567 .halt_reg = 0x503c, 2568 .halt_check = BRANCH_HALT, 2569 .clkr = { 2570 .enable_reg = 0x503c, 2571 .enable_mask = BIT(0), 2572 .hw.init = &(struct clk_init_data){ 2573 .name = "camcc_mclk1_clk", 2574 .parent_hws = (const struct clk_hw*[]){ 2575 &camcc_mclk1_clk_src.clkr.hw, 2576 }, 2577 .num_parents = 1, 2578 .flags = CLK_SET_RATE_PARENT, 2579 .ops = &clk_branch2_ops, 2580 }, 2581 }, 2582 }; 2583 2584 static struct clk_branch camcc_mclk2_clk = { 2585 .halt_reg = 0x505c, 2586 .halt_check = BRANCH_HALT, 2587 .clkr = { 2588 .enable_reg = 0x505c, 2589 .enable_mask = BIT(0), 2590 .hw.init = &(struct clk_init_data){ 2591 .name = "camcc_mclk2_clk", 2592 .parent_hws = (const struct clk_hw*[]){ 2593 &camcc_mclk2_clk_src.clkr.hw, 2594 }, 2595 .num_parents = 1, 2596 .flags = CLK_SET_RATE_PARENT, 2597 .ops = &clk_branch2_ops, 2598 }, 2599 }, 2600 }; 2601 2602 static struct clk_branch camcc_mclk3_clk = { 2603 .halt_reg = 0x507c, 2604 .halt_check = BRANCH_HALT, 2605 .clkr = { 2606 .enable_reg = 0x507c, 2607 .enable_mask = BIT(0), 2608 .hw.init = &(struct clk_init_data){ 2609 .name = "camcc_mclk3_clk", 2610 .parent_hws = (const struct clk_hw*[]){ 2611 &camcc_mclk3_clk_src.clkr.hw, 2612 }, 2613 .num_parents = 1, 2614 .flags = CLK_SET_RATE_PARENT, 2615 .ops = &clk_branch2_ops, 2616 }, 2617 }, 2618 }; 2619 2620 static struct clk_branch camcc_mclk4_clk = { 2621 .halt_reg = 0x509c, 2622 .halt_check = BRANCH_HALT, 2623 .clkr = { 2624 .enable_reg = 0x509c, 2625 .enable_mask = BIT(0), 2626 .hw.init = &(struct clk_init_data){ 2627 .name = "camcc_mclk4_clk", 2628 .parent_hws = (const struct clk_hw*[]){ 2629 &camcc_mclk4_clk_src.clkr.hw, 2630 }, 2631 .num_parents = 1, 2632 .flags = CLK_SET_RATE_PARENT, 2633 .ops = &clk_branch2_ops, 2634 }, 2635 }, 2636 }; 2637 2638 static struct clk_branch camcc_mclk5_clk = { 2639 .halt_reg = 0x50bc, 2640 .halt_check = BRANCH_HALT, 2641 .clkr = { 2642 .enable_reg = 0x50bc, 2643 .enable_mask = BIT(0), 2644 .hw.init = &(struct clk_init_data){ 2645 .name = "camcc_mclk5_clk", 2646 .parent_hws = (const struct clk_hw*[]){ 2647 &camcc_mclk5_clk_src.clkr.hw, 2648 }, 2649 .num_parents = 1, 2650 .flags = CLK_SET_RATE_PARENT, 2651 .ops = &clk_branch2_ops, 2652 }, 2653 }, 2654 }; 2655 2656 static struct clk_branch camcc_mclk6_clk = { 2657 .halt_reg = 0x50dc, 2658 .halt_check = BRANCH_HALT, 2659 .clkr = { 2660 .enable_reg = 0x50dc, 2661 .enable_mask = BIT(0), 2662 .hw.init = &(struct clk_init_data){ 2663 .name = "camcc_mclk6_clk", 2664 .parent_hws = (const struct clk_hw*[]){ 2665 &camcc_mclk6_clk_src.clkr.hw, 2666 }, 2667 .num_parents = 1, 2668 .flags = CLK_SET_RATE_PARENT, 2669 .ops = &clk_branch2_ops, 2670 }, 2671 }, 2672 }; 2673 2674 static struct clk_branch camcc_mclk7_clk = { 2675 .halt_reg = 0x50fc, 2676 .halt_check = BRANCH_HALT, 2677 .clkr = { 2678 .enable_reg = 0x50fc, 2679 .enable_mask = BIT(0), 2680 .hw.init = &(struct clk_init_data){ 2681 .name = "camcc_mclk7_clk", 2682 .parent_hws = (const struct clk_hw*[]){ 2683 &camcc_mclk7_clk_src.clkr.hw, 2684 }, 2685 .num_parents = 1, 2686 .flags = CLK_SET_RATE_PARENT, 2687 .ops = &clk_branch2_ops, 2688 }, 2689 }, 2690 }; 2691 2692 static struct clk_branch camcc_sleep_clk = { 2693 .halt_reg = 0xc200, 2694 .halt_check = BRANCH_HALT, 2695 .clkr = { 2696 .enable_reg = 0xc200, 2697 .enable_mask = BIT(0), 2698 .hw.init = &(struct clk_init_data){ 2699 .name = "camcc_sleep_clk", 2700 .parent_hws = (const struct clk_hw*[]){ 2701 &camcc_sleep_clk_src.clkr.hw, 2702 }, 2703 .num_parents = 1, 2704 .flags = CLK_SET_RATE_PARENT, 2705 .ops = &clk_branch2_ops, 2706 }, 2707 }, 2708 }; 2709 2710 static struct gdsc titan_top_gdsc; 2711 2712 static struct gdsc bps_gdsc = { 2713 .gdscr = 0x7004, 2714 .pd = { 2715 .name = "bps_gdsc", 2716 }, 2717 .flags = HW_CTRL | RETAIN_FF_ENABLE, 2718 .parent = &titan_top_gdsc.pd, 2719 .pwrsts = PWRSTS_OFF_ON, 2720 }; 2721 2722 static struct gdsc ife_0_gdsc = { 2723 .gdscr = 0xa004, 2724 .pd = { 2725 .name = "ife_0_gdsc", 2726 }, 2727 .flags = RETAIN_FF_ENABLE, 2728 .parent = &titan_top_gdsc.pd, 2729 .pwrsts = PWRSTS_OFF_ON, 2730 }; 2731 2732 static struct gdsc ife_1_gdsc = { 2733 .gdscr = 0xb004, 2734 .pd = { 2735 .name = "ife_1_gdsc", 2736 }, 2737 .flags = RETAIN_FF_ENABLE, 2738 .parent = &titan_top_gdsc.pd, 2739 .pwrsts = PWRSTS_OFF_ON, 2740 }; 2741 2742 static struct gdsc ife_2_gdsc = { 2743 .gdscr = 0xf004, 2744 .pd = { 2745 .name = "ife_2_gdsc", 2746 }, 2747 .flags = RETAIN_FF_ENABLE, 2748 .parent = &titan_top_gdsc.pd, 2749 .pwrsts = PWRSTS_OFF_ON, 2750 }; 2751 2752 static struct gdsc ife_3_gdsc = { 2753 .gdscr = 0xf070, 2754 .pd = { 2755 .name = "ife_3_gdsc", 2756 }, 2757 .flags = RETAIN_FF_ENABLE, 2758 .parent = &titan_top_gdsc.pd, 2759 .pwrsts = PWRSTS_OFF_ON, 2760 }; 2761 2762 static struct gdsc ipe_0_gdsc = { 2763 .gdscr = 0x8004, 2764 .pd = { 2765 .name = "ipe_0_gdsc", 2766 }, 2767 .flags = HW_CTRL | RETAIN_FF_ENABLE, 2768 .parent = &titan_top_gdsc.pd, 2769 .pwrsts = PWRSTS_OFF_ON, 2770 }; 2771 2772 static struct gdsc ipe_1_gdsc = { 2773 .gdscr = 0x9004, 2774 .pd = { 2775 .name = "ipe_1_gdsc", 2776 }, 2777 .flags = HW_CTRL | RETAIN_FF_ENABLE, 2778 .parent = &titan_top_gdsc.pd, 2779 .pwrsts = PWRSTS_OFF_ON, 2780 }; 2781 2782 static struct gdsc titan_top_gdsc = { 2783 .gdscr = 0xc1bc, 2784 .pd = { 2785 .name = "titan_top_gdsc", 2786 }, 2787 .flags = RETAIN_FF_ENABLE, 2788 .pwrsts = PWRSTS_OFF_ON, 2789 }; 2790 2791 static struct clk_regmap *camcc_sc8280xp_clocks[] = { 2792 [CAMCC_BPS_AHB_CLK] = &camcc_bps_ahb_clk.clkr, 2793 [CAMCC_BPS_AREG_CLK] = &camcc_bps_areg_clk.clkr, 2794 [CAMCC_BPS_AXI_CLK] = &camcc_bps_axi_clk.clkr, 2795 [CAMCC_BPS_CLK] = &camcc_bps_clk.clkr, 2796 [CAMCC_BPS_CLK_SRC] = &camcc_bps_clk_src.clkr, 2797 [CAMCC_CAMNOC_AXI_CLK] = &camcc_camnoc_axi_clk.clkr, 2798 [CAMCC_CAMNOC_AXI_CLK_SRC] = &camcc_camnoc_axi_clk_src.clkr, 2799 [CAMCC_CAMNOC_DCD_XO_CLK] = &camcc_camnoc_dcd_xo_clk.clkr, 2800 [CAMCC_CCI_0_CLK] = &camcc_cci_0_clk.clkr, 2801 [CAMCC_CCI_0_CLK_SRC] = &camcc_cci_0_clk_src.clkr, 2802 [CAMCC_CCI_1_CLK] = &camcc_cci_1_clk.clkr, 2803 [CAMCC_CCI_1_CLK_SRC] = &camcc_cci_1_clk_src.clkr, 2804 [CAMCC_CCI_2_CLK] = &camcc_cci_2_clk.clkr, 2805 [CAMCC_CCI_2_CLK_SRC] = &camcc_cci_2_clk_src.clkr, 2806 [CAMCC_CCI_3_CLK] = &camcc_cci_3_clk.clkr, 2807 [CAMCC_CCI_3_CLK_SRC] = &camcc_cci_3_clk_src.clkr, 2808 [CAMCC_CORE_AHB_CLK] = &camcc_core_ahb_clk.clkr, 2809 [CAMCC_CPAS_AHB_CLK] = &camcc_cpas_ahb_clk.clkr, 2810 [CAMCC_CPHY_RX_CLK_SRC] = &camcc_cphy_rx_clk_src.clkr, 2811 [CAMCC_CSI0PHYTIMER_CLK] = &camcc_csi0phytimer_clk.clkr, 2812 [CAMCC_CSI0PHYTIMER_CLK_SRC] = &camcc_csi0phytimer_clk_src.clkr, 2813 [CAMCC_CSI1PHYTIMER_CLK] = &camcc_csi1phytimer_clk.clkr, 2814 [CAMCC_CSI1PHYTIMER_CLK_SRC] = &camcc_csi1phytimer_clk_src.clkr, 2815 [CAMCC_CSI2PHYTIMER_CLK] = &camcc_csi2phytimer_clk.clkr, 2816 [CAMCC_CSI2PHYTIMER_CLK_SRC] = &camcc_csi2phytimer_clk_src.clkr, 2817 [CAMCC_CSI3PHYTIMER_CLK] = &camcc_csi3phytimer_clk.clkr, 2818 [CAMCC_CSI3PHYTIMER_CLK_SRC] = &camcc_csi3phytimer_clk_src.clkr, 2819 [CAMCC_CSIPHY0_CLK] = &camcc_csiphy0_clk.clkr, 2820 [CAMCC_CSIPHY1_CLK] = &camcc_csiphy1_clk.clkr, 2821 [CAMCC_CSIPHY2_CLK] = &camcc_csiphy2_clk.clkr, 2822 [CAMCC_CSIPHY3_CLK] = &camcc_csiphy3_clk.clkr, 2823 [CAMCC_FAST_AHB_CLK_SRC] = &camcc_fast_ahb_clk_src.clkr, 2824 [CAMCC_ICP_AHB_CLK] = &camcc_icp_ahb_clk.clkr, 2825 [CAMCC_ICP_CLK] = &camcc_icp_clk.clkr, 2826 [CAMCC_ICP_CLK_SRC] = &camcc_icp_clk_src.clkr, 2827 [CAMCC_IFE_0_AXI_CLK] = &camcc_ife_0_axi_clk.clkr, 2828 [CAMCC_IFE_0_CLK] = &camcc_ife_0_clk.clkr, 2829 [CAMCC_IFE_0_CLK_SRC] = &camcc_ife_0_clk_src.clkr, 2830 [CAMCC_IFE_0_CPHY_RX_CLK] = &camcc_ife_0_cphy_rx_clk.clkr, 2831 [CAMCC_IFE_0_CSID_CLK] = &camcc_ife_0_csid_clk.clkr, 2832 [CAMCC_IFE_0_CSID_CLK_SRC] = &camcc_ife_0_csid_clk_src.clkr, 2833 [CAMCC_IFE_0_DSP_CLK] = &camcc_ife_0_dsp_clk.clkr, 2834 [CAMCC_IFE_1_AXI_CLK] = &camcc_ife_1_axi_clk.clkr, 2835 [CAMCC_IFE_1_CLK] = &camcc_ife_1_clk.clkr, 2836 [CAMCC_IFE_1_CLK_SRC] = &camcc_ife_1_clk_src.clkr, 2837 [CAMCC_IFE_1_CPHY_RX_CLK] = &camcc_ife_1_cphy_rx_clk.clkr, 2838 [CAMCC_IFE_1_CSID_CLK] = &camcc_ife_1_csid_clk.clkr, 2839 [CAMCC_IFE_1_CSID_CLK_SRC] = &camcc_ife_1_csid_clk_src.clkr, 2840 [CAMCC_IFE_1_DSP_CLK] = &camcc_ife_1_dsp_clk.clkr, 2841 [CAMCC_IFE_2_AXI_CLK] = &camcc_ife_2_axi_clk.clkr, 2842 [CAMCC_IFE_2_CLK] = &camcc_ife_2_clk.clkr, 2843 [CAMCC_IFE_2_CLK_SRC] = &camcc_ife_2_clk_src.clkr, 2844 [CAMCC_IFE_2_CPHY_RX_CLK] = &camcc_ife_2_cphy_rx_clk.clkr, 2845 [CAMCC_IFE_2_CSID_CLK] = &camcc_ife_2_csid_clk.clkr, 2846 [CAMCC_IFE_2_CSID_CLK_SRC] = &camcc_ife_2_csid_clk_src.clkr, 2847 [CAMCC_IFE_2_DSP_CLK] = &camcc_ife_2_dsp_clk.clkr, 2848 [CAMCC_IFE_3_AXI_CLK] = &camcc_ife_3_axi_clk.clkr, 2849 [CAMCC_IFE_3_CLK] = &camcc_ife_3_clk.clkr, 2850 [CAMCC_IFE_3_CLK_SRC] = &camcc_ife_3_clk_src.clkr, 2851 [CAMCC_IFE_3_CPHY_RX_CLK] = &camcc_ife_3_cphy_rx_clk.clkr, 2852 [CAMCC_IFE_3_CSID_CLK] = &camcc_ife_3_csid_clk.clkr, 2853 [CAMCC_IFE_3_CSID_CLK_SRC] = &camcc_ife_3_csid_clk_src.clkr, 2854 [CAMCC_IFE_3_DSP_CLK] = &camcc_ife_3_dsp_clk.clkr, 2855 [CAMCC_IFE_LITE_0_CLK] = &camcc_ife_lite_0_clk.clkr, 2856 [CAMCC_IFE_LITE_0_CLK_SRC] = &camcc_ife_lite_0_clk_src.clkr, 2857 [CAMCC_IFE_LITE_0_CPHY_RX_CLK] = &camcc_ife_lite_0_cphy_rx_clk.clkr, 2858 [CAMCC_IFE_LITE_0_CSID_CLK] = &camcc_ife_lite_0_csid_clk.clkr, 2859 [CAMCC_IFE_LITE_0_CSID_CLK_SRC] = &camcc_ife_lite_0_csid_clk_src.clkr, 2860 [CAMCC_IFE_LITE_1_CLK] = &camcc_ife_lite_1_clk.clkr, 2861 [CAMCC_IFE_LITE_1_CLK_SRC] = &camcc_ife_lite_1_clk_src.clkr, 2862 [CAMCC_IFE_LITE_1_CPHY_RX_CLK] = &camcc_ife_lite_1_cphy_rx_clk.clkr, 2863 [CAMCC_IFE_LITE_1_CSID_CLK] = &camcc_ife_lite_1_csid_clk.clkr, 2864 [CAMCC_IFE_LITE_1_CSID_CLK_SRC] = &camcc_ife_lite_1_csid_clk_src.clkr, 2865 [CAMCC_IFE_LITE_2_CLK] = &camcc_ife_lite_2_clk.clkr, 2866 [CAMCC_IFE_LITE_2_CLK_SRC] = &camcc_ife_lite_2_clk_src.clkr, 2867 [CAMCC_IFE_LITE_2_CPHY_RX_CLK] = &camcc_ife_lite_2_cphy_rx_clk.clkr, 2868 [CAMCC_IFE_LITE_2_CSID_CLK] = &camcc_ife_lite_2_csid_clk.clkr, 2869 [CAMCC_IFE_LITE_2_CSID_CLK_SRC] = &camcc_ife_lite_2_csid_clk_src.clkr, 2870 [CAMCC_IFE_LITE_3_CLK] = &camcc_ife_lite_3_clk.clkr, 2871 [CAMCC_IFE_LITE_3_CLK_SRC] = &camcc_ife_lite_3_clk_src.clkr, 2872 [CAMCC_IFE_LITE_3_CPHY_RX_CLK] = &camcc_ife_lite_3_cphy_rx_clk.clkr, 2873 [CAMCC_IFE_LITE_3_CSID_CLK] = &camcc_ife_lite_3_csid_clk.clkr, 2874 [CAMCC_IFE_LITE_3_CSID_CLK_SRC] = &camcc_ife_lite_3_csid_clk_src.clkr, 2875 [CAMCC_IPE_0_AHB_CLK] = &camcc_ipe_0_ahb_clk.clkr, 2876 [CAMCC_IPE_0_AREG_CLK] = &camcc_ipe_0_areg_clk.clkr, 2877 [CAMCC_IPE_0_AXI_CLK] = &camcc_ipe_0_axi_clk.clkr, 2878 [CAMCC_IPE_0_CLK] = &camcc_ipe_0_clk.clkr, 2879 [CAMCC_IPE_0_CLK_SRC] = &camcc_ipe_0_clk_src.clkr, 2880 [CAMCC_IPE_1_AHB_CLK] = &camcc_ipe_1_ahb_clk.clkr, 2881 [CAMCC_IPE_1_AREG_CLK] = &camcc_ipe_1_areg_clk.clkr, 2882 [CAMCC_IPE_1_AXI_CLK] = &camcc_ipe_1_axi_clk.clkr, 2883 [CAMCC_IPE_1_CLK] = &camcc_ipe_1_clk.clkr, 2884 [CAMCC_JPEG_CLK] = &camcc_jpeg_clk.clkr, 2885 [CAMCC_JPEG_CLK_SRC] = &camcc_jpeg_clk_src.clkr, 2886 [CAMCC_LRME_CLK] = &camcc_lrme_clk.clkr, 2887 [CAMCC_LRME_CLK_SRC] = &camcc_lrme_clk_src.clkr, 2888 [CAMCC_MCLK0_CLK] = &camcc_mclk0_clk.clkr, 2889 [CAMCC_MCLK0_CLK_SRC] = &camcc_mclk0_clk_src.clkr, 2890 [CAMCC_MCLK1_CLK] = &camcc_mclk1_clk.clkr, 2891 [CAMCC_MCLK1_CLK_SRC] = &camcc_mclk1_clk_src.clkr, 2892 [CAMCC_MCLK2_CLK] = &camcc_mclk2_clk.clkr, 2893 [CAMCC_MCLK2_CLK_SRC] = &camcc_mclk2_clk_src.clkr, 2894 [CAMCC_MCLK3_CLK] = &camcc_mclk3_clk.clkr, 2895 [CAMCC_MCLK3_CLK_SRC] = &camcc_mclk3_clk_src.clkr, 2896 [CAMCC_MCLK4_CLK] = &camcc_mclk4_clk.clkr, 2897 [CAMCC_MCLK4_CLK_SRC] = &camcc_mclk4_clk_src.clkr, 2898 [CAMCC_MCLK5_CLK] = &camcc_mclk5_clk.clkr, 2899 [CAMCC_MCLK5_CLK_SRC] = &camcc_mclk5_clk_src.clkr, 2900 [CAMCC_MCLK6_CLK] = &camcc_mclk6_clk.clkr, 2901 [CAMCC_MCLK6_CLK_SRC] = &camcc_mclk6_clk_src.clkr, 2902 [CAMCC_MCLK7_CLK] = &camcc_mclk7_clk.clkr, 2903 [CAMCC_MCLK7_CLK_SRC] = &camcc_mclk7_clk_src.clkr, 2904 [CAMCC_PLL0] = &camcc_pll0.clkr, 2905 [CAMCC_PLL0_OUT_EVEN] = &camcc_pll0_out_even.clkr, 2906 [CAMCC_PLL0_OUT_ODD] = &camcc_pll0_out_odd.clkr, 2907 [CAMCC_PLL1] = &camcc_pll1.clkr, 2908 [CAMCC_PLL1_OUT_EVEN] = &camcc_pll1_out_even.clkr, 2909 [CAMCC_PLL2] = &camcc_pll2.clkr, 2910 [CAMCC_PLL3] = &camcc_pll3.clkr, 2911 [CAMCC_PLL3_OUT_EVEN] = &camcc_pll3_out_even.clkr, 2912 [CAMCC_PLL4] = &camcc_pll4.clkr, 2913 [CAMCC_PLL4_OUT_EVEN] = &camcc_pll4_out_even.clkr, 2914 [CAMCC_PLL5] = &camcc_pll5.clkr, 2915 [CAMCC_PLL5_OUT_EVEN] = &camcc_pll5_out_even.clkr, 2916 [CAMCC_PLL6] = &camcc_pll6.clkr, 2917 [CAMCC_PLL6_OUT_EVEN] = &camcc_pll6_out_even.clkr, 2918 [CAMCC_PLL7] = &camcc_pll7.clkr, 2919 [CAMCC_PLL7_OUT_EVEN] = &camcc_pll7_out_even.clkr, 2920 [CAMCC_PLL7_OUT_ODD] = &camcc_pll7_out_odd.clkr, 2921 [CAMCC_SLEEP_CLK] = &camcc_sleep_clk.clkr, 2922 [CAMCC_SLEEP_CLK_SRC] = &camcc_sleep_clk_src.clkr, 2923 [CAMCC_SLOW_AHB_CLK_SRC] = &camcc_slow_ahb_clk_src.clkr, 2924 [CAMCC_XO_CLK_SRC] = &camcc_xo_clk_src.clkr, 2925 }; 2926 2927 static struct gdsc *camcc_sc8280xp_gdscs[] = { 2928 [BPS_GDSC] = &bps_gdsc, 2929 [IFE_0_GDSC] = &ife_0_gdsc, 2930 [IFE_1_GDSC] = &ife_1_gdsc, 2931 [IFE_2_GDSC] = &ife_2_gdsc, 2932 [IFE_3_GDSC] = &ife_3_gdsc, 2933 [IPE_0_GDSC] = &ipe_0_gdsc, 2934 [IPE_1_GDSC] = &ipe_1_gdsc, 2935 [TITAN_TOP_GDSC] = &titan_top_gdsc, 2936 }; 2937 2938 static const struct qcom_reset_map camcc_sc8280xp_resets[] = { 2939 [CAMCC_BPS_BCR] = { 0x7000 }, 2940 [CAMCC_CAMNOC_BCR] = { 0xc16c }, 2941 [CAMCC_CCI_BCR] = { 0xc104 }, 2942 [CAMCC_CPAS_BCR] = { 0xc164 }, 2943 [CAMCC_CSI0PHY_BCR] = { 0x6000 }, 2944 [CAMCC_CSI1PHY_BCR] = { 0x6024 }, 2945 [CAMCC_CSI2PHY_BCR] = { 0x6048 }, 2946 [CAMCC_CSI3PHY_BCR] = { 0x6070 }, 2947 [CAMCC_ICP_BCR] = { 0xc0b4 }, 2948 [CAMCC_IFE_0_BCR] = { 0xa000 }, 2949 [CAMCC_IFE_1_BCR] = { 0xb000 }, 2950 [CAMCC_IFE_2_BCR] = { 0xf000 }, 2951 [CAMCC_IFE_3_BCR] = { 0xf06c }, 2952 [CAMCC_IFE_LITE_0_BCR] = { 0xc000 }, 2953 [CAMCC_IFE_LITE_1_BCR] = { 0xc044 }, 2954 [CAMCC_IFE_LITE_2_BCR] = { 0xc23c }, 2955 [CAMCC_IFE_LITE_3_BCR] = { 0xc280 }, 2956 [CAMCC_IPE_0_BCR] = { 0x8000 }, 2957 [CAMCC_IPE_1_BCR] = { 0x9000 }, 2958 [CAMCC_JPEG_BCR] = { 0xc088 }, 2959 [CAMCC_LRME_BCR] = { 0xc140 }, 2960 }; 2961 2962 static const struct regmap_config camcc_sc8280xp_regmap_config = { 2963 .reg_bits = 32, 2964 .reg_stride = 4, 2965 .val_bits = 32, 2966 .max_register = 0x13020, 2967 .fast_io = true, 2968 }; 2969 2970 static const struct qcom_cc_desc camcc_sc8280xp_desc = { 2971 .config = &camcc_sc8280xp_regmap_config, 2972 .clks = camcc_sc8280xp_clocks, 2973 .num_clks = ARRAY_SIZE(camcc_sc8280xp_clocks), 2974 .resets = camcc_sc8280xp_resets, 2975 .num_resets = ARRAY_SIZE(camcc_sc8280xp_resets), 2976 .gdscs = camcc_sc8280xp_gdscs, 2977 .num_gdscs = ARRAY_SIZE(camcc_sc8280xp_gdscs), 2978 }; 2979 2980 static const struct of_device_id camcc_sc8280xp_match_table[] = { 2981 { .compatible = "qcom,sc8280xp-camcc" }, 2982 { } 2983 }; 2984 MODULE_DEVICE_TABLE(of, camcc_sc8280xp_match_table); 2985 2986 static int camcc_sc8280xp_probe(struct platform_device *pdev) 2987 { 2988 struct regmap *regmap; 2989 int ret; 2990 2991 ret = devm_pm_runtime_enable(&pdev->dev); 2992 if (ret) 2993 return ret; 2994 2995 ret = pm_runtime_resume_and_get(&pdev->dev); 2996 if (ret) 2997 return ret; 2998 2999 regmap = qcom_cc_map(pdev, &camcc_sc8280xp_desc); 3000 if (IS_ERR(regmap)) { 3001 ret = PTR_ERR(regmap); 3002 goto err_put_rpm; 3003 } 3004 3005 clk_lucid_pll_configure(&camcc_pll0, regmap, &camcc_pll0_config); 3006 clk_lucid_pll_configure(&camcc_pll1, regmap, &camcc_pll1_config); 3007 clk_zonda_pll_configure(&camcc_pll2, regmap, &camcc_pll2_config); 3008 clk_lucid_pll_configure(&camcc_pll3, regmap, &camcc_pll3_config); 3009 clk_lucid_pll_configure(&camcc_pll4, regmap, &camcc_pll4_config); 3010 clk_lucid_pll_configure(&camcc_pll5, regmap, &camcc_pll5_config); 3011 clk_lucid_pll_configure(&camcc_pll6, regmap, &camcc_pll6_config); 3012 clk_lucid_pll_configure(&camcc_pll7, regmap, &camcc_pll7_config); 3013 3014 /* Keep some clocks always-on */ 3015 qcom_branch_set_clk_en(regmap, 0xc1e4); /* CAMCC_GDSC_CLK */ 3016 3017 ret = qcom_cc_really_probe(&pdev->dev, &camcc_sc8280xp_desc, regmap); 3018 if (ret) 3019 goto err_disable; 3020 3021 pm_runtime_put(&pdev->dev); 3022 3023 return 0; 3024 3025 err_disable: 3026 regmap_update_bits(regmap, 0xc1e4, BIT(0), 0); 3027 err_put_rpm: 3028 pm_runtime_put_sync(&pdev->dev); 3029 3030 return ret; 3031 } 3032 3033 static struct platform_driver camcc_sc8280xp_driver = { 3034 .probe = camcc_sc8280xp_probe, 3035 .driver = { 3036 .name = "camcc-sc8280xp", 3037 .of_match_table = camcc_sc8280xp_match_table, 3038 }, 3039 }; 3040 3041 module_platform_driver(camcc_sc8280xp_driver); 3042 3043 MODULE_DESCRIPTION("QCOM CAMCC SC8280XP Driver"); 3044 MODULE_LICENSE("GPL"); 3045