1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,sc8180x-camcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "common.h" 19 #include "gdsc.h" 20 #include "reset.h" 21 22 enum { 23 DT_IFACE, 24 DT_BI_TCXO, 25 DT_SLEEP_CLK, 26 }; 27 28 enum { 29 P_BI_TCXO, 30 P_CAM_CC_PLL0_OUT_EVEN, 31 P_CAM_CC_PLL0_OUT_MAIN, 32 P_CAM_CC_PLL0_OUT_ODD, 33 P_CAM_CC_PLL1_OUT_EVEN, 34 P_CAM_CC_PLL2_OUT_EARLY, 35 P_CAM_CC_PLL2_OUT_MAIN, 36 P_CAM_CC_PLL3_OUT_EVEN, 37 P_CAM_CC_PLL4_OUT_EVEN, 38 P_CAM_CC_PLL5_OUT_EVEN, 39 P_CAM_CC_PLL6_OUT_EVEN, 40 P_SLEEP_CLK, 41 }; 42 43 static const struct pll_vco regera_vco[] = { 44 { 600000000, 3300000000, 0 }, 45 }; 46 47 static const struct pll_vco trion_vco[] = { 48 { 249600000, 2000000000, 0 }, 49 }; 50 51 static const struct alpha_pll_config cam_cc_pll0_config = { 52 .l = 0x3e, 53 .alpha = 0x8000, 54 .config_ctl_val = 0x20485699, 55 .config_ctl_hi_val = 0x00002267, 56 .config_ctl_hi1_val = 0x00000024, 57 .test_ctl_hi1_val = 0x00000020, 58 .user_ctl_val = 0x00003100, 59 .user_ctl_hi_val = 0x00000805, 60 .user_ctl_hi1_val = 0x000000d0, 61 }; 62 63 static struct clk_alpha_pll cam_cc_pll0 = { 64 .offset = 0x0, 65 .config = &cam_cc_pll0_config, 66 .vco_table = trion_vco, 67 .num_vco = ARRAY_SIZE(trion_vco), 68 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 69 .clkr = { 70 .hw.init = &(const struct clk_init_data) { 71 .name = "cam_cc_pll0", 72 .parent_data = &(const struct clk_parent_data) { 73 .index = DT_BI_TCXO, 74 }, 75 .num_parents = 1, 76 .ops = &clk_alpha_pll_trion_ops, 77 }, 78 }, 79 }; 80 81 static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { 82 { 0x1, 2 }, 83 { } 84 }; 85 86 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { 87 .offset = 0x0, 88 .post_div_shift = 8, 89 .post_div_table = post_div_table_cam_cc_pll0_out_even, 90 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), 91 .width = 4, 92 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 93 .clkr.hw.init = &(const struct clk_init_data) { 94 .name = "cam_cc_pll0_out_even", 95 .parent_hws = (const struct clk_hw*[]) { 96 &cam_cc_pll0.clkr.hw, 97 }, 98 .num_parents = 1, 99 .flags = CLK_SET_RATE_PARENT, 100 .ops = &clk_alpha_pll_postdiv_trion_ops, 101 }, 102 }; 103 104 static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { 105 { 0x3, 3 }, 106 { } 107 }; 108 109 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { 110 .offset = 0x0, 111 .post_div_shift = 12, 112 .post_div_table = post_div_table_cam_cc_pll0_out_odd, 113 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), 114 .width = 4, 115 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 116 .clkr.hw.init = &(const struct clk_init_data) { 117 .name = "cam_cc_pll0_out_odd", 118 .parent_hws = (const struct clk_hw*[]) { 119 &cam_cc_pll0.clkr.hw, 120 }, 121 .num_parents = 1, 122 .flags = CLK_SET_RATE_PARENT, 123 .ops = &clk_alpha_pll_postdiv_trion_ops, 124 }, 125 }; 126 127 static const struct alpha_pll_config cam_cc_pll1_config = { 128 .l = 0x13, 129 .alpha = 0x8800, 130 .config_ctl_val = 0x20485699, 131 .config_ctl_hi_val = 0x00002267, 132 .config_ctl_hi1_val = 0x00000024, 133 .test_ctl_hi1_val = 0x00000020, 134 .user_ctl_val = 0x00000000, 135 .user_ctl_hi_val = 0x00000805, 136 .user_ctl_hi1_val = 0x000000d0, 137 }; 138 139 static struct clk_alpha_pll cam_cc_pll1 = { 140 .offset = 0x1000, 141 .config = &cam_cc_pll1_config, 142 .vco_table = trion_vco, 143 .num_vco = ARRAY_SIZE(trion_vco), 144 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 145 .clkr = { 146 .hw.init = &(const struct clk_init_data) { 147 .name = "cam_cc_pll1", 148 .parent_data = &(const struct clk_parent_data) { 149 .index = DT_BI_TCXO, 150 }, 151 .num_parents = 1, 152 .ops = &clk_alpha_pll_trion_ops, 153 }, 154 }, 155 }; 156 157 static const struct alpha_pll_config cam_cc_pll2_config = { 158 .l = 0x32, 159 .alpha = 0x0, 160 .config_ctl_val = 0x10000807, 161 .config_ctl_hi_val = 0x00000011, 162 .config_ctl_hi1_val = 0x04300142, 163 .test_ctl_val = 0x04000400, 164 .test_ctl_hi_val = 0x00004000, 165 .test_ctl_hi1_val = 0x00000000, 166 .user_ctl_val = 0x00000100, 167 }; 168 169 static struct clk_alpha_pll cam_cc_pll2 = { 170 .offset = 0x2000, 171 .config = &cam_cc_pll2_config, 172 .vco_table = regera_vco, 173 .num_vco = ARRAY_SIZE(regera_vco), 174 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_REGERA], 175 .clkr = { 176 .hw.init = &(const struct clk_init_data) { 177 .name = "cam_cc_pll2", 178 .parent_data = &(const struct clk_parent_data) { 179 .index = DT_BI_TCXO, 180 }, 181 .num_parents = 1, 182 .ops = &clk_alpha_pll_regera_ops, 183 }, 184 }, 185 }; 186 187 static const struct clk_div_table post_div_table_cam_cc_pll2_out_main[] = { 188 { 0x1, 2 }, 189 { } 190 }; 191 192 static struct clk_alpha_pll_postdiv cam_cc_pll2_out_main = { 193 .offset = 0x2000, 194 .post_div_shift = 8, 195 .post_div_table = post_div_table_cam_cc_pll2_out_main, 196 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_main), 197 .width = 2, 198 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_REGERA], 199 .clkr.hw.init = &(const struct clk_init_data) { 200 .name = "cam_cc_pll2_out_main", 201 .parent_hws = (const struct clk_hw*[]) { 202 &cam_cc_pll2.clkr.hw, 203 }, 204 .num_parents = 1, 205 .flags = CLK_SET_RATE_PARENT, 206 .ops = &clk_alpha_pll_postdiv_trion_ops, 207 }, 208 }; 209 210 static const struct alpha_pll_config cam_cc_pll3_config = { 211 .l = 0x14, 212 .alpha = 0xd555, 213 .config_ctl_val = 0x20485699, 214 .config_ctl_hi_val = 0x00002267, 215 .config_ctl_hi1_val = 0x00000024, 216 .test_ctl_hi1_val = 0x00000020, 217 .user_ctl_val = 0x00000000, 218 .user_ctl_hi_val = 0x00000805, 219 .user_ctl_hi1_val = 0x000000d0, 220 }; 221 222 static struct clk_alpha_pll cam_cc_pll3 = { 223 .offset = 0x3000, 224 .config = &cam_cc_pll3_config, 225 .vco_table = trion_vco, 226 .num_vco = ARRAY_SIZE(trion_vco), 227 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 228 .clkr = { 229 .hw.init = &(const struct clk_init_data) { 230 .name = "cam_cc_pll3", 231 .parent_data = &(const struct clk_parent_data) { 232 .index = DT_BI_TCXO, 233 }, 234 .num_parents = 1, 235 .ops = &clk_alpha_pll_trion_ops, 236 }, 237 }, 238 }; 239 240 static const struct alpha_pll_config cam_cc_pll4_config = { 241 .l = 0x14, 242 .alpha = 0xd555, 243 .config_ctl_val = 0x20485699, 244 .config_ctl_hi_val = 0x00002267, 245 .config_ctl_hi1_val = 0x00000024, 246 .test_ctl_hi1_val = 0x00000020, 247 .user_ctl_val = 0x00000000, 248 .user_ctl_hi_val = 0x00000805, 249 .user_ctl_hi1_val = 0x000000d0, 250 }; 251 252 static struct clk_alpha_pll cam_cc_pll4 = { 253 .offset = 0x4000, 254 .config = &cam_cc_pll4_config, 255 .vco_table = trion_vco, 256 .num_vco = ARRAY_SIZE(trion_vco), 257 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 258 .clkr = { 259 .hw.init = &(const struct clk_init_data) { 260 .name = "cam_cc_pll4", 261 .parent_data = &(const struct clk_parent_data) { 262 .index = DT_BI_TCXO, 263 }, 264 .num_parents = 1, 265 .ops = &clk_alpha_pll_trion_ops, 266 }, 267 }, 268 }; 269 270 static const struct alpha_pll_config cam_cc_pll5_config = { 271 .l = 0x14, 272 .alpha = 0xd555, 273 .config_ctl_val = 0x20485699, 274 .config_ctl_hi_val = 0x00002267, 275 .config_ctl_hi1_val = 0x00000024, 276 .test_ctl_hi1_val = 0x00000020, 277 .user_ctl_val = 0x00000000, 278 .user_ctl_hi_val = 0x00000805, 279 .user_ctl_hi1_val = 0x000000d0, 280 }; 281 282 static struct clk_alpha_pll cam_cc_pll5 = { 283 .offset = 0x4078, 284 .config = &cam_cc_pll5_config, 285 .vco_table = trion_vco, 286 .num_vco = ARRAY_SIZE(trion_vco), 287 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 288 .clkr = { 289 .hw.init = &(const struct clk_init_data) { 290 .name = "cam_cc_pll5", 291 .parent_data = &(const struct clk_parent_data) { 292 .index = DT_BI_TCXO, 293 }, 294 .num_parents = 1, 295 .ops = &clk_alpha_pll_trion_ops, 296 }, 297 }, 298 }; 299 300 static const struct alpha_pll_config cam_cc_pll6_config = { 301 .l = 0x14, 302 .alpha = 0xd555, 303 .config_ctl_val = 0x20485699, 304 .config_ctl_hi_val = 0x00002267, 305 .config_ctl_hi1_val = 0x00000024, 306 .test_ctl_hi1_val = 0x00000020, 307 .user_ctl_val = 0x00000000, 308 .user_ctl_hi_val = 0x00000805, 309 .user_ctl_hi1_val = 0x000000d0, 310 }; 311 312 static struct clk_alpha_pll cam_cc_pll6 = { 313 .offset = 0x40f0, 314 .config = &cam_cc_pll6_config, 315 .vco_table = trion_vco, 316 .num_vco = ARRAY_SIZE(trion_vco), 317 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 318 .clkr = { 319 .hw.init = &(const struct clk_init_data) { 320 .name = "cam_cc_pll6", 321 .parent_data = &(const struct clk_parent_data) { 322 .index = DT_BI_TCXO, 323 }, 324 .num_parents = 1, 325 .ops = &clk_alpha_pll_trion_ops, 326 }, 327 }, 328 }; 329 330 static const struct parent_map cam_cc_parent_map_0[] = { 331 { P_BI_TCXO, 0 }, 332 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 333 { P_CAM_CC_PLL0_OUT_EVEN, 2 }, 334 { P_CAM_CC_PLL0_OUT_ODD, 3 }, 335 { P_CAM_CC_PLL2_OUT_MAIN, 5 }, 336 }; 337 338 static const struct clk_parent_data cam_cc_parent_data_0[] = { 339 { .index = DT_BI_TCXO }, 340 { .hw = &cam_cc_pll0.clkr.hw }, 341 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 342 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 343 { .hw = &cam_cc_pll2_out_main.clkr.hw }, 344 }; 345 346 static const struct parent_map cam_cc_parent_map_1[] = { 347 { P_BI_TCXO, 0 }, 348 { P_CAM_CC_PLL2_OUT_EARLY, 5 }, 349 }; 350 351 static const struct clk_parent_data cam_cc_parent_data_1[] = { 352 { .index = DT_BI_TCXO }, 353 { .hw = &cam_cc_pll2.clkr.hw }, 354 }; 355 356 static const struct parent_map cam_cc_parent_map_2[] = { 357 { P_BI_TCXO, 0 }, 358 { P_CAM_CC_PLL3_OUT_EVEN, 6 }, 359 }; 360 361 static const struct clk_parent_data cam_cc_parent_data_2[] = { 362 { .index = DT_BI_TCXO }, 363 { .hw = &cam_cc_pll3.clkr.hw }, 364 }; 365 366 static const struct parent_map cam_cc_parent_map_3[] = { 367 { P_BI_TCXO, 0 }, 368 { P_CAM_CC_PLL4_OUT_EVEN, 6 }, 369 }; 370 371 static const struct clk_parent_data cam_cc_parent_data_3[] = { 372 { .index = DT_BI_TCXO }, 373 { .hw = &cam_cc_pll4.clkr.hw }, 374 }; 375 376 static const struct parent_map cam_cc_parent_map_4[] = { 377 { P_BI_TCXO, 0 }, 378 { P_CAM_CC_PLL5_OUT_EVEN, 6 }, 379 }; 380 381 static const struct clk_parent_data cam_cc_parent_data_4[] = { 382 { .index = DT_BI_TCXO }, 383 { .hw = &cam_cc_pll5.clkr.hw }, 384 }; 385 386 static const struct parent_map cam_cc_parent_map_5[] = { 387 { P_BI_TCXO, 0 }, 388 { P_CAM_CC_PLL6_OUT_EVEN, 6 }, 389 }; 390 391 static const struct clk_parent_data cam_cc_parent_data_5[] = { 392 { .index = DT_BI_TCXO }, 393 { .hw = &cam_cc_pll6.clkr.hw }, 394 }; 395 396 static const struct parent_map cam_cc_parent_map_6[] = { 397 { P_BI_TCXO, 0 }, 398 { P_CAM_CC_PLL1_OUT_EVEN, 4 }, 399 }; 400 401 static const struct clk_parent_data cam_cc_parent_data_6[] = { 402 { .index = DT_BI_TCXO }, 403 { .hw = &cam_cc_pll1.clkr.hw }, 404 }; 405 406 static const struct parent_map cam_cc_parent_map_7[] = { 407 { P_BI_TCXO, 0 }, 408 }; 409 410 static const struct clk_parent_data cam_cc_parent_data_7[] = { 411 { .index = DT_BI_TCXO }, 412 }; 413 414 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { 415 F(19200000, P_BI_TCXO, 1, 0, 0), 416 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 417 F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), 418 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 419 F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0), 420 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 421 { } 422 }; 423 424 static struct clk_rcg2 cam_cc_bps_clk_src = { 425 .cmd_rcgr = 0x7010, 426 .mnd_width = 0, 427 .hid_width = 5, 428 .parent_map = cam_cc_parent_map_0, 429 .freq_tbl = ftbl_cam_cc_bps_clk_src, 430 .clkr.hw.init = &(const struct clk_init_data) { 431 .name = "cam_cc_bps_clk_src", 432 .parent_data = cam_cc_parent_data_0, 433 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 434 .flags = CLK_SET_RATE_PARENT, 435 .ops = &clk_rcg2_shared_ops, 436 }, 437 }; 438 439 static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = { 440 F(19200000, P_BI_TCXO, 1, 0, 0), 441 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), 442 F(266666667, P_CAM_CC_PLL0_OUT_ODD, 1.5, 0, 0), 443 F(320000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0), 444 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 445 F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0), 446 { } 447 }; 448 449 static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = { 450 .cmd_rcgr = 0xc170, 451 .mnd_width = 0, 452 .hid_width = 5, 453 .parent_map = cam_cc_parent_map_0, 454 .freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src, 455 .clkr.hw.init = &(const struct clk_init_data) { 456 .name = "cam_cc_camnoc_axi_clk_src", 457 .parent_data = cam_cc_parent_data_0, 458 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 459 .flags = CLK_SET_RATE_PARENT, 460 .ops = &clk_rcg2_shared_ops, 461 }, 462 }; 463 464 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { 465 F(19200000, P_BI_TCXO, 1, 0, 0), 466 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 467 { } 468 }; 469 470 static struct clk_rcg2 cam_cc_cci_0_clk_src = { 471 .cmd_rcgr = 0xc108, 472 .mnd_width = 8, 473 .hid_width = 5, 474 .parent_map = cam_cc_parent_map_0, 475 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 476 .clkr.hw.init = &(const struct clk_init_data) { 477 .name = "cam_cc_cci_0_clk_src", 478 .parent_data = cam_cc_parent_data_0, 479 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 480 .flags = CLK_SET_RATE_PARENT, 481 .ops = &clk_rcg2_shared_ops, 482 }, 483 }; 484 485 static struct clk_rcg2 cam_cc_cci_1_clk_src = { 486 .cmd_rcgr = 0xc124, 487 .mnd_width = 8, 488 .hid_width = 5, 489 .parent_map = cam_cc_parent_map_0, 490 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 491 .clkr.hw.init = &(const struct clk_init_data) { 492 .name = "cam_cc_cci_1_clk_src", 493 .parent_data = cam_cc_parent_data_0, 494 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 495 .flags = CLK_SET_RATE_PARENT, 496 .ops = &clk_rcg2_shared_ops, 497 }, 498 }; 499 500 static struct clk_rcg2 cam_cc_cci_2_clk_src = { 501 .cmd_rcgr = 0xc204, 502 .mnd_width = 8, 503 .hid_width = 5, 504 .parent_map = cam_cc_parent_map_0, 505 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 506 .clkr.hw.init = &(const struct clk_init_data) { 507 .name = "cam_cc_cci_2_clk_src", 508 .parent_data = cam_cc_parent_data_0, 509 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 510 .flags = CLK_SET_RATE_PARENT, 511 .ops = &clk_rcg2_shared_ops, 512 }, 513 }; 514 515 static struct clk_rcg2 cam_cc_cci_3_clk_src = { 516 .cmd_rcgr = 0xc220, 517 .mnd_width = 8, 518 .hid_width = 5, 519 .parent_map = cam_cc_parent_map_0, 520 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 521 .clkr.hw.init = &(const struct clk_init_data) { 522 .name = "cam_cc_cci_3_clk_src", 523 .parent_data = cam_cc_parent_data_0, 524 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 525 .flags = CLK_SET_RATE_PARENT, 526 .ops = &clk_rcg2_shared_ops, 527 }, 528 }; 529 530 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 531 F(19200000, P_BI_TCXO, 1, 0, 0), 532 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 533 { } 534 }; 535 536 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 537 .cmd_rcgr = 0xa064, 538 .mnd_width = 0, 539 .hid_width = 5, 540 .parent_map = cam_cc_parent_map_0, 541 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 542 .clkr.hw.init = &(const struct clk_init_data) { 543 .name = "cam_cc_cphy_rx_clk_src", 544 .parent_data = cam_cc_parent_data_0, 545 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 546 .flags = CLK_SET_RATE_PARENT, 547 .ops = &clk_rcg2_shared_ops, 548 }, 549 }; 550 551 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 552 F(19200000, P_BI_TCXO, 1, 0, 0), 553 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 554 { } 555 }; 556 557 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 558 .cmd_rcgr = 0x6004, 559 .mnd_width = 0, 560 .hid_width = 5, 561 .parent_map = cam_cc_parent_map_0, 562 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 563 .clkr.hw.init = &(const struct clk_init_data) { 564 .name = "cam_cc_csi0phytimer_clk_src", 565 .parent_data = cam_cc_parent_data_0, 566 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 567 .flags = CLK_SET_RATE_PARENT, 568 .ops = &clk_rcg2_shared_ops, 569 }, 570 }; 571 572 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 573 .cmd_rcgr = 0x6028, 574 .mnd_width = 0, 575 .hid_width = 5, 576 .parent_map = cam_cc_parent_map_0, 577 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 578 .clkr.hw.init = &(const struct clk_init_data) { 579 .name = "cam_cc_csi1phytimer_clk_src", 580 .parent_data = cam_cc_parent_data_0, 581 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 582 .flags = CLK_SET_RATE_PARENT, 583 .ops = &clk_rcg2_shared_ops, 584 }, 585 }; 586 587 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 588 .cmd_rcgr = 0x604c, 589 .mnd_width = 0, 590 .hid_width = 5, 591 .parent_map = cam_cc_parent_map_0, 592 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 593 .clkr.hw.init = &(const struct clk_init_data) { 594 .name = "cam_cc_csi2phytimer_clk_src", 595 .parent_data = cam_cc_parent_data_0, 596 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 597 .flags = CLK_SET_RATE_PARENT, 598 .ops = &clk_rcg2_shared_ops, 599 }, 600 }; 601 602 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 603 .cmd_rcgr = 0x6070, 604 .mnd_width = 0, 605 .hid_width = 5, 606 .parent_map = cam_cc_parent_map_0, 607 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 608 .clkr.hw.init = &(const struct clk_init_data) { 609 .name = "cam_cc_csi3phytimer_clk_src", 610 .parent_data = cam_cc_parent_data_0, 611 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 612 .flags = CLK_SET_RATE_PARENT, 613 .ops = &clk_rcg2_shared_ops, 614 }, 615 }; 616 617 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 618 F(19200000, P_BI_TCXO, 1, 0, 0), 619 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0), 620 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 621 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 622 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), 623 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 624 { } 625 }; 626 627 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 628 .cmd_rcgr = 0x703c, 629 .mnd_width = 0, 630 .hid_width = 5, 631 .parent_map = cam_cc_parent_map_0, 632 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 633 .clkr.hw.init = &(const struct clk_init_data) { 634 .name = "cam_cc_fast_ahb_clk_src", 635 .parent_data = cam_cc_parent_data_0, 636 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 637 .flags = CLK_SET_RATE_PARENT, 638 .ops = &clk_rcg2_shared_ops, 639 }, 640 }; 641 642 static const struct freq_tbl ftbl_cam_cc_fd_core_clk_src[] = { 643 F(19200000, P_BI_TCXO, 1, 0, 0), 644 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 645 F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0), 646 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 647 { } 648 }; 649 650 static struct clk_rcg2 cam_cc_fd_core_clk_src = { 651 .cmd_rcgr = 0xc0e0, 652 .mnd_width = 0, 653 .hid_width = 5, 654 .parent_map = cam_cc_parent_map_0, 655 .freq_tbl = ftbl_cam_cc_fd_core_clk_src, 656 .clkr.hw.init = &(const struct clk_init_data) { 657 .name = "cam_cc_fd_core_clk_src", 658 .parent_data = cam_cc_parent_data_0, 659 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 660 .flags = CLK_SET_RATE_PARENT, 661 .ops = &clk_rcg2_shared_ops, 662 }, 663 }; 664 665 static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 666 F(19200000, P_BI_TCXO, 1, 0, 0), 667 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 668 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 669 { } 670 }; 671 672 static struct clk_rcg2 cam_cc_icp_clk_src = { 673 .cmd_rcgr = 0xc0b8, 674 .mnd_width = 0, 675 .hid_width = 5, 676 .parent_map = cam_cc_parent_map_0, 677 .freq_tbl = ftbl_cam_cc_icp_clk_src, 678 .clkr.hw.init = &(const struct clk_init_data) { 679 .name = "cam_cc_icp_clk_src", 680 .parent_data = cam_cc_parent_data_0, 681 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 682 .flags = CLK_SET_RATE_PARENT, 683 .ops = &clk_rcg2_shared_ops, 684 }, 685 }; 686 687 static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { 688 F(19200000, P_BI_TCXO, 1, 0, 0), 689 F(400000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 690 F(558000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 691 F(637000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 692 F(760000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 693 { } 694 }; 695 696 static struct clk_rcg2 cam_cc_ife_0_clk_src = { 697 .cmd_rcgr = 0xa010, 698 .mnd_width = 0, 699 .hid_width = 5, 700 .parent_map = cam_cc_parent_map_2, 701 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 702 .clkr.hw.init = &(const struct clk_init_data) { 703 .name = "cam_cc_ife_0_clk_src", 704 .parent_data = cam_cc_parent_data_2, 705 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 706 .flags = CLK_SET_RATE_PARENT, 707 .ops = &clk_rcg2_shared_ops, 708 }, 709 }; 710 711 static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = { 712 F(19200000, P_BI_TCXO, 1, 0, 0), 713 F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0), 714 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 715 F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0), 716 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 717 { } 718 }; 719 720 static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { 721 .cmd_rcgr = 0xa03c, 722 .mnd_width = 0, 723 .hid_width = 5, 724 .parent_map = cam_cc_parent_map_0, 725 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 726 .clkr.hw.init = &(const struct clk_init_data) { 727 .name = "cam_cc_ife_0_csid_clk_src", 728 .parent_data = cam_cc_parent_data_0, 729 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 730 .flags = CLK_SET_RATE_PARENT, 731 .ops = &clk_rcg2_shared_ops, 732 }, 733 }; 734 735 static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = { 736 F(19200000, P_BI_TCXO, 1, 0, 0), 737 F(400000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 738 F(558000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 739 F(637000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 740 F(760000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 741 { } 742 }; 743 744 static struct clk_rcg2 cam_cc_ife_1_clk_src = { 745 .cmd_rcgr = 0xb010, 746 .mnd_width = 0, 747 .hid_width = 5, 748 .parent_map = cam_cc_parent_map_3, 749 .freq_tbl = ftbl_cam_cc_ife_1_clk_src, 750 .clkr.hw.init = &(const struct clk_init_data) { 751 .name = "cam_cc_ife_1_clk_src", 752 .parent_data = cam_cc_parent_data_3, 753 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 754 .flags = CLK_SET_RATE_PARENT, 755 .ops = &clk_rcg2_shared_ops, 756 }, 757 }; 758 759 static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { 760 .cmd_rcgr = 0xb034, 761 .mnd_width = 0, 762 .hid_width = 5, 763 .parent_map = cam_cc_parent_map_0, 764 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 765 .clkr.hw.init = &(const struct clk_init_data) { 766 .name = "cam_cc_ife_1_csid_clk_src", 767 .parent_data = cam_cc_parent_data_0, 768 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 769 .flags = CLK_SET_RATE_PARENT, 770 .ops = &clk_rcg2_shared_ops, 771 }, 772 }; 773 774 static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = { 775 F(19200000, P_BI_TCXO, 1, 0, 0), 776 F(400000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 777 F(558000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 778 F(637000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 779 F(760000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 780 { } 781 }; 782 783 static struct clk_rcg2 cam_cc_ife_2_clk_src = { 784 .cmd_rcgr = 0xf010, 785 .mnd_width = 0, 786 .hid_width = 5, 787 .parent_map = cam_cc_parent_map_4, 788 .freq_tbl = ftbl_cam_cc_ife_2_clk_src, 789 .clkr.hw.init = &(const struct clk_init_data) { 790 .name = "cam_cc_ife_2_clk_src", 791 .parent_data = cam_cc_parent_data_4, 792 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 793 .flags = CLK_SET_RATE_PARENT, 794 .ops = &clk_rcg2_shared_ops, 795 }, 796 }; 797 798 static struct clk_rcg2 cam_cc_ife_2_csid_clk_src = { 799 .cmd_rcgr = 0xf03c, 800 .mnd_width = 0, 801 .hid_width = 5, 802 .parent_map = cam_cc_parent_map_0, 803 .freq_tbl = ftbl_cam_cc_fd_core_clk_src, 804 .clkr.hw.init = &(const struct clk_init_data) { 805 .name = "cam_cc_ife_2_csid_clk_src", 806 .parent_data = cam_cc_parent_data_0, 807 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 808 .flags = CLK_SET_RATE_PARENT, 809 .ops = &clk_rcg2_shared_ops, 810 }, 811 }; 812 813 static const struct freq_tbl ftbl_cam_cc_ife_3_clk_src[] = { 814 F(19200000, P_BI_TCXO, 1, 0, 0), 815 F(400000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 816 F(558000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 817 F(637000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 818 F(760000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 819 { } 820 }; 821 822 static struct clk_rcg2 cam_cc_ife_3_clk_src = { 823 .cmd_rcgr = 0xf07c, 824 .mnd_width = 0, 825 .hid_width = 5, 826 .parent_map = cam_cc_parent_map_5, 827 .freq_tbl = ftbl_cam_cc_ife_3_clk_src, 828 .clkr.hw.init = &(const struct clk_init_data) { 829 .name = "cam_cc_ife_3_clk_src", 830 .parent_data = cam_cc_parent_data_5, 831 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 832 .flags = CLK_SET_RATE_PARENT, 833 .ops = &clk_rcg2_shared_ops, 834 }, 835 }; 836 837 static struct clk_rcg2 cam_cc_ife_3_csid_clk_src = { 838 .cmd_rcgr = 0xf0a8, 839 .mnd_width = 0, 840 .hid_width = 5, 841 .parent_map = cam_cc_parent_map_0, 842 .freq_tbl = ftbl_cam_cc_fd_core_clk_src, 843 .clkr.hw.init = &(const struct clk_init_data) { 844 .name = "cam_cc_ife_3_csid_clk_src", 845 .parent_data = cam_cc_parent_data_0, 846 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 847 .flags = CLK_SET_RATE_PARENT, 848 .ops = &clk_rcg2_shared_ops, 849 }, 850 }; 851 852 static const struct freq_tbl ftbl_cam_cc_ife_lite_0_clk_src[] = { 853 F(19200000, P_BI_TCXO, 1, 0, 0), 854 F(320000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0), 855 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 856 F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0), 857 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 858 { } 859 }; 860 861 static struct clk_rcg2 cam_cc_ife_lite_0_clk_src = { 862 .cmd_rcgr = 0xc004, 863 .mnd_width = 0, 864 .hid_width = 5, 865 .parent_map = cam_cc_parent_map_0, 866 .freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src, 867 .clkr.hw.init = &(const struct clk_init_data) { 868 .name = "cam_cc_ife_lite_0_clk_src", 869 .parent_data = cam_cc_parent_data_0, 870 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 871 .flags = CLK_SET_RATE_PARENT, 872 .ops = &clk_rcg2_shared_ops, 873 }, 874 }; 875 876 static struct clk_rcg2 cam_cc_ife_lite_0_csid_clk_src = { 877 .cmd_rcgr = 0xc020, 878 .mnd_width = 0, 879 .hid_width = 5, 880 .parent_map = cam_cc_parent_map_0, 881 .freq_tbl = ftbl_cam_cc_fd_core_clk_src, 882 .clkr.hw.init = &(const struct clk_init_data) { 883 .name = "cam_cc_ife_lite_0_csid_clk_src", 884 .parent_data = cam_cc_parent_data_0, 885 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 886 .flags = CLK_SET_RATE_PARENT, 887 .ops = &clk_rcg2_shared_ops, 888 }, 889 }; 890 891 static struct clk_rcg2 cam_cc_ife_lite_1_clk_src = { 892 .cmd_rcgr = 0xc048, 893 .mnd_width = 0, 894 .hid_width = 5, 895 .parent_map = cam_cc_parent_map_0, 896 .freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src, 897 .clkr.hw.init = &(const struct clk_init_data) { 898 .name = "cam_cc_ife_lite_1_clk_src", 899 .parent_data = cam_cc_parent_data_0, 900 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 901 .flags = CLK_SET_RATE_PARENT, 902 .ops = &clk_rcg2_shared_ops, 903 }, 904 }; 905 906 static struct clk_rcg2 cam_cc_ife_lite_1_csid_clk_src = { 907 .cmd_rcgr = 0xc064, 908 .mnd_width = 0, 909 .hid_width = 5, 910 .parent_map = cam_cc_parent_map_0, 911 .freq_tbl = ftbl_cam_cc_fd_core_clk_src, 912 .clkr.hw.init = &(const struct clk_init_data) { 913 .name = "cam_cc_ife_lite_1_csid_clk_src", 914 .parent_data = cam_cc_parent_data_0, 915 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 916 .flags = CLK_SET_RATE_PARENT, 917 .ops = &clk_rcg2_shared_ops, 918 }, 919 }; 920 921 static struct clk_rcg2 cam_cc_ife_lite_2_clk_src = { 922 .cmd_rcgr = 0xc240, 923 .mnd_width = 0, 924 .hid_width = 5, 925 .parent_map = cam_cc_parent_map_0, 926 .freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src, 927 .clkr.hw.init = &(const struct clk_init_data) { 928 .name = "cam_cc_ife_lite_2_clk_src", 929 .parent_data = cam_cc_parent_data_0, 930 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 931 .flags = CLK_SET_RATE_PARENT, 932 .ops = &clk_rcg2_shared_ops, 933 }, 934 }; 935 936 static struct clk_rcg2 cam_cc_ife_lite_2_csid_clk_src = { 937 .cmd_rcgr = 0xc25c, 938 .mnd_width = 0, 939 .hid_width = 5, 940 .parent_map = cam_cc_parent_map_0, 941 .freq_tbl = ftbl_cam_cc_fd_core_clk_src, 942 .clkr.hw.init = &(const struct clk_init_data) { 943 .name = "cam_cc_ife_lite_2_csid_clk_src", 944 .parent_data = cam_cc_parent_data_0, 945 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 946 .flags = CLK_SET_RATE_PARENT, 947 .ops = &clk_rcg2_shared_ops, 948 }, 949 }; 950 951 static struct clk_rcg2 cam_cc_ife_lite_3_clk_src = { 952 .cmd_rcgr = 0xc284, 953 .mnd_width = 0, 954 .hid_width = 5, 955 .parent_map = cam_cc_parent_map_0, 956 .freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src, 957 .clkr.hw.init = &(const struct clk_init_data) { 958 .name = "cam_cc_ife_lite_3_clk_src", 959 .parent_data = cam_cc_parent_data_0, 960 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 961 .flags = CLK_SET_RATE_PARENT, 962 .ops = &clk_rcg2_shared_ops, 963 }, 964 }; 965 966 static struct clk_rcg2 cam_cc_ife_lite_3_csid_clk_src = { 967 .cmd_rcgr = 0xc2a0, 968 .mnd_width = 0, 969 .hid_width = 5, 970 .parent_map = cam_cc_parent_map_0, 971 .freq_tbl = ftbl_cam_cc_fd_core_clk_src, 972 .clkr.hw.init = &(const struct clk_init_data) { 973 .name = "cam_cc_ife_lite_3_csid_clk_src", 974 .parent_data = cam_cc_parent_data_0, 975 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 976 .flags = CLK_SET_RATE_PARENT, 977 .ops = &clk_rcg2_shared_ops, 978 }, 979 }; 980 981 static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = { 982 F(19200000, P_BI_TCXO, 1, 0, 0), 983 F(375000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 984 F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 985 F(520000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 986 F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 987 { } 988 }; 989 990 static struct clk_rcg2 cam_cc_ipe_0_clk_src = { 991 .cmd_rcgr = 0x8010, 992 .mnd_width = 0, 993 .hid_width = 5, 994 .parent_map = cam_cc_parent_map_6, 995 .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, 996 .clkr.hw.init = &(const struct clk_init_data) { 997 .name = "cam_cc_ipe_0_clk_src", 998 .parent_data = cam_cc_parent_data_6, 999 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), 1000 .flags = CLK_SET_RATE_PARENT, 1001 .ops = &clk_rcg2_shared_ops, 1002 }, 1003 }; 1004 1005 static struct clk_rcg2 cam_cc_jpeg_clk_src = { 1006 .cmd_rcgr = 0xc08c, 1007 .mnd_width = 0, 1008 .hid_width = 5, 1009 .parent_map = cam_cc_parent_map_0, 1010 .freq_tbl = ftbl_cam_cc_bps_clk_src, 1011 .clkr.hw.init = &(const struct clk_init_data) { 1012 .name = "cam_cc_jpeg_clk_src", 1013 .parent_data = cam_cc_parent_data_0, 1014 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 1015 .flags = CLK_SET_RATE_PARENT, 1016 .ops = &clk_rcg2_shared_ops, 1017 }, 1018 }; 1019 1020 static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = { 1021 F(19200000, P_BI_TCXO, 1, 0, 0), 1022 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 1023 F(240000000, P_CAM_CC_PLL2_OUT_MAIN, 2, 0, 0), 1024 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 1025 F(320000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0), 1026 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 1027 { } 1028 }; 1029 1030 static struct clk_rcg2 cam_cc_lrme_clk_src = { 1031 .cmd_rcgr = 0xc144, 1032 .mnd_width = 0, 1033 .hid_width = 5, 1034 .parent_map = cam_cc_parent_map_0, 1035 .freq_tbl = ftbl_cam_cc_lrme_clk_src, 1036 .clkr.hw.init = &(const struct clk_init_data) { 1037 .name = "cam_cc_lrme_clk_src", 1038 .parent_data = cam_cc_parent_data_0, 1039 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 1040 .flags = CLK_SET_RATE_PARENT, 1041 .ops = &clk_rcg2_shared_ops, 1042 }, 1043 }; 1044 1045 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 1046 F(19200000, P_BI_TCXO, 1, 0, 0), 1047 F(24000000, P_CAM_CC_PLL2_OUT_EARLY, 10, 1, 4), 1048 F(68571429, P_CAM_CC_PLL2_OUT_EARLY, 14, 0, 0), 1049 { } 1050 }; 1051 1052 static struct clk_rcg2 cam_cc_mclk0_clk_src = { 1053 .cmd_rcgr = 0x5004, 1054 .mnd_width = 8, 1055 .hid_width = 5, 1056 .parent_map = cam_cc_parent_map_1, 1057 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1058 .clkr.hw.init = &(const struct clk_init_data) { 1059 .name = "cam_cc_mclk0_clk_src", 1060 .parent_data = cam_cc_parent_data_1, 1061 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1062 .flags = CLK_SET_RATE_PARENT, 1063 .ops = &clk_rcg2_shared_ops, 1064 }, 1065 }; 1066 1067 static struct clk_rcg2 cam_cc_mclk1_clk_src = { 1068 .cmd_rcgr = 0x5024, 1069 .mnd_width = 8, 1070 .hid_width = 5, 1071 .parent_map = cam_cc_parent_map_1, 1072 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1073 .clkr.hw.init = &(const struct clk_init_data) { 1074 .name = "cam_cc_mclk1_clk_src", 1075 .parent_data = cam_cc_parent_data_1, 1076 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1077 .flags = CLK_SET_RATE_PARENT, 1078 .ops = &clk_rcg2_shared_ops, 1079 }, 1080 }; 1081 1082 static struct clk_rcg2 cam_cc_mclk2_clk_src = { 1083 .cmd_rcgr = 0x5044, 1084 .mnd_width = 8, 1085 .hid_width = 5, 1086 .parent_map = cam_cc_parent_map_1, 1087 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1088 .clkr.hw.init = &(const struct clk_init_data) { 1089 .name = "cam_cc_mclk2_clk_src", 1090 .parent_data = cam_cc_parent_data_1, 1091 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1092 .flags = CLK_SET_RATE_PARENT, 1093 .ops = &clk_rcg2_shared_ops, 1094 }, 1095 }; 1096 1097 static struct clk_rcg2 cam_cc_mclk3_clk_src = { 1098 .cmd_rcgr = 0x5064, 1099 .mnd_width = 8, 1100 .hid_width = 5, 1101 .parent_map = cam_cc_parent_map_1, 1102 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1103 .clkr.hw.init = &(const struct clk_init_data) { 1104 .name = "cam_cc_mclk3_clk_src", 1105 .parent_data = cam_cc_parent_data_1, 1106 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1107 .flags = CLK_SET_RATE_PARENT, 1108 .ops = &clk_rcg2_shared_ops, 1109 }, 1110 }; 1111 1112 static struct clk_rcg2 cam_cc_mclk4_clk_src = { 1113 .cmd_rcgr = 0x5084, 1114 .mnd_width = 8, 1115 .hid_width = 5, 1116 .parent_map = cam_cc_parent_map_1, 1117 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1118 .clkr.hw.init = &(const struct clk_init_data) { 1119 .name = "cam_cc_mclk4_clk_src", 1120 .parent_data = cam_cc_parent_data_1, 1121 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1122 .flags = CLK_SET_RATE_PARENT, 1123 .ops = &clk_rcg2_shared_ops, 1124 }, 1125 }; 1126 1127 static struct clk_rcg2 cam_cc_mclk5_clk_src = { 1128 .cmd_rcgr = 0x50a4, 1129 .mnd_width = 8, 1130 .hid_width = 5, 1131 .parent_map = cam_cc_parent_map_1, 1132 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1133 .clkr.hw.init = &(const struct clk_init_data) { 1134 .name = "cam_cc_mclk5_clk_src", 1135 .parent_data = cam_cc_parent_data_1, 1136 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1137 .flags = CLK_SET_RATE_PARENT, 1138 .ops = &clk_rcg2_shared_ops, 1139 }, 1140 }; 1141 1142 static struct clk_rcg2 cam_cc_mclk6_clk_src = { 1143 .cmd_rcgr = 0x50c4, 1144 .mnd_width = 8, 1145 .hid_width = 5, 1146 .parent_map = cam_cc_parent_map_1, 1147 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1148 .clkr.hw.init = &(const struct clk_init_data) { 1149 .name = "cam_cc_mclk6_clk_src", 1150 .parent_data = cam_cc_parent_data_1, 1151 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1152 .flags = CLK_SET_RATE_PARENT, 1153 .ops = &clk_rcg2_shared_ops, 1154 }, 1155 }; 1156 1157 static struct clk_rcg2 cam_cc_mclk7_clk_src = { 1158 .cmd_rcgr = 0x50e4, 1159 .mnd_width = 8, 1160 .hid_width = 5, 1161 .parent_map = cam_cc_parent_map_1, 1162 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 1163 .clkr.hw.init = &(const struct clk_init_data) { 1164 .name = "cam_cc_mclk7_clk_src", 1165 .parent_data = cam_cc_parent_data_1, 1166 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 1167 .flags = CLK_SET_RATE_PARENT, 1168 .ops = &clk_rcg2_shared_ops, 1169 }, 1170 }; 1171 1172 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 1173 F(19200000, P_BI_TCXO, 1, 0, 0), 1174 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 1175 { } 1176 }; 1177 1178 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 1179 .cmd_rcgr = 0x7058, 1180 .mnd_width = 8, 1181 .hid_width = 5, 1182 .parent_map = cam_cc_parent_map_0, 1183 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 1184 .clkr.hw.init = &(const struct clk_init_data) { 1185 .name = "cam_cc_slow_ahb_clk_src", 1186 .parent_data = cam_cc_parent_data_0, 1187 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 1188 .flags = CLK_SET_RATE_PARENT, 1189 .ops = &clk_rcg2_shared_ops, 1190 }, 1191 }; 1192 1193 static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { 1194 F(19200000, P_BI_TCXO, 1, 0, 0), 1195 { } 1196 }; 1197 1198 static struct clk_rcg2 cam_cc_xo_clk_src = { 1199 .cmd_rcgr = 0xc1cc, 1200 .mnd_width = 0, 1201 .hid_width = 5, 1202 .parent_map = cam_cc_parent_map_7, 1203 .freq_tbl = ftbl_cam_cc_xo_clk_src, 1204 .clkr.hw.init = &(const struct clk_init_data) { 1205 .name = "cam_cc_xo_clk_src", 1206 .parent_data = cam_cc_parent_data_7, 1207 .num_parents = ARRAY_SIZE(cam_cc_parent_data_7), 1208 .flags = CLK_SET_RATE_PARENT, 1209 .ops = &clk_rcg2_shared_ops, 1210 }, 1211 }; 1212 1213 static struct clk_branch cam_cc_bps_ahb_clk = { 1214 .halt_reg = 0x7070, 1215 .halt_check = BRANCH_HALT, 1216 .clkr = { 1217 .enable_reg = 0x7070, 1218 .enable_mask = BIT(0), 1219 .hw.init = &(const struct clk_init_data) { 1220 .name = "cam_cc_bps_ahb_clk", 1221 .parent_hws = (const struct clk_hw*[]) { 1222 &cam_cc_slow_ahb_clk_src.clkr.hw, 1223 }, 1224 .num_parents = 1, 1225 .flags = CLK_SET_RATE_PARENT, 1226 .ops = &clk_branch2_ops, 1227 }, 1228 }, 1229 }; 1230 1231 static struct clk_branch cam_cc_bps_areg_clk = { 1232 .halt_reg = 0x7054, 1233 .halt_check = BRANCH_HALT, 1234 .clkr = { 1235 .enable_reg = 0x7054, 1236 .enable_mask = BIT(0), 1237 .hw.init = &(const struct clk_init_data) { 1238 .name = "cam_cc_bps_areg_clk", 1239 .parent_hws = (const struct clk_hw*[]) { 1240 &cam_cc_fast_ahb_clk_src.clkr.hw, 1241 }, 1242 .num_parents = 1, 1243 .flags = CLK_SET_RATE_PARENT, 1244 .ops = &clk_branch2_ops, 1245 }, 1246 }, 1247 }; 1248 1249 static struct clk_branch cam_cc_bps_axi_clk = { 1250 .halt_reg = 0x7038, 1251 .halt_check = BRANCH_HALT, 1252 .clkr = { 1253 .enable_reg = 0x7038, 1254 .enable_mask = BIT(0), 1255 .hw.init = &(const struct clk_init_data) { 1256 .name = "cam_cc_bps_axi_clk", 1257 .parent_hws = (const struct clk_hw*[]) { 1258 &cam_cc_camnoc_axi_clk_src.clkr.hw, 1259 }, 1260 .num_parents = 1, 1261 .flags = CLK_SET_RATE_PARENT, 1262 .ops = &clk_branch2_ops, 1263 }, 1264 }, 1265 }; 1266 1267 static struct clk_branch cam_cc_bps_clk = { 1268 .halt_reg = 0x7028, 1269 .halt_check = BRANCH_HALT, 1270 .clkr = { 1271 .enable_reg = 0x7028, 1272 .enable_mask = BIT(0), 1273 .hw.init = &(const struct clk_init_data) { 1274 .name = "cam_cc_bps_clk", 1275 .parent_hws = (const struct clk_hw*[]) { 1276 &cam_cc_bps_clk_src.clkr.hw, 1277 }, 1278 .num_parents = 1, 1279 .flags = CLK_SET_RATE_PARENT, 1280 .ops = &clk_branch2_ops, 1281 }, 1282 }, 1283 }; 1284 1285 static struct clk_branch cam_cc_camnoc_axi_clk = { 1286 .halt_reg = 0xc18c, 1287 .halt_check = BRANCH_HALT, 1288 .clkr = { 1289 .enable_reg = 0xc18c, 1290 .enable_mask = BIT(0), 1291 .hw.init = &(const struct clk_init_data) { 1292 .name = "cam_cc_camnoc_axi_clk", 1293 .parent_hws = (const struct clk_hw*[]) { 1294 &cam_cc_camnoc_axi_clk_src.clkr.hw, 1295 }, 1296 .num_parents = 1, 1297 .flags = CLK_SET_RATE_PARENT, 1298 .ops = &clk_branch2_ops, 1299 }, 1300 }, 1301 }; 1302 1303 static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { 1304 .halt_reg = 0xc194, 1305 .halt_check = BRANCH_HALT, 1306 .clkr = { 1307 .enable_reg = 0xc194, 1308 .enable_mask = BIT(0), 1309 .hw.init = &(const struct clk_init_data) { 1310 .name = "cam_cc_camnoc_dcd_xo_clk", 1311 .parent_hws = (const struct clk_hw*[]) { 1312 &cam_cc_xo_clk_src.clkr.hw, 1313 }, 1314 .num_parents = 1, 1315 .flags = CLK_SET_RATE_PARENT, 1316 .ops = &clk_branch2_ops, 1317 }, 1318 }, 1319 }; 1320 1321 static struct clk_branch cam_cc_cci_0_clk = { 1322 .halt_reg = 0xc120, 1323 .halt_check = BRANCH_HALT, 1324 .clkr = { 1325 .enable_reg = 0xc120, 1326 .enable_mask = BIT(0), 1327 .hw.init = &(const struct clk_init_data) { 1328 .name = "cam_cc_cci_0_clk", 1329 .parent_hws = (const struct clk_hw*[]) { 1330 &cam_cc_cci_0_clk_src.clkr.hw, 1331 }, 1332 .num_parents = 1, 1333 .flags = CLK_SET_RATE_PARENT, 1334 .ops = &clk_branch2_ops, 1335 }, 1336 }, 1337 }; 1338 1339 static struct clk_branch cam_cc_cci_1_clk = { 1340 .halt_reg = 0xc13c, 1341 .halt_check = BRANCH_HALT, 1342 .clkr = { 1343 .enable_reg = 0xc13c, 1344 .enable_mask = BIT(0), 1345 .hw.init = &(const struct clk_init_data) { 1346 .name = "cam_cc_cci_1_clk", 1347 .parent_hws = (const struct clk_hw*[]) { 1348 &cam_cc_cci_1_clk_src.clkr.hw, 1349 }, 1350 .num_parents = 1, 1351 .flags = CLK_SET_RATE_PARENT, 1352 .ops = &clk_branch2_ops, 1353 }, 1354 }, 1355 }; 1356 1357 static struct clk_branch cam_cc_cci_2_clk = { 1358 .halt_reg = 0xc21c, 1359 .halt_check = BRANCH_HALT, 1360 .clkr = { 1361 .enable_reg = 0xc21c, 1362 .enable_mask = BIT(0), 1363 .hw.init = &(const struct clk_init_data) { 1364 .name = "cam_cc_cci_2_clk", 1365 .parent_hws = (const struct clk_hw*[]) { 1366 &cam_cc_cci_2_clk_src.clkr.hw, 1367 }, 1368 .num_parents = 1, 1369 .flags = CLK_SET_RATE_PARENT, 1370 .ops = &clk_branch2_ops, 1371 }, 1372 }, 1373 }; 1374 1375 static struct clk_branch cam_cc_cci_3_clk = { 1376 .halt_reg = 0xc238, 1377 .halt_check = BRANCH_HALT, 1378 .clkr = { 1379 .enable_reg = 0xc238, 1380 .enable_mask = BIT(0), 1381 .hw.init = &(const struct clk_init_data) { 1382 .name = "cam_cc_cci_3_clk", 1383 .parent_hws = (const struct clk_hw*[]) { 1384 &cam_cc_cci_3_clk_src.clkr.hw, 1385 }, 1386 .num_parents = 1, 1387 .flags = CLK_SET_RATE_PARENT, 1388 .ops = &clk_branch2_ops, 1389 }, 1390 }, 1391 }; 1392 1393 static struct clk_branch cam_cc_core_ahb_clk = { 1394 .halt_reg = 0xc1c8, 1395 .halt_check = BRANCH_HALT_VOTED, 1396 .clkr = { 1397 .enable_reg = 0xc1c8, 1398 .enable_mask = BIT(0), 1399 .hw.init = &(const struct clk_init_data) { 1400 .name = "cam_cc_core_ahb_clk", 1401 .parent_hws = (const struct clk_hw*[]) { 1402 &cam_cc_slow_ahb_clk_src.clkr.hw, 1403 }, 1404 .num_parents = 1, 1405 .flags = CLK_SET_RATE_PARENT, 1406 .ops = &clk_branch2_ops, 1407 }, 1408 }, 1409 }; 1410 1411 static struct clk_branch cam_cc_cpas_ahb_clk = { 1412 .halt_reg = 0xc168, 1413 .halt_check = BRANCH_HALT, 1414 .clkr = { 1415 .enable_reg = 0xc168, 1416 .enable_mask = BIT(0), 1417 .hw.init = &(const struct clk_init_data) { 1418 .name = "cam_cc_cpas_ahb_clk", 1419 .parent_hws = (const struct clk_hw*[]) { 1420 &cam_cc_slow_ahb_clk_src.clkr.hw, 1421 }, 1422 .num_parents = 1, 1423 .flags = CLK_SET_RATE_PARENT, 1424 .ops = &clk_branch2_ops, 1425 }, 1426 }, 1427 }; 1428 1429 static struct clk_branch cam_cc_csi0phytimer_clk = { 1430 .halt_reg = 0x601c, 1431 .halt_check = BRANCH_HALT, 1432 .clkr = { 1433 .enable_reg = 0x601c, 1434 .enable_mask = BIT(0), 1435 .hw.init = &(const struct clk_init_data) { 1436 .name = "cam_cc_csi0phytimer_clk", 1437 .parent_hws = (const struct clk_hw*[]) { 1438 &cam_cc_csi0phytimer_clk_src.clkr.hw, 1439 }, 1440 .num_parents = 1, 1441 .flags = CLK_SET_RATE_PARENT, 1442 .ops = &clk_branch2_ops, 1443 }, 1444 }, 1445 }; 1446 1447 static struct clk_branch cam_cc_csi1phytimer_clk = { 1448 .halt_reg = 0x6040, 1449 .halt_check = BRANCH_HALT, 1450 .clkr = { 1451 .enable_reg = 0x6040, 1452 .enable_mask = BIT(0), 1453 .hw.init = &(const struct clk_init_data) { 1454 .name = "cam_cc_csi1phytimer_clk", 1455 .parent_hws = (const struct clk_hw*[]) { 1456 &cam_cc_csi1phytimer_clk_src.clkr.hw, 1457 }, 1458 .num_parents = 1, 1459 .flags = CLK_SET_RATE_PARENT, 1460 .ops = &clk_branch2_ops, 1461 }, 1462 }, 1463 }; 1464 1465 static struct clk_branch cam_cc_csi2phytimer_clk = { 1466 .halt_reg = 0x6064, 1467 .halt_check = BRANCH_HALT, 1468 .clkr = { 1469 .enable_reg = 0x6064, 1470 .enable_mask = BIT(0), 1471 .hw.init = &(const struct clk_init_data) { 1472 .name = "cam_cc_csi2phytimer_clk", 1473 .parent_hws = (const struct clk_hw*[]) { 1474 &cam_cc_csi2phytimer_clk_src.clkr.hw, 1475 }, 1476 .num_parents = 1, 1477 .flags = CLK_SET_RATE_PARENT, 1478 .ops = &clk_branch2_ops, 1479 }, 1480 }, 1481 }; 1482 1483 static struct clk_branch cam_cc_csi3phytimer_clk = { 1484 .halt_reg = 0x6088, 1485 .halt_check = BRANCH_HALT, 1486 .clkr = { 1487 .enable_reg = 0x6088, 1488 .enable_mask = BIT(0), 1489 .hw.init = &(const struct clk_init_data) { 1490 .name = "cam_cc_csi3phytimer_clk", 1491 .parent_hws = (const struct clk_hw*[]) { 1492 &cam_cc_csi3phytimer_clk_src.clkr.hw, 1493 }, 1494 .num_parents = 1, 1495 .flags = CLK_SET_RATE_PARENT, 1496 .ops = &clk_branch2_ops, 1497 }, 1498 }, 1499 }; 1500 1501 static struct clk_branch cam_cc_csiphy0_clk = { 1502 .halt_reg = 0x6020, 1503 .halt_check = BRANCH_HALT, 1504 .clkr = { 1505 .enable_reg = 0x6020, 1506 .enable_mask = BIT(0), 1507 .hw.init = &(const struct clk_init_data) { 1508 .name = "cam_cc_csiphy0_clk", 1509 .parent_hws = (const struct clk_hw*[]) { 1510 &cam_cc_cphy_rx_clk_src.clkr.hw, 1511 }, 1512 .num_parents = 1, 1513 .flags = CLK_SET_RATE_PARENT, 1514 .ops = &clk_branch2_ops, 1515 }, 1516 }, 1517 }; 1518 1519 static struct clk_branch cam_cc_csiphy1_clk = { 1520 .halt_reg = 0x6044, 1521 .halt_check = BRANCH_HALT, 1522 .clkr = { 1523 .enable_reg = 0x6044, 1524 .enable_mask = BIT(0), 1525 .hw.init = &(const struct clk_init_data) { 1526 .name = "cam_cc_csiphy1_clk", 1527 .parent_hws = (const struct clk_hw*[]) { 1528 &cam_cc_cphy_rx_clk_src.clkr.hw, 1529 }, 1530 .num_parents = 1, 1531 .flags = CLK_SET_RATE_PARENT, 1532 .ops = &clk_branch2_ops, 1533 }, 1534 }, 1535 }; 1536 1537 static struct clk_branch cam_cc_csiphy2_clk = { 1538 .halt_reg = 0x6068, 1539 .halt_check = BRANCH_HALT, 1540 .clkr = { 1541 .enable_reg = 0x6068, 1542 .enable_mask = BIT(0), 1543 .hw.init = &(const struct clk_init_data) { 1544 .name = "cam_cc_csiphy2_clk", 1545 .parent_hws = (const struct clk_hw*[]) { 1546 &cam_cc_cphy_rx_clk_src.clkr.hw, 1547 }, 1548 .num_parents = 1, 1549 .flags = CLK_SET_RATE_PARENT, 1550 .ops = &clk_branch2_ops, 1551 }, 1552 }, 1553 }; 1554 1555 static struct clk_branch cam_cc_csiphy3_clk = { 1556 .halt_reg = 0x608c, 1557 .halt_check = BRANCH_HALT, 1558 .clkr = { 1559 .enable_reg = 0x608c, 1560 .enable_mask = BIT(0), 1561 .hw.init = &(const struct clk_init_data) { 1562 .name = "cam_cc_csiphy3_clk", 1563 .parent_hws = (const struct clk_hw*[]) { 1564 &cam_cc_cphy_rx_clk_src.clkr.hw, 1565 }, 1566 .num_parents = 1, 1567 .flags = CLK_SET_RATE_PARENT, 1568 .ops = &clk_branch2_ops, 1569 }, 1570 }, 1571 }; 1572 1573 static struct clk_branch cam_cc_fd_core_clk = { 1574 .halt_reg = 0xc0f8, 1575 .halt_check = BRANCH_HALT, 1576 .clkr = { 1577 .enable_reg = 0xc0f8, 1578 .enable_mask = BIT(0), 1579 .hw.init = &(const struct clk_init_data) { 1580 .name = "cam_cc_fd_core_clk", 1581 .parent_hws = (const struct clk_hw*[]) { 1582 &cam_cc_fd_core_clk_src.clkr.hw, 1583 }, 1584 .num_parents = 1, 1585 .flags = CLK_SET_RATE_PARENT, 1586 .ops = &clk_branch2_ops, 1587 }, 1588 }, 1589 }; 1590 1591 static struct clk_branch cam_cc_fd_core_uar_clk = { 1592 .halt_reg = 0xc100, 1593 .halt_check = BRANCH_HALT, 1594 .clkr = { 1595 .enable_reg = 0xc100, 1596 .enable_mask = BIT(0), 1597 .hw.init = &(const struct clk_init_data) { 1598 .name = "cam_cc_fd_core_uar_clk", 1599 .parent_hws = (const struct clk_hw*[]) { 1600 &cam_cc_fd_core_clk_src.clkr.hw, 1601 }, 1602 .num_parents = 1, 1603 .flags = CLK_SET_RATE_PARENT, 1604 .ops = &clk_branch2_ops, 1605 }, 1606 }, 1607 }; 1608 1609 static struct clk_branch cam_cc_icp_ahb_clk = { 1610 .halt_reg = 0xc0d8, 1611 .halt_check = BRANCH_HALT, 1612 .clkr = { 1613 .enable_reg = 0xc0d8, 1614 .enable_mask = BIT(0), 1615 .hw.init = &(const struct clk_init_data) { 1616 .name = "cam_cc_icp_ahb_clk", 1617 .parent_hws = (const struct clk_hw*[]) { 1618 &cam_cc_slow_ahb_clk_src.clkr.hw, 1619 }, 1620 .num_parents = 1, 1621 .flags = CLK_SET_RATE_PARENT, 1622 .ops = &clk_branch2_ops, 1623 }, 1624 }, 1625 }; 1626 1627 static struct clk_branch cam_cc_icp_clk = { 1628 .halt_reg = 0xc0d0, 1629 .halt_check = BRANCH_HALT, 1630 .clkr = { 1631 .enable_reg = 0xc0d0, 1632 .enable_mask = BIT(0), 1633 .hw.init = &(const struct clk_init_data) { 1634 .name = "cam_cc_icp_clk", 1635 .parent_hws = (const struct clk_hw*[]) { 1636 &cam_cc_icp_clk_src.clkr.hw, 1637 }, 1638 .num_parents = 1, 1639 .flags = CLK_SET_RATE_PARENT, 1640 .ops = &clk_branch2_ops, 1641 }, 1642 }, 1643 }; 1644 1645 static struct clk_branch cam_cc_ife_0_axi_clk = { 1646 .halt_reg = 0xa080, 1647 .halt_check = BRANCH_HALT, 1648 .clkr = { 1649 .enable_reg = 0xa080, 1650 .enable_mask = BIT(0), 1651 .hw.init = &(const struct clk_init_data) { 1652 .name = "cam_cc_ife_0_axi_clk", 1653 .parent_hws = (const struct clk_hw*[]) { 1654 &cam_cc_camnoc_axi_clk_src.clkr.hw, 1655 }, 1656 .num_parents = 1, 1657 .flags = CLK_SET_RATE_PARENT, 1658 .ops = &clk_branch2_ops, 1659 }, 1660 }, 1661 }; 1662 1663 static struct clk_branch cam_cc_ife_0_clk = { 1664 .halt_reg = 0xa028, 1665 .halt_check = BRANCH_HALT, 1666 .clkr = { 1667 .enable_reg = 0xa028, 1668 .enable_mask = BIT(0), 1669 .hw.init = &(const struct clk_init_data) { 1670 .name = "cam_cc_ife_0_clk", 1671 .parent_hws = (const struct clk_hw*[]) { 1672 &cam_cc_ife_0_clk_src.clkr.hw, 1673 }, 1674 .num_parents = 1, 1675 .flags = CLK_SET_RATE_PARENT, 1676 .ops = &clk_branch2_ops, 1677 }, 1678 }, 1679 }; 1680 1681 static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { 1682 .halt_reg = 0xa07c, 1683 .halt_check = BRANCH_HALT, 1684 .clkr = { 1685 .enable_reg = 0xa07c, 1686 .enable_mask = BIT(0), 1687 .hw.init = &(const struct clk_init_data) { 1688 .name = "cam_cc_ife_0_cphy_rx_clk", 1689 .parent_hws = (const struct clk_hw*[]) { 1690 &cam_cc_cphy_rx_clk_src.clkr.hw, 1691 }, 1692 .num_parents = 1, 1693 .flags = CLK_SET_RATE_PARENT, 1694 .ops = &clk_branch2_ops, 1695 }, 1696 }, 1697 }; 1698 1699 static struct clk_branch cam_cc_ife_0_csid_clk = { 1700 .halt_reg = 0xa054, 1701 .halt_check = BRANCH_HALT, 1702 .clkr = { 1703 .enable_reg = 0xa054, 1704 .enable_mask = BIT(0), 1705 .hw.init = &(const struct clk_init_data) { 1706 .name = "cam_cc_ife_0_csid_clk", 1707 .parent_hws = (const struct clk_hw*[]) { 1708 &cam_cc_ife_0_csid_clk_src.clkr.hw, 1709 }, 1710 .num_parents = 1, 1711 .flags = CLK_SET_RATE_PARENT, 1712 .ops = &clk_branch2_ops, 1713 }, 1714 }, 1715 }; 1716 1717 static struct clk_branch cam_cc_ife_0_dsp_clk = { 1718 .halt_reg = 0xa038, 1719 .halt_check = BRANCH_HALT, 1720 .clkr = { 1721 .enable_reg = 0xa038, 1722 .enable_mask = BIT(0), 1723 .hw.init = &(const struct clk_init_data) { 1724 .name = "cam_cc_ife_0_dsp_clk", 1725 .parent_hws = (const struct clk_hw*[]) { 1726 &cam_cc_ife_0_clk_src.clkr.hw, 1727 }, 1728 .num_parents = 1, 1729 .flags = CLK_SET_RATE_PARENT, 1730 .ops = &clk_branch2_ops, 1731 }, 1732 }, 1733 }; 1734 1735 static struct clk_branch cam_cc_ife_1_axi_clk = { 1736 .halt_reg = 0xb058, 1737 .halt_check = BRANCH_HALT, 1738 .clkr = { 1739 .enable_reg = 0xb058, 1740 .enable_mask = BIT(0), 1741 .hw.init = &(const struct clk_init_data) { 1742 .name = "cam_cc_ife_1_axi_clk", 1743 .parent_hws = (const struct clk_hw*[]) { 1744 &cam_cc_camnoc_axi_clk_src.clkr.hw, 1745 }, 1746 .num_parents = 1, 1747 .flags = CLK_SET_RATE_PARENT, 1748 .ops = &clk_branch2_ops, 1749 }, 1750 }, 1751 }; 1752 1753 static struct clk_branch cam_cc_ife_1_clk = { 1754 .halt_reg = 0xb028, 1755 .halt_check = BRANCH_HALT, 1756 .clkr = { 1757 .enable_reg = 0xb028, 1758 .enable_mask = BIT(0), 1759 .hw.init = &(const struct clk_init_data) { 1760 .name = "cam_cc_ife_1_clk", 1761 .parent_hws = (const struct clk_hw*[]) { 1762 &cam_cc_ife_1_clk_src.clkr.hw, 1763 }, 1764 .num_parents = 1, 1765 .flags = CLK_SET_RATE_PARENT, 1766 .ops = &clk_branch2_ops, 1767 }, 1768 }, 1769 }; 1770 1771 static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { 1772 .halt_reg = 0xb054, 1773 .halt_check = BRANCH_HALT, 1774 .clkr = { 1775 .enable_reg = 0xb054, 1776 .enable_mask = BIT(0), 1777 .hw.init = &(const struct clk_init_data) { 1778 .name = "cam_cc_ife_1_cphy_rx_clk", 1779 .parent_hws = (const struct clk_hw*[]) { 1780 &cam_cc_cphy_rx_clk_src.clkr.hw, 1781 }, 1782 .num_parents = 1, 1783 .flags = CLK_SET_RATE_PARENT, 1784 .ops = &clk_branch2_ops, 1785 }, 1786 }, 1787 }; 1788 1789 static struct clk_branch cam_cc_ife_1_csid_clk = { 1790 .halt_reg = 0xb04c, 1791 .halt_check = BRANCH_HALT, 1792 .clkr = { 1793 .enable_reg = 0xb04c, 1794 .enable_mask = BIT(0), 1795 .hw.init = &(const struct clk_init_data) { 1796 .name = "cam_cc_ife_1_csid_clk", 1797 .parent_hws = (const struct clk_hw*[]) { 1798 &cam_cc_ife_1_csid_clk_src.clkr.hw, 1799 }, 1800 .num_parents = 1, 1801 .flags = CLK_SET_RATE_PARENT, 1802 .ops = &clk_branch2_ops, 1803 }, 1804 }, 1805 }; 1806 1807 static struct clk_branch cam_cc_ife_1_dsp_clk = { 1808 .halt_reg = 0xb030, 1809 .halt_check = BRANCH_HALT, 1810 .clkr = { 1811 .enable_reg = 0xb030, 1812 .enable_mask = BIT(0), 1813 .hw.init = &(const struct clk_init_data) { 1814 .name = "cam_cc_ife_1_dsp_clk", 1815 .parent_hws = (const struct clk_hw*[]) { 1816 &cam_cc_ife_1_clk_src.clkr.hw, 1817 }, 1818 .num_parents = 1, 1819 .flags = CLK_SET_RATE_PARENT, 1820 .ops = &clk_branch2_ops, 1821 }, 1822 }, 1823 }; 1824 1825 static struct clk_branch cam_cc_ife_2_axi_clk = { 1826 .halt_reg = 0xf068, 1827 .halt_check = BRANCH_HALT, 1828 .clkr = { 1829 .enable_reg = 0xf068, 1830 .enable_mask = BIT(0), 1831 .hw.init = &(const struct clk_init_data) { 1832 .name = "cam_cc_ife_2_axi_clk", 1833 .parent_hws = (const struct clk_hw*[]) { 1834 &cam_cc_camnoc_axi_clk_src.clkr.hw, 1835 }, 1836 .num_parents = 1, 1837 .flags = CLK_SET_RATE_PARENT, 1838 .ops = &clk_branch2_ops, 1839 }, 1840 }, 1841 }; 1842 1843 static struct clk_branch cam_cc_ife_2_clk = { 1844 .halt_reg = 0xf028, 1845 .halt_check = BRANCH_HALT, 1846 .clkr = { 1847 .enable_reg = 0xf028, 1848 .enable_mask = BIT(0), 1849 .hw.init = &(const struct clk_init_data) { 1850 .name = "cam_cc_ife_2_clk", 1851 .parent_hws = (const struct clk_hw*[]) { 1852 &cam_cc_ife_2_clk_src.clkr.hw, 1853 }, 1854 .num_parents = 1, 1855 .flags = CLK_SET_RATE_PARENT, 1856 .ops = &clk_branch2_ops, 1857 }, 1858 }, 1859 }; 1860 1861 static struct clk_branch cam_cc_ife_2_cphy_rx_clk = { 1862 .halt_reg = 0xf064, 1863 .halt_check = BRANCH_HALT, 1864 .clkr = { 1865 .enable_reg = 0xf064, 1866 .enable_mask = BIT(0), 1867 .hw.init = &(const struct clk_init_data) { 1868 .name = "cam_cc_ife_2_cphy_rx_clk", 1869 .parent_hws = (const struct clk_hw*[]) { 1870 &cam_cc_cphy_rx_clk_src.clkr.hw, 1871 }, 1872 .num_parents = 1, 1873 .flags = CLK_SET_RATE_PARENT, 1874 .ops = &clk_branch2_ops, 1875 }, 1876 }, 1877 }; 1878 1879 static struct clk_branch cam_cc_ife_2_csid_clk = { 1880 .halt_reg = 0xf054, 1881 .halt_check = BRANCH_HALT, 1882 .clkr = { 1883 .enable_reg = 0xf054, 1884 .enable_mask = BIT(0), 1885 .hw.init = &(const struct clk_init_data) { 1886 .name = "cam_cc_ife_2_csid_clk", 1887 .parent_hws = (const struct clk_hw*[]) { 1888 &cam_cc_ife_2_csid_clk_src.clkr.hw, 1889 }, 1890 .num_parents = 1, 1891 .flags = CLK_SET_RATE_PARENT, 1892 .ops = &clk_branch2_ops, 1893 }, 1894 }, 1895 }; 1896 1897 static struct clk_branch cam_cc_ife_2_dsp_clk = { 1898 .halt_reg = 0xf038, 1899 .halt_check = BRANCH_HALT, 1900 .clkr = { 1901 .enable_reg = 0xf038, 1902 .enable_mask = BIT(0), 1903 .hw.init = &(const struct clk_init_data) { 1904 .name = "cam_cc_ife_2_dsp_clk", 1905 .parent_hws = (const struct clk_hw*[]) { 1906 &cam_cc_ife_2_clk_src.clkr.hw, 1907 }, 1908 .num_parents = 1, 1909 .flags = CLK_SET_RATE_PARENT, 1910 .ops = &clk_branch2_ops, 1911 }, 1912 }, 1913 }; 1914 1915 static struct clk_branch cam_cc_ife_3_axi_clk = { 1916 .halt_reg = 0xf0d4, 1917 .halt_check = BRANCH_HALT, 1918 .clkr = { 1919 .enable_reg = 0xf0d4, 1920 .enable_mask = BIT(0), 1921 .hw.init = &(const struct clk_init_data) { 1922 .name = "cam_cc_ife_3_axi_clk", 1923 .parent_hws = (const struct clk_hw*[]) { 1924 &cam_cc_camnoc_axi_clk_src.clkr.hw, 1925 }, 1926 .num_parents = 1, 1927 .flags = CLK_SET_RATE_PARENT, 1928 .ops = &clk_branch2_ops, 1929 }, 1930 }, 1931 }; 1932 1933 static struct clk_branch cam_cc_ife_3_clk = { 1934 .halt_reg = 0xf094, 1935 .halt_check = BRANCH_HALT, 1936 .clkr = { 1937 .enable_reg = 0xf094, 1938 .enable_mask = BIT(0), 1939 .hw.init = &(const struct clk_init_data) { 1940 .name = "cam_cc_ife_3_clk", 1941 .parent_hws = (const struct clk_hw*[]) { 1942 &cam_cc_ife_3_clk_src.clkr.hw, 1943 }, 1944 .num_parents = 1, 1945 .flags = CLK_SET_RATE_PARENT, 1946 .ops = &clk_branch2_ops, 1947 }, 1948 }, 1949 }; 1950 1951 static struct clk_branch cam_cc_ife_3_cphy_rx_clk = { 1952 .halt_reg = 0xf0d0, 1953 .halt_check = BRANCH_HALT, 1954 .clkr = { 1955 .enable_reg = 0xf0d0, 1956 .enable_mask = BIT(0), 1957 .hw.init = &(const struct clk_init_data) { 1958 .name = "cam_cc_ife_3_cphy_rx_clk", 1959 .parent_hws = (const struct clk_hw*[]) { 1960 &cam_cc_cphy_rx_clk_src.clkr.hw, 1961 }, 1962 .num_parents = 1, 1963 .flags = CLK_SET_RATE_PARENT, 1964 .ops = &clk_branch2_ops, 1965 }, 1966 }, 1967 }; 1968 1969 static struct clk_branch cam_cc_ife_3_csid_clk = { 1970 .halt_reg = 0xf0c0, 1971 .halt_check = BRANCH_HALT, 1972 .clkr = { 1973 .enable_reg = 0xf0c0, 1974 .enable_mask = BIT(0), 1975 .hw.init = &(const struct clk_init_data) { 1976 .name = "cam_cc_ife_3_csid_clk", 1977 .parent_hws = (const struct clk_hw*[]) { 1978 &cam_cc_ife_3_csid_clk_src.clkr.hw, 1979 }, 1980 .num_parents = 1, 1981 .flags = CLK_SET_RATE_PARENT, 1982 .ops = &clk_branch2_ops, 1983 }, 1984 }, 1985 }; 1986 1987 static struct clk_branch cam_cc_ife_3_dsp_clk = { 1988 .halt_reg = 0xf0a4, 1989 .halt_check = BRANCH_HALT, 1990 .clkr = { 1991 .enable_reg = 0xf0a4, 1992 .enable_mask = BIT(0), 1993 .hw.init = &(const struct clk_init_data) { 1994 .name = "cam_cc_ife_3_dsp_clk", 1995 .parent_hws = (const struct clk_hw*[]) { 1996 &cam_cc_ife_3_clk_src.clkr.hw, 1997 }, 1998 .num_parents = 1, 1999 .flags = CLK_SET_RATE_PARENT, 2000 .ops = &clk_branch2_ops, 2001 }, 2002 }, 2003 }; 2004 2005 static struct clk_branch cam_cc_ife_lite_0_clk = { 2006 .halt_reg = 0xc01c, 2007 .halt_check = BRANCH_HALT, 2008 .clkr = { 2009 .enable_reg = 0xc01c, 2010 .enable_mask = BIT(0), 2011 .hw.init = &(const struct clk_init_data) { 2012 .name = "cam_cc_ife_lite_0_clk", 2013 .parent_hws = (const struct clk_hw*[]) { 2014 &cam_cc_ife_lite_0_clk_src.clkr.hw, 2015 }, 2016 .num_parents = 1, 2017 .flags = CLK_SET_RATE_PARENT, 2018 .ops = &clk_branch2_ops, 2019 }, 2020 }, 2021 }; 2022 2023 static struct clk_branch cam_cc_ife_lite_0_cphy_rx_clk = { 2024 .halt_reg = 0xc040, 2025 .halt_check = BRANCH_HALT, 2026 .clkr = { 2027 .enable_reg = 0xc040, 2028 .enable_mask = BIT(0), 2029 .hw.init = &(const struct clk_init_data) { 2030 .name = "cam_cc_ife_lite_0_cphy_rx_clk", 2031 .parent_hws = (const struct clk_hw*[]) { 2032 &cam_cc_cphy_rx_clk_src.clkr.hw, 2033 }, 2034 .num_parents = 1, 2035 .flags = CLK_SET_RATE_PARENT, 2036 .ops = &clk_branch2_ops, 2037 }, 2038 }, 2039 }; 2040 2041 static struct clk_branch cam_cc_ife_lite_0_csid_clk = { 2042 .halt_reg = 0xc038, 2043 .halt_check = BRANCH_HALT, 2044 .clkr = { 2045 .enable_reg = 0xc038, 2046 .enable_mask = BIT(0), 2047 .hw.init = &(const struct clk_init_data) { 2048 .name = "cam_cc_ife_lite_0_csid_clk", 2049 .parent_hws = (const struct clk_hw*[]) { 2050 &cam_cc_ife_lite_0_csid_clk_src.clkr.hw, 2051 }, 2052 .num_parents = 1, 2053 .flags = CLK_SET_RATE_PARENT, 2054 .ops = &clk_branch2_ops, 2055 }, 2056 }, 2057 }; 2058 2059 static struct clk_branch cam_cc_ife_lite_1_clk = { 2060 .halt_reg = 0xc060, 2061 .halt_check = BRANCH_HALT, 2062 .clkr = { 2063 .enable_reg = 0xc060, 2064 .enable_mask = BIT(0), 2065 .hw.init = &(const struct clk_init_data) { 2066 .name = "cam_cc_ife_lite_1_clk", 2067 .parent_hws = (const struct clk_hw*[]) { 2068 &cam_cc_ife_lite_1_clk_src.clkr.hw, 2069 }, 2070 .num_parents = 1, 2071 .flags = CLK_SET_RATE_PARENT, 2072 .ops = &clk_branch2_ops, 2073 }, 2074 }, 2075 }; 2076 2077 static struct clk_branch cam_cc_ife_lite_1_cphy_rx_clk = { 2078 .halt_reg = 0xc084, 2079 .halt_check = BRANCH_HALT, 2080 .clkr = { 2081 .enable_reg = 0xc084, 2082 .enable_mask = BIT(0), 2083 .hw.init = &(const struct clk_init_data) { 2084 .name = "cam_cc_ife_lite_1_cphy_rx_clk", 2085 .parent_hws = (const struct clk_hw*[]) { 2086 &cam_cc_cphy_rx_clk_src.clkr.hw, 2087 }, 2088 .num_parents = 1, 2089 .flags = CLK_SET_RATE_PARENT, 2090 .ops = &clk_branch2_ops, 2091 }, 2092 }, 2093 }; 2094 2095 static struct clk_branch cam_cc_ife_lite_1_csid_clk = { 2096 .halt_reg = 0xc07c, 2097 .halt_check = BRANCH_HALT, 2098 .clkr = { 2099 .enable_reg = 0xc07c, 2100 .enable_mask = BIT(0), 2101 .hw.init = &(const struct clk_init_data) { 2102 .name = "cam_cc_ife_lite_1_csid_clk", 2103 .parent_hws = (const struct clk_hw*[]) { 2104 &cam_cc_ife_lite_1_csid_clk_src.clkr.hw, 2105 }, 2106 .num_parents = 1, 2107 .flags = CLK_SET_RATE_PARENT, 2108 .ops = &clk_branch2_ops, 2109 }, 2110 }, 2111 }; 2112 2113 static struct clk_branch cam_cc_ife_lite_2_clk = { 2114 .halt_reg = 0xc258, 2115 .halt_check = BRANCH_HALT, 2116 .clkr = { 2117 .enable_reg = 0xc258, 2118 .enable_mask = BIT(0), 2119 .hw.init = &(const struct clk_init_data) { 2120 .name = "cam_cc_ife_lite_2_clk", 2121 .parent_hws = (const struct clk_hw*[]) { 2122 &cam_cc_ife_lite_2_clk_src.clkr.hw, 2123 }, 2124 .num_parents = 1, 2125 .flags = CLK_SET_RATE_PARENT, 2126 .ops = &clk_branch2_ops, 2127 }, 2128 }, 2129 }; 2130 2131 static struct clk_branch cam_cc_ife_lite_2_cphy_rx_clk = { 2132 .halt_reg = 0xc27c, 2133 .halt_check = BRANCH_HALT, 2134 .clkr = { 2135 .enable_reg = 0xc27c, 2136 .enable_mask = BIT(0), 2137 .hw.init = &(const struct clk_init_data) { 2138 .name = "cam_cc_ife_lite_2_cphy_rx_clk", 2139 .parent_hws = (const struct clk_hw*[]) { 2140 &cam_cc_cphy_rx_clk_src.clkr.hw, 2141 }, 2142 .num_parents = 1, 2143 .flags = CLK_SET_RATE_PARENT, 2144 .ops = &clk_branch2_ops, 2145 }, 2146 }, 2147 }; 2148 2149 static struct clk_branch cam_cc_ife_lite_2_csid_clk = { 2150 .halt_reg = 0xc274, 2151 .halt_check = BRANCH_HALT, 2152 .clkr = { 2153 .enable_reg = 0xc274, 2154 .enable_mask = BIT(0), 2155 .hw.init = &(const struct clk_init_data) { 2156 .name = "cam_cc_ife_lite_2_csid_clk", 2157 .parent_hws = (const struct clk_hw*[]) { 2158 &cam_cc_ife_lite_2_csid_clk_src.clkr.hw, 2159 }, 2160 .num_parents = 1, 2161 .flags = CLK_SET_RATE_PARENT, 2162 .ops = &clk_branch2_ops, 2163 }, 2164 }, 2165 }; 2166 2167 static struct clk_branch cam_cc_ife_lite_3_clk = { 2168 .halt_reg = 0xc29c, 2169 .halt_check = BRANCH_HALT, 2170 .clkr = { 2171 .enable_reg = 0xc29c, 2172 .enable_mask = BIT(0), 2173 .hw.init = &(const struct clk_init_data) { 2174 .name = "cam_cc_ife_lite_3_clk", 2175 .parent_hws = (const struct clk_hw*[]) { 2176 &cam_cc_ife_lite_3_clk_src.clkr.hw, 2177 }, 2178 .num_parents = 1, 2179 .flags = CLK_SET_RATE_PARENT, 2180 .ops = &clk_branch2_ops, 2181 }, 2182 }, 2183 }; 2184 2185 static struct clk_branch cam_cc_ife_lite_3_cphy_rx_clk = { 2186 .halt_reg = 0xc2c0, 2187 .halt_check = BRANCH_HALT, 2188 .clkr = { 2189 .enable_reg = 0xc2c0, 2190 .enable_mask = BIT(0), 2191 .hw.init = &(const struct clk_init_data) { 2192 .name = "cam_cc_ife_lite_3_cphy_rx_clk", 2193 .parent_hws = (const struct clk_hw*[]) { 2194 &cam_cc_cphy_rx_clk_src.clkr.hw, 2195 }, 2196 .num_parents = 1, 2197 .flags = CLK_SET_RATE_PARENT, 2198 .ops = &clk_branch2_ops, 2199 }, 2200 }, 2201 }; 2202 2203 static struct clk_branch cam_cc_ife_lite_3_csid_clk = { 2204 .halt_reg = 0xc2b8, 2205 .halt_check = BRANCH_HALT, 2206 .clkr = { 2207 .enable_reg = 0xc2b8, 2208 .enable_mask = BIT(0), 2209 .hw.init = &(const struct clk_init_data) { 2210 .name = "cam_cc_ife_lite_3_csid_clk", 2211 .parent_hws = (const struct clk_hw*[]) { 2212 &cam_cc_ife_lite_3_csid_clk_src.clkr.hw, 2213 }, 2214 .num_parents = 1, 2215 .flags = CLK_SET_RATE_PARENT, 2216 .ops = &clk_branch2_ops, 2217 }, 2218 }, 2219 }; 2220 2221 static struct clk_branch cam_cc_ipe_0_ahb_clk = { 2222 .halt_reg = 0x8040, 2223 .halt_check = BRANCH_HALT, 2224 .clkr = { 2225 .enable_reg = 0x8040, 2226 .enable_mask = BIT(0), 2227 .hw.init = &(const struct clk_init_data) { 2228 .name = "cam_cc_ipe_0_ahb_clk", 2229 .parent_hws = (const struct clk_hw*[]) { 2230 &cam_cc_slow_ahb_clk_src.clkr.hw, 2231 }, 2232 .num_parents = 1, 2233 .flags = CLK_SET_RATE_PARENT, 2234 .ops = &clk_branch2_ops, 2235 }, 2236 }, 2237 }; 2238 2239 static struct clk_branch cam_cc_ipe_0_areg_clk = { 2240 .halt_reg = 0x803c, 2241 .halt_check = BRANCH_HALT, 2242 .clkr = { 2243 .enable_reg = 0x803c, 2244 .enable_mask = BIT(0), 2245 .hw.init = &(const struct clk_init_data) { 2246 .name = "cam_cc_ipe_0_areg_clk", 2247 .parent_hws = (const struct clk_hw*[]) { 2248 &cam_cc_fast_ahb_clk_src.clkr.hw, 2249 }, 2250 .num_parents = 1, 2251 .flags = CLK_SET_RATE_PARENT, 2252 .ops = &clk_branch2_ops, 2253 }, 2254 }, 2255 }; 2256 2257 static struct clk_branch cam_cc_ipe_0_axi_clk = { 2258 .halt_reg = 0x8038, 2259 .halt_check = BRANCH_HALT, 2260 .clkr = { 2261 .enable_reg = 0x8038, 2262 .enable_mask = BIT(0), 2263 .hw.init = &(const struct clk_init_data) { 2264 .name = "cam_cc_ipe_0_axi_clk", 2265 .parent_hws = (const struct clk_hw*[]) { 2266 &cam_cc_camnoc_axi_clk_src.clkr.hw, 2267 }, 2268 .num_parents = 1, 2269 .flags = CLK_SET_RATE_PARENT, 2270 .ops = &clk_branch2_ops, 2271 }, 2272 }, 2273 }; 2274 2275 static struct clk_branch cam_cc_ipe_0_clk = { 2276 .halt_reg = 0x8028, 2277 .halt_check = BRANCH_HALT, 2278 .clkr = { 2279 .enable_reg = 0x8028, 2280 .enable_mask = BIT(0), 2281 .hw.init = &(const struct clk_init_data) { 2282 .name = "cam_cc_ipe_0_clk", 2283 .parent_hws = (const struct clk_hw*[]) { 2284 &cam_cc_ipe_0_clk_src.clkr.hw, 2285 }, 2286 .num_parents = 1, 2287 .flags = CLK_SET_RATE_PARENT, 2288 .ops = &clk_branch2_ops, 2289 }, 2290 }, 2291 }; 2292 2293 static struct clk_branch cam_cc_ipe_1_ahb_clk = { 2294 .halt_reg = 0x9028, 2295 .halt_check = BRANCH_HALT, 2296 .clkr = { 2297 .enable_reg = 0x9028, 2298 .enable_mask = BIT(0), 2299 .hw.init = &(const struct clk_init_data) { 2300 .name = "cam_cc_ipe_1_ahb_clk", 2301 .parent_hws = (const struct clk_hw*[]) { 2302 &cam_cc_slow_ahb_clk_src.clkr.hw, 2303 }, 2304 .num_parents = 1, 2305 .flags = CLK_SET_RATE_PARENT, 2306 .ops = &clk_branch2_ops, 2307 }, 2308 }, 2309 }; 2310 2311 static struct clk_branch cam_cc_ipe_1_areg_clk = { 2312 .halt_reg = 0x9024, 2313 .halt_check = BRANCH_HALT, 2314 .clkr = { 2315 .enable_reg = 0x9024, 2316 .enable_mask = BIT(0), 2317 .hw.init = &(const struct clk_init_data) { 2318 .name = "cam_cc_ipe_1_areg_clk", 2319 .parent_hws = (const struct clk_hw*[]) { 2320 &cam_cc_fast_ahb_clk_src.clkr.hw, 2321 }, 2322 .num_parents = 1, 2323 .flags = CLK_SET_RATE_PARENT, 2324 .ops = &clk_branch2_ops, 2325 }, 2326 }, 2327 }; 2328 2329 static struct clk_branch cam_cc_ipe_1_axi_clk = { 2330 .halt_reg = 0x9020, 2331 .halt_check = BRANCH_HALT, 2332 .clkr = { 2333 .enable_reg = 0x9020, 2334 .enable_mask = BIT(0), 2335 .hw.init = &(const struct clk_init_data) { 2336 .name = "cam_cc_ipe_1_axi_clk", 2337 .parent_hws = (const struct clk_hw*[]) { 2338 &cam_cc_camnoc_axi_clk_src.clkr.hw, 2339 }, 2340 .num_parents = 1, 2341 .flags = CLK_SET_RATE_PARENT, 2342 .ops = &clk_branch2_ops, 2343 }, 2344 }, 2345 }; 2346 2347 static struct clk_branch cam_cc_ipe_1_clk = { 2348 .halt_reg = 0x9010, 2349 .halt_check = BRANCH_HALT, 2350 .clkr = { 2351 .enable_reg = 0x9010, 2352 .enable_mask = BIT(0), 2353 .hw.init = &(const struct clk_init_data) { 2354 .name = "cam_cc_ipe_1_clk", 2355 .parent_hws = (const struct clk_hw*[]) { 2356 &cam_cc_ipe_0_clk_src.clkr.hw, 2357 }, 2358 .num_parents = 1, 2359 .flags = CLK_SET_RATE_PARENT, 2360 .ops = &clk_branch2_ops, 2361 }, 2362 }, 2363 }; 2364 2365 static struct clk_branch cam_cc_jpeg_clk = { 2366 .halt_reg = 0xc0a4, 2367 .halt_check = BRANCH_HALT, 2368 .clkr = { 2369 .enable_reg = 0xc0a4, 2370 .enable_mask = BIT(0), 2371 .hw.init = &(const struct clk_init_data) { 2372 .name = "cam_cc_jpeg_clk", 2373 .parent_hws = (const struct clk_hw*[]) { 2374 &cam_cc_jpeg_clk_src.clkr.hw, 2375 }, 2376 .num_parents = 1, 2377 .flags = CLK_SET_RATE_PARENT, 2378 .ops = &clk_branch2_ops, 2379 }, 2380 }, 2381 }; 2382 2383 static struct clk_branch cam_cc_lrme_clk = { 2384 .halt_reg = 0xc15c, 2385 .halt_check = BRANCH_HALT, 2386 .clkr = { 2387 .enable_reg = 0xc15c, 2388 .enable_mask = BIT(0), 2389 .hw.init = &(const struct clk_init_data) { 2390 .name = "cam_cc_lrme_clk", 2391 .parent_hws = (const struct clk_hw*[]) { 2392 &cam_cc_lrme_clk_src.clkr.hw, 2393 }, 2394 .num_parents = 1, 2395 .flags = CLK_SET_RATE_PARENT, 2396 .ops = &clk_branch2_ops, 2397 }, 2398 }, 2399 }; 2400 2401 static struct clk_branch cam_cc_mclk0_clk = { 2402 .halt_reg = 0x501c, 2403 .halt_check = BRANCH_HALT, 2404 .clkr = { 2405 .enable_reg = 0x501c, 2406 .enable_mask = BIT(0), 2407 .hw.init = &(const struct clk_init_data) { 2408 .name = "cam_cc_mclk0_clk", 2409 .parent_hws = (const struct clk_hw*[]) { 2410 &cam_cc_mclk0_clk_src.clkr.hw, 2411 }, 2412 .num_parents = 1, 2413 .flags = CLK_SET_RATE_PARENT, 2414 .ops = &clk_branch2_ops, 2415 }, 2416 }, 2417 }; 2418 2419 static struct clk_branch cam_cc_mclk1_clk = { 2420 .halt_reg = 0x503c, 2421 .halt_check = BRANCH_HALT, 2422 .clkr = { 2423 .enable_reg = 0x503c, 2424 .enable_mask = BIT(0), 2425 .hw.init = &(const struct clk_init_data) { 2426 .name = "cam_cc_mclk1_clk", 2427 .parent_hws = (const struct clk_hw*[]) { 2428 &cam_cc_mclk1_clk_src.clkr.hw, 2429 }, 2430 .num_parents = 1, 2431 .flags = CLK_SET_RATE_PARENT, 2432 .ops = &clk_branch2_ops, 2433 }, 2434 }, 2435 }; 2436 2437 static struct clk_branch cam_cc_mclk2_clk = { 2438 .halt_reg = 0x505c, 2439 .halt_check = BRANCH_HALT, 2440 .clkr = { 2441 .enable_reg = 0x505c, 2442 .enable_mask = BIT(0), 2443 .hw.init = &(const struct clk_init_data) { 2444 .name = "cam_cc_mclk2_clk", 2445 .parent_hws = (const struct clk_hw*[]) { 2446 &cam_cc_mclk2_clk_src.clkr.hw, 2447 }, 2448 .num_parents = 1, 2449 .flags = CLK_SET_RATE_PARENT, 2450 .ops = &clk_branch2_ops, 2451 }, 2452 }, 2453 }; 2454 2455 static struct clk_branch cam_cc_mclk3_clk = { 2456 .halt_reg = 0x507c, 2457 .halt_check = BRANCH_HALT, 2458 .clkr = { 2459 .enable_reg = 0x507c, 2460 .enable_mask = BIT(0), 2461 .hw.init = &(const struct clk_init_data) { 2462 .name = "cam_cc_mclk3_clk", 2463 .parent_hws = (const struct clk_hw*[]) { 2464 &cam_cc_mclk3_clk_src.clkr.hw, 2465 }, 2466 .num_parents = 1, 2467 .flags = CLK_SET_RATE_PARENT, 2468 .ops = &clk_branch2_ops, 2469 }, 2470 }, 2471 }; 2472 2473 static struct clk_branch cam_cc_mclk4_clk = { 2474 .halt_reg = 0x509c, 2475 .halt_check = BRANCH_HALT, 2476 .clkr = { 2477 .enable_reg = 0x509c, 2478 .enable_mask = BIT(0), 2479 .hw.init = &(const struct clk_init_data) { 2480 .name = "cam_cc_mclk4_clk", 2481 .parent_hws = (const struct clk_hw*[]) { 2482 &cam_cc_mclk4_clk_src.clkr.hw, 2483 }, 2484 .num_parents = 1, 2485 .flags = CLK_SET_RATE_PARENT, 2486 .ops = &clk_branch2_ops, 2487 }, 2488 }, 2489 }; 2490 2491 static struct clk_branch cam_cc_mclk5_clk = { 2492 .halt_reg = 0x50bc, 2493 .halt_check = BRANCH_HALT, 2494 .clkr = { 2495 .enable_reg = 0x50bc, 2496 .enable_mask = BIT(0), 2497 .hw.init = &(const struct clk_init_data) { 2498 .name = "cam_cc_mclk5_clk", 2499 .parent_hws = (const struct clk_hw*[]) { 2500 &cam_cc_mclk5_clk_src.clkr.hw, 2501 }, 2502 .num_parents = 1, 2503 .flags = CLK_SET_RATE_PARENT, 2504 .ops = &clk_branch2_ops, 2505 }, 2506 }, 2507 }; 2508 2509 static struct clk_branch cam_cc_mclk6_clk = { 2510 .halt_reg = 0x50dc, 2511 .halt_check = BRANCH_HALT, 2512 .clkr = { 2513 .enable_reg = 0x50dc, 2514 .enable_mask = BIT(0), 2515 .hw.init = &(const struct clk_init_data) { 2516 .name = "cam_cc_mclk6_clk", 2517 .parent_hws = (const struct clk_hw*[]) { 2518 &cam_cc_mclk6_clk_src.clkr.hw, 2519 }, 2520 .num_parents = 1, 2521 .flags = CLK_SET_RATE_PARENT, 2522 .ops = &clk_branch2_ops, 2523 }, 2524 }, 2525 }; 2526 2527 static struct clk_branch cam_cc_mclk7_clk = { 2528 .halt_reg = 0x50fc, 2529 .halt_check = BRANCH_HALT, 2530 .clkr = { 2531 .enable_reg = 0x50fc, 2532 .enable_mask = BIT(0), 2533 .hw.init = &(const struct clk_init_data) { 2534 .name = "cam_cc_mclk7_clk", 2535 .parent_hws = (const struct clk_hw*[]) { 2536 &cam_cc_mclk7_clk_src.clkr.hw, 2537 }, 2538 .num_parents = 1, 2539 .flags = CLK_SET_RATE_PARENT, 2540 .ops = &clk_branch2_ops, 2541 }, 2542 }, 2543 }; 2544 2545 static struct gdsc titan_top_gdsc = { 2546 .gdscr = 0xc1bc, 2547 .en_rest_wait_val = 0x2, 2548 .en_few_wait_val = 0x2, 2549 .clk_dis_wait_val = 0xf, 2550 .pd = { 2551 .name = "titan_top_gdsc", 2552 }, 2553 .pwrsts = PWRSTS_OFF_ON, 2554 .flags = POLL_CFG_GDSCR, 2555 }; 2556 2557 static struct gdsc bps_gdsc = { 2558 .gdscr = 0x7004, 2559 .en_rest_wait_val = 0x2, 2560 .en_few_wait_val = 0x2, 2561 .clk_dis_wait_val = 0xf, 2562 .pd = { 2563 .name = "bps_gdsc", 2564 }, 2565 .pwrsts = PWRSTS_OFF_ON, 2566 .parent = &titan_top_gdsc.pd, 2567 .flags = POLL_CFG_GDSCR, 2568 }; 2569 2570 static struct gdsc ife_0_gdsc = { 2571 .gdscr = 0xa004, 2572 .en_rest_wait_val = 0x2, 2573 .en_few_wait_val = 0x2, 2574 .clk_dis_wait_val = 0xf, 2575 .pd = { 2576 .name = "ife_0_gdsc", 2577 }, 2578 .pwrsts = PWRSTS_OFF_ON, 2579 .parent = &titan_top_gdsc.pd, 2580 .flags = POLL_CFG_GDSCR, 2581 }; 2582 2583 static struct gdsc ife_1_gdsc = { 2584 .gdscr = 0xb004, 2585 .en_rest_wait_val = 0x2, 2586 .en_few_wait_val = 0x2, 2587 .clk_dis_wait_val = 0xf, 2588 .pd = { 2589 .name = "ife_1_gdsc", 2590 }, 2591 .pwrsts = PWRSTS_OFF_ON, 2592 .parent = &titan_top_gdsc.pd, 2593 .flags = POLL_CFG_GDSCR, 2594 }; 2595 2596 static struct gdsc ife_2_gdsc = { 2597 .gdscr = 0xf004, 2598 .en_rest_wait_val = 0x2, 2599 .en_few_wait_val = 0x2, 2600 .clk_dis_wait_val = 0xf, 2601 .pd = { 2602 .name = "ife_2_gdsc", 2603 }, 2604 .pwrsts = PWRSTS_OFF_ON, 2605 .parent = &titan_top_gdsc.pd, 2606 .flags = POLL_CFG_GDSCR, 2607 }; 2608 2609 static struct gdsc ife_3_gdsc = { 2610 .gdscr = 0xf070, 2611 .en_rest_wait_val = 0x2, 2612 .en_few_wait_val = 0x2, 2613 .clk_dis_wait_val = 0xf, 2614 .pd = { 2615 .name = "ife_3_gdsc", 2616 }, 2617 .pwrsts = PWRSTS_OFF_ON, 2618 .parent = &titan_top_gdsc.pd, 2619 .flags = POLL_CFG_GDSCR, 2620 }; 2621 2622 static struct gdsc ipe_0_gdsc = { 2623 .gdscr = 0x8004, 2624 .en_rest_wait_val = 0x2, 2625 .en_few_wait_val = 0x2, 2626 .clk_dis_wait_val = 0xf, 2627 .pd = { 2628 .name = "ipe_0_gdsc", 2629 }, 2630 .pwrsts = PWRSTS_OFF_ON, 2631 .parent = &titan_top_gdsc.pd, 2632 .flags = POLL_CFG_GDSCR, 2633 }; 2634 2635 static struct gdsc ipe_1_gdsc = { 2636 .gdscr = 0x9004, 2637 .en_rest_wait_val = 0x2, 2638 .en_few_wait_val = 0x2, 2639 .clk_dis_wait_val = 0xf, 2640 .pd = { 2641 .name = "ipe_1_gdsc", 2642 }, 2643 .pwrsts = PWRSTS_OFF_ON, 2644 .parent = &titan_top_gdsc.pd, 2645 .flags = POLL_CFG_GDSCR, 2646 }; 2647 2648 static struct clk_regmap *cam_cc_sc8180x_clocks[] = { 2649 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, 2650 [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr, 2651 [CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr, 2652 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, 2653 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, 2654 [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr, 2655 [CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr, 2656 [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, 2657 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, 2658 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, 2659 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, 2660 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, 2661 [CAM_CC_CCI_2_CLK] = &cam_cc_cci_2_clk.clkr, 2662 [CAM_CC_CCI_2_CLK_SRC] = &cam_cc_cci_2_clk_src.clkr, 2663 [CAM_CC_CCI_3_CLK] = &cam_cc_cci_3_clk.clkr, 2664 [CAM_CC_CCI_3_CLK_SRC] = &cam_cc_cci_3_clk_src.clkr, 2665 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 2666 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 2667 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 2668 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 2669 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 2670 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 2671 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 2672 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 2673 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 2674 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 2675 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 2676 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 2677 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 2678 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 2679 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 2680 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 2681 [CAM_CC_FD_CORE_CLK] = &cam_cc_fd_core_clk.clkr, 2682 [CAM_CC_FD_CORE_CLK_SRC] = &cam_cc_fd_core_clk_src.clkr, 2683 [CAM_CC_FD_CORE_UAR_CLK] = &cam_cc_fd_core_uar_clk.clkr, 2684 [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr, 2685 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 2686 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 2687 [CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr, 2688 [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, 2689 [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, 2690 [CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr, 2691 [CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr, 2692 [CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr, 2693 [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, 2694 [CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr, 2695 [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, 2696 [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, 2697 [CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr, 2698 [CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr, 2699 [CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr, 2700 [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, 2701 [CAM_CC_IFE_2_AXI_CLK] = &cam_cc_ife_2_axi_clk.clkr, 2702 [CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr, 2703 [CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr, 2704 [CAM_CC_IFE_2_CPHY_RX_CLK] = &cam_cc_ife_2_cphy_rx_clk.clkr, 2705 [CAM_CC_IFE_2_CSID_CLK] = &cam_cc_ife_2_csid_clk.clkr, 2706 [CAM_CC_IFE_2_CSID_CLK_SRC] = &cam_cc_ife_2_csid_clk_src.clkr, 2707 [CAM_CC_IFE_2_DSP_CLK] = &cam_cc_ife_2_dsp_clk.clkr, 2708 [CAM_CC_IFE_3_AXI_CLK] = &cam_cc_ife_3_axi_clk.clkr, 2709 [CAM_CC_IFE_3_CLK] = &cam_cc_ife_3_clk.clkr, 2710 [CAM_CC_IFE_3_CLK_SRC] = &cam_cc_ife_3_clk_src.clkr, 2711 [CAM_CC_IFE_3_CPHY_RX_CLK] = &cam_cc_ife_3_cphy_rx_clk.clkr, 2712 [CAM_CC_IFE_3_CSID_CLK] = &cam_cc_ife_3_csid_clk.clkr, 2713 [CAM_CC_IFE_3_CSID_CLK_SRC] = &cam_cc_ife_3_csid_clk_src.clkr, 2714 [CAM_CC_IFE_3_DSP_CLK] = &cam_cc_ife_3_dsp_clk.clkr, 2715 [CAM_CC_IFE_LITE_0_CLK] = &cam_cc_ife_lite_0_clk.clkr, 2716 [CAM_CC_IFE_LITE_0_CLK_SRC] = &cam_cc_ife_lite_0_clk_src.clkr, 2717 [CAM_CC_IFE_LITE_0_CPHY_RX_CLK] = &cam_cc_ife_lite_0_cphy_rx_clk.clkr, 2718 [CAM_CC_IFE_LITE_0_CSID_CLK] = &cam_cc_ife_lite_0_csid_clk.clkr, 2719 [CAM_CC_IFE_LITE_0_CSID_CLK_SRC] = &cam_cc_ife_lite_0_csid_clk_src.clkr, 2720 [CAM_CC_IFE_LITE_1_CLK] = &cam_cc_ife_lite_1_clk.clkr, 2721 [CAM_CC_IFE_LITE_1_CLK_SRC] = &cam_cc_ife_lite_1_clk_src.clkr, 2722 [CAM_CC_IFE_LITE_1_CPHY_RX_CLK] = &cam_cc_ife_lite_1_cphy_rx_clk.clkr, 2723 [CAM_CC_IFE_LITE_1_CSID_CLK] = &cam_cc_ife_lite_1_csid_clk.clkr, 2724 [CAM_CC_IFE_LITE_1_CSID_CLK_SRC] = &cam_cc_ife_lite_1_csid_clk_src.clkr, 2725 [CAM_CC_IFE_LITE_2_CLK] = &cam_cc_ife_lite_2_clk.clkr, 2726 [CAM_CC_IFE_LITE_2_CLK_SRC] = &cam_cc_ife_lite_2_clk_src.clkr, 2727 [CAM_CC_IFE_LITE_2_CPHY_RX_CLK] = &cam_cc_ife_lite_2_cphy_rx_clk.clkr, 2728 [CAM_CC_IFE_LITE_2_CSID_CLK] = &cam_cc_ife_lite_2_csid_clk.clkr, 2729 [CAM_CC_IFE_LITE_2_CSID_CLK_SRC] = &cam_cc_ife_lite_2_csid_clk_src.clkr, 2730 [CAM_CC_IFE_LITE_3_CLK] = &cam_cc_ife_lite_3_clk.clkr, 2731 [CAM_CC_IFE_LITE_3_CLK_SRC] = &cam_cc_ife_lite_3_clk_src.clkr, 2732 [CAM_CC_IFE_LITE_3_CPHY_RX_CLK] = &cam_cc_ife_lite_3_cphy_rx_clk.clkr, 2733 [CAM_CC_IFE_LITE_3_CSID_CLK] = &cam_cc_ife_lite_3_csid_clk.clkr, 2734 [CAM_CC_IFE_LITE_3_CSID_CLK_SRC] = &cam_cc_ife_lite_3_csid_clk_src.clkr, 2735 [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr, 2736 [CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr, 2737 [CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr, 2738 [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr, 2739 [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr, 2740 [CAM_CC_IPE_1_AHB_CLK] = &cam_cc_ipe_1_ahb_clk.clkr, 2741 [CAM_CC_IPE_1_AREG_CLK] = &cam_cc_ipe_1_areg_clk.clkr, 2742 [CAM_CC_IPE_1_AXI_CLK] = &cam_cc_ipe_1_axi_clk.clkr, 2743 [CAM_CC_IPE_1_CLK] = &cam_cc_ipe_1_clk.clkr, 2744 [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, 2745 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, 2746 [CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr, 2747 [CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr, 2748 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 2749 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 2750 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 2751 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 2752 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 2753 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 2754 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 2755 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 2756 [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, 2757 [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, 2758 [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr, 2759 [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr, 2760 [CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr, 2761 [CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr, 2762 [CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr, 2763 [CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr, 2764 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 2765 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, 2766 [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, 2767 [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 2768 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 2769 [CAM_CC_PLL2_OUT_MAIN] = &cam_cc_pll2_out_main.clkr, 2770 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 2771 [CAM_CC_PLL4] = &cam_cc_pll4.clkr, 2772 [CAM_CC_PLL5] = &cam_cc_pll5.clkr, 2773 [CAM_CC_PLL6] = &cam_cc_pll6.clkr, 2774 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 2775 [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, 2776 }; 2777 2778 static struct gdsc *cam_cc_sc8180x_gdscs[] = { 2779 [BPS_GDSC] = &bps_gdsc, 2780 [IFE_0_GDSC] = &ife_0_gdsc, 2781 [IFE_1_GDSC] = &ife_1_gdsc, 2782 [IFE_2_GDSC] = &ife_2_gdsc, 2783 [IFE_3_GDSC] = &ife_3_gdsc, 2784 [IPE_0_GDSC] = &ipe_0_gdsc, 2785 [IPE_1_GDSC] = &ipe_1_gdsc, 2786 [TITAN_TOP_GDSC] = &titan_top_gdsc, 2787 }; 2788 2789 static const struct qcom_reset_map cam_cc_sc8180x_resets[] = { 2790 [CAM_CC_BPS_BCR] = { 0x7000 }, 2791 [CAM_CC_CAMNOC_BCR] = { 0xc16c }, 2792 [CAM_CC_CCI_BCR] = { 0xc104 }, 2793 [CAM_CC_CPAS_BCR] = { 0xc164 }, 2794 [CAM_CC_CSI0PHY_BCR] = { 0x6000 }, 2795 [CAM_CC_CSI1PHY_BCR] = { 0x6024 }, 2796 [CAM_CC_CSI2PHY_BCR] = { 0x6048 }, 2797 [CAM_CC_CSI3PHY_BCR] = { 0x606c }, 2798 [CAM_CC_FD_BCR] = { 0xc0dc }, 2799 [CAM_CC_ICP_BCR] = { 0xc0b4 }, 2800 [CAM_CC_IFE_0_BCR] = { 0xa000 }, 2801 [CAM_CC_IFE_1_BCR] = { 0xb000 }, 2802 [CAM_CC_IFE_2_BCR] = { 0xf000 }, 2803 [CAM_CC_IFE_3_BCR] = { 0xf06c }, 2804 [CAM_CC_IFE_LITE_0_BCR] = { 0xc000 }, 2805 [CAM_CC_IFE_LITE_1_BCR] = { 0xc044 }, 2806 [CAM_CC_IFE_LITE_2_BCR] = { 0xc23c }, 2807 [CAM_CC_IFE_LITE_3_BCR] = { 0xc280 }, 2808 [CAM_CC_IPE_0_BCR] = { 0x8000 }, 2809 [CAM_CC_IPE_1_BCR] = { 0x9000 }, 2810 [CAM_CC_JPEG_BCR] = { 0xc088 }, 2811 [CAM_CC_LRME_BCR] = { 0xc140 }, 2812 [CAM_CC_MCLK0_BCR] = { 0x5000 }, 2813 [CAM_CC_MCLK1_BCR] = { 0x5020 }, 2814 [CAM_CC_MCLK2_BCR] = { 0x5040 }, 2815 [CAM_CC_MCLK3_BCR] = { 0x5060 }, 2816 [CAM_CC_MCLK4_BCR] = { 0x5080 }, 2817 [CAM_CC_MCLK5_BCR] = { 0x50a0 }, 2818 [CAM_CC_MCLK6_BCR] = { 0x50c0 }, 2819 [CAM_CC_MCLK7_BCR] = { 0x50e0 }, 2820 }; 2821 2822 static struct clk_alpha_pll *cam_cc_sc8180x_plls[] = { 2823 &cam_cc_pll0, 2824 &cam_cc_pll1, 2825 &cam_cc_pll2, 2826 &cam_cc_pll3, 2827 &cam_cc_pll4, 2828 &cam_cc_pll5, 2829 &cam_cc_pll6, 2830 }; 2831 2832 static const u32 cam_cc_sc8180x_critical_cbcrs[] = { 2833 0xc1e4, /* CAM_CC_GDSC_CLK */ 2834 0xc200, /* CAM_CC_SLEEP_CLK */ 2835 }; 2836 2837 static const struct regmap_config cam_cc_sc8180x_regmap_config = { 2838 .reg_bits = 32, 2839 .reg_stride = 4, 2840 .val_bits = 32, 2841 .max_register = 0xf0d4, 2842 .fast_io = true, 2843 }; 2844 2845 static const struct qcom_cc_driver_data cam_cc_sc8180x_driver_data = { 2846 .alpha_plls = cam_cc_sc8180x_plls, 2847 .num_alpha_plls = ARRAY_SIZE(cam_cc_sc8180x_plls), 2848 .clk_cbcrs = cam_cc_sc8180x_critical_cbcrs, 2849 .num_clk_cbcrs = ARRAY_SIZE(cam_cc_sc8180x_critical_cbcrs), 2850 }; 2851 2852 static const struct qcom_cc_desc cam_cc_sc8180x_desc = { 2853 .config = &cam_cc_sc8180x_regmap_config, 2854 .clks = cam_cc_sc8180x_clocks, 2855 .num_clks = ARRAY_SIZE(cam_cc_sc8180x_clocks), 2856 .resets = cam_cc_sc8180x_resets, 2857 .num_resets = ARRAY_SIZE(cam_cc_sc8180x_resets), 2858 .gdscs = cam_cc_sc8180x_gdscs, 2859 .num_gdscs = ARRAY_SIZE(cam_cc_sc8180x_gdscs), 2860 .use_rpm = true, 2861 .driver_data = &cam_cc_sc8180x_driver_data, 2862 }; 2863 2864 static const struct of_device_id cam_cc_sc8180x_match_table[] = { 2865 { .compatible = "qcom,sc8180x-camcc" }, 2866 { } 2867 }; 2868 MODULE_DEVICE_TABLE(of, cam_cc_sc8180x_match_table); 2869 2870 static int cam_cc_sc8180x_probe(struct platform_device *pdev) 2871 { 2872 return qcom_cc_probe(pdev, &cam_cc_sc8180x_desc); 2873 } 2874 2875 static struct platform_driver cam_cc_sc8180x_driver = { 2876 .probe = cam_cc_sc8180x_probe, 2877 .driver = { 2878 .name = "camcc-sc8180x", 2879 .of_match_table = cam_cc_sc8180x_match_table, 2880 }, 2881 }; 2882 2883 module_platform_driver(cam_cc_sc8180x_driver); 2884 2885 MODULE_DESCRIPTION("QTI CAMCC SC8180X Driver"); 2886 MODULE_LICENSE("GPL"); 2887