1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/err.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/pm_clock.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/regmap.h> 13 14 #include <dt-bindings/clock/qcom,camcc-sc7180.h> 15 16 #include "clk-alpha-pll.h" 17 #include "clk-branch.h" 18 #include "clk-rcg.h" 19 #include "clk-regmap.h" 20 #include "common.h" 21 #include "gdsc.h" 22 #include "reset.h" 23 24 enum { 25 P_BI_TCXO, 26 P_CAM_CC_PLL0_OUT_EVEN, 27 P_CAM_CC_PLL1_OUT_EVEN, 28 P_CAM_CC_PLL2_OUT_AUX, 29 P_CAM_CC_PLL2_OUT_EARLY, 30 P_CAM_CC_PLL3_OUT_MAIN, 31 }; 32 33 static const struct pll_vco agera_vco[] = { 34 { 600000000, 3300000000UL, 0 }, 35 }; 36 37 static const struct pll_vco fabia_vco[] = { 38 { 249600000, 2000000000UL, 0 }, 39 }; 40 41 /* 600MHz configuration */ 42 static const struct alpha_pll_config cam_cc_pll0_config = { 43 .l = 0x1f, 44 .alpha = 0x4000, 45 .config_ctl_val = 0x20485699, 46 .config_ctl_hi_val = 0x00002067, 47 .test_ctl_val = 0x40000000, 48 .user_ctl_hi_val = 0x00004805, 49 .user_ctl_val = 0x00000001, 50 }; 51 52 static struct clk_alpha_pll cam_cc_pll0 = { 53 .offset = 0x0, 54 .vco_table = fabia_vco, 55 .num_vco = ARRAY_SIZE(fabia_vco), 56 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 57 .clkr = { 58 .hw.init = &(struct clk_init_data){ 59 .name = "cam_cc_pll0", 60 .parent_data = &(const struct clk_parent_data){ 61 .fw_name = "bi_tcxo", 62 }, 63 .num_parents = 1, 64 .ops = &clk_alpha_pll_fabia_ops, 65 }, 66 }, 67 }; 68 69 /* 860MHz configuration */ 70 static const struct alpha_pll_config cam_cc_pll1_config = { 71 .l = 0x2a, 72 .alpha = 0x1555, 73 .config_ctl_val = 0x20485699, 74 .config_ctl_hi_val = 0x00002067, 75 .test_ctl_val = 0x40000000, 76 .user_ctl_hi_val = 0x00004805, 77 }; 78 79 static struct clk_alpha_pll cam_cc_pll1 = { 80 .offset = 0x1000, 81 .vco_table = fabia_vco, 82 .num_vco = ARRAY_SIZE(fabia_vco), 83 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 84 .clkr = { 85 .hw.init = &(struct clk_init_data){ 86 .name = "cam_cc_pll1", 87 .parent_data = &(const struct clk_parent_data){ 88 .fw_name = "bi_tcxo", 89 }, 90 .num_parents = 1, 91 .ops = &clk_alpha_pll_fabia_ops, 92 }, 93 }, 94 }; 95 96 /* 1920MHz configuration */ 97 static const struct alpha_pll_config cam_cc_pll2_config = { 98 .l = 0x64, 99 .config_ctl_val = 0x20000800, 100 .config_ctl_hi_val = 0x400003D2, 101 .test_ctl_val = 0x04000400, 102 .test_ctl_hi_val = 0x00004000, 103 .user_ctl_val = 0x0000030F, 104 }; 105 106 static struct clk_alpha_pll cam_cc_pll2 = { 107 .offset = 0x2000, 108 .vco_table = agera_vco, 109 .num_vco = ARRAY_SIZE(agera_vco), 110 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA], 111 .clkr = { 112 .hw.init = &(struct clk_init_data){ 113 .name = "cam_cc_pll2", 114 .parent_data = &(const struct clk_parent_data){ 115 .fw_name = "bi_tcxo", 116 }, 117 .num_parents = 1, 118 .ops = &clk_alpha_pll_agera_ops, 119 }, 120 }, 121 }; 122 123 static struct clk_fixed_factor cam_cc_pll2_out_early = { 124 .mult = 1, 125 .div = 2, 126 .hw.init = &(struct clk_init_data){ 127 .name = "cam_cc_pll2_out_early", 128 .parent_hws = (const struct clk_hw*[]){ 129 &cam_cc_pll2.clkr.hw, 130 }, 131 .num_parents = 1, 132 .ops = &clk_fixed_factor_ops, 133 }, 134 }; 135 136 static const struct clk_div_table post_div_table_cam_cc_pll2_out_aux[] = { 137 { 0x3, 4 }, 138 { } 139 }; 140 141 static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux = { 142 .offset = 0x2000, 143 .post_div_shift = 8, 144 .post_div_table = post_div_table_cam_cc_pll2_out_aux, 145 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_aux), 146 .width = 2, 147 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA], 148 .clkr.hw.init = &(struct clk_init_data){ 149 .name = "cam_cc_pll2_out_aux", 150 .parent_hws = (const struct clk_hw*[]){ 151 &cam_cc_pll2.clkr.hw, 152 }, 153 .num_parents = 1, 154 .flags = CLK_SET_RATE_PARENT, 155 .ops = &clk_alpha_pll_postdiv_ops, 156 }, 157 }; 158 159 /* 1080MHz configuration */ 160 static const struct alpha_pll_config cam_cc_pll3_config = { 161 .l = 0x38, 162 .alpha = 0x4000, 163 .config_ctl_val = 0x20485699, 164 .config_ctl_hi_val = 0x00002067, 165 .test_ctl_val = 0x40000000, 166 .user_ctl_hi_val = 0x00004805, 167 }; 168 169 static struct clk_alpha_pll cam_cc_pll3 = { 170 .offset = 0x3000, 171 .vco_table = fabia_vco, 172 .num_vco = ARRAY_SIZE(fabia_vco), 173 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 174 .clkr = { 175 .hw.init = &(struct clk_init_data){ 176 .name = "cam_cc_pll3", 177 .parent_data = &(const struct clk_parent_data){ 178 .fw_name = "bi_tcxo", 179 }, 180 .num_parents = 1, 181 .ops = &clk_alpha_pll_fabia_ops, 182 }, 183 }, 184 }; 185 186 static const struct parent_map cam_cc_parent_map_0[] = { 187 { P_BI_TCXO, 0 }, 188 { P_CAM_CC_PLL1_OUT_EVEN, 2 }, 189 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 190 }; 191 192 static const struct clk_parent_data cam_cc_parent_data_0[] = { 193 { .fw_name = "bi_tcxo" }, 194 { .hw = &cam_cc_pll1.clkr.hw }, 195 { .hw = &cam_cc_pll0.clkr.hw }, 196 }; 197 198 static const struct parent_map cam_cc_parent_map_1[] = { 199 { P_BI_TCXO, 0 }, 200 { P_CAM_CC_PLL2_OUT_AUX, 1 }, 201 }; 202 203 static const struct clk_parent_data cam_cc_parent_data_1[] = { 204 { .fw_name = "bi_tcxo" }, 205 { .hw = &cam_cc_pll2_out_aux.clkr.hw }, 206 }; 207 208 static const struct parent_map cam_cc_parent_map_2[] = { 209 { P_BI_TCXO, 0 }, 210 { P_CAM_CC_PLL2_OUT_EARLY, 4 }, 211 { P_CAM_CC_PLL3_OUT_MAIN, 5 }, 212 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 213 }; 214 215 static const struct clk_parent_data cam_cc_parent_data_2[] = { 216 { .fw_name = "bi_tcxo" }, 217 { .hw = &cam_cc_pll2_out_early.hw }, 218 { .hw = &cam_cc_pll3.clkr.hw }, 219 { .hw = &cam_cc_pll0.clkr.hw }, 220 }; 221 222 static const struct parent_map cam_cc_parent_map_3[] = { 223 { P_BI_TCXO, 0 }, 224 { P_CAM_CC_PLL1_OUT_EVEN, 2 }, 225 { P_CAM_CC_PLL2_OUT_EARLY, 4 }, 226 { P_CAM_CC_PLL3_OUT_MAIN, 5 }, 227 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 228 }; 229 230 static const struct clk_parent_data cam_cc_parent_data_3[] = { 231 { .fw_name = "bi_tcxo" }, 232 { .hw = &cam_cc_pll1.clkr.hw }, 233 { .hw = &cam_cc_pll2_out_early.hw }, 234 { .hw = &cam_cc_pll3.clkr.hw }, 235 { .hw = &cam_cc_pll0.clkr.hw }, 236 }; 237 238 static const struct parent_map cam_cc_parent_map_4[] = { 239 { P_BI_TCXO, 0 }, 240 { P_CAM_CC_PLL3_OUT_MAIN, 5 }, 241 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 242 }; 243 244 static const struct clk_parent_data cam_cc_parent_data_4[] = { 245 { .fw_name = "bi_tcxo" }, 246 { .hw = &cam_cc_pll3.clkr.hw }, 247 { .hw = &cam_cc_pll0.clkr.hw }, 248 }; 249 250 static const struct parent_map cam_cc_parent_map_5[] = { 251 { P_BI_TCXO, 0 }, 252 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 253 }; 254 255 static const struct clk_parent_data cam_cc_parent_data_5[] = { 256 { .fw_name = "bi_tcxo" }, 257 { .hw = &cam_cc_pll0.clkr.hw }, 258 }; 259 260 static const struct parent_map cam_cc_parent_map_6[] = { 261 { P_BI_TCXO, 0 }, 262 { P_CAM_CC_PLL1_OUT_EVEN, 2 }, 263 { P_CAM_CC_PLL3_OUT_MAIN, 5 }, 264 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 265 }; 266 267 static const struct clk_parent_data cam_cc_parent_data_6[] = { 268 { .fw_name = "bi_tcxo" }, 269 { .hw = &cam_cc_pll1.clkr.hw }, 270 { .hw = &cam_cc_pll3.clkr.hw }, 271 { .hw = &cam_cc_pll0.clkr.hw }, 272 }; 273 274 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { 275 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 276 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 277 F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), 278 F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), 279 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 280 { } 281 }; 282 283 static struct clk_rcg2 cam_cc_bps_clk_src = { 284 .cmd_rcgr = 0x6010, 285 .mnd_width = 0, 286 .hid_width = 5, 287 .parent_map = cam_cc_parent_map_2, 288 .freq_tbl = ftbl_cam_cc_bps_clk_src, 289 .clkr.hw.init = &(struct clk_init_data){ 290 .name = "cam_cc_bps_clk_src", 291 .parent_data = cam_cc_parent_data_2, 292 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 293 .ops = &clk_rcg2_shared_ops, 294 }, 295 }; 296 297 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { 298 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 299 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0), 300 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 301 { } 302 }; 303 304 static struct clk_rcg2 cam_cc_cci_0_clk_src = { 305 .cmd_rcgr = 0xb0d8, 306 .mnd_width = 8, 307 .hid_width = 5, 308 .parent_map = cam_cc_parent_map_5, 309 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 310 .clkr.hw.init = &(struct clk_init_data){ 311 .name = "cam_cc_cci_0_clk_src", 312 .parent_data = cam_cc_parent_data_5, 313 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 314 .ops = &clk_rcg2_shared_ops, 315 }, 316 }; 317 318 static struct clk_rcg2 cam_cc_cci_1_clk_src = { 319 .cmd_rcgr = 0xb14c, 320 .mnd_width = 8, 321 .hid_width = 5, 322 .parent_map = cam_cc_parent_map_5, 323 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 324 .clkr.hw.init = &(struct clk_init_data){ 325 .name = "cam_cc_cci_1_clk_src", 326 .parent_data = cam_cc_parent_data_5, 327 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 328 .ops = &clk_rcg2_shared_ops, 329 }, 330 }; 331 332 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 333 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), 334 F(270000000, P_CAM_CC_PLL3_OUT_MAIN, 4, 0, 0), 335 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 336 { } 337 }; 338 339 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 340 .cmd_rcgr = 0x9064, 341 .mnd_width = 0, 342 .hid_width = 5, 343 .parent_map = cam_cc_parent_map_3, 344 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 345 .clkr.hw.init = &(struct clk_init_data){ 346 .name = "cam_cc_cphy_rx_clk_src", 347 .parent_data = cam_cc_parent_data_3, 348 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 349 .ops = &clk_rcg2_shared_ops, 350 }, 351 }; 352 353 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 354 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 355 { } 356 }; 357 358 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 359 .cmd_rcgr = 0x5004, 360 .mnd_width = 0, 361 .hid_width = 5, 362 .parent_map = cam_cc_parent_map_0, 363 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 364 .clkr.hw.init = &(struct clk_init_data){ 365 .name = "cam_cc_csi0phytimer_clk_src", 366 .parent_data = cam_cc_parent_data_0, 367 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 368 .ops = &clk_rcg2_shared_ops, 369 }, 370 }; 371 372 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 373 .cmd_rcgr = 0x5028, 374 .mnd_width = 0, 375 .hid_width = 5, 376 .parent_map = cam_cc_parent_map_0, 377 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 378 .clkr.hw.init = &(struct clk_init_data){ 379 .name = "cam_cc_csi1phytimer_clk_src", 380 .parent_data = cam_cc_parent_data_0, 381 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 382 .ops = &clk_rcg2_shared_ops, 383 }, 384 }; 385 386 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 387 .cmd_rcgr = 0x504c, 388 .mnd_width = 0, 389 .hid_width = 5, 390 .parent_map = cam_cc_parent_map_0, 391 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 392 .clkr.hw.init = &(struct clk_init_data){ 393 .name = "cam_cc_csi2phytimer_clk_src", 394 .parent_data = cam_cc_parent_data_0, 395 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 396 .ops = &clk_rcg2_shared_ops, 397 }, 398 }; 399 400 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 401 .cmd_rcgr = 0x5070, 402 .mnd_width = 0, 403 .hid_width = 5, 404 .parent_map = cam_cc_parent_map_0, 405 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 406 .clkr.hw.init = &(struct clk_init_data){ 407 .name = "cam_cc_csi3phytimer_clk_src", 408 .parent_data = cam_cc_parent_data_0, 409 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 410 .ops = &clk_rcg2_shared_ops, 411 }, 412 }; 413 414 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 415 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 416 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 417 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 418 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0), 419 { } 420 }; 421 422 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 423 .cmd_rcgr = 0x603c, 424 .mnd_width = 0, 425 .hid_width = 5, 426 .parent_map = cam_cc_parent_map_0, 427 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 428 .clkr.hw.init = &(struct clk_init_data){ 429 .name = "cam_cc_fast_ahb_clk_src", 430 .parent_data = cam_cc_parent_data_0, 431 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 432 .ops = &clk_rcg2_shared_ops, 433 }, 434 }; 435 436 static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 437 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), 438 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 439 F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), 440 F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), 441 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 442 { } 443 }; 444 445 static struct clk_rcg2 cam_cc_icp_clk_src = { 446 .cmd_rcgr = 0xb088, 447 .mnd_width = 0, 448 .hid_width = 5, 449 .parent_map = cam_cc_parent_map_2, 450 .freq_tbl = ftbl_cam_cc_icp_clk_src, 451 .clkr.hw.init = &(struct clk_init_data){ 452 .name = "cam_cc_icp_clk_src", 453 .parent_data = cam_cc_parent_data_2, 454 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 455 .ops = &clk_rcg2_shared_ops, 456 }, 457 }; 458 459 static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { 460 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), 461 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 462 F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), 463 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 464 { } 465 }; 466 467 static struct clk_rcg2 cam_cc_ife_0_clk_src = { 468 .cmd_rcgr = 0x9010, 469 .mnd_width = 0, 470 .hid_width = 5, 471 .parent_map = cam_cc_parent_map_4, 472 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 473 .clkr.hw.init = &(struct clk_init_data){ 474 .name = "cam_cc_ife_0_clk_src", 475 .parent_data = cam_cc_parent_data_4, 476 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 477 .ops = &clk_rcg2_shared_ops, 478 }, 479 }; 480 481 static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = { 482 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), 483 F(270000000, P_CAM_CC_PLL3_OUT_MAIN, 4, 0, 0), 484 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 485 F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), 486 { } 487 }; 488 489 static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { 490 .cmd_rcgr = 0x903c, 491 .mnd_width = 0, 492 .hid_width = 5, 493 .parent_map = cam_cc_parent_map_3, 494 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 495 .clkr.hw.init = &(struct clk_init_data){ 496 .name = "cam_cc_ife_0_csid_clk_src", 497 .parent_data = cam_cc_parent_data_3, 498 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 499 .ops = &clk_rcg2_shared_ops, 500 }, 501 }; 502 503 static struct clk_rcg2 cam_cc_ife_1_clk_src = { 504 .cmd_rcgr = 0xa010, 505 .mnd_width = 0, 506 .hid_width = 5, 507 .parent_map = cam_cc_parent_map_4, 508 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 509 .clkr.hw.init = &(struct clk_init_data){ 510 .name = "cam_cc_ife_1_clk_src", 511 .parent_data = cam_cc_parent_data_4, 512 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 513 .ops = &clk_rcg2_shared_ops, 514 }, 515 }; 516 517 static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { 518 .cmd_rcgr = 0xa034, 519 .mnd_width = 0, 520 .hid_width = 5, 521 .parent_map = cam_cc_parent_map_3, 522 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 523 .clkr.hw.init = &(struct clk_init_data){ 524 .name = "cam_cc_ife_1_csid_clk_src", 525 .parent_data = cam_cc_parent_data_3, 526 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 527 .ops = &clk_rcg2_shared_ops, 528 }, 529 }; 530 531 static struct clk_rcg2 cam_cc_ife_lite_clk_src = { 532 .cmd_rcgr = 0xb004, 533 .mnd_width = 0, 534 .hid_width = 5, 535 .parent_map = cam_cc_parent_map_4, 536 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 537 .clkr.hw.init = &(struct clk_init_data){ 538 .name = "cam_cc_ife_lite_clk_src", 539 .parent_data = cam_cc_parent_data_4, 540 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 541 .flags = CLK_SET_RATE_PARENT, 542 .ops = &clk_rcg2_shared_ops, 543 }, 544 }; 545 546 static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { 547 .cmd_rcgr = 0xb024, 548 .mnd_width = 0, 549 .hid_width = 5, 550 .parent_map = cam_cc_parent_map_3, 551 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 552 .clkr.hw.init = &(struct clk_init_data){ 553 .name = "cam_cc_ife_lite_csid_clk_src", 554 .parent_data = cam_cc_parent_data_3, 555 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 556 .ops = &clk_rcg2_shared_ops, 557 }, 558 }; 559 560 static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = { 561 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), 562 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 563 F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), 564 F(540000000, P_CAM_CC_PLL3_OUT_MAIN, 2, 0, 0), 565 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 566 { } 567 }; 568 569 static struct clk_rcg2 cam_cc_ipe_0_clk_src = { 570 .cmd_rcgr = 0x7010, 571 .mnd_width = 0, 572 .hid_width = 5, 573 .parent_map = cam_cc_parent_map_2, 574 .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, 575 .clkr.hw.init = &(struct clk_init_data){ 576 .name = "cam_cc_ipe_0_clk_src", 577 .parent_data = cam_cc_parent_data_2, 578 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 579 .ops = &clk_rcg2_shared_ops, 580 }, 581 }; 582 583 static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = { 584 F(66666667, P_CAM_CC_PLL0_OUT_EVEN, 9, 0, 0), 585 F(133333333, P_CAM_CC_PLL0_OUT_EVEN, 4.5, 0, 0), 586 F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0), 587 F(320000000, P_CAM_CC_PLL2_OUT_EARLY, 3, 0, 0), 588 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 589 { } 590 }; 591 592 static struct clk_rcg2 cam_cc_jpeg_clk_src = { 593 .cmd_rcgr = 0xb04c, 594 .mnd_width = 0, 595 .hid_width = 5, 596 .parent_map = cam_cc_parent_map_2, 597 .freq_tbl = ftbl_cam_cc_jpeg_clk_src, 598 .clkr.hw.init = &(struct clk_init_data){ 599 .name = "cam_cc_jpeg_clk_src", 600 .parent_data = cam_cc_parent_data_2, 601 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 602 .ops = &clk_rcg2_shared_ops, 603 }, 604 }; 605 606 static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = { 607 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 608 F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0), 609 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 610 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0), 611 { } 612 }; 613 614 static struct clk_rcg2 cam_cc_lrme_clk_src = { 615 .cmd_rcgr = 0xb0f8, 616 .mnd_width = 0, 617 .hid_width = 5, 618 .parent_map = cam_cc_parent_map_6, 619 .freq_tbl = ftbl_cam_cc_lrme_clk_src, 620 .clkr.hw.init = &(struct clk_init_data){ 621 .name = "cam_cc_lrme_clk_src", 622 .parent_data = cam_cc_parent_data_6, 623 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), 624 .ops = &clk_rcg2_shared_ops, 625 }, 626 }; 627 628 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 629 F(19200000, P_BI_TCXO, 1, 0, 0), 630 F(24000000, P_CAM_CC_PLL2_OUT_AUX, 10, 1, 2), 631 F(64000000, P_CAM_CC_PLL2_OUT_AUX, 7.5, 0, 0), 632 { } 633 }; 634 635 static struct clk_rcg2 cam_cc_mclk0_clk_src = { 636 .cmd_rcgr = 0x4004, 637 .mnd_width = 8, 638 .hid_width = 5, 639 .parent_map = cam_cc_parent_map_1, 640 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 641 .clkr.hw.init = &(struct clk_init_data){ 642 .name = "cam_cc_mclk0_clk_src", 643 .parent_data = cam_cc_parent_data_1, 644 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 645 .ops = &clk_rcg2_shared_ops, 646 }, 647 }; 648 649 static struct clk_rcg2 cam_cc_mclk1_clk_src = { 650 .cmd_rcgr = 0x4024, 651 .mnd_width = 8, 652 .hid_width = 5, 653 .parent_map = cam_cc_parent_map_1, 654 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 655 .clkr.hw.init = &(struct clk_init_data){ 656 .name = "cam_cc_mclk1_clk_src", 657 .parent_data = cam_cc_parent_data_1, 658 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 659 .ops = &clk_rcg2_shared_ops, 660 }, 661 }; 662 663 static struct clk_rcg2 cam_cc_mclk2_clk_src = { 664 .cmd_rcgr = 0x4044, 665 .mnd_width = 8, 666 .hid_width = 5, 667 .parent_map = cam_cc_parent_map_1, 668 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 669 .clkr.hw.init = &(struct clk_init_data){ 670 .name = "cam_cc_mclk2_clk_src", 671 .parent_data = cam_cc_parent_data_1, 672 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 673 .ops = &clk_rcg2_shared_ops, 674 }, 675 }; 676 677 static struct clk_rcg2 cam_cc_mclk3_clk_src = { 678 .cmd_rcgr = 0x4064, 679 .mnd_width = 8, 680 .hid_width = 5, 681 .parent_map = cam_cc_parent_map_1, 682 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 683 .clkr.hw.init = &(struct clk_init_data){ 684 .name = "cam_cc_mclk3_clk_src", 685 .parent_data = cam_cc_parent_data_1, 686 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 687 .ops = &clk_rcg2_shared_ops, 688 }, 689 }; 690 691 static struct clk_rcg2 cam_cc_mclk4_clk_src = { 692 .cmd_rcgr = 0x4084, 693 .mnd_width = 8, 694 .hid_width = 5, 695 .parent_map = cam_cc_parent_map_1, 696 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 697 .clkr.hw.init = &(struct clk_init_data){ 698 .name = "cam_cc_mclk4_clk_src", 699 .parent_data = cam_cc_parent_data_1, 700 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 701 .ops = &clk_rcg2_shared_ops, 702 }, 703 }; 704 705 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 706 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 707 { } 708 }; 709 710 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 711 .cmd_rcgr = 0x6058, 712 .mnd_width = 0, 713 .hid_width = 5, 714 .parent_map = cam_cc_parent_map_0, 715 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 716 .clkr.hw.init = &(struct clk_init_data){ 717 .name = "cam_cc_slow_ahb_clk_src", 718 .parent_data = cam_cc_parent_data_0, 719 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 720 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 721 .ops = &clk_rcg2_shared_ops, 722 }, 723 }; 724 725 static struct clk_branch cam_cc_bps_ahb_clk = { 726 .halt_reg = 0x6070, 727 .halt_check = BRANCH_HALT, 728 .clkr = { 729 .enable_reg = 0x6070, 730 .enable_mask = BIT(0), 731 .hw.init = &(struct clk_init_data){ 732 .name = "cam_cc_bps_ahb_clk", 733 .parent_hws = (const struct clk_hw*[]){ 734 &cam_cc_slow_ahb_clk_src.clkr.hw, 735 }, 736 .num_parents = 1, 737 .flags = CLK_SET_RATE_PARENT, 738 .ops = &clk_branch2_ops, 739 }, 740 }, 741 }; 742 743 static struct clk_branch cam_cc_bps_areg_clk = { 744 .halt_reg = 0x6054, 745 .halt_check = BRANCH_HALT, 746 .clkr = { 747 .enable_reg = 0x6054, 748 .enable_mask = BIT(0), 749 .hw.init = &(struct clk_init_data){ 750 .name = "cam_cc_bps_areg_clk", 751 .parent_hws = (const struct clk_hw*[]){ 752 &cam_cc_fast_ahb_clk_src.clkr.hw, 753 }, 754 .num_parents = 1, 755 .flags = CLK_SET_RATE_PARENT, 756 .ops = &clk_branch2_ops, 757 }, 758 }, 759 }; 760 761 static struct clk_branch cam_cc_bps_axi_clk = { 762 .halt_reg = 0x6038, 763 .halt_check = BRANCH_HALT, 764 .clkr = { 765 .enable_reg = 0x6038, 766 .enable_mask = BIT(0), 767 .hw.init = &(struct clk_init_data){ 768 .name = "cam_cc_bps_axi_clk", 769 .ops = &clk_branch2_ops, 770 }, 771 }, 772 }; 773 774 static struct clk_branch cam_cc_bps_clk = { 775 .halt_reg = 0x6028, 776 .halt_check = BRANCH_HALT, 777 .clkr = { 778 .enable_reg = 0x6028, 779 .enable_mask = BIT(0), 780 .hw.init = &(struct clk_init_data){ 781 .name = "cam_cc_bps_clk", 782 .parent_hws = (const struct clk_hw*[]){ 783 &cam_cc_bps_clk_src.clkr.hw, 784 }, 785 .num_parents = 1, 786 .flags = CLK_SET_RATE_PARENT, 787 .ops = &clk_branch2_ops, 788 }, 789 }, 790 }; 791 792 static struct clk_branch cam_cc_camnoc_axi_clk = { 793 .halt_reg = 0xb124, 794 .halt_check = BRANCH_HALT, 795 .clkr = { 796 .enable_reg = 0xb124, 797 .enable_mask = BIT(0), 798 .hw.init = &(struct clk_init_data){ 799 .name = "cam_cc_camnoc_axi_clk", 800 .ops = &clk_branch2_ops, 801 }, 802 }, 803 }; 804 805 static struct clk_branch cam_cc_cci_0_clk = { 806 .halt_reg = 0xb0f0, 807 .halt_check = BRANCH_HALT, 808 .clkr = { 809 .enable_reg = 0xb0f0, 810 .enable_mask = BIT(0), 811 .hw.init = &(struct clk_init_data){ 812 .name = "cam_cc_cci_0_clk", 813 .parent_hws = (const struct clk_hw*[]){ 814 &cam_cc_cci_0_clk_src.clkr.hw, 815 }, 816 .num_parents = 1, 817 .flags = CLK_SET_RATE_PARENT, 818 .ops = &clk_branch2_ops, 819 }, 820 }, 821 }; 822 823 static struct clk_branch cam_cc_cci_1_clk = { 824 .halt_reg = 0xb164, 825 .halt_check = BRANCH_HALT, 826 .clkr = { 827 .enable_reg = 0xb164, 828 .enable_mask = BIT(0), 829 .hw.init = &(struct clk_init_data){ 830 .name = "cam_cc_cci_1_clk", 831 .parent_hws = (const struct clk_hw*[]){ 832 &cam_cc_cci_1_clk_src.clkr.hw, 833 }, 834 .num_parents = 1, 835 .flags = CLK_SET_RATE_PARENT, 836 .ops = &clk_branch2_ops, 837 }, 838 }, 839 }; 840 841 static struct clk_branch cam_cc_core_ahb_clk = { 842 .halt_reg = 0xb144, 843 .halt_check = BRANCH_HALT_DELAY, 844 .clkr = { 845 .enable_reg = 0xb144, 846 .enable_mask = BIT(0), 847 .hw.init = &(struct clk_init_data){ 848 .name = "cam_cc_core_ahb_clk", 849 .parent_hws = (const struct clk_hw*[]){ 850 &cam_cc_slow_ahb_clk_src.clkr.hw, 851 }, 852 .num_parents = 1, 853 .flags = CLK_SET_RATE_PARENT, 854 .ops = &clk_branch2_ops, 855 }, 856 }, 857 }; 858 859 static struct clk_branch cam_cc_cpas_ahb_clk = { 860 .halt_reg = 0xb11c, 861 .halt_check = BRANCH_HALT, 862 .clkr = { 863 .enable_reg = 0xb11c, 864 .enable_mask = BIT(0), 865 .hw.init = &(struct clk_init_data){ 866 .name = "cam_cc_cpas_ahb_clk", 867 .parent_hws = (const struct clk_hw*[]){ 868 &cam_cc_slow_ahb_clk_src.clkr.hw, 869 }, 870 .num_parents = 1, 871 .flags = CLK_SET_RATE_PARENT, 872 .ops = &clk_branch2_ops, 873 }, 874 }, 875 }; 876 877 static struct clk_branch cam_cc_csi0phytimer_clk = { 878 .halt_reg = 0x501c, 879 .halt_check = BRANCH_HALT, 880 .clkr = { 881 .enable_reg = 0x501c, 882 .enable_mask = BIT(0), 883 .hw.init = &(struct clk_init_data){ 884 .name = "cam_cc_csi0phytimer_clk", 885 .parent_hws = (const struct clk_hw*[]){ 886 &cam_cc_csi0phytimer_clk_src.clkr.hw, 887 }, 888 .num_parents = 1, 889 .flags = CLK_SET_RATE_PARENT, 890 .ops = &clk_branch2_ops, 891 }, 892 }, 893 }; 894 895 static struct clk_branch cam_cc_csi1phytimer_clk = { 896 .halt_reg = 0x5040, 897 .halt_check = BRANCH_HALT, 898 .clkr = { 899 .enable_reg = 0x5040, 900 .enable_mask = BIT(0), 901 .hw.init = &(struct clk_init_data){ 902 .name = "cam_cc_csi1phytimer_clk", 903 .parent_hws = (const struct clk_hw*[]){ 904 &cam_cc_csi1phytimer_clk_src.clkr.hw, 905 }, 906 .num_parents = 1, 907 .flags = CLK_SET_RATE_PARENT, 908 .ops = &clk_branch2_ops, 909 }, 910 }, 911 }; 912 913 static struct clk_branch cam_cc_csi2phytimer_clk = { 914 .halt_reg = 0x5064, 915 .halt_check = BRANCH_HALT, 916 .clkr = { 917 .enable_reg = 0x5064, 918 .enable_mask = BIT(0), 919 .hw.init = &(struct clk_init_data){ 920 .name = "cam_cc_csi2phytimer_clk", 921 .parent_hws = (const struct clk_hw*[]){ 922 &cam_cc_csi2phytimer_clk_src.clkr.hw, 923 }, 924 .num_parents = 1, 925 .flags = CLK_SET_RATE_PARENT, 926 .ops = &clk_branch2_ops, 927 }, 928 }, 929 }; 930 931 static struct clk_branch cam_cc_csi3phytimer_clk = { 932 .halt_reg = 0x5088, 933 .halt_check = BRANCH_HALT, 934 .clkr = { 935 .enable_reg = 0x5088, 936 .enable_mask = BIT(0), 937 .hw.init = &(struct clk_init_data){ 938 .name = "cam_cc_csi3phytimer_clk", 939 .parent_hws = (const struct clk_hw*[]){ 940 &cam_cc_csi3phytimer_clk_src.clkr.hw, 941 }, 942 .num_parents = 1, 943 .flags = CLK_SET_RATE_PARENT, 944 .ops = &clk_branch2_ops, 945 }, 946 }, 947 }; 948 949 static struct clk_branch cam_cc_csiphy0_clk = { 950 .halt_reg = 0x5020, 951 .halt_check = BRANCH_HALT, 952 .clkr = { 953 .enable_reg = 0x5020, 954 .enable_mask = BIT(0), 955 .hw.init = &(struct clk_init_data){ 956 .name = "cam_cc_csiphy0_clk", 957 .parent_hws = (const struct clk_hw*[]){ 958 &cam_cc_cphy_rx_clk_src.clkr.hw, 959 }, 960 .num_parents = 1, 961 .flags = CLK_SET_RATE_PARENT, 962 .ops = &clk_branch2_ops, 963 }, 964 }, 965 }; 966 967 static struct clk_branch cam_cc_csiphy1_clk = { 968 .halt_reg = 0x5044, 969 .halt_check = BRANCH_HALT, 970 .clkr = { 971 .enable_reg = 0x5044, 972 .enable_mask = BIT(0), 973 .hw.init = &(struct clk_init_data){ 974 .name = "cam_cc_csiphy1_clk", 975 .parent_hws = (const struct clk_hw*[]){ 976 &cam_cc_cphy_rx_clk_src.clkr.hw, 977 }, 978 .num_parents = 1, 979 .flags = CLK_SET_RATE_PARENT, 980 .ops = &clk_branch2_ops, 981 }, 982 }, 983 }; 984 985 static struct clk_branch cam_cc_csiphy2_clk = { 986 .halt_reg = 0x5068, 987 .halt_check = BRANCH_HALT, 988 .clkr = { 989 .enable_reg = 0x5068, 990 .enable_mask = BIT(0), 991 .hw.init = &(struct clk_init_data){ 992 .name = "cam_cc_csiphy2_clk", 993 .parent_hws = (const struct clk_hw*[]){ 994 &cam_cc_cphy_rx_clk_src.clkr.hw, 995 }, 996 .num_parents = 1, 997 .flags = CLK_SET_RATE_PARENT, 998 .ops = &clk_branch2_ops, 999 }, 1000 }, 1001 }; 1002 1003 static struct clk_branch cam_cc_csiphy3_clk = { 1004 .halt_reg = 0x508c, 1005 .halt_check = BRANCH_HALT, 1006 .clkr = { 1007 .enable_reg = 0x508c, 1008 .enable_mask = BIT(0), 1009 .hw.init = &(struct clk_init_data){ 1010 .name = "cam_cc_csiphy3_clk", 1011 .parent_hws = (const struct clk_hw*[]){ 1012 &cam_cc_cphy_rx_clk_src.clkr.hw, 1013 }, 1014 .num_parents = 1, 1015 .flags = CLK_SET_RATE_PARENT, 1016 .ops = &clk_branch2_ops, 1017 }, 1018 }, 1019 }; 1020 1021 static struct clk_branch cam_cc_icp_clk = { 1022 .halt_reg = 0xb0a0, 1023 .halt_check = BRANCH_HALT, 1024 .clkr = { 1025 .enable_reg = 0xb0a0, 1026 .enable_mask = BIT(0), 1027 .hw.init = &(struct clk_init_data){ 1028 .name = "cam_cc_icp_clk", 1029 .parent_hws = (const struct clk_hw*[]){ 1030 &cam_cc_icp_clk_src.clkr.hw, 1031 }, 1032 .num_parents = 1, 1033 .flags = CLK_SET_RATE_PARENT, 1034 .ops = &clk_branch2_ops, 1035 }, 1036 }, 1037 }; 1038 1039 static struct clk_branch cam_cc_ife_0_axi_clk = { 1040 .halt_reg = 0x9080, 1041 .halt_check = BRANCH_HALT, 1042 .clkr = { 1043 .enable_reg = 0x9080, 1044 .enable_mask = BIT(0), 1045 .hw.init = &(struct clk_init_data){ 1046 .name = "cam_cc_ife_0_axi_clk", 1047 .ops = &clk_branch2_ops, 1048 }, 1049 }, 1050 }; 1051 1052 static struct clk_branch cam_cc_ife_0_clk = { 1053 .halt_reg = 0x9028, 1054 .halt_check = BRANCH_HALT, 1055 .clkr = { 1056 .enable_reg = 0x9028, 1057 .enable_mask = BIT(0), 1058 .hw.init = &(struct clk_init_data){ 1059 .name = "cam_cc_ife_0_clk", 1060 .parent_hws = (const struct clk_hw*[]){ 1061 &cam_cc_ife_0_clk_src.clkr.hw, 1062 }, 1063 .num_parents = 1, 1064 .flags = CLK_SET_RATE_PARENT, 1065 .ops = &clk_branch2_ops, 1066 }, 1067 }, 1068 }; 1069 1070 static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { 1071 .halt_reg = 0x907c, 1072 .halt_check = BRANCH_HALT, 1073 .clkr = { 1074 .enable_reg = 0x907c, 1075 .enable_mask = BIT(0), 1076 .hw.init = &(struct clk_init_data){ 1077 .name = "cam_cc_ife_0_cphy_rx_clk", 1078 .parent_hws = (const struct clk_hw*[]){ 1079 &cam_cc_cphy_rx_clk_src.clkr.hw, 1080 }, 1081 .num_parents = 1, 1082 .flags = CLK_SET_RATE_PARENT, 1083 .ops = &clk_branch2_ops, 1084 }, 1085 }, 1086 }; 1087 1088 static struct clk_branch cam_cc_ife_0_csid_clk = { 1089 .halt_reg = 0x9054, 1090 .halt_check = BRANCH_HALT, 1091 .clkr = { 1092 .enable_reg = 0x9054, 1093 .enable_mask = BIT(0), 1094 .hw.init = &(struct clk_init_data){ 1095 .name = "cam_cc_ife_0_csid_clk", 1096 .parent_hws = (const struct clk_hw*[]){ 1097 &cam_cc_ife_0_csid_clk_src.clkr.hw, 1098 }, 1099 .num_parents = 1, 1100 .flags = CLK_SET_RATE_PARENT, 1101 .ops = &clk_branch2_ops, 1102 }, 1103 }, 1104 }; 1105 1106 static struct clk_branch cam_cc_ife_0_dsp_clk = { 1107 .halt_reg = 0x9038, 1108 .halt_check = BRANCH_HALT, 1109 .clkr = { 1110 .enable_reg = 0x9038, 1111 .enable_mask = BIT(0), 1112 .hw.init = &(struct clk_init_data){ 1113 .name = "cam_cc_ife_0_dsp_clk", 1114 .parent_hws = (const struct clk_hw*[]){ 1115 &cam_cc_ife_0_clk_src.clkr.hw, 1116 }, 1117 .num_parents = 1, 1118 .flags = CLK_SET_RATE_PARENT, 1119 .ops = &clk_branch2_ops, 1120 }, 1121 }, 1122 }; 1123 1124 static struct clk_branch cam_cc_ife_1_axi_clk = { 1125 .halt_reg = 0xa058, 1126 .halt_check = BRANCH_HALT, 1127 .clkr = { 1128 .enable_reg = 0xa058, 1129 .enable_mask = BIT(0), 1130 .hw.init = &(struct clk_init_data){ 1131 .name = "cam_cc_ife_1_axi_clk", 1132 .ops = &clk_branch2_ops, 1133 }, 1134 }, 1135 }; 1136 1137 static struct clk_branch cam_cc_ife_1_clk = { 1138 .halt_reg = 0xa028, 1139 .halt_check = BRANCH_HALT, 1140 .clkr = { 1141 .enable_reg = 0xa028, 1142 .enable_mask = BIT(0), 1143 .hw.init = &(struct clk_init_data){ 1144 .name = "cam_cc_ife_1_clk", 1145 .parent_hws = (const struct clk_hw*[]){ 1146 &cam_cc_ife_1_clk_src.clkr.hw, 1147 }, 1148 .num_parents = 1, 1149 .flags = CLK_SET_RATE_PARENT, 1150 .ops = &clk_branch2_ops, 1151 }, 1152 }, 1153 }; 1154 1155 static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { 1156 .halt_reg = 0xa054, 1157 .halt_check = BRANCH_HALT, 1158 .clkr = { 1159 .enable_reg = 0xa054, 1160 .enable_mask = BIT(0), 1161 .hw.init = &(struct clk_init_data){ 1162 .name = "cam_cc_ife_1_cphy_rx_clk", 1163 .parent_hws = (const struct clk_hw*[]){ 1164 &cam_cc_cphy_rx_clk_src.clkr.hw, 1165 }, 1166 .num_parents = 1, 1167 .flags = CLK_SET_RATE_PARENT, 1168 .ops = &clk_branch2_ops, 1169 }, 1170 }, 1171 }; 1172 1173 static struct clk_branch cam_cc_ife_1_csid_clk = { 1174 .halt_reg = 0xa04c, 1175 .halt_check = BRANCH_HALT, 1176 .clkr = { 1177 .enable_reg = 0xa04c, 1178 .enable_mask = BIT(0), 1179 .hw.init = &(struct clk_init_data){ 1180 .name = "cam_cc_ife_1_csid_clk", 1181 .parent_hws = (const struct clk_hw*[]){ 1182 &cam_cc_ife_1_csid_clk_src.clkr.hw, 1183 }, 1184 .num_parents = 1, 1185 .flags = CLK_SET_RATE_PARENT, 1186 .ops = &clk_branch2_ops, 1187 }, 1188 }, 1189 }; 1190 1191 static struct clk_branch cam_cc_ife_1_dsp_clk = { 1192 .halt_reg = 0xa030, 1193 .halt_check = BRANCH_HALT, 1194 .clkr = { 1195 .enable_reg = 0xa030, 1196 .enable_mask = BIT(0), 1197 .hw.init = &(struct clk_init_data){ 1198 .name = "cam_cc_ife_1_dsp_clk", 1199 .parent_hws = (const struct clk_hw*[]){ 1200 &cam_cc_ife_1_clk_src.clkr.hw, 1201 }, 1202 .num_parents = 1, 1203 .flags = CLK_SET_RATE_PARENT, 1204 .ops = &clk_branch2_ops, 1205 }, 1206 }, 1207 }; 1208 1209 static struct clk_branch cam_cc_ife_lite_clk = { 1210 .halt_reg = 0xb01c, 1211 .halt_check = BRANCH_HALT, 1212 .clkr = { 1213 .enable_reg = 0xb01c, 1214 .enable_mask = BIT(0), 1215 .hw.init = &(struct clk_init_data){ 1216 .name = "cam_cc_ife_lite_clk", 1217 .parent_hws = (const struct clk_hw*[]){ 1218 &cam_cc_ife_lite_clk_src.clkr.hw, 1219 }, 1220 .num_parents = 1, 1221 .flags = CLK_SET_RATE_PARENT, 1222 .ops = &clk_branch2_ops, 1223 }, 1224 }, 1225 }; 1226 1227 static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { 1228 .halt_reg = 0xb044, 1229 .halt_check = BRANCH_HALT, 1230 .clkr = { 1231 .enable_reg = 0xb044, 1232 .enable_mask = BIT(0), 1233 .hw.init = &(struct clk_init_data){ 1234 .name = "cam_cc_ife_lite_cphy_rx_clk", 1235 .parent_hws = (const struct clk_hw*[]){ 1236 &cam_cc_cphy_rx_clk_src.clkr.hw, 1237 }, 1238 .num_parents = 1, 1239 .flags = CLK_SET_RATE_PARENT, 1240 .ops = &clk_branch2_ops, 1241 }, 1242 }, 1243 }; 1244 1245 static struct clk_branch cam_cc_ife_lite_csid_clk = { 1246 .halt_reg = 0xb03c, 1247 .halt_check = BRANCH_HALT, 1248 .clkr = { 1249 .enable_reg = 0xb03c, 1250 .enable_mask = BIT(0), 1251 .hw.init = &(struct clk_init_data){ 1252 .name = "cam_cc_ife_lite_csid_clk", 1253 .parent_hws = (const struct clk_hw*[]){ 1254 &cam_cc_ife_lite_csid_clk_src.clkr.hw, 1255 }, 1256 .num_parents = 1, 1257 .flags = CLK_SET_RATE_PARENT, 1258 .ops = &clk_branch2_ops, 1259 }, 1260 }, 1261 }; 1262 1263 static struct clk_branch cam_cc_ipe_0_ahb_clk = { 1264 .halt_reg = 0x7040, 1265 .halt_check = BRANCH_HALT, 1266 .clkr = { 1267 .enable_reg = 0x7040, 1268 .enable_mask = BIT(0), 1269 .hw.init = &(struct clk_init_data){ 1270 .name = "cam_cc_ipe_0_ahb_clk", 1271 .parent_hws = (const struct clk_hw*[]){ 1272 &cam_cc_slow_ahb_clk_src.clkr.hw, 1273 }, 1274 .num_parents = 1, 1275 .flags = CLK_SET_RATE_PARENT, 1276 .ops = &clk_branch2_ops, 1277 }, 1278 }, 1279 }; 1280 1281 static struct clk_branch cam_cc_ipe_0_areg_clk = { 1282 .halt_reg = 0x703c, 1283 .halt_check = BRANCH_HALT, 1284 .clkr = { 1285 .enable_reg = 0x703c, 1286 .enable_mask = BIT(0), 1287 .hw.init = &(struct clk_init_data){ 1288 .name = "cam_cc_ipe_0_areg_clk", 1289 .parent_hws = (const struct clk_hw*[]){ 1290 &cam_cc_fast_ahb_clk_src.clkr.hw, 1291 }, 1292 .num_parents = 1, 1293 .flags = CLK_SET_RATE_PARENT, 1294 .ops = &clk_branch2_ops, 1295 }, 1296 }, 1297 }; 1298 1299 static struct clk_branch cam_cc_ipe_0_axi_clk = { 1300 .halt_reg = 0x7038, 1301 .halt_check = BRANCH_HALT, 1302 .clkr = { 1303 .enable_reg = 0x7038, 1304 .enable_mask = BIT(0), 1305 .hw.init = &(struct clk_init_data){ 1306 .name = "cam_cc_ipe_0_axi_clk", 1307 .ops = &clk_branch2_ops, 1308 }, 1309 }, 1310 }; 1311 1312 static struct clk_branch cam_cc_ipe_0_clk = { 1313 .halt_reg = 0x7028, 1314 .halt_check = BRANCH_HALT, 1315 .clkr = { 1316 .enable_reg = 0x7028, 1317 .enable_mask = BIT(0), 1318 .hw.init = &(struct clk_init_data){ 1319 .name = "cam_cc_ipe_0_clk", 1320 .parent_hws = (const struct clk_hw*[]){ 1321 &cam_cc_ipe_0_clk_src.clkr.hw, 1322 }, 1323 .num_parents = 1, 1324 .flags = CLK_SET_RATE_PARENT, 1325 .ops = &clk_branch2_ops, 1326 }, 1327 }, 1328 }; 1329 1330 static struct clk_branch cam_cc_jpeg_clk = { 1331 .halt_reg = 0xb064, 1332 .halt_check = BRANCH_HALT, 1333 .clkr = { 1334 .enable_reg = 0xb064, 1335 .enable_mask = BIT(0), 1336 .hw.init = &(struct clk_init_data){ 1337 .name = "cam_cc_jpeg_clk", 1338 .parent_hws = (const struct clk_hw*[]){ 1339 &cam_cc_jpeg_clk_src.clkr.hw, 1340 }, 1341 .num_parents = 1, 1342 .flags = CLK_SET_RATE_PARENT, 1343 .ops = &clk_branch2_ops, 1344 }, 1345 }, 1346 }; 1347 1348 static struct clk_branch cam_cc_lrme_clk = { 1349 .halt_reg = 0xb110, 1350 .halt_check = BRANCH_HALT, 1351 .clkr = { 1352 .enable_reg = 0xb110, 1353 .enable_mask = BIT(0), 1354 .hw.init = &(struct clk_init_data){ 1355 .name = "cam_cc_lrme_clk", 1356 .parent_hws = (const struct clk_hw*[]){ 1357 &cam_cc_lrme_clk_src.clkr.hw, 1358 }, 1359 .num_parents = 1, 1360 .flags = CLK_SET_RATE_PARENT, 1361 .ops = &clk_branch2_ops, 1362 }, 1363 }, 1364 }; 1365 1366 static struct clk_branch cam_cc_mclk0_clk = { 1367 .halt_reg = 0x401c, 1368 .halt_check = BRANCH_HALT, 1369 .clkr = { 1370 .enable_reg = 0x401c, 1371 .enable_mask = BIT(0), 1372 .hw.init = &(struct clk_init_data){ 1373 .name = "cam_cc_mclk0_clk", 1374 .parent_hws = (const struct clk_hw*[]){ 1375 &cam_cc_mclk0_clk_src.clkr.hw, 1376 }, 1377 .num_parents = 1, 1378 .flags = CLK_SET_RATE_PARENT, 1379 .ops = &clk_branch2_ops, 1380 }, 1381 }, 1382 }; 1383 1384 static struct clk_branch cam_cc_mclk1_clk = { 1385 .halt_reg = 0x403c, 1386 .halt_check = BRANCH_HALT, 1387 .clkr = { 1388 .enable_reg = 0x403c, 1389 .enable_mask = BIT(0), 1390 .hw.init = &(struct clk_init_data){ 1391 .name = "cam_cc_mclk1_clk", 1392 .parent_hws = (const struct clk_hw*[]){ 1393 &cam_cc_mclk1_clk_src.clkr.hw, 1394 }, 1395 .num_parents = 1, 1396 .flags = CLK_SET_RATE_PARENT, 1397 .ops = &clk_branch2_ops, 1398 }, 1399 }, 1400 }; 1401 1402 static struct clk_branch cam_cc_mclk2_clk = { 1403 .halt_reg = 0x405c, 1404 .halt_check = BRANCH_HALT, 1405 .clkr = { 1406 .enable_reg = 0x405c, 1407 .enable_mask = BIT(0), 1408 .hw.init = &(struct clk_init_data){ 1409 .name = "cam_cc_mclk2_clk", 1410 .parent_hws = (const struct clk_hw*[]){ 1411 &cam_cc_mclk2_clk_src.clkr.hw, 1412 }, 1413 .num_parents = 1, 1414 .flags = CLK_SET_RATE_PARENT, 1415 .ops = &clk_branch2_ops, 1416 }, 1417 }, 1418 }; 1419 1420 static struct clk_branch cam_cc_mclk3_clk = { 1421 .halt_reg = 0x407c, 1422 .halt_check = BRANCH_HALT, 1423 .clkr = { 1424 .enable_reg = 0x407c, 1425 .enable_mask = BIT(0), 1426 .hw.init = &(struct clk_init_data){ 1427 .name = "cam_cc_mclk3_clk", 1428 .parent_hws = (const struct clk_hw*[]){ 1429 &cam_cc_mclk3_clk_src.clkr.hw, 1430 }, 1431 .num_parents = 1, 1432 .flags = CLK_SET_RATE_PARENT, 1433 .ops = &clk_branch2_ops, 1434 }, 1435 }, 1436 }; 1437 1438 static struct clk_branch cam_cc_mclk4_clk = { 1439 .halt_reg = 0x409c, 1440 .halt_check = BRANCH_HALT, 1441 .clkr = { 1442 .enable_reg = 0x409c, 1443 .enable_mask = BIT(0), 1444 .hw.init = &(struct clk_init_data){ 1445 .name = "cam_cc_mclk4_clk", 1446 .parent_hws = (const struct clk_hw*[]){ 1447 &cam_cc_mclk4_clk_src.clkr.hw, 1448 }, 1449 .num_parents = 1, 1450 .flags = CLK_SET_RATE_PARENT, 1451 .ops = &clk_branch2_ops, 1452 }, 1453 }, 1454 }; 1455 1456 static struct clk_branch cam_cc_soc_ahb_clk = { 1457 .halt_reg = 0xb140, 1458 .halt_check = BRANCH_HALT, 1459 .clkr = { 1460 .enable_reg = 0xb140, 1461 .enable_mask = BIT(0), 1462 .hw.init = &(struct clk_init_data){ 1463 .name = "cam_cc_soc_ahb_clk", 1464 .ops = &clk_branch2_ops, 1465 }, 1466 }, 1467 }; 1468 1469 static struct clk_branch cam_cc_sys_tmr_clk = { 1470 .halt_reg = 0xb0a8, 1471 .halt_check = BRANCH_HALT, 1472 .clkr = { 1473 .enable_reg = 0xb0a8, 1474 .enable_mask = BIT(0), 1475 .hw.init = &(struct clk_init_data){ 1476 .name = "cam_cc_sys_tmr_clk", 1477 .ops = &clk_branch2_ops, 1478 }, 1479 }, 1480 }; 1481 1482 static struct gdsc titan_top_gdsc = { 1483 .gdscr = 0xb134, 1484 .pd = { 1485 .name = "titan_top_gdsc", 1486 }, 1487 .pwrsts = PWRSTS_OFF_ON, 1488 }; 1489 1490 static struct gdsc bps_gdsc = { 1491 .gdscr = 0x6004, 1492 .pd = { 1493 .name = "bps_gdsc", 1494 }, 1495 .pwrsts = PWRSTS_OFF_ON, 1496 .parent = &titan_top_gdsc.pd, 1497 .flags = HW_CTRL, 1498 }; 1499 1500 static struct gdsc ife_0_gdsc = { 1501 .gdscr = 0x9004, 1502 .pd = { 1503 .name = "ife_0_gdsc", 1504 }, 1505 .pwrsts = PWRSTS_OFF_ON, 1506 .parent = &titan_top_gdsc.pd, 1507 }; 1508 1509 static struct gdsc ife_1_gdsc = { 1510 .gdscr = 0xa004, 1511 .pd = { 1512 .name = "ife_1_gdsc", 1513 }, 1514 .pwrsts = PWRSTS_OFF_ON, 1515 .parent = &titan_top_gdsc.pd, 1516 }; 1517 1518 static struct gdsc ipe_0_gdsc = { 1519 .gdscr = 0x7004, 1520 .pd = { 1521 .name = "ipe_0_gdsc", 1522 }, 1523 .pwrsts = PWRSTS_OFF_ON, 1524 .flags = HW_CTRL, 1525 .parent = &titan_top_gdsc.pd, 1526 }; 1527 1528 1529 static struct clk_hw *cam_cc_sc7180_hws[] = { 1530 [CAM_CC_PLL2_OUT_EARLY] = &cam_cc_pll2_out_early.hw, 1531 }; 1532 1533 static struct clk_regmap *cam_cc_sc7180_clocks[] = { 1534 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, 1535 [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr, 1536 [CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr, 1537 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, 1538 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, 1539 [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr, 1540 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, 1541 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, 1542 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, 1543 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, 1544 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 1545 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 1546 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 1547 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 1548 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 1549 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 1550 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 1551 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 1552 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 1553 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 1554 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 1555 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 1556 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 1557 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 1558 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 1559 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 1560 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 1561 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 1562 [CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr, 1563 [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, 1564 [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, 1565 [CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr, 1566 [CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr, 1567 [CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr, 1568 [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, 1569 [CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr, 1570 [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, 1571 [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, 1572 [CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr, 1573 [CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr, 1574 [CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr, 1575 [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, 1576 [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, 1577 [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, 1578 [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, 1579 [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, 1580 [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, 1581 [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr, 1582 [CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr, 1583 [CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr, 1584 [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr, 1585 [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr, 1586 [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, 1587 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, 1588 [CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr, 1589 [CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr, 1590 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 1591 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 1592 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 1593 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 1594 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 1595 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 1596 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 1597 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 1598 [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, 1599 [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, 1600 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 1601 [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 1602 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 1603 [CAM_CC_PLL2_OUT_AUX] = &cam_cc_pll2_out_aux.clkr, 1604 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 1605 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 1606 [CAM_CC_SOC_AHB_CLK] = &cam_cc_soc_ahb_clk.clkr, 1607 [CAM_CC_SYS_TMR_CLK] = &cam_cc_sys_tmr_clk.clkr, 1608 }; 1609 static struct gdsc *cam_cc_sc7180_gdscs[] = { 1610 [BPS_GDSC] = &bps_gdsc, 1611 [IFE_0_GDSC] = &ife_0_gdsc, 1612 [IFE_1_GDSC] = &ife_1_gdsc, 1613 [IPE_0_GDSC] = &ipe_0_gdsc, 1614 [TITAN_TOP_GDSC] = &titan_top_gdsc, 1615 }; 1616 1617 static const struct regmap_config cam_cc_sc7180_regmap_config = { 1618 .reg_bits = 32, 1619 .reg_stride = 4, 1620 .val_bits = 32, 1621 .max_register = 0xd028, 1622 .fast_io = true, 1623 }; 1624 1625 static const struct qcom_cc_desc cam_cc_sc7180_desc = { 1626 .config = &cam_cc_sc7180_regmap_config, 1627 .clk_hws = cam_cc_sc7180_hws, 1628 .num_clk_hws = ARRAY_SIZE(cam_cc_sc7180_hws), 1629 .clks = cam_cc_sc7180_clocks, 1630 .num_clks = ARRAY_SIZE(cam_cc_sc7180_clocks), 1631 .gdscs = cam_cc_sc7180_gdscs, 1632 .num_gdscs = ARRAY_SIZE(cam_cc_sc7180_gdscs), 1633 }; 1634 1635 static const struct of_device_id cam_cc_sc7180_match_table[] = { 1636 { .compatible = "qcom,sc7180-camcc" }, 1637 { } 1638 }; 1639 MODULE_DEVICE_TABLE(of, cam_cc_sc7180_match_table); 1640 1641 static int cam_cc_sc7180_probe(struct platform_device *pdev) 1642 { 1643 struct regmap *regmap; 1644 int ret; 1645 1646 ret = devm_pm_runtime_enable(&pdev->dev); 1647 if (ret < 0) 1648 return ret; 1649 1650 ret = devm_pm_clk_create(&pdev->dev); 1651 if (ret < 0) 1652 return ret; 1653 1654 ret = pm_clk_add(&pdev->dev, "xo"); 1655 if (ret < 0) { 1656 dev_err(&pdev->dev, "Failed to acquire XO clock\n"); 1657 return ret; 1658 } 1659 1660 ret = pm_clk_add(&pdev->dev, "iface"); 1661 if (ret < 0) { 1662 dev_err(&pdev->dev, "Failed to acquire iface clock\n"); 1663 return ret; 1664 } 1665 1666 ret = pm_runtime_resume_and_get(&pdev->dev); 1667 if (ret) 1668 return ret; 1669 1670 regmap = qcom_cc_map(pdev, &cam_cc_sc7180_desc); 1671 if (IS_ERR(regmap)) { 1672 ret = PTR_ERR(regmap); 1673 pm_runtime_put(&pdev->dev); 1674 return ret; 1675 } 1676 1677 clk_fabia_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); 1678 clk_fabia_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); 1679 clk_agera_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); 1680 clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); 1681 1682 ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sc7180_desc, regmap); 1683 pm_runtime_put(&pdev->dev); 1684 if (ret < 0) { 1685 dev_err(&pdev->dev, "Failed to register CAM CC clocks\n"); 1686 return ret; 1687 } 1688 1689 return 0; 1690 } 1691 1692 static const struct dev_pm_ops cam_cc_pm_ops = { 1693 SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) 1694 }; 1695 1696 static struct platform_driver cam_cc_sc7180_driver = { 1697 .probe = cam_cc_sc7180_probe, 1698 .driver = { 1699 .name = "cam_cc-sc7180", 1700 .of_match_table = cam_cc_sc7180_match_table, 1701 .pm = &cam_cc_pm_ops, 1702 }, 1703 }; 1704 1705 module_platform_driver(cam_cc_sc7180_driver); 1706 1707 MODULE_DESCRIPTION("QTI CAM_CC SC7180 Driver"); 1708 MODULE_LICENSE("GPL v2"); 1709