1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/mod_devicetable.h> 9 #include <linux/platform_device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/regmap.h> 12 13 #include <dt-bindings/clock/qcom,qcs8300-camcc.h> 14 15 #include "clk-alpha-pll.h" 16 #include "clk-branch.h" 17 #include "clk-pll.h" 18 #include "clk-rcg.h" 19 #include "clk-regmap.h" 20 #include "clk-regmap-divider.h" 21 #include "clk-regmap-mux.h" 22 #include "common.h" 23 #include "gdsc.h" 24 #include "reset.h" 25 26 enum { 27 DT_IFACE, 28 DT_BI_TCXO, 29 DT_BI_TCXO_AO, 30 DT_SLEEP_CLK, 31 }; 32 33 enum { 34 P_BI_TCXO, 35 P_BI_TCXO_AO, 36 P_CAM_CC_PLL0_OUT_EVEN, 37 P_CAM_CC_PLL0_OUT_MAIN, 38 P_CAM_CC_PLL0_OUT_ODD, 39 P_CAM_CC_PLL2_OUT_EVEN, 40 P_CAM_CC_PLL2_OUT_MAIN, 41 P_CAM_CC_PLL3_OUT_EVEN, 42 P_CAM_CC_PLL4_OUT_EVEN, 43 P_CAM_CC_PLL5_OUT_EVEN, 44 P_SLEEP_CLK, 45 }; 46 47 static const struct pll_vco lucid_evo_vco[] = { 48 { 249600000, 2020000000, 0 }, 49 }; 50 51 static const struct pll_vco rivian_evo_vco[] = { 52 { 864000000, 1056000000, 0 }, 53 }; 54 55 static const struct alpha_pll_config cam_cc_pll0_config = { 56 .l = 0x3e, 57 .alpha = 0x8000, 58 .config_ctl_val = 0x20485699, 59 .config_ctl_hi_val = 0x00182261, 60 .config_ctl_hi1_val = 0x32aa299c, 61 .user_ctl_val = 0x00008400, 62 .user_ctl_hi_val = 0x00400805, 63 }; 64 65 static struct clk_alpha_pll cam_cc_pll0 = { 66 .offset = 0x0, 67 .vco_table = lucid_evo_vco, 68 .num_vco = ARRAY_SIZE(lucid_evo_vco), 69 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 70 .clkr = { 71 .hw.init = &(const struct clk_init_data) { 72 .name = "cam_cc_pll0", 73 .parent_data = &(const struct clk_parent_data) { 74 .index = DT_BI_TCXO, 75 }, 76 .num_parents = 1, 77 .ops = &clk_alpha_pll_lucid_evo_ops, 78 }, 79 }, 80 }; 81 82 static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { 83 { 0x1, 2 }, 84 { } 85 }; 86 87 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { 88 .offset = 0x0, 89 .post_div_shift = 10, 90 .post_div_table = post_div_table_cam_cc_pll0_out_even, 91 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), 92 .width = 4, 93 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 94 .clkr.hw.init = &(const struct clk_init_data) { 95 .name = "cam_cc_pll0_out_even", 96 .parent_hws = (const struct clk_hw*[]) { 97 &cam_cc_pll0.clkr.hw, 98 }, 99 .num_parents = 1, 100 .flags = CLK_SET_RATE_PARENT, 101 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 102 }, 103 }; 104 105 static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { 106 { 0x2, 3 }, 107 { } 108 }; 109 110 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { 111 .offset = 0x0, 112 .post_div_shift = 14, 113 .post_div_table = post_div_table_cam_cc_pll0_out_odd, 114 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), 115 .width = 4, 116 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 117 .clkr.hw.init = &(const struct clk_init_data) { 118 .name = "cam_cc_pll0_out_odd", 119 .parent_hws = (const struct clk_hw*[]) { 120 &cam_cc_pll0.clkr.hw, 121 }, 122 .num_parents = 1, 123 .flags = CLK_SET_RATE_PARENT, 124 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 125 }, 126 }; 127 128 static const struct alpha_pll_config cam_cc_pll2_config = { 129 .l = 0x32, 130 .alpha = 0x0, 131 .config_ctl_val = 0x90008820, 132 .config_ctl_hi_val = 0x00890263, 133 .config_ctl_hi1_val = 0x00000247, 134 .user_ctl_val = 0x00000000, 135 .user_ctl_hi_val = 0x00400000, 136 }; 137 138 static struct clk_alpha_pll cam_cc_pll2 = { 139 .offset = 0x1000, 140 .vco_table = rivian_evo_vco, 141 .num_vco = ARRAY_SIZE(rivian_evo_vco), 142 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], 143 .clkr = { 144 .hw.init = &(const struct clk_init_data) { 145 .name = "cam_cc_pll2", 146 .parent_data = &(const struct clk_parent_data) { 147 .index = DT_BI_TCXO, 148 }, 149 .num_parents = 1, 150 .ops = &clk_alpha_pll_rivian_evo_ops, 151 }, 152 }, 153 }; 154 155 static const struct alpha_pll_config cam_cc_pll3_config = { 156 .l = 0x32, 157 .alpha = 0x0, 158 .config_ctl_val = 0x20485699, 159 .config_ctl_hi_val = 0x00182261, 160 .config_ctl_hi1_val = 0x32aa299c, 161 .user_ctl_val = 0x00000400, 162 .user_ctl_hi_val = 0x00400805, 163 }; 164 165 static struct clk_alpha_pll cam_cc_pll3 = { 166 .offset = 0x2000, 167 .vco_table = lucid_evo_vco, 168 .num_vco = ARRAY_SIZE(lucid_evo_vco), 169 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 170 .clkr = { 171 .hw.init = &(const struct clk_init_data) { 172 .name = "cam_cc_pll3", 173 .parent_data = &(const struct clk_parent_data) { 174 .index = DT_BI_TCXO, 175 }, 176 .num_parents = 1, 177 .ops = &clk_alpha_pll_lucid_evo_ops, 178 }, 179 }, 180 }; 181 182 static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { 183 { 0x1, 2 }, 184 { } 185 }; 186 187 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 188 .offset = 0x2000, 189 .post_div_shift = 10, 190 .post_div_table = post_div_table_cam_cc_pll3_out_even, 191 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), 192 .width = 4, 193 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 194 .clkr.hw.init = &(const struct clk_init_data) { 195 .name = "cam_cc_pll3_out_even", 196 .parent_hws = (const struct clk_hw*[]) { 197 &cam_cc_pll3.clkr.hw, 198 }, 199 .num_parents = 1, 200 .flags = CLK_SET_RATE_PARENT, 201 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 202 }, 203 }; 204 205 static const struct alpha_pll_config cam_cc_pll4_config = { 206 .l = 0x32, 207 .alpha = 0x0, 208 .config_ctl_val = 0x20485699, 209 .config_ctl_hi_val = 0x00182261, 210 .config_ctl_hi1_val = 0x32aa299c, 211 .user_ctl_val = 0x00000400, 212 .user_ctl_hi_val = 0x00400805, 213 }; 214 215 static struct clk_alpha_pll cam_cc_pll4 = { 216 .offset = 0x3000, 217 .vco_table = lucid_evo_vco, 218 .num_vco = ARRAY_SIZE(lucid_evo_vco), 219 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 220 .clkr = { 221 .hw.init = &(const struct clk_init_data) { 222 .name = "cam_cc_pll4", 223 .parent_data = &(const struct clk_parent_data) { 224 .index = DT_BI_TCXO, 225 }, 226 .num_parents = 1, 227 .ops = &clk_alpha_pll_lucid_evo_ops, 228 }, 229 }, 230 }; 231 232 static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { 233 { 0x1, 2 }, 234 { } 235 }; 236 237 static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { 238 .offset = 0x3000, 239 .post_div_shift = 10, 240 .post_div_table = post_div_table_cam_cc_pll4_out_even, 241 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), 242 .width = 4, 243 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 244 .clkr.hw.init = &(const struct clk_init_data) { 245 .name = "cam_cc_pll4_out_even", 246 .parent_hws = (const struct clk_hw*[]) { 247 &cam_cc_pll4.clkr.hw, 248 }, 249 .num_parents = 1, 250 .flags = CLK_SET_RATE_PARENT, 251 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 252 }, 253 }; 254 255 static const struct alpha_pll_config cam_cc_pll5_config = { 256 .l = 0x32, 257 .alpha = 0x0, 258 .config_ctl_val = 0x20485699, 259 .config_ctl_hi_val = 0x00182261, 260 .config_ctl_hi1_val = 0x32aa299c, 261 .user_ctl_val = 0x00000400, 262 .user_ctl_hi_val = 0x00400805, 263 }; 264 265 static struct clk_alpha_pll cam_cc_pll5 = { 266 .offset = 0x4000, 267 .vco_table = lucid_evo_vco, 268 .num_vco = ARRAY_SIZE(lucid_evo_vco), 269 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 270 .clkr = { 271 .hw.init = &(const struct clk_init_data) { 272 .name = "cam_cc_pll5", 273 .parent_data = &(const struct clk_parent_data) { 274 .index = DT_BI_TCXO, 275 }, 276 .num_parents = 1, 277 .ops = &clk_alpha_pll_lucid_evo_ops, 278 }, 279 }, 280 }; 281 282 static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = { 283 { 0x1, 2 }, 284 { } 285 }; 286 287 static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { 288 .offset = 0x4000, 289 .post_div_shift = 10, 290 .post_div_table = post_div_table_cam_cc_pll5_out_even, 291 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), 292 .width = 4, 293 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 294 .clkr.hw.init = &(const struct clk_init_data) { 295 .name = "cam_cc_pll5_out_even", 296 .parent_hws = (const struct clk_hw*[]) { 297 &cam_cc_pll5.clkr.hw, 298 }, 299 .num_parents = 1, 300 .flags = CLK_SET_RATE_PARENT, 301 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 302 }, 303 }; 304 305 static const struct parent_map cam_cc_parent_map_0[] = { 306 { P_BI_TCXO, 0 }, 307 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 308 { P_CAM_CC_PLL0_OUT_EVEN, 2 }, 309 { P_CAM_CC_PLL0_OUT_ODD, 3 }, 310 }; 311 312 static const struct clk_parent_data cam_cc_parent_data_0[] = { 313 { .index = DT_BI_TCXO }, 314 { .hw = &cam_cc_pll0.clkr.hw }, 315 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 316 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 317 }; 318 319 static const struct parent_map cam_cc_parent_map_1[] = { 320 { P_BI_TCXO, 0 }, 321 { P_CAM_CC_PLL2_OUT_EVEN, 3 }, 322 { P_CAM_CC_PLL2_OUT_MAIN, 5 }, 323 }; 324 325 static const struct clk_parent_data cam_cc_parent_data_1[] = { 326 { .index = DT_BI_TCXO }, 327 { .hw = &cam_cc_pll2.clkr.hw }, 328 { .hw = &cam_cc_pll2.clkr.hw }, 329 }; 330 331 static const struct parent_map cam_cc_parent_map_2[] = { 332 { P_BI_TCXO, 0 }, 333 { P_CAM_CC_PLL4_OUT_EVEN, 6 }, 334 }; 335 336 static const struct clk_parent_data cam_cc_parent_data_2[] = { 337 { .index = DT_BI_TCXO }, 338 { .hw = &cam_cc_pll4_out_even.clkr.hw }, 339 }; 340 341 static const struct parent_map cam_cc_parent_map_3[] = { 342 { P_BI_TCXO, 0 }, 343 { P_CAM_CC_PLL5_OUT_EVEN, 6 }, 344 }; 345 346 static const struct clk_parent_data cam_cc_parent_data_3[] = { 347 { .index = DT_BI_TCXO }, 348 { .hw = &cam_cc_pll5_out_even.clkr.hw }, 349 }; 350 351 static const struct parent_map cam_cc_parent_map_4[] = { 352 { P_BI_TCXO, 0 }, 353 { P_CAM_CC_PLL3_OUT_EVEN, 6 }, 354 }; 355 356 static const struct clk_parent_data cam_cc_parent_data_4[] = { 357 { .index = DT_BI_TCXO }, 358 { .hw = &cam_cc_pll3_out_even.clkr.hw }, 359 }; 360 361 static const struct parent_map cam_cc_parent_map_5[] = { 362 { P_SLEEP_CLK, 0 }, 363 }; 364 365 static const struct clk_parent_data cam_cc_parent_data_5[] = { 366 { .index = DT_SLEEP_CLK }, 367 }; 368 369 static const struct parent_map cam_cc_parent_map_6_ao[] = { 370 { P_BI_TCXO_AO, 0 }, 371 }; 372 373 static const struct clk_parent_data cam_cc_parent_data_6_ao[] = { 374 { .index = DT_BI_TCXO_AO }, 375 }; 376 377 static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = { 378 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 379 { } 380 }; 381 382 static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = { 383 .cmd_rcgr = 0x13170, 384 .mnd_width = 0, 385 .hid_width = 5, 386 .parent_map = cam_cc_parent_map_0, 387 .freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src, 388 .clkr.hw.init = &(const struct clk_init_data) { 389 .name = "cam_cc_camnoc_axi_clk_src", 390 .parent_data = cam_cc_parent_data_0, 391 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 392 .flags = CLK_SET_RATE_PARENT, 393 .ops = &clk_rcg2_shared_ops, 394 }, 395 }; 396 397 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { 398 F(37500000, P_CAM_CC_PLL0_OUT_MAIN, 16, 1, 2), 399 { } 400 }; 401 402 static struct clk_rcg2 cam_cc_cci_0_clk_src = { 403 .cmd_rcgr = 0x130a0, 404 .mnd_width = 8, 405 .hid_width = 5, 406 .parent_map = cam_cc_parent_map_0, 407 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 408 .clkr.hw.init = &(const struct clk_init_data) { 409 .name = "cam_cc_cci_0_clk_src", 410 .parent_data = cam_cc_parent_data_0, 411 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 412 .flags = CLK_SET_RATE_PARENT, 413 .ops = &clk_rcg2_shared_ops, 414 }, 415 }; 416 417 static struct clk_rcg2 cam_cc_cci_1_clk_src = { 418 .cmd_rcgr = 0x130bc, 419 .mnd_width = 8, 420 .hid_width = 5, 421 .parent_map = cam_cc_parent_map_0, 422 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 423 .clkr.hw.init = &(const struct clk_init_data) { 424 .name = "cam_cc_cci_1_clk_src", 425 .parent_data = cam_cc_parent_data_0, 426 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 427 .flags = CLK_SET_RATE_PARENT, 428 .ops = &clk_rcg2_shared_ops, 429 }, 430 }; 431 432 static struct clk_rcg2 cam_cc_cci_2_clk_src = { 433 .cmd_rcgr = 0x130d8, 434 .mnd_width = 8, 435 .hid_width = 5, 436 .parent_map = cam_cc_parent_map_0, 437 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 438 .clkr.hw.init = &(const struct clk_init_data) { 439 .name = "cam_cc_cci_2_clk_src", 440 .parent_data = cam_cc_parent_data_0, 441 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 442 .flags = CLK_SET_RATE_PARENT, 443 .ops = &clk_rcg2_shared_ops, 444 }, 445 }; 446 447 static struct clk_rcg2 cam_cc_cci_3_clk_src = { 448 .cmd_rcgr = 0x130f4, 449 .mnd_width = 8, 450 .hid_width = 5, 451 .parent_map = cam_cc_parent_map_0, 452 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 453 .clkr.hw.init = &(const struct clk_init_data) { 454 .name = "cam_cc_cci_3_clk_src", 455 .parent_data = cam_cc_parent_data_0, 456 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 457 .flags = CLK_SET_RATE_PARENT, 458 .ops = &clk_rcg2_shared_ops, 459 }, 460 }; 461 462 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 463 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 464 { } 465 }; 466 467 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 468 .cmd_rcgr = 0x11034, 469 .mnd_width = 0, 470 .hid_width = 5, 471 .parent_map = cam_cc_parent_map_0, 472 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 473 .clkr.hw.init = &(const struct clk_init_data) { 474 .name = "cam_cc_cphy_rx_clk_src", 475 .parent_data = cam_cc_parent_data_0, 476 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 477 .flags = CLK_SET_RATE_PARENT, 478 .ops = &clk_rcg2_shared_ops, 479 }, 480 }; 481 482 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 483 .cmd_rcgr = 0x15074, 484 .mnd_width = 0, 485 .hid_width = 5, 486 .parent_map = cam_cc_parent_map_0, 487 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 488 .clkr.hw.init = &(const struct clk_init_data) { 489 .name = "cam_cc_csi0phytimer_clk_src", 490 .parent_data = cam_cc_parent_data_0, 491 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 492 .flags = CLK_SET_RATE_PARENT, 493 .ops = &clk_rcg2_shared_ops, 494 }, 495 }; 496 497 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 498 .cmd_rcgr = 0x15098, 499 .mnd_width = 0, 500 .hid_width = 5, 501 .parent_map = cam_cc_parent_map_0, 502 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 503 .clkr.hw.init = &(const struct clk_init_data) { 504 .name = "cam_cc_csi1phytimer_clk_src", 505 .parent_data = cam_cc_parent_data_0, 506 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 507 .flags = CLK_SET_RATE_PARENT, 508 .ops = &clk_rcg2_shared_ops, 509 }, 510 }; 511 512 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 513 .cmd_rcgr = 0x150b8, 514 .mnd_width = 0, 515 .hid_width = 5, 516 .parent_map = cam_cc_parent_map_0, 517 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 518 .clkr.hw.init = &(const struct clk_init_data) { 519 .name = "cam_cc_csi2phytimer_clk_src", 520 .parent_data = cam_cc_parent_data_0, 521 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 522 .flags = CLK_SET_RATE_PARENT, 523 .ops = &clk_rcg2_shared_ops, 524 }, 525 }; 526 527 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 528 .cmd_rcgr = 0x150d8, 529 .mnd_width = 0, 530 .hid_width = 5, 531 .parent_map = cam_cc_parent_map_0, 532 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 533 .clkr.hw.init = &(const struct clk_init_data) { 534 .name = "cam_cc_csi3phytimer_clk_src", 535 .parent_data = cam_cc_parent_data_0, 536 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 537 .flags = CLK_SET_RATE_PARENT, 538 .ops = &clk_rcg2_shared_ops, 539 }, 540 }; 541 542 static struct clk_rcg2 cam_cc_csid_clk_src = { 543 .cmd_rcgr = 0x13150, 544 .mnd_width = 0, 545 .hid_width = 5, 546 .parent_map = cam_cc_parent_map_0, 547 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 548 .clkr.hw.init = &(const struct clk_init_data) { 549 .name = "cam_cc_csid_clk_src", 550 .parent_data = cam_cc_parent_data_0, 551 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 552 .flags = CLK_SET_RATE_PARENT, 553 .ops = &clk_rcg2_shared_ops, 554 }, 555 }; 556 557 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 558 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), 559 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 560 { } 561 }; 562 563 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 564 .cmd_rcgr = 0x13120, 565 .mnd_width = 0, 566 .hid_width = 5, 567 .parent_map = cam_cc_parent_map_0, 568 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 569 .clkr.hw.init = &(const struct clk_init_data) { 570 .name = "cam_cc_fast_ahb_clk_src", 571 .parent_data = cam_cc_parent_data_0, 572 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 573 .flags = CLK_SET_RATE_PARENT, 574 .ops = &clk_rcg2_shared_ops, 575 }, 576 }; 577 578 static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 579 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 580 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 581 { } 582 }; 583 584 static struct clk_rcg2 cam_cc_icp_clk_src = { 585 .cmd_rcgr = 0x1307c, 586 .mnd_width = 0, 587 .hid_width = 5, 588 .parent_map = cam_cc_parent_map_0, 589 .freq_tbl = ftbl_cam_cc_icp_clk_src, 590 .clkr.hw.init = &(const struct clk_init_data) { 591 .name = "cam_cc_icp_clk_src", 592 .parent_data = cam_cc_parent_data_0, 593 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 594 .flags = CLK_SET_RATE_PARENT, 595 .ops = &clk_rcg2_shared_ops, 596 }, 597 }; 598 599 static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { 600 F(480000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 601 F(600000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 602 { } 603 }; 604 605 static struct clk_rcg2 cam_cc_ife_0_clk_src = { 606 .cmd_rcgr = 0x11004, 607 .mnd_width = 0, 608 .hid_width = 5, 609 .parent_map = cam_cc_parent_map_2, 610 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 611 .clkr.hw.init = &(const struct clk_init_data) { 612 .name = "cam_cc_ife_0_clk_src", 613 .parent_data = cam_cc_parent_data_2, 614 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 615 .flags = CLK_SET_RATE_PARENT, 616 .ops = &clk_rcg2_shared_ops, 617 }, 618 }; 619 620 static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = { 621 F(480000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 622 F(600000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 623 { } 624 }; 625 626 static struct clk_rcg2 cam_cc_ife_1_clk_src = { 627 .cmd_rcgr = 0x12004, 628 .mnd_width = 0, 629 .hid_width = 5, 630 .parent_map = cam_cc_parent_map_3, 631 .freq_tbl = ftbl_cam_cc_ife_1_clk_src, 632 .clkr.hw.init = &(const struct clk_init_data) { 633 .name = "cam_cc_ife_1_clk_src", 634 .parent_data = cam_cc_parent_data_3, 635 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 636 .flags = CLK_SET_RATE_PARENT, 637 .ops = &clk_rcg2_shared_ops, 638 }, 639 }; 640 641 static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = { 642 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 643 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 644 { } 645 }; 646 647 static struct clk_rcg2 cam_cc_ife_lite_clk_src = { 648 .cmd_rcgr = 0x13000, 649 .mnd_width = 0, 650 .hid_width = 5, 651 .parent_map = cam_cc_parent_map_0, 652 .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, 653 .clkr.hw.init = &(const struct clk_init_data) { 654 .name = "cam_cc_ife_lite_clk_src", 655 .parent_data = cam_cc_parent_data_0, 656 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 657 .flags = CLK_SET_RATE_PARENT, 658 .ops = &clk_rcg2_shared_ops, 659 }, 660 }; 661 662 static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { 663 .cmd_rcgr = 0x13020, 664 .mnd_width = 0, 665 .hid_width = 5, 666 .parent_map = cam_cc_parent_map_0, 667 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 668 .clkr.hw.init = &(const struct clk_init_data) { 669 .name = "cam_cc_ife_lite_csid_clk_src", 670 .parent_data = cam_cc_parent_data_0, 671 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 672 .flags = CLK_SET_RATE_PARENT, 673 .ops = &clk_rcg2_shared_ops, 674 }, 675 }; 676 677 static const struct freq_tbl ftbl_cam_cc_ipe_clk_src[] = { 678 F(480000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 679 F(600000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 680 { } 681 }; 682 683 static struct clk_rcg2 cam_cc_ipe_clk_src = { 684 .cmd_rcgr = 0x10004, 685 .mnd_width = 0, 686 .hid_width = 5, 687 .parent_map = cam_cc_parent_map_4, 688 .freq_tbl = ftbl_cam_cc_ipe_clk_src, 689 .clkr.hw.init = &(const struct clk_init_data) { 690 .name = "cam_cc_ipe_clk_src", 691 .parent_data = cam_cc_parent_data_4, 692 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 693 .flags = CLK_SET_RATE_PARENT, 694 .ops = &clk_rcg2_shared_ops, 695 }, 696 }; 697 698 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 699 F(19200000, P_CAM_CC_PLL2_OUT_MAIN, 1, 1, 50), 700 F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4), 701 F(64000000, P_CAM_CC_PLL2_OUT_MAIN, 15, 0, 0), 702 { } 703 }; 704 705 static struct clk_rcg2 cam_cc_mclk0_clk_src = { 706 .cmd_rcgr = 0x15004, 707 .mnd_width = 8, 708 .hid_width = 5, 709 .parent_map = cam_cc_parent_map_1, 710 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 711 .clkr.hw.init = &(const struct clk_init_data) { 712 .name = "cam_cc_mclk0_clk_src", 713 .parent_data = cam_cc_parent_data_1, 714 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 715 .flags = CLK_SET_RATE_PARENT, 716 .ops = &clk_rcg2_shared_ops, 717 }, 718 }; 719 720 static struct clk_rcg2 cam_cc_mclk1_clk_src = { 721 .cmd_rcgr = 0x15020, 722 .mnd_width = 8, 723 .hid_width = 5, 724 .parent_map = cam_cc_parent_map_1, 725 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 726 .clkr.hw.init = &(const struct clk_init_data) { 727 .name = "cam_cc_mclk1_clk_src", 728 .parent_data = cam_cc_parent_data_1, 729 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 730 .flags = CLK_SET_RATE_PARENT, 731 .ops = &clk_rcg2_shared_ops, 732 }, 733 }; 734 735 static struct clk_rcg2 cam_cc_mclk2_clk_src = { 736 .cmd_rcgr = 0x1503c, 737 .mnd_width = 8, 738 .hid_width = 5, 739 .parent_map = cam_cc_parent_map_1, 740 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 741 .clkr.hw.init = &(const struct clk_init_data) { 742 .name = "cam_cc_mclk2_clk_src", 743 .parent_data = cam_cc_parent_data_1, 744 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 745 .flags = CLK_SET_RATE_PARENT, 746 .ops = &clk_rcg2_shared_ops, 747 }, 748 }; 749 750 static struct clk_rcg2 cam_cc_mclk3_clk_src = { 751 .cmd_rcgr = 0x15058, 752 .mnd_width = 8, 753 .hid_width = 5, 754 .parent_map = cam_cc_parent_map_1, 755 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 756 .clkr.hw.init = &(const struct clk_init_data) { 757 .name = "cam_cc_mclk3_clk_src", 758 .parent_data = cam_cc_parent_data_1, 759 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 760 .flags = CLK_SET_RATE_PARENT, 761 .ops = &clk_rcg2_shared_ops, 762 }, 763 }; 764 765 static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { 766 F(32000, P_SLEEP_CLK, 1, 0, 0), 767 { } 768 }; 769 770 static struct clk_rcg2 cam_cc_sleep_clk_src = { 771 .cmd_rcgr = 0x131f0, 772 .mnd_width = 0, 773 .hid_width = 5, 774 .parent_map = cam_cc_parent_map_5, 775 .freq_tbl = ftbl_cam_cc_sleep_clk_src, 776 .clkr.hw.init = &(const struct clk_init_data) { 777 .name = "cam_cc_sleep_clk_src", 778 .parent_data = cam_cc_parent_data_5, 779 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 780 .flags = CLK_SET_RATE_PARENT, 781 .ops = &clk_rcg2_shared_ops, 782 }, 783 }; 784 785 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 786 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 787 { } 788 }; 789 790 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 791 .cmd_rcgr = 0x13138, 792 .mnd_width = 8, 793 .hid_width = 5, 794 .parent_map = cam_cc_parent_map_0, 795 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 796 .clkr.hw.init = &(const struct clk_init_data) { 797 .name = "cam_cc_slow_ahb_clk_src", 798 .parent_data = cam_cc_parent_data_0, 799 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 800 .flags = CLK_SET_RATE_PARENT, 801 .ops = &clk_rcg2_shared_ops, 802 }, 803 }; 804 805 static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { 806 F(19200000, P_BI_TCXO_AO, 1, 0, 0), 807 { } 808 }; 809 810 static struct clk_rcg2 cam_cc_xo_clk_src = { 811 .cmd_rcgr = 0x131d4, 812 .mnd_width = 0, 813 .hid_width = 5, 814 .parent_map = cam_cc_parent_map_6_ao, 815 .freq_tbl = ftbl_cam_cc_xo_clk_src, 816 .clkr.hw.init = &(const struct clk_init_data) { 817 .name = "cam_cc_xo_clk_src", 818 .parent_data = cam_cc_parent_data_6_ao, 819 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6_ao), 820 .flags = CLK_SET_RATE_PARENT, 821 .ops = &clk_rcg2_shared_ops, 822 }, 823 }; 824 825 static struct clk_branch cam_cc_camnoc_axi_clk = { 826 .halt_reg = 0x13188, 827 .halt_check = BRANCH_HALT, 828 .clkr = { 829 .enable_reg = 0x13188, 830 .enable_mask = BIT(0), 831 .hw.init = &(const struct clk_init_data) { 832 .name = "cam_cc_camnoc_axi_clk", 833 .parent_hws = (const struct clk_hw*[]) { 834 &cam_cc_camnoc_axi_clk_src.clkr.hw, 835 }, 836 .num_parents = 1, 837 .flags = CLK_SET_RATE_PARENT, 838 .ops = &clk_branch2_ops, 839 }, 840 }, 841 }; 842 843 static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { 844 .halt_reg = 0x13190, 845 .halt_check = BRANCH_HALT, 846 .clkr = { 847 .enable_reg = 0x13190, 848 .enable_mask = BIT(0), 849 .hw.init = &(const struct clk_init_data) { 850 .name = "cam_cc_camnoc_dcd_xo_clk", 851 .parent_hws = (const struct clk_hw*[]) { 852 &cam_cc_xo_clk_src.clkr.hw, 853 }, 854 .num_parents = 1, 855 .flags = CLK_SET_RATE_PARENT, 856 .ops = &clk_branch2_ops, 857 }, 858 }, 859 }; 860 861 static struct clk_branch cam_cc_qdss_debug_xo_clk = { 862 .halt_reg = 0x131b8, 863 .halt_check = BRANCH_HALT, 864 .clkr = { 865 .enable_reg = 0x131b8, 866 .enable_mask = BIT(0), 867 .hw.init = &(const struct clk_init_data) { 868 .name = "cam_cc_qdss_debug_xo_clk", 869 .parent_hws = (const struct clk_hw*[]) { 870 &cam_cc_xo_clk_src.clkr.hw, 871 }, 872 .num_parents = 1, 873 .flags = CLK_SET_RATE_PARENT, 874 .ops = &clk_branch2_ops, 875 }, 876 }, 877 }; 878 879 static struct clk_branch cam_cc_cci_0_clk = { 880 .halt_reg = 0x130b8, 881 .halt_check = BRANCH_HALT, 882 .clkr = { 883 .enable_reg = 0x130b8, 884 .enable_mask = BIT(0), 885 .hw.init = &(const struct clk_init_data) { 886 .name = "cam_cc_cci_0_clk", 887 .parent_hws = (const struct clk_hw*[]) { 888 &cam_cc_cci_0_clk_src.clkr.hw, 889 }, 890 .num_parents = 1, 891 .flags = CLK_SET_RATE_PARENT, 892 .ops = &clk_branch2_ops, 893 }, 894 }, 895 }; 896 897 static struct clk_branch cam_cc_cci_1_clk = { 898 .halt_reg = 0x130d4, 899 .halt_check = BRANCH_HALT, 900 .clkr = { 901 .enable_reg = 0x130d4, 902 .enable_mask = BIT(0), 903 .hw.init = &(const struct clk_init_data) { 904 .name = "cam_cc_cci_1_clk", 905 .parent_hws = (const struct clk_hw*[]) { 906 &cam_cc_cci_1_clk_src.clkr.hw, 907 }, 908 .num_parents = 1, 909 .flags = CLK_SET_RATE_PARENT, 910 .ops = &clk_branch2_ops, 911 }, 912 }, 913 }; 914 915 static struct clk_branch cam_cc_cci_2_clk = { 916 .halt_reg = 0x130f0, 917 .halt_check = BRANCH_HALT, 918 .clkr = { 919 .enable_reg = 0x130f0, 920 .enable_mask = BIT(0), 921 .hw.init = &(const struct clk_init_data) { 922 .name = "cam_cc_cci_2_clk", 923 .parent_hws = (const struct clk_hw*[]) { 924 &cam_cc_cci_2_clk_src.clkr.hw, 925 }, 926 .num_parents = 1, 927 .flags = CLK_SET_RATE_PARENT, 928 .ops = &clk_branch2_ops, 929 }, 930 }, 931 }; 932 933 static struct clk_branch cam_cc_cci_3_clk = { 934 .halt_reg = 0x1310c, 935 .halt_check = BRANCH_HALT, 936 .clkr = { 937 .enable_reg = 0x1310c, 938 .enable_mask = BIT(0), 939 .hw.init = &(const struct clk_init_data) { 940 .name = "cam_cc_cci_3_clk", 941 .parent_hws = (const struct clk_hw*[]) { 942 &cam_cc_cci_3_clk_src.clkr.hw, 943 }, 944 .num_parents = 1, 945 .flags = CLK_SET_RATE_PARENT, 946 .ops = &clk_branch2_ops, 947 }, 948 }, 949 }; 950 951 static struct clk_branch cam_cc_core_ahb_clk = { 952 .halt_reg = 0x131d0, 953 .halt_check = BRANCH_HALT_DELAY, 954 .clkr = { 955 .enable_reg = 0x131d0, 956 .enable_mask = BIT(0), 957 .hw.init = &(const struct clk_init_data) { 958 .name = "cam_cc_core_ahb_clk", 959 .parent_hws = (const struct clk_hw*[]) { 960 &cam_cc_slow_ahb_clk_src.clkr.hw, 961 }, 962 .num_parents = 1, 963 .flags = CLK_SET_RATE_PARENT, 964 .ops = &clk_branch2_ops, 965 }, 966 }, 967 }; 968 969 static struct clk_branch cam_cc_cpas_ahb_clk = { 970 .halt_reg = 0x13110, 971 .halt_check = BRANCH_HALT, 972 .clkr = { 973 .enable_reg = 0x13110, 974 .enable_mask = BIT(0), 975 .hw.init = &(const struct clk_init_data) { 976 .name = "cam_cc_cpas_ahb_clk", 977 .parent_hws = (const struct clk_hw*[]) { 978 &cam_cc_slow_ahb_clk_src.clkr.hw, 979 }, 980 .num_parents = 1, 981 .flags = CLK_SET_RATE_PARENT, 982 .ops = &clk_branch2_ops, 983 }, 984 }, 985 }; 986 987 static struct clk_branch cam_cc_cpas_fast_ahb_clk = { 988 .halt_reg = 0x13118, 989 .halt_check = BRANCH_HALT, 990 .clkr = { 991 .enable_reg = 0x13118, 992 .enable_mask = BIT(0), 993 .hw.init = &(const struct clk_init_data) { 994 .name = "cam_cc_cpas_fast_ahb_clk", 995 .parent_hws = (const struct clk_hw*[]) { 996 &cam_cc_fast_ahb_clk_src.clkr.hw, 997 }, 998 .num_parents = 1, 999 .flags = CLK_SET_RATE_PARENT, 1000 .ops = &clk_branch2_ops, 1001 }, 1002 }, 1003 }; 1004 1005 static struct clk_branch cam_cc_cpas_ife_0_clk = { 1006 .halt_reg = 0x11024, 1007 .halt_check = BRANCH_HALT, 1008 .clkr = { 1009 .enable_reg = 0x11024, 1010 .enable_mask = BIT(0), 1011 .hw.init = &(const struct clk_init_data) { 1012 .name = "cam_cc_cpas_ife_0_clk", 1013 .parent_hws = (const struct clk_hw*[]) { 1014 &cam_cc_ife_0_clk_src.clkr.hw, 1015 }, 1016 .num_parents = 1, 1017 .flags = CLK_SET_RATE_PARENT, 1018 .ops = &clk_branch2_ops, 1019 }, 1020 }, 1021 }; 1022 1023 static struct clk_branch cam_cc_cpas_ife_1_clk = { 1024 .halt_reg = 0x12024, 1025 .halt_check = BRANCH_HALT, 1026 .clkr = { 1027 .enable_reg = 0x12024, 1028 .enable_mask = BIT(0), 1029 .hw.init = &(const struct clk_init_data) { 1030 .name = "cam_cc_cpas_ife_1_clk", 1031 .parent_hws = (const struct clk_hw*[]) { 1032 &cam_cc_ife_1_clk_src.clkr.hw, 1033 }, 1034 .num_parents = 1, 1035 .flags = CLK_SET_RATE_PARENT, 1036 .ops = &clk_branch2_ops, 1037 }, 1038 }, 1039 }; 1040 1041 static struct clk_branch cam_cc_cpas_ife_lite_clk = { 1042 .halt_reg = 0x1301c, 1043 .halt_check = BRANCH_HALT, 1044 .clkr = { 1045 .enable_reg = 0x1301c, 1046 .enable_mask = BIT(0), 1047 .hw.init = &(const struct clk_init_data) { 1048 .name = "cam_cc_cpas_ife_lite_clk", 1049 .parent_hws = (const struct clk_hw*[]) { 1050 &cam_cc_ife_lite_clk_src.clkr.hw, 1051 }, 1052 .num_parents = 1, 1053 .flags = CLK_SET_RATE_PARENT, 1054 .ops = &clk_branch2_ops, 1055 }, 1056 }, 1057 }; 1058 1059 static struct clk_branch cam_cc_cpas_ipe_clk = { 1060 .halt_reg = 0x10024, 1061 .halt_check = BRANCH_HALT, 1062 .clkr = { 1063 .enable_reg = 0x10024, 1064 .enable_mask = BIT(0), 1065 .hw.init = &(const struct clk_init_data) { 1066 .name = "cam_cc_cpas_ipe_clk", 1067 .parent_hws = (const struct clk_hw*[]) { 1068 &cam_cc_ipe_clk_src.clkr.hw, 1069 }, 1070 .num_parents = 1, 1071 .flags = CLK_SET_RATE_PARENT, 1072 .ops = &clk_branch2_ops, 1073 }, 1074 }, 1075 }; 1076 1077 static struct clk_branch cam_cc_cpas_sfe_lite_0_clk = { 1078 .halt_reg = 0x13050, 1079 .halt_check = BRANCH_HALT, 1080 .clkr = { 1081 .enable_reg = 0x13050, 1082 .enable_mask = BIT(0), 1083 .hw.init = &(const struct clk_init_data) { 1084 .name = "cam_cc_cpas_sfe_lite_0_clk", 1085 .parent_hws = (const struct clk_hw*[]) { 1086 &cam_cc_ife_0_clk_src.clkr.hw, 1087 }, 1088 .num_parents = 1, 1089 .flags = CLK_SET_RATE_PARENT, 1090 .ops = &clk_branch2_ops, 1091 }, 1092 }, 1093 }; 1094 1095 static struct clk_branch cam_cc_cpas_sfe_lite_1_clk = { 1096 .halt_reg = 0x13068, 1097 .halt_check = BRANCH_HALT, 1098 .clkr = { 1099 .enable_reg = 0x13068, 1100 .enable_mask = BIT(0), 1101 .hw.init = &(const struct clk_init_data) { 1102 .name = "cam_cc_cpas_sfe_lite_1_clk", 1103 .parent_hws = (const struct clk_hw*[]) { 1104 &cam_cc_ife_1_clk_src.clkr.hw, 1105 }, 1106 .num_parents = 1, 1107 .flags = CLK_SET_RATE_PARENT, 1108 .ops = &clk_branch2_ops, 1109 }, 1110 }, 1111 }; 1112 1113 static struct clk_branch cam_cc_csi0phytimer_clk = { 1114 .halt_reg = 0x1508c, 1115 .halt_check = BRANCH_HALT, 1116 .clkr = { 1117 .enable_reg = 0x1508c, 1118 .enable_mask = BIT(0), 1119 .hw.init = &(const struct clk_init_data) { 1120 .name = "cam_cc_csi0phytimer_clk", 1121 .parent_hws = (const struct clk_hw*[]) { 1122 &cam_cc_csi0phytimer_clk_src.clkr.hw, 1123 }, 1124 .num_parents = 1, 1125 .flags = CLK_SET_RATE_PARENT, 1126 .ops = &clk_branch2_ops, 1127 }, 1128 }, 1129 }; 1130 1131 static struct clk_branch cam_cc_csi1phytimer_clk = { 1132 .halt_reg = 0x150b0, 1133 .halt_check = BRANCH_HALT, 1134 .clkr = { 1135 .enable_reg = 0x150b0, 1136 .enable_mask = BIT(0), 1137 .hw.init = &(const struct clk_init_data) { 1138 .name = "cam_cc_csi1phytimer_clk", 1139 .parent_hws = (const struct clk_hw*[]) { 1140 &cam_cc_csi1phytimer_clk_src.clkr.hw, 1141 }, 1142 .num_parents = 1, 1143 .flags = CLK_SET_RATE_PARENT, 1144 .ops = &clk_branch2_ops, 1145 }, 1146 }, 1147 }; 1148 1149 static struct clk_branch cam_cc_csi2phytimer_clk = { 1150 .halt_reg = 0x150d0, 1151 .halt_check = BRANCH_HALT, 1152 .clkr = { 1153 .enable_reg = 0x150d0, 1154 .enable_mask = BIT(0), 1155 .hw.init = &(const struct clk_init_data) { 1156 .name = "cam_cc_csi2phytimer_clk", 1157 .parent_hws = (const struct clk_hw*[]) { 1158 &cam_cc_csi2phytimer_clk_src.clkr.hw, 1159 }, 1160 .num_parents = 1, 1161 .flags = CLK_SET_RATE_PARENT, 1162 .ops = &clk_branch2_ops, 1163 }, 1164 }, 1165 }; 1166 1167 static struct clk_branch cam_cc_csi3phytimer_clk = { 1168 .halt_reg = 0x150f0, 1169 .halt_check = BRANCH_HALT, 1170 .clkr = { 1171 .enable_reg = 0x150f0, 1172 .enable_mask = BIT(0), 1173 .hw.init = &(const struct clk_init_data) { 1174 .name = "cam_cc_csi3phytimer_clk", 1175 .parent_hws = (const struct clk_hw*[]) { 1176 &cam_cc_csi3phytimer_clk_src.clkr.hw, 1177 }, 1178 .num_parents = 1, 1179 .flags = CLK_SET_RATE_PARENT, 1180 .ops = &clk_branch2_ops, 1181 }, 1182 }, 1183 }; 1184 1185 static struct clk_branch cam_cc_csid_clk = { 1186 .halt_reg = 0x13168, 1187 .halt_check = BRANCH_HALT, 1188 .clkr = { 1189 .enable_reg = 0x13168, 1190 .enable_mask = BIT(0), 1191 .hw.init = &(const struct clk_init_data) { 1192 .name = "cam_cc_csid_clk", 1193 .parent_hws = (const struct clk_hw*[]) { 1194 &cam_cc_csid_clk_src.clkr.hw, 1195 }, 1196 .num_parents = 1, 1197 .flags = CLK_SET_RATE_PARENT, 1198 .ops = &clk_branch2_ops, 1199 }, 1200 }, 1201 }; 1202 1203 static struct clk_branch cam_cc_csid_csiphy_rx_clk = { 1204 .halt_reg = 0x15094, 1205 .halt_check = BRANCH_HALT, 1206 .clkr = { 1207 .enable_reg = 0x15094, 1208 .enable_mask = BIT(0), 1209 .hw.init = &(const struct clk_init_data) { 1210 .name = "cam_cc_csid_csiphy_rx_clk", 1211 .parent_hws = (const struct clk_hw*[]) { 1212 &cam_cc_cphy_rx_clk_src.clkr.hw, 1213 }, 1214 .num_parents = 1, 1215 .flags = CLK_SET_RATE_PARENT, 1216 .ops = &clk_branch2_ops, 1217 }, 1218 }, 1219 }; 1220 1221 static struct clk_branch cam_cc_csiphy0_clk = { 1222 .halt_reg = 0x15090, 1223 .halt_check = BRANCH_HALT, 1224 .clkr = { 1225 .enable_reg = 0x15090, 1226 .enable_mask = BIT(0), 1227 .hw.init = &(const struct clk_init_data) { 1228 .name = "cam_cc_csiphy0_clk", 1229 .parent_hws = (const struct clk_hw*[]) { 1230 &cam_cc_cphy_rx_clk_src.clkr.hw, 1231 }, 1232 .num_parents = 1, 1233 .flags = CLK_SET_RATE_PARENT, 1234 .ops = &clk_branch2_ops, 1235 }, 1236 }, 1237 }; 1238 1239 static struct clk_branch cam_cc_csiphy1_clk = { 1240 .halt_reg = 0x150b4, 1241 .halt_check = BRANCH_HALT, 1242 .clkr = { 1243 .enable_reg = 0x150b4, 1244 .enable_mask = BIT(0), 1245 .hw.init = &(const struct clk_init_data) { 1246 .name = "cam_cc_csiphy1_clk", 1247 .parent_hws = (const struct clk_hw*[]) { 1248 &cam_cc_cphy_rx_clk_src.clkr.hw, 1249 }, 1250 .num_parents = 1, 1251 .flags = CLK_SET_RATE_PARENT, 1252 .ops = &clk_branch2_ops, 1253 }, 1254 }, 1255 }; 1256 1257 static struct clk_branch cam_cc_csiphy2_clk = { 1258 .halt_reg = 0x150d4, 1259 .halt_check = BRANCH_HALT, 1260 .clkr = { 1261 .enable_reg = 0x150d4, 1262 .enable_mask = BIT(0), 1263 .hw.init = &(const struct clk_init_data) { 1264 .name = "cam_cc_csiphy2_clk", 1265 .parent_hws = (const struct clk_hw*[]) { 1266 &cam_cc_cphy_rx_clk_src.clkr.hw, 1267 }, 1268 .num_parents = 1, 1269 .flags = CLK_SET_RATE_PARENT, 1270 .ops = &clk_branch2_ops, 1271 }, 1272 }, 1273 }; 1274 1275 static struct clk_branch cam_cc_csiphy3_clk = { 1276 .halt_reg = 0x150f4, 1277 .halt_check = BRANCH_HALT, 1278 .clkr = { 1279 .enable_reg = 0x150f4, 1280 .enable_mask = BIT(0), 1281 .hw.init = &(const struct clk_init_data) { 1282 .name = "cam_cc_csiphy3_clk", 1283 .parent_hws = (const struct clk_hw*[]) { 1284 &cam_cc_cphy_rx_clk_src.clkr.hw, 1285 }, 1286 .num_parents = 1, 1287 .flags = CLK_SET_RATE_PARENT, 1288 .ops = &clk_branch2_ops, 1289 }, 1290 }, 1291 }; 1292 1293 static struct clk_branch cam_cc_icp_ahb_clk = { 1294 .halt_reg = 0x1309c, 1295 .halt_check = BRANCH_HALT, 1296 .clkr = { 1297 .enable_reg = 0x1309c, 1298 .enable_mask = BIT(0), 1299 .hw.init = &(const struct clk_init_data) { 1300 .name = "cam_cc_icp_ahb_clk", 1301 .parent_hws = (const struct clk_hw*[]) { 1302 &cam_cc_slow_ahb_clk_src.clkr.hw, 1303 }, 1304 .num_parents = 1, 1305 .flags = CLK_SET_RATE_PARENT, 1306 .ops = &clk_branch2_ops, 1307 }, 1308 }, 1309 }; 1310 1311 static struct clk_branch cam_cc_icp_clk = { 1312 .halt_reg = 0x13094, 1313 .halt_check = BRANCH_HALT, 1314 .clkr = { 1315 .enable_reg = 0x13094, 1316 .enable_mask = BIT(0), 1317 .hw.init = &(const struct clk_init_data) { 1318 .name = "cam_cc_icp_clk", 1319 .parent_hws = (const struct clk_hw*[]) { 1320 &cam_cc_icp_clk_src.clkr.hw, 1321 }, 1322 .num_parents = 1, 1323 .flags = CLK_SET_RATE_PARENT, 1324 .ops = &clk_branch2_ops, 1325 }, 1326 }, 1327 }; 1328 1329 static struct clk_branch cam_cc_ife_0_clk = { 1330 .halt_reg = 0x1101c, 1331 .halt_check = BRANCH_HALT, 1332 .clkr = { 1333 .enable_reg = 0x1101c, 1334 .enable_mask = BIT(0), 1335 .hw.init = &(const struct clk_init_data) { 1336 .name = "cam_cc_ife_0_clk", 1337 .parent_hws = (const struct clk_hw*[]) { 1338 &cam_cc_ife_0_clk_src.clkr.hw, 1339 }, 1340 .num_parents = 1, 1341 .flags = CLK_SET_RATE_PARENT, 1342 .ops = &clk_branch2_ops, 1343 }, 1344 }, 1345 }; 1346 1347 static struct clk_branch cam_cc_ife_0_fast_ahb_clk = { 1348 .halt_reg = 0x11030, 1349 .halt_check = BRANCH_HALT, 1350 .clkr = { 1351 .enable_reg = 0x11030, 1352 .enable_mask = BIT(0), 1353 .hw.init = &(const struct clk_init_data) { 1354 .name = "cam_cc_ife_0_fast_ahb_clk", 1355 .parent_hws = (const struct clk_hw*[]) { 1356 &cam_cc_fast_ahb_clk_src.clkr.hw, 1357 }, 1358 .num_parents = 1, 1359 .flags = CLK_SET_RATE_PARENT, 1360 .ops = &clk_branch2_ops, 1361 }, 1362 }, 1363 }; 1364 1365 static struct clk_branch cam_cc_ife_1_clk = { 1366 .halt_reg = 0x1201c, 1367 .halt_check = BRANCH_HALT, 1368 .clkr = { 1369 .enable_reg = 0x1201c, 1370 .enable_mask = BIT(0), 1371 .hw.init = &(const struct clk_init_data) { 1372 .name = "cam_cc_ife_1_clk", 1373 .parent_hws = (const struct clk_hw*[]) { 1374 &cam_cc_ife_1_clk_src.clkr.hw, 1375 }, 1376 .num_parents = 1, 1377 .flags = CLK_SET_RATE_PARENT, 1378 .ops = &clk_branch2_ops, 1379 }, 1380 }, 1381 }; 1382 1383 static struct clk_branch cam_cc_ife_1_fast_ahb_clk = { 1384 .halt_reg = 0x12030, 1385 .halt_check = BRANCH_HALT, 1386 .clkr = { 1387 .enable_reg = 0x12030, 1388 .enable_mask = BIT(0), 1389 .hw.init = &(const struct clk_init_data) { 1390 .name = "cam_cc_ife_1_fast_ahb_clk", 1391 .parent_hws = (const struct clk_hw*[]) { 1392 &cam_cc_fast_ahb_clk_src.clkr.hw, 1393 }, 1394 .num_parents = 1, 1395 .flags = CLK_SET_RATE_PARENT, 1396 .ops = &clk_branch2_ops, 1397 }, 1398 }, 1399 }; 1400 1401 static struct clk_branch cam_cc_ife_lite_ahb_clk = { 1402 .halt_reg = 0x13044, 1403 .halt_check = BRANCH_HALT, 1404 .clkr = { 1405 .enable_reg = 0x13044, 1406 .enable_mask = BIT(0), 1407 .hw.init = &(const struct clk_init_data) { 1408 .name = "cam_cc_ife_lite_ahb_clk", 1409 .parent_hws = (const struct clk_hw*[]) { 1410 &cam_cc_slow_ahb_clk_src.clkr.hw, 1411 }, 1412 .num_parents = 1, 1413 .flags = CLK_SET_RATE_PARENT, 1414 .ops = &clk_branch2_ops, 1415 }, 1416 }, 1417 }; 1418 1419 static struct clk_branch cam_cc_ife_lite_clk = { 1420 .halt_reg = 0x13018, 1421 .halt_check = BRANCH_HALT, 1422 .clkr = { 1423 .enable_reg = 0x13018, 1424 .enable_mask = BIT(0), 1425 .hw.init = &(const struct clk_init_data) { 1426 .name = "cam_cc_ife_lite_clk", 1427 .parent_hws = (const struct clk_hw*[]) { 1428 &cam_cc_ife_lite_clk_src.clkr.hw, 1429 }, 1430 .num_parents = 1, 1431 .flags = CLK_SET_RATE_PARENT, 1432 .ops = &clk_branch2_ops, 1433 }, 1434 }, 1435 }; 1436 1437 static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { 1438 .halt_reg = 0x13040, 1439 .halt_check = BRANCH_HALT, 1440 .clkr = { 1441 .enable_reg = 0x13040, 1442 .enable_mask = BIT(0), 1443 .hw.init = &(const struct clk_init_data) { 1444 .name = "cam_cc_ife_lite_cphy_rx_clk", 1445 .parent_hws = (const struct clk_hw*[]) { 1446 &cam_cc_cphy_rx_clk_src.clkr.hw, 1447 }, 1448 .num_parents = 1, 1449 .flags = CLK_SET_RATE_PARENT, 1450 .ops = &clk_branch2_ops, 1451 }, 1452 }, 1453 }; 1454 1455 static struct clk_branch cam_cc_ife_lite_csid_clk = { 1456 .halt_reg = 0x13038, 1457 .halt_check = BRANCH_HALT, 1458 .clkr = { 1459 .enable_reg = 0x13038, 1460 .enable_mask = BIT(0), 1461 .hw.init = &(const struct clk_init_data) { 1462 .name = "cam_cc_ife_lite_csid_clk", 1463 .parent_hws = (const struct clk_hw*[]) { 1464 &cam_cc_ife_lite_csid_clk_src.clkr.hw, 1465 }, 1466 .num_parents = 1, 1467 .flags = CLK_SET_RATE_PARENT, 1468 .ops = &clk_branch2_ops, 1469 }, 1470 }, 1471 }; 1472 1473 static struct clk_branch cam_cc_ipe_ahb_clk = { 1474 .halt_reg = 0x10030, 1475 .halt_check = BRANCH_HALT, 1476 .clkr = { 1477 .enable_reg = 0x10030, 1478 .enable_mask = BIT(0), 1479 .hw.init = &(const struct clk_init_data) { 1480 .name = "cam_cc_ipe_ahb_clk", 1481 .parent_hws = (const struct clk_hw*[]) { 1482 &cam_cc_slow_ahb_clk_src.clkr.hw, 1483 }, 1484 .num_parents = 1, 1485 .flags = CLK_SET_RATE_PARENT, 1486 .ops = &clk_branch2_ops, 1487 }, 1488 }, 1489 }; 1490 1491 static struct clk_branch cam_cc_ipe_clk = { 1492 .halt_reg = 0x1001c, 1493 .halt_check = BRANCH_HALT, 1494 .clkr = { 1495 .enable_reg = 0x1001c, 1496 .enable_mask = BIT(0), 1497 .hw.init = &(const struct clk_init_data) { 1498 .name = "cam_cc_ipe_clk", 1499 .parent_hws = (const struct clk_hw*[]) { 1500 &cam_cc_ipe_clk_src.clkr.hw, 1501 }, 1502 .num_parents = 1, 1503 .flags = CLK_SET_RATE_PARENT, 1504 .ops = &clk_branch2_ops, 1505 }, 1506 }, 1507 }; 1508 1509 static struct clk_branch cam_cc_ipe_fast_ahb_clk = { 1510 .halt_reg = 0x10034, 1511 .halt_check = BRANCH_HALT, 1512 .clkr = { 1513 .enable_reg = 0x10034, 1514 .enable_mask = BIT(0), 1515 .hw.init = &(const struct clk_init_data) { 1516 .name = "cam_cc_ipe_fast_ahb_clk", 1517 .parent_hws = (const struct clk_hw*[]) { 1518 &cam_cc_fast_ahb_clk_src.clkr.hw, 1519 }, 1520 .num_parents = 1, 1521 .flags = CLK_SET_RATE_PARENT, 1522 .ops = &clk_branch2_ops, 1523 }, 1524 }, 1525 }; 1526 1527 static struct clk_branch cam_cc_mclk0_clk = { 1528 .halt_reg = 0x1501c, 1529 .halt_check = BRANCH_HALT, 1530 .clkr = { 1531 .enable_reg = 0x1501c, 1532 .enable_mask = BIT(0), 1533 .hw.init = &(const struct clk_init_data) { 1534 .name = "cam_cc_mclk0_clk", 1535 .parent_hws = (const struct clk_hw*[]) { 1536 &cam_cc_mclk0_clk_src.clkr.hw, 1537 }, 1538 .num_parents = 1, 1539 .flags = CLK_SET_RATE_PARENT, 1540 .ops = &clk_branch2_ops, 1541 }, 1542 }, 1543 }; 1544 1545 static struct clk_branch cam_cc_mclk1_clk = { 1546 .halt_reg = 0x15038, 1547 .halt_check = BRANCH_HALT, 1548 .clkr = { 1549 .enable_reg = 0x15038, 1550 .enable_mask = BIT(0), 1551 .hw.init = &(const struct clk_init_data) { 1552 .name = "cam_cc_mclk1_clk", 1553 .parent_hws = (const struct clk_hw*[]) { 1554 &cam_cc_mclk1_clk_src.clkr.hw, 1555 }, 1556 .num_parents = 1, 1557 .flags = CLK_SET_RATE_PARENT, 1558 .ops = &clk_branch2_ops, 1559 }, 1560 }, 1561 }; 1562 1563 static struct clk_branch cam_cc_mclk2_clk = { 1564 .halt_reg = 0x15054, 1565 .halt_check = BRANCH_HALT, 1566 .clkr = { 1567 .enable_reg = 0x15054, 1568 .enable_mask = BIT(0), 1569 .hw.init = &(const struct clk_init_data) { 1570 .name = "cam_cc_mclk2_clk", 1571 .parent_hws = (const struct clk_hw*[]) { 1572 &cam_cc_mclk2_clk_src.clkr.hw, 1573 }, 1574 .num_parents = 1, 1575 .flags = CLK_SET_RATE_PARENT, 1576 .ops = &clk_branch2_ops, 1577 }, 1578 }, 1579 }; 1580 1581 static struct clk_branch cam_cc_mclk3_clk = { 1582 .halt_reg = 0x15070, 1583 .halt_check = BRANCH_HALT, 1584 .clkr = { 1585 .enable_reg = 0x15070, 1586 .enable_mask = BIT(0), 1587 .hw.init = &(const struct clk_init_data) { 1588 .name = "cam_cc_mclk3_clk", 1589 .parent_hws = (const struct clk_hw*[]) { 1590 &cam_cc_mclk3_clk_src.clkr.hw, 1591 }, 1592 .num_parents = 1, 1593 .flags = CLK_SET_RATE_PARENT, 1594 .ops = &clk_branch2_ops, 1595 }, 1596 }, 1597 }; 1598 1599 static struct clk_branch cam_cc_sfe_lite_0_clk = { 1600 .halt_reg = 0x1304c, 1601 .halt_check = BRANCH_HALT, 1602 .clkr = { 1603 .enable_reg = 0x1304c, 1604 .enable_mask = BIT(0), 1605 .hw.init = &(const struct clk_init_data) { 1606 .name = "cam_cc_sfe_lite_0_clk", 1607 .parent_hws = (const struct clk_hw*[]) { 1608 &cam_cc_ife_0_clk_src.clkr.hw, 1609 }, 1610 .num_parents = 1, 1611 .flags = CLK_SET_RATE_PARENT, 1612 .ops = &clk_branch2_ops, 1613 }, 1614 }, 1615 }; 1616 1617 static struct clk_branch cam_cc_sfe_lite_0_fast_ahb_clk = { 1618 .halt_reg = 0x1305c, 1619 .halt_check = BRANCH_HALT, 1620 .clkr = { 1621 .enable_reg = 0x1305c, 1622 .enable_mask = BIT(0), 1623 .hw.init = &(const struct clk_init_data) { 1624 .name = "cam_cc_sfe_lite_0_fast_ahb_clk", 1625 .parent_hws = (const struct clk_hw*[]) { 1626 &cam_cc_fast_ahb_clk_src.clkr.hw, 1627 }, 1628 .num_parents = 1, 1629 .flags = CLK_SET_RATE_PARENT, 1630 .ops = &clk_branch2_ops, 1631 }, 1632 }, 1633 }; 1634 1635 static struct clk_branch cam_cc_sfe_lite_1_clk = { 1636 .halt_reg = 0x13064, 1637 .halt_check = BRANCH_HALT, 1638 .clkr = { 1639 .enable_reg = 0x13064, 1640 .enable_mask = BIT(0), 1641 .hw.init = &(const struct clk_init_data) { 1642 .name = "cam_cc_sfe_lite_1_clk", 1643 .parent_hws = (const struct clk_hw*[]) { 1644 &cam_cc_ife_1_clk_src.clkr.hw, 1645 }, 1646 .num_parents = 1, 1647 .flags = CLK_SET_RATE_PARENT, 1648 .ops = &clk_branch2_ops, 1649 }, 1650 }, 1651 }; 1652 1653 static struct clk_branch cam_cc_sfe_lite_1_fast_ahb_clk = { 1654 .halt_reg = 0x13074, 1655 .halt_check = BRANCH_HALT, 1656 .clkr = { 1657 .enable_reg = 0x13074, 1658 .enable_mask = BIT(0), 1659 .hw.init = &(const struct clk_init_data) { 1660 .name = "cam_cc_sfe_lite_1_fast_ahb_clk", 1661 .parent_hws = (const struct clk_hw*[]) { 1662 &cam_cc_fast_ahb_clk_src.clkr.hw, 1663 }, 1664 .num_parents = 1, 1665 .flags = CLK_SET_RATE_PARENT, 1666 .ops = &clk_branch2_ops, 1667 }, 1668 }, 1669 }; 1670 1671 static struct clk_branch cam_cc_sm_obs_clk = { 1672 .halt_reg = 0x1510c, 1673 .halt_check = BRANCH_HALT_SKIP, 1674 .clkr = { 1675 .enable_reg = 0x1510c, 1676 .enable_mask = BIT(0), 1677 .hw.init = &(const struct clk_init_data) { 1678 .name = "cam_cc_sm_obs_clk", 1679 .ops = &clk_branch2_ops, 1680 }, 1681 }, 1682 }; 1683 1684 static struct clk_branch cam_cc_titan_top_accu_shift_clk = { 1685 .halt_reg = 0x131f0, 1686 .halt_check = BRANCH_HALT_VOTED, 1687 .clkr = { 1688 .enable_reg = 0x131f0, 1689 .enable_mask = BIT(0), 1690 .hw.init = &(const struct clk_init_data) { 1691 .name = "cam_cc_titan_top_accu_shift_clk", 1692 .parent_hws = (const struct clk_hw*[]) { 1693 &cam_cc_xo_clk_src.clkr.hw, 1694 }, 1695 .num_parents = 1, 1696 .flags = CLK_SET_RATE_PARENT, 1697 .ops = &clk_branch2_ops, 1698 }, 1699 }, 1700 }; 1701 1702 static struct gdsc cam_cc_titan_top_gdsc = { 1703 .gdscr = 0x131bc, 1704 .en_rest_wait_val = 0x2, 1705 .en_few_wait_val = 0x2, 1706 .clk_dis_wait_val = 0xf, 1707 .pd = { 1708 .name = "cam_cc_titan_top_gdsc", 1709 }, 1710 .pwrsts = PWRSTS_OFF_ON, 1711 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1712 }; 1713 1714 static struct clk_regmap *cam_cc_sa8775p_clocks[] = { 1715 [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr, 1716 [CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr, 1717 [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, 1718 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, 1719 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, 1720 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, 1721 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, 1722 [CAM_CC_CCI_2_CLK] = &cam_cc_cci_2_clk.clkr, 1723 [CAM_CC_CCI_2_CLK_SRC] = &cam_cc_cci_2_clk_src.clkr, 1724 [CAM_CC_CCI_3_CLK] = &cam_cc_cci_3_clk.clkr, 1725 [CAM_CC_CCI_3_CLK_SRC] = &cam_cc_cci_3_clk_src.clkr, 1726 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 1727 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 1728 [CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr, 1729 [CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr, 1730 [CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr, 1731 [CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr, 1732 [CAM_CC_CPAS_IPE_CLK] = &cam_cc_cpas_ipe_clk.clkr, 1733 [CAM_CC_CPAS_SFE_LITE_0_CLK] = &cam_cc_cpas_sfe_lite_0_clk.clkr, 1734 [CAM_CC_CPAS_SFE_LITE_1_CLK] = &cam_cc_cpas_sfe_lite_1_clk.clkr, 1735 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 1736 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 1737 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 1738 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 1739 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 1740 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 1741 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 1742 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 1743 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 1744 [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr, 1745 [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr, 1746 [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr, 1747 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 1748 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 1749 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 1750 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 1751 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 1752 [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr, 1753 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 1754 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 1755 [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, 1756 [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, 1757 [CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr, 1758 [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, 1759 [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, 1760 [CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr, 1761 [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr, 1762 [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, 1763 [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, 1764 [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, 1765 [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, 1766 [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, 1767 [CAM_CC_IPE_AHB_CLK] = &cam_cc_ipe_ahb_clk.clkr, 1768 [CAM_CC_IPE_CLK] = &cam_cc_ipe_clk.clkr, 1769 [CAM_CC_IPE_CLK_SRC] = &cam_cc_ipe_clk_src.clkr, 1770 [CAM_CC_IPE_FAST_AHB_CLK] = &cam_cc_ipe_fast_ahb_clk.clkr, 1771 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 1772 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 1773 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 1774 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 1775 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 1776 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 1777 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 1778 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 1779 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 1780 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, 1781 [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, 1782 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 1783 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 1784 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, 1785 [CAM_CC_PLL4] = &cam_cc_pll4.clkr, 1786 [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, 1787 [CAM_CC_PLL5] = &cam_cc_pll5.clkr, 1788 [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr, 1789 [CAM_CC_SFE_LITE_0_CLK] = &cam_cc_sfe_lite_0_clk.clkr, 1790 [CAM_CC_SFE_LITE_0_FAST_AHB_CLK] = &cam_cc_sfe_lite_0_fast_ahb_clk.clkr, 1791 [CAM_CC_SFE_LITE_1_CLK] = &cam_cc_sfe_lite_1_clk.clkr, 1792 [CAM_CC_SFE_LITE_1_FAST_AHB_CLK] = &cam_cc_sfe_lite_1_fast_ahb_clk.clkr, 1793 [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, 1794 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 1795 [CAM_CC_SM_OBS_CLK] = &cam_cc_sm_obs_clk.clkr, 1796 [CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] = NULL, 1797 [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, 1798 [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr, 1799 }; 1800 1801 static struct gdsc *cam_cc_sa8775p_gdscs[] = { 1802 [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc, 1803 }; 1804 1805 static const struct qcom_reset_map cam_cc_sa8775p_resets[] = { 1806 [CAM_CC_ICP_BCR] = { 0x13078 }, 1807 [CAM_CC_IFE_0_BCR] = { 0x11000 }, 1808 [CAM_CC_IFE_1_BCR] = { 0x12000 }, 1809 [CAM_CC_IPE_0_BCR] = { 0x10000 }, 1810 [CAM_CC_SFE_LITE_0_BCR] = { 0x13048 }, 1811 [CAM_CC_SFE_LITE_1_BCR] = { 0x13060 }, 1812 }; 1813 1814 static const struct regmap_config cam_cc_sa8775p_regmap_config = { 1815 .reg_bits = 32, 1816 .reg_stride = 4, 1817 .val_bits = 32, 1818 .max_register = 0x16218, 1819 .fast_io = true, 1820 }; 1821 1822 static const struct qcom_cc_desc cam_cc_sa8775p_desc = { 1823 .config = &cam_cc_sa8775p_regmap_config, 1824 .clks = cam_cc_sa8775p_clocks, 1825 .num_clks = ARRAY_SIZE(cam_cc_sa8775p_clocks), 1826 .resets = cam_cc_sa8775p_resets, 1827 .num_resets = ARRAY_SIZE(cam_cc_sa8775p_resets), 1828 .gdscs = cam_cc_sa8775p_gdscs, 1829 .num_gdscs = ARRAY_SIZE(cam_cc_sa8775p_gdscs), 1830 }; 1831 1832 static const struct of_device_id cam_cc_sa8775p_match_table[] = { 1833 { .compatible = "qcom,qcs8300-camcc" }, 1834 { .compatible = "qcom,sa8775p-camcc" }, 1835 { } 1836 }; 1837 MODULE_DEVICE_TABLE(of, cam_cc_sa8775p_match_table); 1838 1839 static int cam_cc_sa8775p_probe(struct platform_device *pdev) 1840 { 1841 struct regmap *regmap; 1842 int ret; 1843 1844 ret = devm_pm_runtime_enable(&pdev->dev); 1845 if (ret) 1846 return ret; 1847 1848 ret = pm_runtime_resume_and_get(&pdev->dev); 1849 if (ret) 1850 return ret; 1851 1852 regmap = qcom_cc_map(pdev, &cam_cc_sa8775p_desc); 1853 if (IS_ERR(regmap)) { 1854 pm_runtime_put(&pdev->dev); 1855 return PTR_ERR(regmap); 1856 } 1857 1858 clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); 1859 clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); 1860 clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); 1861 clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); 1862 clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); 1863 1864 if (device_is_compatible(&pdev->dev, "qcom,qcs8300-camcc")) { 1865 cam_cc_camnoc_axi_clk_src.cmd_rcgr = 0x13154; 1866 cam_cc_camnoc_axi_clk.halt_reg = 0x1316c; 1867 cam_cc_camnoc_axi_clk.clkr.enable_reg = 0x1316c; 1868 cam_cc_camnoc_dcd_xo_clk.halt_reg = 0x13174; 1869 cam_cc_camnoc_dcd_xo_clk.clkr.enable_reg = 0x13174; 1870 1871 cam_cc_csi0phytimer_clk_src.cmd_rcgr = 0x15054; 1872 cam_cc_csi1phytimer_clk_src.cmd_rcgr = 0x15078; 1873 cam_cc_csi2phytimer_clk_src.cmd_rcgr = 0x15098; 1874 cam_cc_csid_clk_src.cmd_rcgr = 0x13134; 1875 1876 cam_cc_mclk0_clk_src.cmd_rcgr = 0x15000; 1877 cam_cc_mclk1_clk_src.cmd_rcgr = 0x1501c; 1878 cam_cc_mclk2_clk_src.cmd_rcgr = 0x15038; 1879 1880 cam_cc_fast_ahb_clk_src.cmd_rcgr = 0x13104; 1881 cam_cc_slow_ahb_clk_src.cmd_rcgr = 0x1311c; 1882 cam_cc_xo_clk_src.cmd_rcgr = 0x131b8; 1883 cam_cc_sleep_clk_src.cmd_rcgr = 0x131d4; 1884 1885 cam_cc_core_ahb_clk.halt_reg = 0x131b4; 1886 cam_cc_core_ahb_clk.clkr.enable_reg = 0x131b4; 1887 1888 cam_cc_cpas_ahb_clk.halt_reg = 0x130f4; 1889 cam_cc_cpas_ahb_clk.clkr.enable_reg = 0x130f4; 1890 cam_cc_cpas_fast_ahb_clk.halt_reg = 0x130fc; 1891 cam_cc_cpas_fast_ahb_clk.clkr.enable_reg = 0x130fc; 1892 1893 cam_cc_csi0phytimer_clk.halt_reg = 0x1506c; 1894 cam_cc_csi0phytimer_clk.clkr.enable_reg = 0x1506c; 1895 cam_cc_csi1phytimer_clk.halt_reg = 0x15090; 1896 cam_cc_csi1phytimer_clk.clkr.enable_reg = 0x15090; 1897 cam_cc_csi2phytimer_clk.halt_reg = 0x150b0; 1898 cam_cc_csi2phytimer_clk.clkr.enable_reg = 0x150b0; 1899 cam_cc_csid_clk.halt_reg = 0x1314c; 1900 cam_cc_csid_clk.clkr.enable_reg = 0x1314c; 1901 cam_cc_csid_csiphy_rx_clk.halt_reg = 0x15074; 1902 cam_cc_csid_csiphy_rx_clk.clkr.enable_reg = 0x15074; 1903 cam_cc_csiphy0_clk.halt_reg = 0x15070; 1904 cam_cc_csiphy0_clk.clkr.enable_reg = 0x15070; 1905 cam_cc_csiphy1_clk.halt_reg = 0x15094; 1906 cam_cc_csiphy1_clk.clkr.enable_reg = 0x15094; 1907 cam_cc_csiphy2_clk.halt_reg = 0x150b4; 1908 cam_cc_csiphy2_clk.clkr.enable_reg = 0x150b4; 1909 1910 cam_cc_mclk0_clk.halt_reg = 0x15018; 1911 cam_cc_mclk0_clk.clkr.enable_reg = 0x15018; 1912 cam_cc_mclk1_clk.halt_reg = 0x15034; 1913 cam_cc_mclk1_clk.clkr.enable_reg = 0x15034; 1914 cam_cc_mclk2_clk.halt_reg = 0x15050; 1915 cam_cc_mclk2_clk.clkr.enable_reg = 0x15050; 1916 cam_cc_qdss_debug_xo_clk.halt_reg = 0x1319c; 1917 cam_cc_qdss_debug_xo_clk.clkr.enable_reg = 0x1319c; 1918 1919 cam_cc_titan_top_gdsc.gdscr = 0x131a0; 1920 1921 cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK] = NULL; 1922 cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK_SRC] = NULL; 1923 cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK] = NULL; 1924 cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK_SRC] = NULL; 1925 cam_cc_sa8775p_clocks[CAM_CC_CSIPHY3_CLK] = NULL; 1926 cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK] = NULL; 1927 cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK_SRC] = NULL; 1928 cam_cc_sa8775p_clocks[CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] = 1929 &cam_cc_titan_top_accu_shift_clk.clkr; 1930 1931 /* Keep some clocks always enabled */ 1932 qcom_branch_set_clk_en(regmap, 0x13178); /* CAM_CC_CAMNOC_XO_CLK */ 1933 qcom_branch_set_clk_en(regmap, 0x131d0); /* CAM_CC_GDSC_CLK */ 1934 qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_SLEEP_CLK */ 1935 } else { 1936 /* Keep some clocks always enabled */ 1937 qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */ 1938 qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */ 1939 qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */ 1940 } 1941 1942 ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sa8775p_desc, regmap); 1943 1944 pm_runtime_put(&pdev->dev); 1945 1946 return ret; 1947 } 1948 1949 static struct platform_driver cam_cc_sa8775p_driver = { 1950 .probe = cam_cc_sa8775p_probe, 1951 .driver = { 1952 .name = "camcc-sa8775p", 1953 .of_match_table = cam_cc_sa8775p_match_table, 1954 }, 1955 }; 1956 1957 module_platform_driver(cam_cc_sa8775p_driver); 1958 1959 MODULE_DESCRIPTION("QTI CAMCC SA8775P Driver"); 1960 MODULE_LICENSE("GPL"); 1961