1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/pm_runtime.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,qcs8300-camcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-pll.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "clk-regmap-divider.h" 20 #include "clk-regmap-mux.h" 21 #include "common.h" 22 #include "gdsc.h" 23 #include "reset.h" 24 25 enum { 26 DT_IFACE, 27 DT_BI_TCXO, 28 DT_BI_TCXO_AO, 29 DT_SLEEP_CLK, 30 }; 31 32 enum { 33 P_BI_TCXO, 34 P_BI_TCXO_AO, 35 P_CAM_CC_PLL0_OUT_EVEN, 36 P_CAM_CC_PLL0_OUT_MAIN, 37 P_CAM_CC_PLL0_OUT_ODD, 38 P_CAM_CC_PLL2_OUT_EVEN, 39 P_CAM_CC_PLL2_OUT_MAIN, 40 P_CAM_CC_PLL3_OUT_EVEN, 41 P_CAM_CC_PLL4_OUT_EVEN, 42 P_CAM_CC_PLL5_OUT_EVEN, 43 P_SLEEP_CLK, 44 }; 45 46 static const struct pll_vco lucid_evo_vco[] = { 47 { 249600000, 2020000000, 0 }, 48 }; 49 50 static const struct pll_vco rivian_evo_vco[] = { 51 { 864000000, 1056000000, 0 }, 52 }; 53 54 static const struct alpha_pll_config cam_cc_pll0_config = { 55 .l = 0x3e, 56 .alpha = 0x8000, 57 .config_ctl_val = 0x20485699, 58 .config_ctl_hi_val = 0x00182261, 59 .config_ctl_hi1_val = 0x32aa299c, 60 .user_ctl_val = 0x00008400, 61 .user_ctl_hi_val = 0x00400805, 62 }; 63 64 static struct clk_alpha_pll cam_cc_pll0 = { 65 .offset = 0x0, 66 .vco_table = lucid_evo_vco, 67 .num_vco = ARRAY_SIZE(lucid_evo_vco), 68 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 69 .clkr = { 70 .hw.init = &(const struct clk_init_data) { 71 .name = "cam_cc_pll0", 72 .parent_data = &(const struct clk_parent_data) { 73 .index = DT_BI_TCXO, 74 }, 75 .num_parents = 1, 76 .ops = &clk_alpha_pll_lucid_evo_ops, 77 }, 78 }, 79 }; 80 81 static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { 82 { 0x1, 2 }, 83 { } 84 }; 85 86 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { 87 .offset = 0x0, 88 .post_div_shift = 10, 89 .post_div_table = post_div_table_cam_cc_pll0_out_even, 90 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), 91 .width = 4, 92 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 93 .clkr.hw.init = &(const struct clk_init_data) { 94 .name = "cam_cc_pll0_out_even", 95 .parent_hws = (const struct clk_hw*[]) { 96 &cam_cc_pll0.clkr.hw, 97 }, 98 .num_parents = 1, 99 .flags = CLK_SET_RATE_PARENT, 100 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 101 }, 102 }; 103 104 static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { 105 { 0x2, 3 }, 106 { } 107 }; 108 109 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { 110 .offset = 0x0, 111 .post_div_shift = 14, 112 .post_div_table = post_div_table_cam_cc_pll0_out_odd, 113 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), 114 .width = 4, 115 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 116 .clkr.hw.init = &(const struct clk_init_data) { 117 .name = "cam_cc_pll0_out_odd", 118 .parent_hws = (const struct clk_hw*[]) { 119 &cam_cc_pll0.clkr.hw, 120 }, 121 .num_parents = 1, 122 .flags = CLK_SET_RATE_PARENT, 123 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 124 }, 125 }; 126 127 static const struct alpha_pll_config cam_cc_pll2_config = { 128 .l = 0x32, 129 .alpha = 0x0, 130 .config_ctl_val = 0x90008820, 131 .config_ctl_hi_val = 0x00890263, 132 .config_ctl_hi1_val = 0x00000247, 133 .user_ctl_val = 0x00000000, 134 .user_ctl_hi_val = 0x00400000, 135 }; 136 137 static struct clk_alpha_pll cam_cc_pll2 = { 138 .offset = 0x1000, 139 .vco_table = rivian_evo_vco, 140 .num_vco = ARRAY_SIZE(rivian_evo_vco), 141 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], 142 .clkr = { 143 .hw.init = &(const struct clk_init_data) { 144 .name = "cam_cc_pll2", 145 .parent_data = &(const struct clk_parent_data) { 146 .index = DT_BI_TCXO, 147 }, 148 .num_parents = 1, 149 .ops = &clk_alpha_pll_rivian_evo_ops, 150 }, 151 }, 152 }; 153 154 static const struct alpha_pll_config cam_cc_pll3_config = { 155 .l = 0x32, 156 .alpha = 0x0, 157 .config_ctl_val = 0x20485699, 158 .config_ctl_hi_val = 0x00182261, 159 .config_ctl_hi1_val = 0x32aa299c, 160 .user_ctl_val = 0x00000400, 161 .user_ctl_hi_val = 0x00400805, 162 }; 163 164 static struct clk_alpha_pll cam_cc_pll3 = { 165 .offset = 0x2000, 166 .vco_table = lucid_evo_vco, 167 .num_vco = ARRAY_SIZE(lucid_evo_vco), 168 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 169 .clkr = { 170 .hw.init = &(const struct clk_init_data) { 171 .name = "cam_cc_pll3", 172 .parent_data = &(const struct clk_parent_data) { 173 .index = DT_BI_TCXO, 174 }, 175 .num_parents = 1, 176 .ops = &clk_alpha_pll_lucid_evo_ops, 177 }, 178 }, 179 }; 180 181 static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { 182 { 0x1, 2 }, 183 { } 184 }; 185 186 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 187 .offset = 0x2000, 188 .post_div_shift = 10, 189 .post_div_table = post_div_table_cam_cc_pll3_out_even, 190 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), 191 .width = 4, 192 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 193 .clkr.hw.init = &(const struct clk_init_data) { 194 .name = "cam_cc_pll3_out_even", 195 .parent_hws = (const struct clk_hw*[]) { 196 &cam_cc_pll3.clkr.hw, 197 }, 198 .num_parents = 1, 199 .flags = CLK_SET_RATE_PARENT, 200 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 201 }, 202 }; 203 204 static const struct alpha_pll_config cam_cc_pll4_config = { 205 .l = 0x32, 206 .alpha = 0x0, 207 .config_ctl_val = 0x20485699, 208 .config_ctl_hi_val = 0x00182261, 209 .config_ctl_hi1_val = 0x32aa299c, 210 .user_ctl_val = 0x00000400, 211 .user_ctl_hi_val = 0x00400805, 212 }; 213 214 static struct clk_alpha_pll cam_cc_pll4 = { 215 .offset = 0x3000, 216 .vco_table = lucid_evo_vco, 217 .num_vco = ARRAY_SIZE(lucid_evo_vco), 218 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 219 .clkr = { 220 .hw.init = &(const struct clk_init_data) { 221 .name = "cam_cc_pll4", 222 .parent_data = &(const struct clk_parent_data) { 223 .index = DT_BI_TCXO, 224 }, 225 .num_parents = 1, 226 .ops = &clk_alpha_pll_lucid_evo_ops, 227 }, 228 }, 229 }; 230 231 static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { 232 { 0x1, 2 }, 233 { } 234 }; 235 236 static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { 237 .offset = 0x3000, 238 .post_div_shift = 10, 239 .post_div_table = post_div_table_cam_cc_pll4_out_even, 240 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), 241 .width = 4, 242 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 243 .clkr.hw.init = &(const struct clk_init_data) { 244 .name = "cam_cc_pll4_out_even", 245 .parent_hws = (const struct clk_hw*[]) { 246 &cam_cc_pll4.clkr.hw, 247 }, 248 .num_parents = 1, 249 .flags = CLK_SET_RATE_PARENT, 250 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 251 }, 252 }; 253 254 static const struct alpha_pll_config cam_cc_pll5_config = { 255 .l = 0x32, 256 .alpha = 0x0, 257 .config_ctl_val = 0x20485699, 258 .config_ctl_hi_val = 0x00182261, 259 .config_ctl_hi1_val = 0x32aa299c, 260 .user_ctl_val = 0x00000400, 261 .user_ctl_hi_val = 0x00400805, 262 }; 263 264 static struct clk_alpha_pll cam_cc_pll5 = { 265 .offset = 0x4000, 266 .vco_table = lucid_evo_vco, 267 .num_vco = ARRAY_SIZE(lucid_evo_vco), 268 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 269 .clkr = { 270 .hw.init = &(const struct clk_init_data) { 271 .name = "cam_cc_pll5", 272 .parent_data = &(const struct clk_parent_data) { 273 .index = DT_BI_TCXO, 274 }, 275 .num_parents = 1, 276 .ops = &clk_alpha_pll_lucid_evo_ops, 277 }, 278 }, 279 }; 280 281 static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = { 282 { 0x1, 2 }, 283 { } 284 }; 285 286 static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { 287 .offset = 0x4000, 288 .post_div_shift = 10, 289 .post_div_table = post_div_table_cam_cc_pll5_out_even, 290 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), 291 .width = 4, 292 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 293 .clkr.hw.init = &(const struct clk_init_data) { 294 .name = "cam_cc_pll5_out_even", 295 .parent_hws = (const struct clk_hw*[]) { 296 &cam_cc_pll5.clkr.hw, 297 }, 298 .num_parents = 1, 299 .flags = CLK_SET_RATE_PARENT, 300 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 301 }, 302 }; 303 304 static const struct parent_map cam_cc_parent_map_0[] = { 305 { P_BI_TCXO, 0 }, 306 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 307 { P_CAM_CC_PLL0_OUT_EVEN, 2 }, 308 { P_CAM_CC_PLL0_OUT_ODD, 3 }, 309 }; 310 311 static const struct clk_parent_data cam_cc_parent_data_0[] = { 312 { .index = DT_BI_TCXO }, 313 { .hw = &cam_cc_pll0.clkr.hw }, 314 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 315 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 316 }; 317 318 static const struct parent_map cam_cc_parent_map_1[] = { 319 { P_BI_TCXO, 0 }, 320 { P_CAM_CC_PLL2_OUT_EVEN, 3 }, 321 { P_CAM_CC_PLL2_OUT_MAIN, 5 }, 322 }; 323 324 static const struct clk_parent_data cam_cc_parent_data_1[] = { 325 { .index = DT_BI_TCXO }, 326 { .hw = &cam_cc_pll2.clkr.hw }, 327 { .hw = &cam_cc_pll2.clkr.hw }, 328 }; 329 330 static const struct parent_map cam_cc_parent_map_2[] = { 331 { P_BI_TCXO, 0 }, 332 { P_CAM_CC_PLL4_OUT_EVEN, 6 }, 333 }; 334 335 static const struct clk_parent_data cam_cc_parent_data_2[] = { 336 { .index = DT_BI_TCXO }, 337 { .hw = &cam_cc_pll4_out_even.clkr.hw }, 338 }; 339 340 static const struct parent_map cam_cc_parent_map_3[] = { 341 { P_BI_TCXO, 0 }, 342 { P_CAM_CC_PLL5_OUT_EVEN, 6 }, 343 }; 344 345 static const struct clk_parent_data cam_cc_parent_data_3[] = { 346 { .index = DT_BI_TCXO }, 347 { .hw = &cam_cc_pll5_out_even.clkr.hw }, 348 }; 349 350 static const struct parent_map cam_cc_parent_map_4[] = { 351 { P_BI_TCXO, 0 }, 352 { P_CAM_CC_PLL3_OUT_EVEN, 6 }, 353 }; 354 355 static const struct clk_parent_data cam_cc_parent_data_4[] = { 356 { .index = DT_BI_TCXO }, 357 { .hw = &cam_cc_pll3_out_even.clkr.hw }, 358 }; 359 360 static const struct parent_map cam_cc_parent_map_5[] = { 361 { P_SLEEP_CLK, 0 }, 362 }; 363 364 static const struct clk_parent_data cam_cc_parent_data_5[] = { 365 { .index = DT_SLEEP_CLK }, 366 }; 367 368 static const struct parent_map cam_cc_parent_map_6_ao[] = { 369 { P_BI_TCXO_AO, 0 }, 370 }; 371 372 static const struct clk_parent_data cam_cc_parent_data_6_ao[] = { 373 { .index = DT_BI_TCXO_AO }, 374 }; 375 376 static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = { 377 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 378 { } 379 }; 380 381 static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = { 382 .cmd_rcgr = 0x13170, 383 .mnd_width = 0, 384 .hid_width = 5, 385 .parent_map = cam_cc_parent_map_0, 386 .freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src, 387 .clkr.hw.init = &(const struct clk_init_data) { 388 .name = "cam_cc_camnoc_axi_clk_src", 389 .parent_data = cam_cc_parent_data_0, 390 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 391 .flags = CLK_SET_RATE_PARENT, 392 .ops = &clk_rcg2_shared_ops, 393 }, 394 }; 395 396 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { 397 F(37500000, P_CAM_CC_PLL0_OUT_MAIN, 16, 1, 2), 398 { } 399 }; 400 401 static struct clk_rcg2 cam_cc_cci_0_clk_src = { 402 .cmd_rcgr = 0x130a0, 403 .mnd_width = 8, 404 .hid_width = 5, 405 .parent_map = cam_cc_parent_map_0, 406 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 407 .clkr.hw.init = &(const struct clk_init_data) { 408 .name = "cam_cc_cci_0_clk_src", 409 .parent_data = cam_cc_parent_data_0, 410 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 411 .flags = CLK_SET_RATE_PARENT, 412 .ops = &clk_rcg2_shared_ops, 413 }, 414 }; 415 416 static struct clk_rcg2 cam_cc_cci_1_clk_src = { 417 .cmd_rcgr = 0x130bc, 418 .mnd_width = 8, 419 .hid_width = 5, 420 .parent_map = cam_cc_parent_map_0, 421 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 422 .clkr.hw.init = &(const struct clk_init_data) { 423 .name = "cam_cc_cci_1_clk_src", 424 .parent_data = cam_cc_parent_data_0, 425 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 426 .flags = CLK_SET_RATE_PARENT, 427 .ops = &clk_rcg2_shared_ops, 428 }, 429 }; 430 431 static struct clk_rcg2 cam_cc_cci_2_clk_src = { 432 .cmd_rcgr = 0x130d8, 433 .mnd_width = 8, 434 .hid_width = 5, 435 .parent_map = cam_cc_parent_map_0, 436 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 437 .clkr.hw.init = &(const struct clk_init_data) { 438 .name = "cam_cc_cci_2_clk_src", 439 .parent_data = cam_cc_parent_data_0, 440 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 441 .flags = CLK_SET_RATE_PARENT, 442 .ops = &clk_rcg2_shared_ops, 443 }, 444 }; 445 446 static struct clk_rcg2 cam_cc_cci_3_clk_src = { 447 .cmd_rcgr = 0x130f4, 448 .mnd_width = 8, 449 .hid_width = 5, 450 .parent_map = cam_cc_parent_map_0, 451 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 452 .clkr.hw.init = &(const struct clk_init_data) { 453 .name = "cam_cc_cci_3_clk_src", 454 .parent_data = cam_cc_parent_data_0, 455 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 456 .flags = CLK_SET_RATE_PARENT, 457 .ops = &clk_rcg2_shared_ops, 458 }, 459 }; 460 461 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 462 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 463 { } 464 }; 465 466 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 467 .cmd_rcgr = 0x11034, 468 .mnd_width = 0, 469 .hid_width = 5, 470 .parent_map = cam_cc_parent_map_0, 471 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 472 .clkr.hw.init = &(const struct clk_init_data) { 473 .name = "cam_cc_cphy_rx_clk_src", 474 .parent_data = cam_cc_parent_data_0, 475 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 476 .flags = CLK_SET_RATE_PARENT, 477 .ops = &clk_rcg2_shared_ops, 478 }, 479 }; 480 481 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 482 .cmd_rcgr = 0x15074, 483 .mnd_width = 0, 484 .hid_width = 5, 485 .parent_map = cam_cc_parent_map_0, 486 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 487 .clkr.hw.init = &(const struct clk_init_data) { 488 .name = "cam_cc_csi0phytimer_clk_src", 489 .parent_data = cam_cc_parent_data_0, 490 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 491 .flags = CLK_SET_RATE_PARENT, 492 .ops = &clk_rcg2_shared_ops, 493 }, 494 }; 495 496 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 497 .cmd_rcgr = 0x15098, 498 .mnd_width = 0, 499 .hid_width = 5, 500 .parent_map = cam_cc_parent_map_0, 501 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 502 .clkr.hw.init = &(const struct clk_init_data) { 503 .name = "cam_cc_csi1phytimer_clk_src", 504 .parent_data = cam_cc_parent_data_0, 505 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 506 .flags = CLK_SET_RATE_PARENT, 507 .ops = &clk_rcg2_shared_ops, 508 }, 509 }; 510 511 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 512 .cmd_rcgr = 0x150b8, 513 .mnd_width = 0, 514 .hid_width = 5, 515 .parent_map = cam_cc_parent_map_0, 516 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 517 .clkr.hw.init = &(const struct clk_init_data) { 518 .name = "cam_cc_csi2phytimer_clk_src", 519 .parent_data = cam_cc_parent_data_0, 520 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 521 .flags = CLK_SET_RATE_PARENT, 522 .ops = &clk_rcg2_shared_ops, 523 }, 524 }; 525 526 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 527 .cmd_rcgr = 0x150d8, 528 .mnd_width = 0, 529 .hid_width = 5, 530 .parent_map = cam_cc_parent_map_0, 531 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 532 .clkr.hw.init = &(const struct clk_init_data) { 533 .name = "cam_cc_csi3phytimer_clk_src", 534 .parent_data = cam_cc_parent_data_0, 535 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 536 .flags = CLK_SET_RATE_PARENT, 537 .ops = &clk_rcg2_shared_ops, 538 }, 539 }; 540 541 static struct clk_rcg2 cam_cc_csid_clk_src = { 542 .cmd_rcgr = 0x13150, 543 .mnd_width = 0, 544 .hid_width = 5, 545 .parent_map = cam_cc_parent_map_0, 546 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 547 .clkr.hw.init = &(const struct clk_init_data) { 548 .name = "cam_cc_csid_clk_src", 549 .parent_data = cam_cc_parent_data_0, 550 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 551 .flags = CLK_SET_RATE_PARENT, 552 .ops = &clk_rcg2_shared_ops, 553 }, 554 }; 555 556 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 557 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), 558 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 559 { } 560 }; 561 562 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 563 .cmd_rcgr = 0x13120, 564 .mnd_width = 0, 565 .hid_width = 5, 566 .parent_map = cam_cc_parent_map_0, 567 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 568 .clkr.hw.init = &(const struct clk_init_data) { 569 .name = "cam_cc_fast_ahb_clk_src", 570 .parent_data = cam_cc_parent_data_0, 571 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 572 .flags = CLK_SET_RATE_PARENT, 573 .ops = &clk_rcg2_shared_ops, 574 }, 575 }; 576 577 static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 578 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 579 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 580 { } 581 }; 582 583 static struct clk_rcg2 cam_cc_icp_clk_src = { 584 .cmd_rcgr = 0x1307c, 585 .mnd_width = 0, 586 .hid_width = 5, 587 .parent_map = cam_cc_parent_map_0, 588 .freq_tbl = ftbl_cam_cc_icp_clk_src, 589 .clkr.hw.init = &(const struct clk_init_data) { 590 .name = "cam_cc_icp_clk_src", 591 .parent_data = cam_cc_parent_data_0, 592 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 593 .flags = CLK_SET_RATE_PARENT, 594 .ops = &clk_rcg2_shared_ops, 595 }, 596 }; 597 598 static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { 599 F(480000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 600 F(600000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 601 { } 602 }; 603 604 static struct clk_rcg2 cam_cc_ife_0_clk_src = { 605 .cmd_rcgr = 0x11004, 606 .mnd_width = 0, 607 .hid_width = 5, 608 .parent_map = cam_cc_parent_map_2, 609 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 610 .clkr.hw.init = &(const struct clk_init_data) { 611 .name = "cam_cc_ife_0_clk_src", 612 .parent_data = cam_cc_parent_data_2, 613 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 614 .flags = CLK_SET_RATE_PARENT, 615 .ops = &clk_rcg2_shared_ops, 616 }, 617 }; 618 619 static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = { 620 F(480000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 621 F(600000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 622 { } 623 }; 624 625 static struct clk_rcg2 cam_cc_ife_1_clk_src = { 626 .cmd_rcgr = 0x12004, 627 .mnd_width = 0, 628 .hid_width = 5, 629 .parent_map = cam_cc_parent_map_3, 630 .freq_tbl = ftbl_cam_cc_ife_1_clk_src, 631 .clkr.hw.init = &(const struct clk_init_data) { 632 .name = "cam_cc_ife_1_clk_src", 633 .parent_data = cam_cc_parent_data_3, 634 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 635 .flags = CLK_SET_RATE_PARENT, 636 .ops = &clk_rcg2_shared_ops, 637 }, 638 }; 639 640 static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = { 641 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 642 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 643 { } 644 }; 645 646 static struct clk_rcg2 cam_cc_ife_lite_clk_src = { 647 .cmd_rcgr = 0x13000, 648 .mnd_width = 0, 649 .hid_width = 5, 650 .parent_map = cam_cc_parent_map_0, 651 .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, 652 .clkr.hw.init = &(const struct clk_init_data) { 653 .name = "cam_cc_ife_lite_clk_src", 654 .parent_data = cam_cc_parent_data_0, 655 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 656 .flags = CLK_SET_RATE_PARENT, 657 .ops = &clk_rcg2_shared_ops, 658 }, 659 }; 660 661 static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { 662 .cmd_rcgr = 0x13020, 663 .mnd_width = 0, 664 .hid_width = 5, 665 .parent_map = cam_cc_parent_map_0, 666 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 667 .clkr.hw.init = &(const struct clk_init_data) { 668 .name = "cam_cc_ife_lite_csid_clk_src", 669 .parent_data = cam_cc_parent_data_0, 670 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 671 .flags = CLK_SET_RATE_PARENT, 672 .ops = &clk_rcg2_shared_ops, 673 }, 674 }; 675 676 static const struct freq_tbl ftbl_cam_cc_ipe_clk_src[] = { 677 F(480000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 678 F(600000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 679 { } 680 }; 681 682 static struct clk_rcg2 cam_cc_ipe_clk_src = { 683 .cmd_rcgr = 0x10004, 684 .mnd_width = 0, 685 .hid_width = 5, 686 .parent_map = cam_cc_parent_map_4, 687 .freq_tbl = ftbl_cam_cc_ipe_clk_src, 688 .clkr.hw.init = &(const struct clk_init_data) { 689 .name = "cam_cc_ipe_clk_src", 690 .parent_data = cam_cc_parent_data_4, 691 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 692 .flags = CLK_SET_RATE_PARENT, 693 .ops = &clk_rcg2_shared_ops, 694 }, 695 }; 696 697 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 698 F(19200000, P_CAM_CC_PLL2_OUT_MAIN, 1, 1, 50), 699 F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4), 700 F(64000000, P_CAM_CC_PLL2_OUT_MAIN, 15, 0, 0), 701 { } 702 }; 703 704 static struct clk_rcg2 cam_cc_mclk0_clk_src = { 705 .cmd_rcgr = 0x15004, 706 .mnd_width = 8, 707 .hid_width = 5, 708 .parent_map = cam_cc_parent_map_1, 709 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 710 .clkr.hw.init = &(const struct clk_init_data) { 711 .name = "cam_cc_mclk0_clk_src", 712 .parent_data = cam_cc_parent_data_1, 713 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 714 .flags = CLK_SET_RATE_PARENT, 715 .ops = &clk_rcg2_shared_ops, 716 }, 717 }; 718 719 static struct clk_rcg2 cam_cc_mclk1_clk_src = { 720 .cmd_rcgr = 0x15020, 721 .mnd_width = 8, 722 .hid_width = 5, 723 .parent_map = cam_cc_parent_map_1, 724 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 725 .clkr.hw.init = &(const struct clk_init_data) { 726 .name = "cam_cc_mclk1_clk_src", 727 .parent_data = cam_cc_parent_data_1, 728 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 729 .flags = CLK_SET_RATE_PARENT, 730 .ops = &clk_rcg2_shared_ops, 731 }, 732 }; 733 734 static struct clk_rcg2 cam_cc_mclk2_clk_src = { 735 .cmd_rcgr = 0x1503c, 736 .mnd_width = 8, 737 .hid_width = 5, 738 .parent_map = cam_cc_parent_map_1, 739 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 740 .clkr.hw.init = &(const struct clk_init_data) { 741 .name = "cam_cc_mclk2_clk_src", 742 .parent_data = cam_cc_parent_data_1, 743 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 744 .flags = CLK_SET_RATE_PARENT, 745 .ops = &clk_rcg2_shared_ops, 746 }, 747 }; 748 749 static struct clk_rcg2 cam_cc_mclk3_clk_src = { 750 .cmd_rcgr = 0x15058, 751 .mnd_width = 8, 752 .hid_width = 5, 753 .parent_map = cam_cc_parent_map_1, 754 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 755 .clkr.hw.init = &(const struct clk_init_data) { 756 .name = "cam_cc_mclk3_clk_src", 757 .parent_data = cam_cc_parent_data_1, 758 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 759 .flags = CLK_SET_RATE_PARENT, 760 .ops = &clk_rcg2_shared_ops, 761 }, 762 }; 763 764 static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { 765 F(32000, P_SLEEP_CLK, 1, 0, 0), 766 { } 767 }; 768 769 static struct clk_rcg2 cam_cc_sleep_clk_src = { 770 .cmd_rcgr = 0x131f0, 771 .mnd_width = 0, 772 .hid_width = 5, 773 .parent_map = cam_cc_parent_map_5, 774 .freq_tbl = ftbl_cam_cc_sleep_clk_src, 775 .clkr.hw.init = &(const struct clk_init_data) { 776 .name = "cam_cc_sleep_clk_src", 777 .parent_data = cam_cc_parent_data_5, 778 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 779 .flags = CLK_SET_RATE_PARENT, 780 .ops = &clk_rcg2_shared_ops, 781 }, 782 }; 783 784 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 785 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 786 { } 787 }; 788 789 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 790 .cmd_rcgr = 0x13138, 791 .mnd_width = 8, 792 .hid_width = 5, 793 .parent_map = cam_cc_parent_map_0, 794 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 795 .clkr.hw.init = &(const struct clk_init_data) { 796 .name = "cam_cc_slow_ahb_clk_src", 797 .parent_data = cam_cc_parent_data_0, 798 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 799 .flags = CLK_SET_RATE_PARENT, 800 .ops = &clk_rcg2_shared_ops, 801 }, 802 }; 803 804 static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { 805 F(19200000, P_BI_TCXO_AO, 1, 0, 0), 806 { } 807 }; 808 809 static struct clk_rcg2 cam_cc_xo_clk_src = { 810 .cmd_rcgr = 0x131d4, 811 .mnd_width = 0, 812 .hid_width = 5, 813 .parent_map = cam_cc_parent_map_6_ao, 814 .freq_tbl = ftbl_cam_cc_xo_clk_src, 815 .clkr.hw.init = &(const struct clk_init_data) { 816 .name = "cam_cc_xo_clk_src", 817 .parent_data = cam_cc_parent_data_6_ao, 818 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6_ao), 819 .flags = CLK_SET_RATE_PARENT, 820 .ops = &clk_rcg2_shared_ops, 821 }, 822 }; 823 824 static struct clk_branch cam_cc_camnoc_axi_clk = { 825 .halt_reg = 0x13188, 826 .halt_check = BRANCH_HALT, 827 .clkr = { 828 .enable_reg = 0x13188, 829 .enable_mask = BIT(0), 830 .hw.init = &(const struct clk_init_data) { 831 .name = "cam_cc_camnoc_axi_clk", 832 .parent_hws = (const struct clk_hw*[]) { 833 &cam_cc_camnoc_axi_clk_src.clkr.hw, 834 }, 835 .num_parents = 1, 836 .flags = CLK_SET_RATE_PARENT, 837 .ops = &clk_branch2_ops, 838 }, 839 }, 840 }; 841 842 static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { 843 .halt_reg = 0x13190, 844 .halt_check = BRANCH_HALT, 845 .clkr = { 846 .enable_reg = 0x13190, 847 .enable_mask = BIT(0), 848 .hw.init = &(const struct clk_init_data) { 849 .name = "cam_cc_camnoc_dcd_xo_clk", 850 .parent_hws = (const struct clk_hw*[]) { 851 &cam_cc_xo_clk_src.clkr.hw, 852 }, 853 .num_parents = 1, 854 .flags = CLK_SET_RATE_PARENT, 855 .ops = &clk_branch2_ops, 856 }, 857 }, 858 }; 859 860 static struct clk_branch cam_cc_qdss_debug_xo_clk = { 861 .halt_reg = 0x131b8, 862 .halt_check = BRANCH_HALT, 863 .clkr = { 864 .enable_reg = 0x131b8, 865 .enable_mask = BIT(0), 866 .hw.init = &(const struct clk_init_data) { 867 .name = "cam_cc_qdss_debug_xo_clk", 868 .parent_hws = (const struct clk_hw*[]) { 869 &cam_cc_xo_clk_src.clkr.hw, 870 }, 871 .num_parents = 1, 872 .flags = CLK_SET_RATE_PARENT, 873 .ops = &clk_branch2_ops, 874 }, 875 }, 876 }; 877 878 static struct clk_branch cam_cc_cci_0_clk = { 879 .halt_reg = 0x130b8, 880 .halt_check = BRANCH_HALT, 881 .clkr = { 882 .enable_reg = 0x130b8, 883 .enable_mask = BIT(0), 884 .hw.init = &(const struct clk_init_data) { 885 .name = "cam_cc_cci_0_clk", 886 .parent_hws = (const struct clk_hw*[]) { 887 &cam_cc_cci_0_clk_src.clkr.hw, 888 }, 889 .num_parents = 1, 890 .flags = CLK_SET_RATE_PARENT, 891 .ops = &clk_branch2_ops, 892 }, 893 }, 894 }; 895 896 static struct clk_branch cam_cc_cci_1_clk = { 897 .halt_reg = 0x130d4, 898 .halt_check = BRANCH_HALT, 899 .clkr = { 900 .enable_reg = 0x130d4, 901 .enable_mask = BIT(0), 902 .hw.init = &(const struct clk_init_data) { 903 .name = "cam_cc_cci_1_clk", 904 .parent_hws = (const struct clk_hw*[]) { 905 &cam_cc_cci_1_clk_src.clkr.hw, 906 }, 907 .num_parents = 1, 908 .flags = CLK_SET_RATE_PARENT, 909 .ops = &clk_branch2_ops, 910 }, 911 }, 912 }; 913 914 static struct clk_branch cam_cc_cci_2_clk = { 915 .halt_reg = 0x130f0, 916 .halt_check = BRANCH_HALT, 917 .clkr = { 918 .enable_reg = 0x130f0, 919 .enable_mask = BIT(0), 920 .hw.init = &(const struct clk_init_data) { 921 .name = "cam_cc_cci_2_clk", 922 .parent_hws = (const struct clk_hw*[]) { 923 &cam_cc_cci_2_clk_src.clkr.hw, 924 }, 925 .num_parents = 1, 926 .flags = CLK_SET_RATE_PARENT, 927 .ops = &clk_branch2_ops, 928 }, 929 }, 930 }; 931 932 static struct clk_branch cam_cc_cci_3_clk = { 933 .halt_reg = 0x1310c, 934 .halt_check = BRANCH_HALT, 935 .clkr = { 936 .enable_reg = 0x1310c, 937 .enable_mask = BIT(0), 938 .hw.init = &(const struct clk_init_data) { 939 .name = "cam_cc_cci_3_clk", 940 .parent_hws = (const struct clk_hw*[]) { 941 &cam_cc_cci_3_clk_src.clkr.hw, 942 }, 943 .num_parents = 1, 944 .flags = CLK_SET_RATE_PARENT, 945 .ops = &clk_branch2_ops, 946 }, 947 }, 948 }; 949 950 static struct clk_branch cam_cc_core_ahb_clk = { 951 .halt_reg = 0x131d0, 952 .halt_check = BRANCH_HALT_DELAY, 953 .clkr = { 954 .enable_reg = 0x131d0, 955 .enable_mask = BIT(0), 956 .hw.init = &(const struct clk_init_data) { 957 .name = "cam_cc_core_ahb_clk", 958 .parent_hws = (const struct clk_hw*[]) { 959 &cam_cc_slow_ahb_clk_src.clkr.hw, 960 }, 961 .num_parents = 1, 962 .flags = CLK_SET_RATE_PARENT, 963 .ops = &clk_branch2_ops, 964 }, 965 }, 966 }; 967 968 static struct clk_branch cam_cc_cpas_ahb_clk = { 969 .halt_reg = 0x13110, 970 .halt_check = BRANCH_HALT, 971 .clkr = { 972 .enable_reg = 0x13110, 973 .enable_mask = BIT(0), 974 .hw.init = &(const struct clk_init_data) { 975 .name = "cam_cc_cpas_ahb_clk", 976 .parent_hws = (const struct clk_hw*[]) { 977 &cam_cc_slow_ahb_clk_src.clkr.hw, 978 }, 979 .num_parents = 1, 980 .flags = CLK_SET_RATE_PARENT, 981 .ops = &clk_branch2_ops, 982 }, 983 }, 984 }; 985 986 static struct clk_branch cam_cc_cpas_fast_ahb_clk = { 987 .halt_reg = 0x13118, 988 .halt_check = BRANCH_HALT, 989 .clkr = { 990 .enable_reg = 0x13118, 991 .enable_mask = BIT(0), 992 .hw.init = &(const struct clk_init_data) { 993 .name = "cam_cc_cpas_fast_ahb_clk", 994 .parent_hws = (const struct clk_hw*[]) { 995 &cam_cc_fast_ahb_clk_src.clkr.hw, 996 }, 997 .num_parents = 1, 998 .flags = CLK_SET_RATE_PARENT, 999 .ops = &clk_branch2_ops, 1000 }, 1001 }, 1002 }; 1003 1004 static struct clk_branch cam_cc_cpas_ife_0_clk = { 1005 .halt_reg = 0x11024, 1006 .halt_check = BRANCH_HALT, 1007 .clkr = { 1008 .enable_reg = 0x11024, 1009 .enable_mask = BIT(0), 1010 .hw.init = &(const struct clk_init_data) { 1011 .name = "cam_cc_cpas_ife_0_clk", 1012 .parent_hws = (const struct clk_hw*[]) { 1013 &cam_cc_ife_0_clk_src.clkr.hw, 1014 }, 1015 .num_parents = 1, 1016 .flags = CLK_SET_RATE_PARENT, 1017 .ops = &clk_branch2_ops, 1018 }, 1019 }, 1020 }; 1021 1022 static struct clk_branch cam_cc_cpas_ife_1_clk = { 1023 .halt_reg = 0x12024, 1024 .halt_check = BRANCH_HALT, 1025 .clkr = { 1026 .enable_reg = 0x12024, 1027 .enable_mask = BIT(0), 1028 .hw.init = &(const struct clk_init_data) { 1029 .name = "cam_cc_cpas_ife_1_clk", 1030 .parent_hws = (const struct clk_hw*[]) { 1031 &cam_cc_ife_1_clk_src.clkr.hw, 1032 }, 1033 .num_parents = 1, 1034 .flags = CLK_SET_RATE_PARENT, 1035 .ops = &clk_branch2_ops, 1036 }, 1037 }, 1038 }; 1039 1040 static struct clk_branch cam_cc_cpas_ife_lite_clk = { 1041 .halt_reg = 0x1301c, 1042 .halt_check = BRANCH_HALT, 1043 .clkr = { 1044 .enable_reg = 0x1301c, 1045 .enable_mask = BIT(0), 1046 .hw.init = &(const struct clk_init_data) { 1047 .name = "cam_cc_cpas_ife_lite_clk", 1048 .parent_hws = (const struct clk_hw*[]) { 1049 &cam_cc_ife_lite_clk_src.clkr.hw, 1050 }, 1051 .num_parents = 1, 1052 .flags = CLK_SET_RATE_PARENT, 1053 .ops = &clk_branch2_ops, 1054 }, 1055 }, 1056 }; 1057 1058 static struct clk_branch cam_cc_cpas_ipe_clk = { 1059 .halt_reg = 0x10024, 1060 .halt_check = BRANCH_HALT, 1061 .clkr = { 1062 .enable_reg = 0x10024, 1063 .enable_mask = BIT(0), 1064 .hw.init = &(const struct clk_init_data) { 1065 .name = "cam_cc_cpas_ipe_clk", 1066 .parent_hws = (const struct clk_hw*[]) { 1067 &cam_cc_ipe_clk_src.clkr.hw, 1068 }, 1069 .num_parents = 1, 1070 .flags = CLK_SET_RATE_PARENT, 1071 .ops = &clk_branch2_ops, 1072 }, 1073 }, 1074 }; 1075 1076 static struct clk_branch cam_cc_cpas_sfe_lite_0_clk = { 1077 .halt_reg = 0x13050, 1078 .halt_check = BRANCH_HALT, 1079 .clkr = { 1080 .enable_reg = 0x13050, 1081 .enable_mask = BIT(0), 1082 .hw.init = &(const struct clk_init_data) { 1083 .name = "cam_cc_cpas_sfe_lite_0_clk", 1084 .parent_hws = (const struct clk_hw*[]) { 1085 &cam_cc_ife_0_clk_src.clkr.hw, 1086 }, 1087 .num_parents = 1, 1088 .flags = CLK_SET_RATE_PARENT, 1089 .ops = &clk_branch2_ops, 1090 }, 1091 }, 1092 }; 1093 1094 static struct clk_branch cam_cc_cpas_sfe_lite_1_clk = { 1095 .halt_reg = 0x13068, 1096 .halt_check = BRANCH_HALT, 1097 .clkr = { 1098 .enable_reg = 0x13068, 1099 .enable_mask = BIT(0), 1100 .hw.init = &(const struct clk_init_data) { 1101 .name = "cam_cc_cpas_sfe_lite_1_clk", 1102 .parent_hws = (const struct clk_hw*[]) { 1103 &cam_cc_ife_1_clk_src.clkr.hw, 1104 }, 1105 .num_parents = 1, 1106 .flags = CLK_SET_RATE_PARENT, 1107 .ops = &clk_branch2_ops, 1108 }, 1109 }, 1110 }; 1111 1112 static struct clk_branch cam_cc_csi0phytimer_clk = { 1113 .halt_reg = 0x1508c, 1114 .halt_check = BRANCH_HALT, 1115 .clkr = { 1116 .enable_reg = 0x1508c, 1117 .enable_mask = BIT(0), 1118 .hw.init = &(const struct clk_init_data) { 1119 .name = "cam_cc_csi0phytimer_clk", 1120 .parent_hws = (const struct clk_hw*[]) { 1121 &cam_cc_csi0phytimer_clk_src.clkr.hw, 1122 }, 1123 .num_parents = 1, 1124 .flags = CLK_SET_RATE_PARENT, 1125 .ops = &clk_branch2_ops, 1126 }, 1127 }, 1128 }; 1129 1130 static struct clk_branch cam_cc_csi1phytimer_clk = { 1131 .halt_reg = 0x150b0, 1132 .halt_check = BRANCH_HALT, 1133 .clkr = { 1134 .enable_reg = 0x150b0, 1135 .enable_mask = BIT(0), 1136 .hw.init = &(const struct clk_init_data) { 1137 .name = "cam_cc_csi1phytimer_clk", 1138 .parent_hws = (const struct clk_hw*[]) { 1139 &cam_cc_csi1phytimer_clk_src.clkr.hw, 1140 }, 1141 .num_parents = 1, 1142 .flags = CLK_SET_RATE_PARENT, 1143 .ops = &clk_branch2_ops, 1144 }, 1145 }, 1146 }; 1147 1148 static struct clk_branch cam_cc_csi2phytimer_clk = { 1149 .halt_reg = 0x150d0, 1150 .halt_check = BRANCH_HALT, 1151 .clkr = { 1152 .enable_reg = 0x150d0, 1153 .enable_mask = BIT(0), 1154 .hw.init = &(const struct clk_init_data) { 1155 .name = "cam_cc_csi2phytimer_clk", 1156 .parent_hws = (const struct clk_hw*[]) { 1157 &cam_cc_csi2phytimer_clk_src.clkr.hw, 1158 }, 1159 .num_parents = 1, 1160 .flags = CLK_SET_RATE_PARENT, 1161 .ops = &clk_branch2_ops, 1162 }, 1163 }, 1164 }; 1165 1166 static struct clk_branch cam_cc_csi3phytimer_clk = { 1167 .halt_reg = 0x150f0, 1168 .halt_check = BRANCH_HALT, 1169 .clkr = { 1170 .enable_reg = 0x150f0, 1171 .enable_mask = BIT(0), 1172 .hw.init = &(const struct clk_init_data) { 1173 .name = "cam_cc_csi3phytimer_clk", 1174 .parent_hws = (const struct clk_hw*[]) { 1175 &cam_cc_csi3phytimer_clk_src.clkr.hw, 1176 }, 1177 .num_parents = 1, 1178 .flags = CLK_SET_RATE_PARENT, 1179 .ops = &clk_branch2_ops, 1180 }, 1181 }, 1182 }; 1183 1184 static struct clk_branch cam_cc_csid_clk = { 1185 .halt_reg = 0x13168, 1186 .halt_check = BRANCH_HALT, 1187 .clkr = { 1188 .enable_reg = 0x13168, 1189 .enable_mask = BIT(0), 1190 .hw.init = &(const struct clk_init_data) { 1191 .name = "cam_cc_csid_clk", 1192 .parent_hws = (const struct clk_hw*[]) { 1193 &cam_cc_csid_clk_src.clkr.hw, 1194 }, 1195 .num_parents = 1, 1196 .flags = CLK_SET_RATE_PARENT, 1197 .ops = &clk_branch2_ops, 1198 }, 1199 }, 1200 }; 1201 1202 static struct clk_branch cam_cc_csid_csiphy_rx_clk = { 1203 .halt_reg = 0x15094, 1204 .halt_check = BRANCH_HALT, 1205 .clkr = { 1206 .enable_reg = 0x15094, 1207 .enable_mask = BIT(0), 1208 .hw.init = &(const struct clk_init_data) { 1209 .name = "cam_cc_csid_csiphy_rx_clk", 1210 .parent_hws = (const struct clk_hw*[]) { 1211 &cam_cc_cphy_rx_clk_src.clkr.hw, 1212 }, 1213 .num_parents = 1, 1214 .flags = CLK_SET_RATE_PARENT, 1215 .ops = &clk_branch2_ops, 1216 }, 1217 }, 1218 }; 1219 1220 static struct clk_branch cam_cc_csiphy0_clk = { 1221 .halt_reg = 0x15090, 1222 .halt_check = BRANCH_HALT, 1223 .clkr = { 1224 .enable_reg = 0x15090, 1225 .enable_mask = BIT(0), 1226 .hw.init = &(const struct clk_init_data) { 1227 .name = "cam_cc_csiphy0_clk", 1228 .parent_hws = (const struct clk_hw*[]) { 1229 &cam_cc_cphy_rx_clk_src.clkr.hw, 1230 }, 1231 .num_parents = 1, 1232 .flags = CLK_SET_RATE_PARENT, 1233 .ops = &clk_branch2_ops, 1234 }, 1235 }, 1236 }; 1237 1238 static struct clk_branch cam_cc_csiphy1_clk = { 1239 .halt_reg = 0x150b4, 1240 .halt_check = BRANCH_HALT, 1241 .clkr = { 1242 .enable_reg = 0x150b4, 1243 .enable_mask = BIT(0), 1244 .hw.init = &(const struct clk_init_data) { 1245 .name = "cam_cc_csiphy1_clk", 1246 .parent_hws = (const struct clk_hw*[]) { 1247 &cam_cc_cphy_rx_clk_src.clkr.hw, 1248 }, 1249 .num_parents = 1, 1250 .flags = CLK_SET_RATE_PARENT, 1251 .ops = &clk_branch2_ops, 1252 }, 1253 }, 1254 }; 1255 1256 static struct clk_branch cam_cc_csiphy2_clk = { 1257 .halt_reg = 0x150d4, 1258 .halt_check = BRANCH_HALT, 1259 .clkr = { 1260 .enable_reg = 0x150d4, 1261 .enable_mask = BIT(0), 1262 .hw.init = &(const struct clk_init_data) { 1263 .name = "cam_cc_csiphy2_clk", 1264 .parent_hws = (const struct clk_hw*[]) { 1265 &cam_cc_cphy_rx_clk_src.clkr.hw, 1266 }, 1267 .num_parents = 1, 1268 .flags = CLK_SET_RATE_PARENT, 1269 .ops = &clk_branch2_ops, 1270 }, 1271 }, 1272 }; 1273 1274 static struct clk_branch cam_cc_csiphy3_clk = { 1275 .halt_reg = 0x150f4, 1276 .halt_check = BRANCH_HALT, 1277 .clkr = { 1278 .enable_reg = 0x150f4, 1279 .enable_mask = BIT(0), 1280 .hw.init = &(const struct clk_init_data) { 1281 .name = "cam_cc_csiphy3_clk", 1282 .parent_hws = (const struct clk_hw*[]) { 1283 &cam_cc_cphy_rx_clk_src.clkr.hw, 1284 }, 1285 .num_parents = 1, 1286 .flags = CLK_SET_RATE_PARENT, 1287 .ops = &clk_branch2_ops, 1288 }, 1289 }, 1290 }; 1291 1292 static struct clk_branch cam_cc_icp_ahb_clk = { 1293 .halt_reg = 0x1309c, 1294 .halt_check = BRANCH_HALT, 1295 .clkr = { 1296 .enable_reg = 0x1309c, 1297 .enable_mask = BIT(0), 1298 .hw.init = &(const struct clk_init_data) { 1299 .name = "cam_cc_icp_ahb_clk", 1300 .parent_hws = (const struct clk_hw*[]) { 1301 &cam_cc_slow_ahb_clk_src.clkr.hw, 1302 }, 1303 .num_parents = 1, 1304 .flags = CLK_SET_RATE_PARENT, 1305 .ops = &clk_branch2_ops, 1306 }, 1307 }, 1308 }; 1309 1310 static struct clk_branch cam_cc_icp_clk = { 1311 .halt_reg = 0x13094, 1312 .halt_check = BRANCH_HALT, 1313 .clkr = { 1314 .enable_reg = 0x13094, 1315 .enable_mask = BIT(0), 1316 .hw.init = &(const struct clk_init_data) { 1317 .name = "cam_cc_icp_clk", 1318 .parent_hws = (const struct clk_hw*[]) { 1319 &cam_cc_icp_clk_src.clkr.hw, 1320 }, 1321 .num_parents = 1, 1322 .flags = CLK_SET_RATE_PARENT, 1323 .ops = &clk_branch2_ops, 1324 }, 1325 }, 1326 }; 1327 1328 static struct clk_branch cam_cc_ife_0_clk = { 1329 .halt_reg = 0x1101c, 1330 .halt_check = BRANCH_HALT, 1331 .clkr = { 1332 .enable_reg = 0x1101c, 1333 .enable_mask = BIT(0), 1334 .hw.init = &(const struct clk_init_data) { 1335 .name = "cam_cc_ife_0_clk", 1336 .parent_hws = (const struct clk_hw*[]) { 1337 &cam_cc_ife_0_clk_src.clkr.hw, 1338 }, 1339 .num_parents = 1, 1340 .flags = CLK_SET_RATE_PARENT, 1341 .ops = &clk_branch2_ops, 1342 }, 1343 }, 1344 }; 1345 1346 static struct clk_branch cam_cc_ife_0_fast_ahb_clk = { 1347 .halt_reg = 0x11030, 1348 .halt_check = BRANCH_HALT, 1349 .clkr = { 1350 .enable_reg = 0x11030, 1351 .enable_mask = BIT(0), 1352 .hw.init = &(const struct clk_init_data) { 1353 .name = "cam_cc_ife_0_fast_ahb_clk", 1354 .parent_hws = (const struct clk_hw*[]) { 1355 &cam_cc_fast_ahb_clk_src.clkr.hw, 1356 }, 1357 .num_parents = 1, 1358 .flags = CLK_SET_RATE_PARENT, 1359 .ops = &clk_branch2_ops, 1360 }, 1361 }, 1362 }; 1363 1364 static struct clk_branch cam_cc_ife_1_clk = { 1365 .halt_reg = 0x1201c, 1366 .halt_check = BRANCH_HALT, 1367 .clkr = { 1368 .enable_reg = 0x1201c, 1369 .enable_mask = BIT(0), 1370 .hw.init = &(const struct clk_init_data) { 1371 .name = "cam_cc_ife_1_clk", 1372 .parent_hws = (const struct clk_hw*[]) { 1373 &cam_cc_ife_1_clk_src.clkr.hw, 1374 }, 1375 .num_parents = 1, 1376 .flags = CLK_SET_RATE_PARENT, 1377 .ops = &clk_branch2_ops, 1378 }, 1379 }, 1380 }; 1381 1382 static struct clk_branch cam_cc_ife_1_fast_ahb_clk = { 1383 .halt_reg = 0x12030, 1384 .halt_check = BRANCH_HALT, 1385 .clkr = { 1386 .enable_reg = 0x12030, 1387 .enable_mask = BIT(0), 1388 .hw.init = &(const struct clk_init_data) { 1389 .name = "cam_cc_ife_1_fast_ahb_clk", 1390 .parent_hws = (const struct clk_hw*[]) { 1391 &cam_cc_fast_ahb_clk_src.clkr.hw, 1392 }, 1393 .num_parents = 1, 1394 .flags = CLK_SET_RATE_PARENT, 1395 .ops = &clk_branch2_ops, 1396 }, 1397 }, 1398 }; 1399 1400 static struct clk_branch cam_cc_ife_lite_ahb_clk = { 1401 .halt_reg = 0x13044, 1402 .halt_check = BRANCH_HALT, 1403 .clkr = { 1404 .enable_reg = 0x13044, 1405 .enable_mask = BIT(0), 1406 .hw.init = &(const struct clk_init_data) { 1407 .name = "cam_cc_ife_lite_ahb_clk", 1408 .parent_hws = (const struct clk_hw*[]) { 1409 &cam_cc_slow_ahb_clk_src.clkr.hw, 1410 }, 1411 .num_parents = 1, 1412 .flags = CLK_SET_RATE_PARENT, 1413 .ops = &clk_branch2_ops, 1414 }, 1415 }, 1416 }; 1417 1418 static struct clk_branch cam_cc_ife_lite_clk = { 1419 .halt_reg = 0x13018, 1420 .halt_check = BRANCH_HALT, 1421 .clkr = { 1422 .enable_reg = 0x13018, 1423 .enable_mask = BIT(0), 1424 .hw.init = &(const struct clk_init_data) { 1425 .name = "cam_cc_ife_lite_clk", 1426 .parent_hws = (const struct clk_hw*[]) { 1427 &cam_cc_ife_lite_clk_src.clkr.hw, 1428 }, 1429 .num_parents = 1, 1430 .flags = CLK_SET_RATE_PARENT, 1431 .ops = &clk_branch2_ops, 1432 }, 1433 }, 1434 }; 1435 1436 static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { 1437 .halt_reg = 0x13040, 1438 .halt_check = BRANCH_HALT, 1439 .clkr = { 1440 .enable_reg = 0x13040, 1441 .enable_mask = BIT(0), 1442 .hw.init = &(const struct clk_init_data) { 1443 .name = "cam_cc_ife_lite_cphy_rx_clk", 1444 .parent_hws = (const struct clk_hw*[]) { 1445 &cam_cc_cphy_rx_clk_src.clkr.hw, 1446 }, 1447 .num_parents = 1, 1448 .flags = CLK_SET_RATE_PARENT, 1449 .ops = &clk_branch2_ops, 1450 }, 1451 }, 1452 }; 1453 1454 static struct clk_branch cam_cc_ife_lite_csid_clk = { 1455 .halt_reg = 0x13038, 1456 .halt_check = BRANCH_HALT, 1457 .clkr = { 1458 .enable_reg = 0x13038, 1459 .enable_mask = BIT(0), 1460 .hw.init = &(const struct clk_init_data) { 1461 .name = "cam_cc_ife_lite_csid_clk", 1462 .parent_hws = (const struct clk_hw*[]) { 1463 &cam_cc_ife_lite_csid_clk_src.clkr.hw, 1464 }, 1465 .num_parents = 1, 1466 .flags = CLK_SET_RATE_PARENT, 1467 .ops = &clk_branch2_ops, 1468 }, 1469 }, 1470 }; 1471 1472 static struct clk_branch cam_cc_ipe_ahb_clk = { 1473 .halt_reg = 0x10030, 1474 .halt_check = BRANCH_HALT, 1475 .clkr = { 1476 .enable_reg = 0x10030, 1477 .enable_mask = BIT(0), 1478 .hw.init = &(const struct clk_init_data) { 1479 .name = "cam_cc_ipe_ahb_clk", 1480 .parent_hws = (const struct clk_hw*[]) { 1481 &cam_cc_slow_ahb_clk_src.clkr.hw, 1482 }, 1483 .num_parents = 1, 1484 .flags = CLK_SET_RATE_PARENT, 1485 .ops = &clk_branch2_ops, 1486 }, 1487 }, 1488 }; 1489 1490 static struct clk_branch cam_cc_ipe_clk = { 1491 .halt_reg = 0x1001c, 1492 .halt_check = BRANCH_HALT, 1493 .clkr = { 1494 .enable_reg = 0x1001c, 1495 .enable_mask = BIT(0), 1496 .hw.init = &(const struct clk_init_data) { 1497 .name = "cam_cc_ipe_clk", 1498 .parent_hws = (const struct clk_hw*[]) { 1499 &cam_cc_ipe_clk_src.clkr.hw, 1500 }, 1501 .num_parents = 1, 1502 .flags = CLK_SET_RATE_PARENT, 1503 .ops = &clk_branch2_ops, 1504 }, 1505 }, 1506 }; 1507 1508 static struct clk_branch cam_cc_ipe_fast_ahb_clk = { 1509 .halt_reg = 0x10034, 1510 .halt_check = BRANCH_HALT, 1511 .clkr = { 1512 .enable_reg = 0x10034, 1513 .enable_mask = BIT(0), 1514 .hw.init = &(const struct clk_init_data) { 1515 .name = "cam_cc_ipe_fast_ahb_clk", 1516 .parent_hws = (const struct clk_hw*[]) { 1517 &cam_cc_fast_ahb_clk_src.clkr.hw, 1518 }, 1519 .num_parents = 1, 1520 .flags = CLK_SET_RATE_PARENT, 1521 .ops = &clk_branch2_ops, 1522 }, 1523 }, 1524 }; 1525 1526 static struct clk_branch cam_cc_mclk0_clk = { 1527 .halt_reg = 0x1501c, 1528 .halt_check = BRANCH_HALT, 1529 .clkr = { 1530 .enable_reg = 0x1501c, 1531 .enable_mask = BIT(0), 1532 .hw.init = &(const struct clk_init_data) { 1533 .name = "cam_cc_mclk0_clk", 1534 .parent_hws = (const struct clk_hw*[]) { 1535 &cam_cc_mclk0_clk_src.clkr.hw, 1536 }, 1537 .num_parents = 1, 1538 .flags = CLK_SET_RATE_PARENT, 1539 .ops = &clk_branch2_ops, 1540 }, 1541 }, 1542 }; 1543 1544 static struct clk_branch cam_cc_mclk1_clk = { 1545 .halt_reg = 0x15038, 1546 .halt_check = BRANCH_HALT, 1547 .clkr = { 1548 .enable_reg = 0x15038, 1549 .enable_mask = BIT(0), 1550 .hw.init = &(const struct clk_init_data) { 1551 .name = "cam_cc_mclk1_clk", 1552 .parent_hws = (const struct clk_hw*[]) { 1553 &cam_cc_mclk1_clk_src.clkr.hw, 1554 }, 1555 .num_parents = 1, 1556 .flags = CLK_SET_RATE_PARENT, 1557 .ops = &clk_branch2_ops, 1558 }, 1559 }, 1560 }; 1561 1562 static struct clk_branch cam_cc_mclk2_clk = { 1563 .halt_reg = 0x15054, 1564 .halt_check = BRANCH_HALT, 1565 .clkr = { 1566 .enable_reg = 0x15054, 1567 .enable_mask = BIT(0), 1568 .hw.init = &(const struct clk_init_data) { 1569 .name = "cam_cc_mclk2_clk", 1570 .parent_hws = (const struct clk_hw*[]) { 1571 &cam_cc_mclk2_clk_src.clkr.hw, 1572 }, 1573 .num_parents = 1, 1574 .flags = CLK_SET_RATE_PARENT, 1575 .ops = &clk_branch2_ops, 1576 }, 1577 }, 1578 }; 1579 1580 static struct clk_branch cam_cc_mclk3_clk = { 1581 .halt_reg = 0x15070, 1582 .halt_check = BRANCH_HALT, 1583 .clkr = { 1584 .enable_reg = 0x15070, 1585 .enable_mask = BIT(0), 1586 .hw.init = &(const struct clk_init_data) { 1587 .name = "cam_cc_mclk3_clk", 1588 .parent_hws = (const struct clk_hw*[]) { 1589 &cam_cc_mclk3_clk_src.clkr.hw, 1590 }, 1591 .num_parents = 1, 1592 .flags = CLK_SET_RATE_PARENT, 1593 .ops = &clk_branch2_ops, 1594 }, 1595 }, 1596 }; 1597 1598 static struct clk_branch cam_cc_sfe_lite_0_clk = { 1599 .halt_reg = 0x1304c, 1600 .halt_check = BRANCH_HALT, 1601 .clkr = { 1602 .enable_reg = 0x1304c, 1603 .enable_mask = BIT(0), 1604 .hw.init = &(const struct clk_init_data) { 1605 .name = "cam_cc_sfe_lite_0_clk", 1606 .parent_hws = (const struct clk_hw*[]) { 1607 &cam_cc_ife_0_clk_src.clkr.hw, 1608 }, 1609 .num_parents = 1, 1610 .flags = CLK_SET_RATE_PARENT, 1611 .ops = &clk_branch2_ops, 1612 }, 1613 }, 1614 }; 1615 1616 static struct clk_branch cam_cc_sfe_lite_0_fast_ahb_clk = { 1617 .halt_reg = 0x1305c, 1618 .halt_check = BRANCH_HALT, 1619 .clkr = { 1620 .enable_reg = 0x1305c, 1621 .enable_mask = BIT(0), 1622 .hw.init = &(const struct clk_init_data) { 1623 .name = "cam_cc_sfe_lite_0_fast_ahb_clk", 1624 .parent_hws = (const struct clk_hw*[]) { 1625 &cam_cc_fast_ahb_clk_src.clkr.hw, 1626 }, 1627 .num_parents = 1, 1628 .flags = CLK_SET_RATE_PARENT, 1629 .ops = &clk_branch2_ops, 1630 }, 1631 }, 1632 }; 1633 1634 static struct clk_branch cam_cc_sfe_lite_1_clk = { 1635 .halt_reg = 0x13064, 1636 .halt_check = BRANCH_HALT, 1637 .clkr = { 1638 .enable_reg = 0x13064, 1639 .enable_mask = BIT(0), 1640 .hw.init = &(const struct clk_init_data) { 1641 .name = "cam_cc_sfe_lite_1_clk", 1642 .parent_hws = (const struct clk_hw*[]) { 1643 &cam_cc_ife_1_clk_src.clkr.hw, 1644 }, 1645 .num_parents = 1, 1646 .flags = CLK_SET_RATE_PARENT, 1647 .ops = &clk_branch2_ops, 1648 }, 1649 }, 1650 }; 1651 1652 static struct clk_branch cam_cc_sfe_lite_1_fast_ahb_clk = { 1653 .halt_reg = 0x13074, 1654 .halt_check = BRANCH_HALT, 1655 .clkr = { 1656 .enable_reg = 0x13074, 1657 .enable_mask = BIT(0), 1658 .hw.init = &(const struct clk_init_data) { 1659 .name = "cam_cc_sfe_lite_1_fast_ahb_clk", 1660 .parent_hws = (const struct clk_hw*[]) { 1661 &cam_cc_fast_ahb_clk_src.clkr.hw, 1662 }, 1663 .num_parents = 1, 1664 .flags = CLK_SET_RATE_PARENT, 1665 .ops = &clk_branch2_ops, 1666 }, 1667 }, 1668 }; 1669 1670 static struct clk_branch cam_cc_sm_obs_clk = { 1671 .halt_reg = 0x1510c, 1672 .halt_check = BRANCH_HALT_SKIP, 1673 .clkr = { 1674 .enable_reg = 0x1510c, 1675 .enable_mask = BIT(0), 1676 .hw.init = &(const struct clk_init_data) { 1677 .name = "cam_cc_sm_obs_clk", 1678 .ops = &clk_branch2_ops, 1679 }, 1680 }, 1681 }; 1682 1683 static struct clk_branch cam_cc_titan_top_accu_shift_clk = { 1684 .halt_reg = 0x131f0, 1685 .halt_check = BRANCH_HALT_VOTED, 1686 .clkr = { 1687 .enable_reg = 0x131f0, 1688 .enable_mask = BIT(0), 1689 .hw.init = &(const struct clk_init_data) { 1690 .name = "cam_cc_titan_top_accu_shift_clk", 1691 .parent_hws = (const struct clk_hw*[]) { 1692 &cam_cc_xo_clk_src.clkr.hw, 1693 }, 1694 .num_parents = 1, 1695 .flags = CLK_SET_RATE_PARENT, 1696 .ops = &clk_branch2_ops, 1697 }, 1698 }, 1699 }; 1700 1701 static struct gdsc cam_cc_titan_top_gdsc = { 1702 .gdscr = 0x131bc, 1703 .en_rest_wait_val = 0x2, 1704 .en_few_wait_val = 0x2, 1705 .clk_dis_wait_val = 0xf, 1706 .pd = { 1707 .name = "cam_cc_titan_top_gdsc", 1708 }, 1709 .pwrsts = PWRSTS_OFF_ON, 1710 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1711 }; 1712 1713 static struct clk_regmap *cam_cc_sa8775p_clocks[] = { 1714 [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr, 1715 [CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr, 1716 [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, 1717 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, 1718 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, 1719 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, 1720 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, 1721 [CAM_CC_CCI_2_CLK] = &cam_cc_cci_2_clk.clkr, 1722 [CAM_CC_CCI_2_CLK_SRC] = &cam_cc_cci_2_clk_src.clkr, 1723 [CAM_CC_CCI_3_CLK] = &cam_cc_cci_3_clk.clkr, 1724 [CAM_CC_CCI_3_CLK_SRC] = &cam_cc_cci_3_clk_src.clkr, 1725 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 1726 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 1727 [CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr, 1728 [CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr, 1729 [CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr, 1730 [CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr, 1731 [CAM_CC_CPAS_IPE_CLK] = &cam_cc_cpas_ipe_clk.clkr, 1732 [CAM_CC_CPAS_SFE_LITE_0_CLK] = &cam_cc_cpas_sfe_lite_0_clk.clkr, 1733 [CAM_CC_CPAS_SFE_LITE_1_CLK] = &cam_cc_cpas_sfe_lite_1_clk.clkr, 1734 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 1735 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 1736 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 1737 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 1738 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 1739 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 1740 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 1741 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 1742 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 1743 [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr, 1744 [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr, 1745 [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr, 1746 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 1747 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 1748 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 1749 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 1750 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 1751 [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr, 1752 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 1753 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 1754 [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, 1755 [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, 1756 [CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr, 1757 [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, 1758 [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, 1759 [CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr, 1760 [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr, 1761 [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, 1762 [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, 1763 [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, 1764 [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, 1765 [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, 1766 [CAM_CC_IPE_AHB_CLK] = &cam_cc_ipe_ahb_clk.clkr, 1767 [CAM_CC_IPE_CLK] = &cam_cc_ipe_clk.clkr, 1768 [CAM_CC_IPE_CLK_SRC] = &cam_cc_ipe_clk_src.clkr, 1769 [CAM_CC_IPE_FAST_AHB_CLK] = &cam_cc_ipe_fast_ahb_clk.clkr, 1770 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 1771 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 1772 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 1773 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 1774 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 1775 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 1776 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 1777 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 1778 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 1779 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, 1780 [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, 1781 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 1782 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 1783 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, 1784 [CAM_CC_PLL4] = &cam_cc_pll4.clkr, 1785 [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, 1786 [CAM_CC_PLL5] = &cam_cc_pll5.clkr, 1787 [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr, 1788 [CAM_CC_SFE_LITE_0_CLK] = &cam_cc_sfe_lite_0_clk.clkr, 1789 [CAM_CC_SFE_LITE_0_FAST_AHB_CLK] = &cam_cc_sfe_lite_0_fast_ahb_clk.clkr, 1790 [CAM_CC_SFE_LITE_1_CLK] = &cam_cc_sfe_lite_1_clk.clkr, 1791 [CAM_CC_SFE_LITE_1_FAST_AHB_CLK] = &cam_cc_sfe_lite_1_fast_ahb_clk.clkr, 1792 [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, 1793 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 1794 [CAM_CC_SM_OBS_CLK] = &cam_cc_sm_obs_clk.clkr, 1795 [CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] = NULL, 1796 [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, 1797 [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr, 1798 }; 1799 1800 static struct gdsc *cam_cc_sa8775p_gdscs[] = { 1801 [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc, 1802 }; 1803 1804 static const struct qcom_reset_map cam_cc_sa8775p_resets[] = { 1805 [CAM_CC_ICP_BCR] = { 0x13078 }, 1806 [CAM_CC_IFE_0_BCR] = { 0x11000 }, 1807 [CAM_CC_IFE_1_BCR] = { 0x12000 }, 1808 [CAM_CC_IPE_0_BCR] = { 0x10000 }, 1809 [CAM_CC_SFE_LITE_0_BCR] = { 0x13048 }, 1810 [CAM_CC_SFE_LITE_1_BCR] = { 0x13060 }, 1811 }; 1812 1813 static const struct regmap_config cam_cc_sa8775p_regmap_config = { 1814 .reg_bits = 32, 1815 .reg_stride = 4, 1816 .val_bits = 32, 1817 .max_register = 0x16218, 1818 .fast_io = true, 1819 }; 1820 1821 static const struct qcom_cc_desc cam_cc_sa8775p_desc = { 1822 .config = &cam_cc_sa8775p_regmap_config, 1823 .clks = cam_cc_sa8775p_clocks, 1824 .num_clks = ARRAY_SIZE(cam_cc_sa8775p_clocks), 1825 .resets = cam_cc_sa8775p_resets, 1826 .num_resets = ARRAY_SIZE(cam_cc_sa8775p_resets), 1827 .gdscs = cam_cc_sa8775p_gdscs, 1828 .num_gdscs = ARRAY_SIZE(cam_cc_sa8775p_gdscs), 1829 }; 1830 1831 static const struct of_device_id cam_cc_sa8775p_match_table[] = { 1832 { .compatible = "qcom,qcs8300-camcc" }, 1833 { .compatible = "qcom,sa8775p-camcc" }, 1834 { } 1835 }; 1836 MODULE_DEVICE_TABLE(of, cam_cc_sa8775p_match_table); 1837 1838 static int cam_cc_sa8775p_probe(struct platform_device *pdev) 1839 { 1840 struct regmap *regmap; 1841 int ret; 1842 1843 ret = devm_pm_runtime_enable(&pdev->dev); 1844 if (ret) 1845 return ret; 1846 1847 ret = pm_runtime_resume_and_get(&pdev->dev); 1848 if (ret) 1849 return ret; 1850 1851 regmap = qcom_cc_map(pdev, &cam_cc_sa8775p_desc); 1852 if (IS_ERR(regmap)) { 1853 pm_runtime_put(&pdev->dev); 1854 return PTR_ERR(regmap); 1855 } 1856 1857 clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); 1858 clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); 1859 clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); 1860 clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); 1861 clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); 1862 1863 if (device_is_compatible(&pdev->dev, "qcom,qcs8300-camcc")) { 1864 cam_cc_camnoc_axi_clk_src.cmd_rcgr = 0x13154; 1865 cam_cc_camnoc_axi_clk.halt_reg = 0x1316c; 1866 cam_cc_camnoc_axi_clk.clkr.enable_reg = 0x1316c; 1867 cam_cc_camnoc_dcd_xo_clk.halt_reg = 0x13174; 1868 cam_cc_camnoc_dcd_xo_clk.clkr.enable_reg = 0x13174; 1869 1870 cam_cc_csi0phytimer_clk_src.cmd_rcgr = 0x15054; 1871 cam_cc_csi1phytimer_clk_src.cmd_rcgr = 0x15078; 1872 cam_cc_csi2phytimer_clk_src.cmd_rcgr = 0x15098; 1873 cam_cc_csid_clk_src.cmd_rcgr = 0x13134; 1874 1875 cam_cc_mclk0_clk_src.cmd_rcgr = 0x15000; 1876 cam_cc_mclk1_clk_src.cmd_rcgr = 0x1501c; 1877 cam_cc_mclk2_clk_src.cmd_rcgr = 0x15038; 1878 1879 cam_cc_fast_ahb_clk_src.cmd_rcgr = 0x13104; 1880 cam_cc_slow_ahb_clk_src.cmd_rcgr = 0x1311c; 1881 cam_cc_xo_clk_src.cmd_rcgr = 0x131b8; 1882 cam_cc_sleep_clk_src.cmd_rcgr = 0x131d4; 1883 1884 cam_cc_core_ahb_clk.halt_reg = 0x131b4; 1885 cam_cc_core_ahb_clk.clkr.enable_reg = 0x131b4; 1886 1887 cam_cc_cpas_ahb_clk.halt_reg = 0x130f4; 1888 cam_cc_cpas_ahb_clk.clkr.enable_reg = 0x130f4; 1889 cam_cc_cpas_fast_ahb_clk.halt_reg = 0x130fc; 1890 cam_cc_cpas_fast_ahb_clk.clkr.enable_reg = 0x130fc; 1891 1892 cam_cc_csi0phytimer_clk.halt_reg = 0x1506c; 1893 cam_cc_csi0phytimer_clk.clkr.enable_reg = 0x1506c; 1894 cam_cc_csi1phytimer_clk.halt_reg = 0x15090; 1895 cam_cc_csi1phytimer_clk.clkr.enable_reg = 0x15090; 1896 cam_cc_csi2phytimer_clk.halt_reg = 0x150b0; 1897 cam_cc_csi2phytimer_clk.clkr.enable_reg = 0x150b0; 1898 cam_cc_csid_clk.halt_reg = 0x1314c; 1899 cam_cc_csid_clk.clkr.enable_reg = 0x1314c; 1900 cam_cc_csid_csiphy_rx_clk.halt_reg = 0x15074; 1901 cam_cc_csid_csiphy_rx_clk.clkr.enable_reg = 0x15074; 1902 cam_cc_csiphy0_clk.halt_reg = 0x15070; 1903 cam_cc_csiphy0_clk.clkr.enable_reg = 0x15070; 1904 cam_cc_csiphy1_clk.halt_reg = 0x15094; 1905 cam_cc_csiphy1_clk.clkr.enable_reg = 0x15094; 1906 cam_cc_csiphy2_clk.halt_reg = 0x150b4; 1907 cam_cc_csiphy2_clk.clkr.enable_reg = 0x150b4; 1908 1909 cam_cc_mclk0_clk.halt_reg = 0x15018; 1910 cam_cc_mclk0_clk.clkr.enable_reg = 0x15018; 1911 cam_cc_mclk1_clk.halt_reg = 0x15034; 1912 cam_cc_mclk1_clk.clkr.enable_reg = 0x15034; 1913 cam_cc_mclk2_clk.halt_reg = 0x15050; 1914 cam_cc_mclk2_clk.clkr.enable_reg = 0x15050; 1915 cam_cc_qdss_debug_xo_clk.halt_reg = 0x1319c; 1916 cam_cc_qdss_debug_xo_clk.clkr.enable_reg = 0x1319c; 1917 1918 cam_cc_titan_top_gdsc.gdscr = 0x131a0; 1919 1920 cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK] = NULL; 1921 cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK_SRC] = NULL; 1922 cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK] = NULL; 1923 cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK_SRC] = NULL; 1924 cam_cc_sa8775p_clocks[CAM_CC_CSIPHY3_CLK] = NULL; 1925 cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK] = NULL; 1926 cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK_SRC] = NULL; 1927 cam_cc_sa8775p_clocks[CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] = 1928 &cam_cc_titan_top_accu_shift_clk.clkr; 1929 1930 /* Keep some clocks always enabled */ 1931 qcom_branch_set_clk_en(regmap, 0x13178); /* CAM_CC_CAMNOC_XO_CLK */ 1932 qcom_branch_set_clk_en(regmap, 0x131d0); /* CAM_CC_GDSC_CLK */ 1933 qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_SLEEP_CLK */ 1934 } else { 1935 /* Keep some clocks always enabled */ 1936 qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */ 1937 qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */ 1938 qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */ 1939 } 1940 1941 ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sa8775p_desc, regmap); 1942 1943 pm_runtime_put(&pdev->dev); 1944 1945 return ret; 1946 } 1947 1948 static struct platform_driver cam_cc_sa8775p_driver = { 1949 .probe = cam_cc_sa8775p_probe, 1950 .driver = { 1951 .name = "camcc-sa8775p", 1952 .of_match_table = cam_cc_sa8775p_match_table, 1953 }, 1954 }; 1955 1956 module_platform_driver(cam_cc_sa8775p_driver); 1957 1958 MODULE_DESCRIPTION("QTI CAMCC SA8775P Driver"); 1959 MODULE_LICENSE("GPL"); 1960