1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,glymur-camcc.h> 12 13 #include "clk-alpha-pll.h" 14 #include "clk-branch.h" 15 #include "clk-rcg.h" 16 #include "clk-regmap.h" 17 #include "common.h" 18 #include "gdsc.h" 19 #include "reset.h" 20 21 enum { 22 DT_IFACE, 23 DT_BI_TCXO, 24 DT_BI_TCXO_AO, 25 DT_SLEEP_CLK, 26 }; 27 28 enum { 29 P_BI_TCXO, 30 P_BI_TCXO_AO, 31 P_CAM_CC_PLL0_OUT_EVEN, 32 P_CAM_CC_PLL0_OUT_MAIN, 33 P_CAM_CC_PLL0_OUT_ODD, 34 P_CAM_CC_PLL1_OUT_EVEN, 35 P_CAM_CC_PLL2_OUT_EVEN, 36 P_CAM_CC_PLL2_OUT_MAIN, 37 P_CAM_CC_PLL3_OUT_EVEN, 38 P_CAM_CC_PLL4_OUT_EVEN, 39 P_CAM_CC_PLL5_OUT_EVEN, 40 P_SLEEP_CLK, 41 }; 42 43 static const struct pll_vco rivian_eko_t_vco[] = { 44 { 883200000, 1171200000, 0 }, 45 }; 46 47 static const struct pll_vco taycan_eko_t_vco[] = { 48 { 249600000, 2500000000, 0 }, 49 }; 50 51 /* 1200.0 MHz Configuration */ 52 static const struct alpha_pll_config cam_cc_pll0_config = { 53 .l = 0x3e, 54 .alpha = 0x8000, 55 .config_ctl_val = 0x25c400e7, 56 .config_ctl_hi_val = 0x0a8060e0, 57 .config_ctl_hi1_val = 0xf51dea20, 58 .user_ctl_val = 0x00008408, 59 .user_ctl_hi_val = 0x00000002, 60 }; 61 62 static struct clk_alpha_pll cam_cc_pll0 = { 63 .offset = 0x0, 64 .config = &cam_cc_pll0_config, 65 .vco_table = taycan_eko_t_vco, 66 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 67 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 68 .clkr = { 69 .hw.init = &(const struct clk_init_data) { 70 .name = "cam_cc_pll0", 71 .parent_data = &(const struct clk_parent_data) { 72 .index = DT_BI_TCXO, 73 }, 74 .num_parents = 1, 75 .ops = &clk_alpha_pll_taycan_eko_t_ops, 76 }, 77 }, 78 }; 79 80 static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { 81 { 0x1, 2 }, 82 { } 83 }; 84 85 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { 86 .offset = 0x0, 87 .post_div_shift = 10, 88 .post_div_table = post_div_table_cam_cc_pll0_out_even, 89 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), 90 .width = 4, 91 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 92 .clkr.hw.init = &(const struct clk_init_data) { 93 .name = "cam_cc_pll0_out_even", 94 .parent_hws = (const struct clk_hw*[]) { 95 &cam_cc_pll0.clkr.hw, 96 }, 97 .num_parents = 1, 98 .flags = CLK_SET_RATE_PARENT, 99 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 100 }, 101 }; 102 103 static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { 104 { 0x2, 3 }, 105 { } 106 }; 107 108 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { 109 .offset = 0x0, 110 .post_div_shift = 14, 111 .post_div_table = post_div_table_cam_cc_pll0_out_odd, 112 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), 113 .width = 4, 114 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 115 .clkr.hw.init = &(const struct clk_init_data) { 116 .name = "cam_cc_pll0_out_odd", 117 .parent_hws = (const struct clk_hw*[]) { 118 &cam_cc_pll0.clkr.hw, 119 }, 120 .num_parents = 1, 121 .flags = CLK_SET_RATE_PARENT, 122 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 123 }, 124 }; 125 126 /* 608.0 MHz Configuration */ 127 static const struct alpha_pll_config cam_cc_pll1_config = { 128 .l = 0x1f, 129 .alpha = 0xaaaa, 130 .config_ctl_val = 0x25c400e7, 131 .config_ctl_hi_val = 0x0a8060e0, 132 .config_ctl_hi1_val = 0xf51dea20, 133 .user_ctl_val = 0x00000408, 134 .user_ctl_hi_val = 0x00000002, 135 }; 136 137 static struct clk_alpha_pll cam_cc_pll1 = { 138 .offset = 0x1000, 139 .config = &cam_cc_pll1_config, 140 .vco_table = taycan_eko_t_vco, 141 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 142 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 143 .clkr = { 144 .hw.init = &(const struct clk_init_data) { 145 .name = "cam_cc_pll1", 146 .parent_data = &(const struct clk_parent_data) { 147 .index = DT_BI_TCXO, 148 }, 149 .num_parents = 1, 150 .ops = &clk_alpha_pll_taycan_eko_t_ops, 151 }, 152 }, 153 }; 154 155 static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { 156 { 0x1, 2 }, 157 { } 158 }; 159 160 static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { 161 .offset = 0x1000, 162 .post_div_shift = 10, 163 .post_div_table = post_div_table_cam_cc_pll1_out_even, 164 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), 165 .width = 4, 166 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 167 .clkr.hw.init = &(const struct clk_init_data) { 168 .name = "cam_cc_pll1_out_even", 169 .parent_hws = (const struct clk_hw*[]) { 170 &cam_cc_pll1.clkr.hw, 171 }, 172 .num_parents = 1, 173 .flags = CLK_SET_RATE_PARENT, 174 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 175 }, 176 }; 177 178 /* 960.0 MHz Configuration */ 179 static const struct alpha_pll_config cam_cc_pll2_config = { 180 .l = 0x32, 181 .alpha = 0x0, 182 .config_ctl_val = 0x12000000, 183 .config_ctl_hi_val = 0x00890263, 184 .config_ctl_hi1_val = 0x1af04237, 185 .config_ctl_hi2_val = 0x00000000, 186 }; 187 188 static struct clk_alpha_pll cam_cc_pll2 = { 189 .offset = 0x2000, 190 .config = &cam_cc_pll2_config, 191 .vco_table = rivian_eko_t_vco, 192 .num_vco = ARRAY_SIZE(rivian_eko_t_vco), 193 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EKO_T], 194 .clkr = { 195 .hw.init = &(const struct clk_init_data) { 196 .name = "cam_cc_pll2", 197 .parent_data = &(const struct clk_parent_data) { 198 .index = DT_BI_TCXO, 199 }, 200 .num_parents = 1, 201 .ops = &clk_alpha_pll_rivian_eko_t_ops, 202 }, 203 }, 204 }; 205 206 /* 691.2 MHz Configuration */ 207 static const struct alpha_pll_config cam_cc_pll3_config = { 208 .l = 0x24, 209 .alpha = 0x0, 210 .config_ctl_val = 0x25c400e7, 211 .config_ctl_hi_val = 0x0a8060e0, 212 .config_ctl_hi1_val = 0xf51dea20, 213 .user_ctl_val = 0x00000408, 214 .user_ctl_hi_val = 0x00000002, 215 }; 216 217 static struct clk_alpha_pll cam_cc_pll3 = { 218 .offset = 0x3000, 219 .config = &cam_cc_pll3_config, 220 .vco_table = taycan_eko_t_vco, 221 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 222 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 223 .clkr = { 224 .hw.init = &(const struct clk_init_data) { 225 .name = "cam_cc_pll3", 226 .parent_data = &(const struct clk_parent_data) { 227 .index = DT_BI_TCXO, 228 }, 229 .num_parents = 1, 230 .ops = &clk_alpha_pll_taycan_eko_t_ops, 231 }, 232 }, 233 }; 234 235 static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { 236 { 0x1, 2 }, 237 { } 238 }; 239 240 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 241 .offset = 0x3000, 242 .post_div_shift = 10, 243 .post_div_table = post_div_table_cam_cc_pll3_out_even, 244 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), 245 .width = 4, 246 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 247 .clkr.hw.init = &(const struct clk_init_data) { 248 .name = "cam_cc_pll3_out_even", 249 .parent_hws = (const struct clk_hw*[]) { 250 &cam_cc_pll3.clkr.hw, 251 }, 252 .num_parents = 1, 253 .flags = CLK_SET_RATE_PARENT, 254 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 255 }, 256 }; 257 258 /* 691.2 MHz Configuration */ 259 static const struct alpha_pll_config cam_cc_pll4_config = { 260 .l = 0x24, 261 .alpha = 0x0, 262 .config_ctl_val = 0x25c400e7, 263 .config_ctl_hi_val = 0x0a8060e0, 264 .config_ctl_hi1_val = 0xf51dea20, 265 .user_ctl_val = 0x00000408, 266 .user_ctl_hi_val = 0x00000002, 267 }; 268 269 static struct clk_alpha_pll cam_cc_pll4 = { 270 .offset = 0x4000, 271 .config = &cam_cc_pll4_config, 272 .vco_table = taycan_eko_t_vco, 273 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 274 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 275 .clkr = { 276 .hw.init = &(const struct clk_init_data) { 277 .name = "cam_cc_pll4", 278 .parent_data = &(const struct clk_parent_data) { 279 .index = DT_BI_TCXO, 280 }, 281 .num_parents = 1, 282 .ops = &clk_alpha_pll_taycan_eko_t_ops, 283 }, 284 }, 285 }; 286 287 static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { 288 { 0x1, 2 }, 289 { } 290 }; 291 292 static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { 293 .offset = 0x4000, 294 .post_div_shift = 10, 295 .post_div_table = post_div_table_cam_cc_pll4_out_even, 296 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), 297 .width = 4, 298 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 299 .clkr.hw.init = &(const struct clk_init_data) { 300 .name = "cam_cc_pll4_out_even", 301 .parent_hws = (const struct clk_hw*[]) { 302 &cam_cc_pll4.clkr.hw, 303 }, 304 .num_parents = 1, 305 .flags = CLK_SET_RATE_PARENT, 306 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 307 }, 308 }; 309 310 /* 960.0 MHz Configuration */ 311 static const struct alpha_pll_config cam_cc_pll5_config = { 312 .l = 0x32, 313 .alpha = 0x0, 314 .config_ctl_val = 0x25c400e7, 315 .config_ctl_hi_val = 0x0a8060e0, 316 .config_ctl_hi1_val = 0xf51dea20, 317 .user_ctl_val = 0x00000408, 318 .user_ctl_hi_val = 0x00000002, 319 }; 320 321 static struct clk_alpha_pll cam_cc_pll5 = { 322 .offset = 0x5000, 323 .config = &cam_cc_pll5_config, 324 .vco_table = taycan_eko_t_vco, 325 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 326 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 327 .clkr = { 328 .hw.init = &(const struct clk_init_data) { 329 .name = "cam_cc_pll5", 330 .parent_data = &(const struct clk_parent_data) { 331 .index = DT_BI_TCXO, 332 }, 333 .num_parents = 1, 334 .ops = &clk_alpha_pll_taycan_eko_t_ops, 335 }, 336 }, 337 }; 338 339 static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = { 340 { 0x1, 2 }, 341 { } 342 }; 343 344 static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { 345 .offset = 0x5000, 346 .post_div_shift = 10, 347 .post_div_table = post_div_table_cam_cc_pll5_out_even, 348 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), 349 .width = 4, 350 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 351 .clkr.hw.init = &(const struct clk_init_data) { 352 .name = "cam_cc_pll5_out_even", 353 .parent_hws = (const struct clk_hw*[]) { 354 &cam_cc_pll5.clkr.hw, 355 }, 356 .num_parents = 1, 357 .flags = CLK_SET_RATE_PARENT, 358 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 359 }, 360 }; 361 362 static const struct parent_map cam_cc_parent_map_0[] = { 363 { P_BI_TCXO, 0 }, 364 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 365 { P_CAM_CC_PLL0_OUT_EVEN, 2 }, 366 { P_CAM_CC_PLL0_OUT_ODD, 3 }, 367 { P_CAM_CC_PLL5_OUT_EVEN, 5 }, 368 }; 369 370 static const struct clk_parent_data cam_cc_parent_data_0[] = { 371 { .index = DT_BI_TCXO }, 372 { .hw = &cam_cc_pll0.clkr.hw }, 373 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 374 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 375 { .hw = &cam_cc_pll5_out_even.clkr.hw }, 376 }; 377 378 static const struct parent_map cam_cc_parent_map_1[] = { 379 { P_BI_TCXO, 0 }, 380 { P_CAM_CC_PLL2_OUT_EVEN, 3 }, 381 { P_CAM_CC_PLL2_OUT_MAIN, 5 }, 382 }; 383 384 static const struct clk_parent_data cam_cc_parent_data_1[] = { 385 { .index = DT_BI_TCXO }, 386 { .hw = &cam_cc_pll2.clkr.hw }, 387 { .hw = &cam_cc_pll2.clkr.hw }, 388 }; 389 390 static const struct parent_map cam_cc_parent_map_2[] = { 391 { P_BI_TCXO, 0 }, 392 { P_CAM_CC_PLL3_OUT_EVEN, 6 }, 393 }; 394 395 static const struct clk_parent_data cam_cc_parent_data_2[] = { 396 { .index = DT_BI_TCXO }, 397 { .hw = &cam_cc_pll3_out_even.clkr.hw }, 398 }; 399 400 static const struct parent_map cam_cc_parent_map_3[] = { 401 { P_BI_TCXO, 0 }, 402 { P_CAM_CC_PLL4_OUT_EVEN, 6 }, 403 }; 404 405 static const struct clk_parent_data cam_cc_parent_data_3[] = { 406 { .index = DT_BI_TCXO }, 407 { .hw = &cam_cc_pll4_out_even.clkr.hw }, 408 }; 409 410 static const struct parent_map cam_cc_parent_map_4[] = { 411 { P_BI_TCXO, 0 }, 412 { P_CAM_CC_PLL1_OUT_EVEN, 4 }, 413 }; 414 415 static const struct clk_parent_data cam_cc_parent_data_4[] = { 416 { .index = DT_BI_TCXO }, 417 { .hw = &cam_cc_pll1_out_even.clkr.hw }, 418 }; 419 420 static const struct parent_map cam_cc_parent_map_5[] = { 421 { P_SLEEP_CLK, 0 }, 422 }; 423 424 static const struct clk_parent_data cam_cc_parent_data_5[] = { 425 { .index = DT_SLEEP_CLK }, 426 }; 427 428 static const struct parent_map cam_cc_parent_map_6_ao[] = { 429 { P_BI_TCXO_AO, 0 }, 430 }; 431 432 static const struct clk_parent_data cam_cc_parent_data_6_ao[] = { 433 { .index = DT_BI_TCXO_AO }, 434 }; 435 436 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { 437 F(160000000, P_CAM_CC_PLL0_OUT_ODD, 2.5, 0, 0), 438 F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), 439 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 440 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 441 { } 442 }; 443 444 static struct clk_rcg2 cam_cc_bps_clk_src = { 445 .cmd_rcgr = 0x10278, 446 .mnd_width = 0, 447 .hid_width = 5, 448 .parent_map = cam_cc_parent_map_0, 449 .freq_tbl = ftbl_cam_cc_bps_clk_src, 450 .hw_clk_ctrl = true, 451 .clkr = { 452 .hw.init = &(const struct clk_init_data) { 453 .name = "cam_cc_bps_clk_src", 454 .parent_data = cam_cc_parent_data_0, 455 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 456 .flags = CLK_SET_RATE_PARENT, 457 .ops = &clk_rcg2_shared_ops, 458 }, 459 }, 460 }; 461 462 static const struct freq_tbl ftbl_cam_cc_camnoc_axi_rt_clk_src[] = { 463 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), 464 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 465 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 466 { } 467 }; 468 469 static struct clk_rcg2 cam_cc_camnoc_axi_rt_clk_src = { 470 .cmd_rcgr = 0x137b4, 471 .mnd_width = 0, 472 .hid_width = 5, 473 .parent_map = cam_cc_parent_map_0, 474 .freq_tbl = ftbl_cam_cc_camnoc_axi_rt_clk_src, 475 .hw_clk_ctrl = true, 476 .clkr = { 477 .hw.init = &(const struct clk_init_data) { 478 .name = "cam_cc_camnoc_axi_rt_clk_src", 479 .parent_data = cam_cc_parent_data_0, 480 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 481 .flags = CLK_SET_RATE_PARENT, 482 .ops = &clk_rcg2_shared_ops, 483 }, 484 }, 485 }; 486 487 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { 488 F(30000000, P_CAM_CC_PLL5_OUT_EVEN, 16, 0, 0), 489 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 490 { } 491 }; 492 493 static struct clk_rcg2 cam_cc_cci_0_clk_src = { 494 .cmd_rcgr = 0x1350c, 495 .mnd_width = 8, 496 .hid_width = 5, 497 .parent_map = cam_cc_parent_map_0, 498 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 499 .hw_clk_ctrl = true, 500 .clkr = { 501 .hw.init = &(const struct clk_init_data) { 502 .name = "cam_cc_cci_0_clk_src", 503 .parent_data = cam_cc_parent_data_0, 504 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 505 .flags = CLK_SET_RATE_PARENT, 506 .ops = &clk_rcg2_shared_ops, 507 }, 508 }, 509 }; 510 511 static struct clk_rcg2 cam_cc_cci_1_clk_src = { 512 .cmd_rcgr = 0x1363c, 513 .mnd_width = 8, 514 .hid_width = 5, 515 .parent_map = cam_cc_parent_map_0, 516 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 517 .hw_clk_ctrl = true, 518 .clkr = { 519 .hw.init = &(const struct clk_init_data) { 520 .name = "cam_cc_cci_1_clk_src", 521 .parent_data = cam_cc_parent_data_0, 522 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 523 .flags = CLK_SET_RATE_PARENT, 524 .ops = &clk_rcg2_shared_ops, 525 }, 526 }, 527 }; 528 529 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 530 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), 531 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 532 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 533 { } 534 }; 535 536 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 537 .cmd_rcgr = 0x11168, 538 .mnd_width = 0, 539 .hid_width = 5, 540 .parent_map = cam_cc_parent_map_0, 541 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 542 .hw_clk_ctrl = true, 543 .clkr = { 544 .hw.init = &(const struct clk_init_data) { 545 .name = "cam_cc_cphy_rx_clk_src", 546 .parent_data = cam_cc_parent_data_0, 547 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 548 .flags = CLK_SET_RATE_PARENT, 549 .ops = &clk_rcg2_shared_ops, 550 }, 551 }, 552 }; 553 554 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 555 F(266666667, P_CAM_CC_PLL0_OUT_ODD, 1.5, 0, 0), 556 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 557 { } 558 }; 559 560 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 561 .cmd_rcgr = 0x150e0, 562 .mnd_width = 0, 563 .hid_width = 5, 564 .parent_map = cam_cc_parent_map_0, 565 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 566 .hw_clk_ctrl = true, 567 .clkr = { 568 .hw.init = &(const struct clk_init_data) { 569 .name = "cam_cc_csi0phytimer_clk_src", 570 .parent_data = cam_cc_parent_data_0, 571 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 572 .flags = CLK_SET_RATE_PARENT, 573 .ops = &clk_rcg2_shared_ops, 574 }, 575 }, 576 }; 577 578 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 579 .cmd_rcgr = 0x15104, 580 .mnd_width = 0, 581 .hid_width = 5, 582 .parent_map = cam_cc_parent_map_0, 583 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 584 .hw_clk_ctrl = true, 585 .clkr = { 586 .hw.init = &(const struct clk_init_data) { 587 .name = "cam_cc_csi1phytimer_clk_src", 588 .parent_data = cam_cc_parent_data_0, 589 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 590 .flags = CLK_SET_RATE_PARENT, 591 .ops = &clk_rcg2_shared_ops, 592 }, 593 }, 594 }; 595 596 static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { 597 .cmd_rcgr = 0x15124, 598 .mnd_width = 0, 599 .hid_width = 5, 600 .parent_map = cam_cc_parent_map_0, 601 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 602 .hw_clk_ctrl = true, 603 .clkr = { 604 .hw.init = &(const struct clk_init_data) { 605 .name = "cam_cc_csi4phytimer_clk_src", 606 .parent_data = cam_cc_parent_data_0, 607 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 608 .flags = CLK_SET_RATE_PARENT, 609 .ops = &clk_rcg2_shared_ops, 610 }, 611 }, 612 }; 613 614 static struct clk_rcg2 cam_cc_csid_clk_src = { 615 .cmd_rcgr = 0x1378c, 616 .mnd_width = 0, 617 .hid_width = 5, 618 .parent_map = cam_cc_parent_map_0, 619 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 620 .hw_clk_ctrl = true, 621 .clkr = { 622 .hw.init = &(const struct clk_init_data) { 623 .name = "cam_cc_csid_clk_src", 624 .parent_data = cam_cc_parent_data_0, 625 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 626 .flags = CLK_SET_RATE_PARENT, 627 .ops = &clk_rcg2_shared_ops, 628 }, 629 }, 630 }; 631 632 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 633 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 634 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 635 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 636 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), 637 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 638 { } 639 }; 640 641 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 642 .cmd_rcgr = 0x10018, 643 .mnd_width = 0, 644 .hid_width = 5, 645 .parent_map = cam_cc_parent_map_0, 646 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 647 .hw_clk_ctrl = true, 648 .clkr = { 649 .hw.init = &(const struct clk_init_data) { 650 .name = "cam_cc_fast_ahb_clk_src", 651 .parent_data = cam_cc_parent_data_0, 652 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 653 .flags = CLK_SET_RATE_PARENT, 654 .ops = &clk_rcg2_shared_ops, 655 }, 656 }, 657 }; 658 659 static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 660 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 661 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 662 F(480000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 663 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 664 { } 665 }; 666 667 static struct clk_rcg2 cam_cc_icp_clk_src = { 668 .cmd_rcgr = 0x133cc, 669 .mnd_width = 0, 670 .hid_width = 5, 671 .parent_map = cam_cc_parent_map_0, 672 .freq_tbl = ftbl_cam_cc_icp_clk_src, 673 .hw_clk_ctrl = true, 674 .clkr = { 675 .hw.init = &(const struct clk_init_data) { 676 .name = "cam_cc_icp_clk_src", 677 .parent_data = cam_cc_parent_data_0, 678 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 679 .flags = CLK_SET_RATE_PARENT, 680 .ops = &clk_rcg2_shared_ops, 681 }, 682 }, 683 }; 684 685 static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { 686 F(345600000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 687 F(432000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 688 F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 689 F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 690 F(727000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 691 { } 692 }; 693 694 static struct clk_rcg2 cam_cc_ife_0_clk_src = { 695 .cmd_rcgr = 0x11018, 696 .mnd_width = 0, 697 .hid_width = 5, 698 .parent_map = cam_cc_parent_map_2, 699 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 700 .hw_clk_ctrl = true, 701 .clkr = { 702 .hw.init = &(const struct clk_init_data) { 703 .name = "cam_cc_ife_0_clk_src", 704 .parent_data = cam_cc_parent_data_2, 705 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 706 .flags = CLK_SET_RATE_PARENT, 707 .ops = &clk_rcg2_shared_ops, 708 }, 709 }, 710 }; 711 712 static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = { 713 F(345600000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 714 F(432000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 715 F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 716 F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 717 F(727000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 718 { } 719 }; 720 721 static struct clk_rcg2 cam_cc_ife_1_clk_src = { 722 .cmd_rcgr = 0x12018, 723 .mnd_width = 0, 724 .hid_width = 5, 725 .parent_map = cam_cc_parent_map_3, 726 .freq_tbl = ftbl_cam_cc_ife_1_clk_src, 727 .hw_clk_ctrl = true, 728 .clkr = { 729 .hw.init = &(const struct clk_init_data) { 730 .name = "cam_cc_ife_1_clk_src", 731 .parent_data = cam_cc_parent_data_3, 732 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 733 .flags = CLK_SET_RATE_PARENT, 734 .ops = &clk_rcg2_shared_ops, 735 }, 736 }, 737 }; 738 739 static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = { 740 F(266666667, P_CAM_CC_PLL0_OUT_ODD, 1.5, 0, 0), 741 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 742 F(480000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 743 { } 744 }; 745 746 static struct clk_rcg2 cam_cc_ife_lite_clk_src = { 747 .cmd_rcgr = 0x13000, 748 .mnd_width = 0, 749 .hid_width = 5, 750 .parent_map = cam_cc_parent_map_0, 751 .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, 752 .hw_clk_ctrl = true, 753 .clkr = { 754 .hw.init = &(const struct clk_init_data) { 755 .name = "cam_cc_ife_lite_clk_src", 756 .parent_data = cam_cc_parent_data_0, 757 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 758 .flags = CLK_SET_RATE_PARENT, 759 .ops = &clk_rcg2_shared_ops, 760 }, 761 }, 762 }; 763 764 static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { 765 .cmd_rcgr = 0x13140, 766 .mnd_width = 0, 767 .hid_width = 5, 768 .parent_map = cam_cc_parent_map_0, 769 .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, 770 .hw_clk_ctrl = true, 771 .clkr = { 772 .hw.init = &(const struct clk_init_data) { 773 .name = "cam_cc_ife_lite_csid_clk_src", 774 .parent_data = cam_cc_parent_data_0, 775 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 776 .flags = CLK_SET_RATE_PARENT, 777 .ops = &clk_rcg2_shared_ops, 778 }, 779 }, 780 }; 781 782 static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = { 783 F(304000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 784 F(364000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 785 F(500000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 786 F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 787 F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 788 { } 789 }; 790 791 static struct clk_rcg2 cam_cc_ipe_nps_clk_src = { 792 .cmd_rcgr = 0x103d0, 793 .mnd_width = 0, 794 .hid_width = 5, 795 .parent_map = cam_cc_parent_map_4, 796 .freq_tbl = ftbl_cam_cc_ipe_nps_clk_src, 797 .hw_clk_ctrl = true, 798 .clkr = { 799 .hw.init = &(const struct clk_init_data) { 800 .name = "cam_cc_ipe_nps_clk_src", 801 .parent_data = cam_cc_parent_data_4, 802 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 803 .flags = CLK_SET_RATE_PARENT, 804 .ops = &clk_rcg2_shared_ops, 805 }, 806 }, 807 }; 808 809 static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = { 810 F(160000000, P_CAM_CC_PLL0_OUT_ODD, 2.5, 0, 0), 811 F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), 812 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 813 F(480000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 814 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 815 { } 816 }; 817 818 static struct clk_rcg2 cam_cc_jpeg_clk_src = { 819 .cmd_rcgr = 0x13284, 820 .mnd_width = 0, 821 .hid_width = 5, 822 .parent_map = cam_cc_parent_map_0, 823 .freq_tbl = ftbl_cam_cc_jpeg_clk_src, 824 .hw_clk_ctrl = true, 825 .clkr = { 826 .hw.init = &(const struct clk_init_data) { 827 .name = "cam_cc_jpeg_clk_src", 828 .parent_data = cam_cc_parent_data_0, 829 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 830 .flags = CLK_SET_RATE_PARENT, 831 .ops = &clk_rcg2_shared_ops, 832 }, 833 }, 834 }; 835 836 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 837 F(19200000, P_BI_TCXO, 1, 0, 0), 838 F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4), 839 F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0), 840 { } 841 }; 842 843 static struct clk_rcg2 cam_cc_mclk0_clk_src = { 844 .cmd_rcgr = 0x15000, 845 .mnd_width = 8, 846 .hid_width = 5, 847 .parent_map = cam_cc_parent_map_1, 848 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 849 .hw_clk_ctrl = true, 850 .clkr = { 851 .hw.init = &(const struct clk_init_data) { 852 .name = "cam_cc_mclk0_clk_src", 853 .parent_data = cam_cc_parent_data_1, 854 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 855 .flags = CLK_SET_RATE_PARENT, 856 .ops = &clk_rcg2_shared_ops, 857 }, 858 }, 859 }; 860 861 static struct clk_rcg2 cam_cc_mclk1_clk_src = { 862 .cmd_rcgr = 0x1501c, 863 .mnd_width = 8, 864 .hid_width = 5, 865 .parent_map = cam_cc_parent_map_1, 866 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 867 .hw_clk_ctrl = true, 868 .clkr = { 869 .hw.init = &(const struct clk_init_data) { 870 .name = "cam_cc_mclk1_clk_src", 871 .parent_data = cam_cc_parent_data_1, 872 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 873 .flags = CLK_SET_RATE_PARENT, 874 .ops = &clk_rcg2_shared_ops, 875 }, 876 }, 877 }; 878 879 static struct clk_rcg2 cam_cc_mclk2_clk_src = { 880 .cmd_rcgr = 0x15038, 881 .mnd_width = 8, 882 .hid_width = 5, 883 .parent_map = cam_cc_parent_map_1, 884 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 885 .hw_clk_ctrl = true, 886 .clkr = { 887 .hw.init = &(const struct clk_init_data) { 888 .name = "cam_cc_mclk2_clk_src", 889 .parent_data = cam_cc_parent_data_1, 890 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 891 .flags = CLK_SET_RATE_PARENT, 892 .ops = &clk_rcg2_shared_ops, 893 }, 894 }, 895 }; 896 897 static struct clk_rcg2 cam_cc_mclk3_clk_src = { 898 .cmd_rcgr = 0x15054, 899 .mnd_width = 8, 900 .hid_width = 5, 901 .parent_map = cam_cc_parent_map_1, 902 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 903 .hw_clk_ctrl = true, 904 .clkr = { 905 .hw.init = &(const struct clk_init_data) { 906 .name = "cam_cc_mclk3_clk_src", 907 .parent_data = cam_cc_parent_data_1, 908 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 909 .flags = CLK_SET_RATE_PARENT, 910 .ops = &clk_rcg2_shared_ops, 911 }, 912 }, 913 }; 914 915 static struct clk_rcg2 cam_cc_mclk4_clk_src = { 916 .cmd_rcgr = 0x15070, 917 .mnd_width = 8, 918 .hid_width = 5, 919 .parent_map = cam_cc_parent_map_1, 920 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 921 .hw_clk_ctrl = true, 922 .clkr = { 923 .hw.init = &(const struct clk_init_data) { 924 .name = "cam_cc_mclk4_clk_src", 925 .parent_data = cam_cc_parent_data_1, 926 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 927 .flags = CLK_SET_RATE_PARENT, 928 .ops = &clk_rcg2_shared_ops, 929 }, 930 }, 931 }; 932 933 static struct clk_rcg2 cam_cc_mclk5_clk_src = { 934 .cmd_rcgr = 0x1508c, 935 .mnd_width = 8, 936 .hid_width = 5, 937 .parent_map = cam_cc_parent_map_1, 938 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 939 .hw_clk_ctrl = true, 940 .clkr = { 941 .hw.init = &(const struct clk_init_data) { 942 .name = "cam_cc_mclk5_clk_src", 943 .parent_data = cam_cc_parent_data_1, 944 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 945 .flags = CLK_SET_RATE_PARENT, 946 .ops = &clk_rcg2_shared_ops, 947 }, 948 }, 949 }; 950 951 static struct clk_rcg2 cam_cc_mclk6_clk_src = { 952 .cmd_rcgr = 0x150a8, 953 .mnd_width = 8, 954 .hid_width = 5, 955 .parent_map = cam_cc_parent_map_1, 956 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 957 .hw_clk_ctrl = true, 958 .clkr = { 959 .hw.init = &(const struct clk_init_data) { 960 .name = "cam_cc_mclk6_clk_src", 961 .parent_data = cam_cc_parent_data_1, 962 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 963 .flags = CLK_SET_RATE_PARENT, 964 .ops = &clk_rcg2_shared_ops, 965 }, 966 }, 967 }; 968 969 static struct clk_rcg2 cam_cc_mclk7_clk_src = { 970 .cmd_rcgr = 0x150c4, 971 .mnd_width = 8, 972 .hid_width = 5, 973 .parent_map = cam_cc_parent_map_1, 974 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 975 .hw_clk_ctrl = true, 976 .clkr = { 977 .hw.init = &(const struct clk_init_data) { 978 .name = "cam_cc_mclk7_clk_src", 979 .parent_data = cam_cc_parent_data_1, 980 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 981 .flags = CLK_SET_RATE_PARENT, 982 .ops = &clk_rcg2_shared_ops, 983 }, 984 }, 985 }; 986 987 static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = { 988 F(60000000, P_CAM_CC_PLL5_OUT_EVEN, 8, 0, 0), 989 F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0), 990 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), 991 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), 992 { } 993 }; 994 995 static struct clk_rcg2 cam_cc_qdss_debug_clk_src = { 996 .cmd_rcgr = 0x137fc, 997 .mnd_width = 0, 998 .hid_width = 5, 999 .parent_map = cam_cc_parent_map_0, 1000 .freq_tbl = ftbl_cam_cc_qdss_debug_clk_src, 1001 .hw_clk_ctrl = true, 1002 .clkr = { 1003 .hw.init = &(const struct clk_init_data) { 1004 .name = "cam_cc_qdss_debug_clk_src", 1005 .parent_data = cam_cc_parent_data_0, 1006 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 1007 .flags = CLK_SET_RATE_PARENT, 1008 .ops = &clk_rcg2_shared_ops, 1009 }, 1010 }, 1011 }; 1012 1013 static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { 1014 F(32000, P_SLEEP_CLK, 1, 0, 0), 1015 { } 1016 }; 1017 1018 static struct clk_rcg2 cam_cc_sleep_clk_src = { 1019 .cmd_rcgr = 0x13964, 1020 .mnd_width = 0, 1021 .hid_width = 5, 1022 .parent_map = cam_cc_parent_map_5, 1023 .freq_tbl = ftbl_cam_cc_sleep_clk_src, 1024 .clkr = { 1025 .hw.init = &(const struct clk_init_data) { 1026 .name = "cam_cc_sleep_clk_src", 1027 .parent_data = cam_cc_parent_data_5, 1028 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 1029 .flags = CLK_SET_RATE_PARENT, 1030 .ops = &clk_rcg2_shared_ops, 1031 }, 1032 }, 1033 }; 1034 1035 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 1036 F(64000000, P_CAM_CC_PLL5_OUT_EVEN, 7.5, 0, 0), 1037 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 1038 { } 1039 }; 1040 1041 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 1042 .cmd_rcgr = 0x10148, 1043 .mnd_width = 8, 1044 .hid_width = 5, 1045 .parent_map = cam_cc_parent_map_0, 1046 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 1047 .hw_clk_ctrl = true, 1048 .clkr = { 1049 .hw.init = &(const struct clk_init_data) { 1050 .name = "cam_cc_slow_ahb_clk_src", 1051 .parent_data = cam_cc_parent_data_0, 1052 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 1053 .flags = CLK_SET_RATE_PARENT, 1054 .ops = &clk_rcg2_shared_ops, 1055 }, 1056 }, 1057 }; 1058 1059 static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { 1060 F(19200000, P_BI_TCXO_AO, 1, 0, 0), 1061 { } 1062 }; 1063 1064 static struct clk_rcg2 cam_cc_xo_clk_src = { 1065 .cmd_rcgr = 0x13948, 1066 .mnd_width = 0, 1067 .hid_width = 5, 1068 .parent_map = cam_cc_parent_map_6_ao, 1069 .freq_tbl = ftbl_cam_cc_xo_clk_src, 1070 .hw_clk_ctrl = true, 1071 .clkr = { 1072 .hw.init = &(const struct clk_init_data) { 1073 .name = "cam_cc_xo_clk_src", 1074 .parent_data = cam_cc_parent_data_6_ao, 1075 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6_ao), 1076 .flags = CLK_SET_RATE_PARENT, 1077 .ops = &clk_rcg2_shared_ops, 1078 }, 1079 }, 1080 }; 1081 1082 static struct clk_branch cam_cc_bps_ahb_clk = { 1083 .halt_reg = 0x10274, 1084 .halt_check = BRANCH_HALT, 1085 .clkr = { 1086 .enable_reg = 0x10274, 1087 .enable_mask = BIT(0), 1088 .hw.init = &(const struct clk_init_data) { 1089 .name = "cam_cc_bps_ahb_clk", 1090 .parent_hws = (const struct clk_hw*[]) { 1091 &cam_cc_slow_ahb_clk_src.clkr.hw, 1092 }, 1093 .num_parents = 1, 1094 .flags = CLK_SET_RATE_PARENT, 1095 .ops = &clk_branch2_ops, 1096 }, 1097 }, 1098 }; 1099 1100 static struct clk_branch cam_cc_bps_clk = { 1101 .halt_reg = 0x103a4, 1102 .halt_check = BRANCH_HALT, 1103 .clkr = { 1104 .enable_reg = 0x103a4, 1105 .enable_mask = BIT(0), 1106 .hw.init = &(const struct clk_init_data) { 1107 .name = "cam_cc_bps_clk", 1108 .parent_hws = (const struct clk_hw*[]) { 1109 &cam_cc_bps_clk_src.clkr.hw, 1110 }, 1111 .num_parents = 1, 1112 .flags = CLK_SET_RATE_PARENT, 1113 .ops = &clk_branch2_ops, 1114 }, 1115 }, 1116 }; 1117 1118 static struct clk_branch cam_cc_bps_fast_ahb_clk = { 1119 .halt_reg = 0x10144, 1120 .halt_check = BRANCH_HALT, 1121 .clkr = { 1122 .enable_reg = 0x10144, 1123 .enable_mask = BIT(0), 1124 .hw.init = &(const struct clk_init_data) { 1125 .name = "cam_cc_bps_fast_ahb_clk", 1126 .parent_hws = (const struct clk_hw*[]) { 1127 &cam_cc_fast_ahb_clk_src.clkr.hw, 1128 }, 1129 .num_parents = 1, 1130 .flags = CLK_SET_RATE_PARENT, 1131 .ops = &clk_branch2_ops, 1132 }, 1133 }, 1134 }; 1135 1136 static struct clk_branch cam_cc_camnoc_axi_nrt_clk = { 1137 .halt_reg = 0x137e0, 1138 .halt_check = BRANCH_HALT_VOTED, 1139 .hwcg_reg = 0x137e0, 1140 .hwcg_bit = 1, 1141 .clkr = { 1142 .enable_reg = 0x137e0, 1143 .enable_mask = BIT(0), 1144 .hw.init = &(const struct clk_init_data) { 1145 .name = "cam_cc_camnoc_axi_nrt_clk", 1146 .parent_hws = (const struct clk_hw*[]) { 1147 &cam_cc_camnoc_axi_rt_clk_src.clkr.hw, 1148 }, 1149 .num_parents = 1, 1150 .flags = CLK_SET_RATE_PARENT, 1151 .ops = &clk_branch2_ops, 1152 }, 1153 }, 1154 }; 1155 1156 static struct clk_branch cam_cc_camnoc_axi_rt_clk = { 1157 .halt_reg = 0x137cc, 1158 .halt_check = BRANCH_HALT, 1159 .clkr = { 1160 .enable_reg = 0x137cc, 1161 .enable_mask = BIT(0), 1162 .hw.init = &(const struct clk_init_data) { 1163 .name = "cam_cc_camnoc_axi_rt_clk", 1164 .parent_hws = (const struct clk_hw*[]) { 1165 &cam_cc_camnoc_axi_rt_clk_src.clkr.hw, 1166 }, 1167 .num_parents = 1, 1168 .flags = CLK_SET_RATE_PARENT, 1169 .ops = &clk_branch2_ops, 1170 }, 1171 }, 1172 }; 1173 1174 static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { 1175 .halt_reg = 0x137f0, 1176 .halt_check = BRANCH_HALT, 1177 .clkr = { 1178 .enable_reg = 0x137f0, 1179 .enable_mask = BIT(0), 1180 .hw.init = &(const struct clk_init_data) { 1181 .name = "cam_cc_camnoc_dcd_xo_clk", 1182 .parent_hws = (const struct clk_hw*[]) { 1183 &cam_cc_xo_clk_src.clkr.hw, 1184 }, 1185 .num_parents = 1, 1186 .flags = CLK_SET_RATE_PARENT, 1187 .ops = &clk_branch2_ops, 1188 }, 1189 }, 1190 }; 1191 1192 static struct clk_branch cam_cc_camnoc_xo_clk = { 1193 .halt_reg = 0x137f4, 1194 .halt_check = BRANCH_HALT, 1195 .clkr = { 1196 .enable_reg = 0x137f4, 1197 .enable_mask = BIT(0), 1198 .hw.init = &(const struct clk_init_data) { 1199 .name = "cam_cc_camnoc_xo_clk", 1200 .parent_hws = (const struct clk_hw*[]) { 1201 &cam_cc_xo_clk_src.clkr.hw, 1202 }, 1203 .num_parents = 1, 1204 .flags = CLK_SET_RATE_PARENT, 1205 .ops = &clk_branch2_ops, 1206 }, 1207 }, 1208 }; 1209 1210 static struct clk_branch cam_cc_cci_0_clk = { 1211 .halt_reg = 0x13638, 1212 .halt_check = BRANCH_HALT, 1213 .clkr = { 1214 .enable_reg = 0x13638, 1215 .enable_mask = BIT(0), 1216 .hw.init = &(const struct clk_init_data) { 1217 .name = "cam_cc_cci_0_clk", 1218 .parent_hws = (const struct clk_hw*[]) { 1219 &cam_cc_cci_0_clk_src.clkr.hw, 1220 }, 1221 .num_parents = 1, 1222 .flags = CLK_SET_RATE_PARENT, 1223 .ops = &clk_branch2_ops, 1224 }, 1225 }, 1226 }; 1227 1228 static struct clk_branch cam_cc_cci_1_clk = { 1229 .halt_reg = 0x13768, 1230 .halt_check = BRANCH_HALT, 1231 .clkr = { 1232 .enable_reg = 0x13768, 1233 .enable_mask = BIT(0), 1234 .hw.init = &(const struct clk_init_data) { 1235 .name = "cam_cc_cci_1_clk", 1236 .parent_hws = (const struct clk_hw*[]) { 1237 &cam_cc_cci_1_clk_src.clkr.hw, 1238 }, 1239 .num_parents = 1, 1240 .flags = CLK_SET_RATE_PARENT, 1241 .ops = &clk_branch2_ops, 1242 }, 1243 }, 1244 }; 1245 1246 static struct clk_branch cam_cc_core_ahb_clk = { 1247 .halt_reg = 0x13944, 1248 .halt_check = BRANCH_HALT_DELAY, 1249 .clkr = { 1250 .enable_reg = 0x13944, 1251 .enable_mask = BIT(0), 1252 .hw.init = &(const struct clk_init_data) { 1253 .name = "cam_cc_core_ahb_clk", 1254 .parent_hws = (const struct clk_hw*[]) { 1255 &cam_cc_slow_ahb_clk_src.clkr.hw, 1256 }, 1257 .num_parents = 1, 1258 .flags = CLK_SET_RATE_PARENT, 1259 .ops = &clk_branch2_ops, 1260 }, 1261 }, 1262 }; 1263 1264 static struct clk_branch cam_cc_cpas_ahb_clk = { 1265 .halt_reg = 0x1376c, 1266 .halt_check = BRANCH_HALT, 1267 .clkr = { 1268 .enable_reg = 0x1376c, 1269 .enable_mask = BIT(0), 1270 .hw.init = &(const struct clk_init_data) { 1271 .name = "cam_cc_cpas_ahb_clk", 1272 .parent_hws = (const struct clk_hw*[]) { 1273 &cam_cc_slow_ahb_clk_src.clkr.hw, 1274 }, 1275 .num_parents = 1, 1276 .flags = CLK_SET_RATE_PARENT, 1277 .ops = &clk_branch2_ops, 1278 }, 1279 }, 1280 }; 1281 1282 static struct clk_branch cam_cc_cpas_bps_clk = { 1283 .halt_reg = 0x103b4, 1284 .halt_check = BRANCH_HALT, 1285 .clkr = { 1286 .enable_reg = 0x103b4, 1287 .enable_mask = BIT(0), 1288 .hw.init = &(const struct clk_init_data) { 1289 .name = "cam_cc_cpas_bps_clk", 1290 .parent_hws = (const struct clk_hw*[]) { 1291 &cam_cc_bps_clk_src.clkr.hw, 1292 }, 1293 .num_parents = 1, 1294 .flags = CLK_SET_RATE_PARENT, 1295 .ops = &clk_branch2_ops, 1296 }, 1297 }, 1298 }; 1299 1300 static struct clk_branch cam_cc_cpas_fast_ahb_clk = { 1301 .halt_reg = 0x1377c, 1302 .halt_check = BRANCH_HALT, 1303 .clkr = { 1304 .enable_reg = 0x1377c, 1305 .enable_mask = BIT(0), 1306 .hw.init = &(const struct clk_init_data) { 1307 .name = "cam_cc_cpas_fast_ahb_clk", 1308 .parent_hws = (const struct clk_hw*[]) { 1309 &cam_cc_fast_ahb_clk_src.clkr.hw, 1310 }, 1311 .num_parents = 1, 1312 .flags = CLK_SET_RATE_PARENT, 1313 .ops = &clk_branch2_ops, 1314 }, 1315 }, 1316 }; 1317 1318 static struct clk_branch cam_cc_cpas_ife_0_clk = { 1319 .halt_reg = 0x11154, 1320 .halt_check = BRANCH_HALT, 1321 .clkr = { 1322 .enable_reg = 0x11154, 1323 .enable_mask = BIT(0), 1324 .hw.init = &(const struct clk_init_data) { 1325 .name = "cam_cc_cpas_ife_0_clk", 1326 .parent_hws = (const struct clk_hw*[]) { 1327 &cam_cc_ife_0_clk_src.clkr.hw, 1328 }, 1329 .num_parents = 1, 1330 .flags = CLK_SET_RATE_PARENT, 1331 .ops = &clk_branch2_ops, 1332 }, 1333 }, 1334 }; 1335 1336 static struct clk_branch cam_cc_cpas_ife_1_clk = { 1337 .halt_reg = 0x12040, 1338 .halt_check = BRANCH_HALT, 1339 .clkr = { 1340 .enable_reg = 0x12040, 1341 .enable_mask = BIT(0), 1342 .hw.init = &(const struct clk_init_data) { 1343 .name = "cam_cc_cpas_ife_1_clk", 1344 .parent_hws = (const struct clk_hw*[]) { 1345 &cam_cc_ife_1_clk_src.clkr.hw, 1346 }, 1347 .num_parents = 1, 1348 .flags = CLK_SET_RATE_PARENT, 1349 .ops = &clk_branch2_ops, 1350 }, 1351 }, 1352 }; 1353 1354 static struct clk_branch cam_cc_cpas_ife_lite_clk = { 1355 .halt_reg = 0x1313c, 1356 .halt_check = BRANCH_HALT, 1357 .clkr = { 1358 .enable_reg = 0x1313c, 1359 .enable_mask = BIT(0), 1360 .hw.init = &(const struct clk_init_data) { 1361 .name = "cam_cc_cpas_ife_lite_clk", 1362 .parent_hws = (const struct clk_hw*[]) { 1363 &cam_cc_ife_lite_clk_src.clkr.hw, 1364 }, 1365 .num_parents = 1, 1366 .flags = CLK_SET_RATE_PARENT, 1367 .ops = &clk_branch2_ops, 1368 }, 1369 }, 1370 }; 1371 1372 static struct clk_branch cam_cc_cpas_ipe_nps_clk = { 1373 .halt_reg = 0x1050c, 1374 .halt_check = BRANCH_HALT, 1375 .clkr = { 1376 .enable_reg = 0x1050c, 1377 .enable_mask = BIT(0), 1378 .hw.init = &(const struct clk_init_data) { 1379 .name = "cam_cc_cpas_ipe_nps_clk", 1380 .parent_hws = (const struct clk_hw*[]) { 1381 &cam_cc_ipe_nps_clk_src.clkr.hw, 1382 }, 1383 .num_parents = 1, 1384 .flags = CLK_SET_RATE_PARENT, 1385 .ops = &clk_branch2_ops, 1386 }, 1387 }, 1388 }; 1389 1390 static struct clk_branch cam_cc_csi0phytimer_clk = { 1391 .halt_reg = 0x150f8, 1392 .halt_check = BRANCH_HALT, 1393 .clkr = { 1394 .enable_reg = 0x150f8, 1395 .enable_mask = BIT(0), 1396 .hw.init = &(const struct clk_init_data) { 1397 .name = "cam_cc_csi0phytimer_clk", 1398 .parent_hws = (const struct clk_hw*[]) { 1399 &cam_cc_csi0phytimer_clk_src.clkr.hw, 1400 }, 1401 .num_parents = 1, 1402 .flags = CLK_SET_RATE_PARENT, 1403 .ops = &clk_branch2_ops, 1404 }, 1405 }, 1406 }; 1407 1408 static struct clk_branch cam_cc_csi1phytimer_clk = { 1409 .halt_reg = 0x1511c, 1410 .halt_check = BRANCH_HALT, 1411 .clkr = { 1412 .enable_reg = 0x1511c, 1413 .enable_mask = BIT(0), 1414 .hw.init = &(const struct clk_init_data) { 1415 .name = "cam_cc_csi1phytimer_clk", 1416 .parent_hws = (const struct clk_hw*[]) { 1417 &cam_cc_csi1phytimer_clk_src.clkr.hw, 1418 }, 1419 .num_parents = 1, 1420 .flags = CLK_SET_RATE_PARENT, 1421 .ops = &clk_branch2_ops, 1422 }, 1423 }, 1424 }; 1425 1426 static struct clk_branch cam_cc_csi4phytimer_clk = { 1427 .halt_reg = 0x15250, 1428 .halt_check = BRANCH_HALT, 1429 .clkr = { 1430 .enable_reg = 0x15250, 1431 .enable_mask = BIT(0), 1432 .hw.init = &(const struct clk_init_data) { 1433 .name = "cam_cc_csi4phytimer_clk", 1434 .parent_hws = (const struct clk_hw*[]) { 1435 &cam_cc_csi4phytimer_clk_src.clkr.hw, 1436 }, 1437 .num_parents = 1, 1438 .flags = CLK_SET_RATE_PARENT, 1439 .ops = &clk_branch2_ops, 1440 }, 1441 }, 1442 }; 1443 1444 static struct clk_branch cam_cc_csid_clk = { 1445 .halt_reg = 0x137a4, 1446 .halt_check = BRANCH_HALT, 1447 .clkr = { 1448 .enable_reg = 0x137a4, 1449 .enable_mask = BIT(0), 1450 .hw.init = &(const struct clk_init_data) { 1451 .name = "cam_cc_csid_clk", 1452 .parent_hws = (const struct clk_hw*[]) { 1453 &cam_cc_csid_clk_src.clkr.hw, 1454 }, 1455 .num_parents = 1, 1456 .flags = CLK_SET_RATE_PARENT, 1457 .ops = &clk_branch2_ops, 1458 }, 1459 }, 1460 }; 1461 1462 static struct clk_branch cam_cc_csid_csiphy_rx_clk = { 1463 .halt_reg = 0x15100, 1464 .halt_check = BRANCH_HALT, 1465 .clkr = { 1466 .enable_reg = 0x15100, 1467 .enable_mask = BIT(0), 1468 .hw.init = &(const struct clk_init_data) { 1469 .name = "cam_cc_csid_csiphy_rx_clk", 1470 .parent_hws = (const struct clk_hw*[]) { 1471 &cam_cc_cphy_rx_clk_src.clkr.hw, 1472 }, 1473 .num_parents = 1, 1474 .flags = CLK_SET_RATE_PARENT, 1475 .ops = &clk_branch2_ops, 1476 }, 1477 }, 1478 }; 1479 1480 static struct clk_branch cam_cc_csiphy0_clk = { 1481 .halt_reg = 0x150fc, 1482 .halt_check = BRANCH_HALT, 1483 .clkr = { 1484 .enable_reg = 0x150fc, 1485 .enable_mask = BIT(0), 1486 .hw.init = &(const struct clk_init_data) { 1487 .name = "cam_cc_csiphy0_clk", 1488 .parent_hws = (const struct clk_hw*[]) { 1489 &cam_cc_cphy_rx_clk_src.clkr.hw, 1490 }, 1491 .num_parents = 1, 1492 .flags = CLK_SET_RATE_PARENT, 1493 .ops = &clk_branch2_ops, 1494 }, 1495 }, 1496 }; 1497 1498 static struct clk_branch cam_cc_csiphy1_clk = { 1499 .halt_reg = 0x15120, 1500 .halt_check = BRANCH_HALT, 1501 .clkr = { 1502 .enable_reg = 0x15120, 1503 .enable_mask = BIT(0), 1504 .hw.init = &(const struct clk_init_data) { 1505 .name = "cam_cc_csiphy1_clk", 1506 .parent_hws = (const struct clk_hw*[]) { 1507 &cam_cc_cphy_rx_clk_src.clkr.hw, 1508 }, 1509 .num_parents = 1, 1510 .flags = CLK_SET_RATE_PARENT, 1511 .ops = &clk_branch2_ops, 1512 }, 1513 }, 1514 }; 1515 1516 static struct clk_branch cam_cc_csiphy4_clk = { 1517 .halt_reg = 0x15254, 1518 .halt_check = BRANCH_HALT, 1519 .clkr = { 1520 .enable_reg = 0x15254, 1521 .enable_mask = BIT(0), 1522 .hw.init = &(const struct clk_init_data) { 1523 .name = "cam_cc_csiphy4_clk", 1524 .parent_hws = (const struct clk_hw*[]) { 1525 &cam_cc_cphy_rx_clk_src.clkr.hw, 1526 }, 1527 .num_parents = 1, 1528 .flags = CLK_SET_RATE_PARENT, 1529 .ops = &clk_branch2_ops, 1530 }, 1531 }, 1532 }; 1533 1534 static struct clk_branch cam_cc_icp_ahb_clk = { 1535 .halt_reg = 0x13508, 1536 .halt_check = BRANCH_HALT, 1537 .clkr = { 1538 .enable_reg = 0x13508, 1539 .enable_mask = BIT(0), 1540 .hw.init = &(const struct clk_init_data) { 1541 .name = "cam_cc_icp_ahb_clk", 1542 .parent_hws = (const struct clk_hw*[]) { 1543 &cam_cc_slow_ahb_clk_src.clkr.hw, 1544 }, 1545 .num_parents = 1, 1546 .flags = CLK_SET_RATE_PARENT, 1547 .ops = &clk_branch2_ops, 1548 }, 1549 }, 1550 }; 1551 1552 static struct clk_branch cam_cc_icp_clk = { 1553 .halt_reg = 0x134f8, 1554 .halt_check = BRANCH_HALT, 1555 .clkr = { 1556 .enable_reg = 0x134f8, 1557 .enable_mask = BIT(0), 1558 .hw.init = &(const struct clk_init_data) { 1559 .name = "cam_cc_icp_clk", 1560 .parent_hws = (const struct clk_hw*[]) { 1561 &cam_cc_icp_clk_src.clkr.hw, 1562 }, 1563 .num_parents = 1, 1564 .flags = CLK_SET_RATE_PARENT, 1565 .ops = &clk_branch2_ops, 1566 }, 1567 }, 1568 }; 1569 1570 static struct clk_branch cam_cc_ife_0_clk = { 1571 .halt_reg = 0x11144, 1572 .halt_check = BRANCH_HALT, 1573 .clkr = { 1574 .enable_reg = 0x11144, 1575 .enable_mask = BIT(0), 1576 .hw.init = &(const struct clk_init_data) { 1577 .name = "cam_cc_ife_0_clk", 1578 .parent_hws = (const struct clk_hw*[]) { 1579 &cam_cc_ife_0_clk_src.clkr.hw, 1580 }, 1581 .num_parents = 1, 1582 .flags = CLK_SET_RATE_PARENT, 1583 .ops = &clk_branch2_ops, 1584 }, 1585 }, 1586 }; 1587 1588 static struct clk_branch cam_cc_ife_0_dsp_clk = { 1589 .halt_reg = 0x11158, 1590 .halt_check = BRANCH_HALT, 1591 .clkr = { 1592 .enable_reg = 0x11158, 1593 .enable_mask = BIT(0), 1594 .hw.init = &(const struct clk_init_data) { 1595 .name = "cam_cc_ife_0_dsp_clk", 1596 .parent_hws = (const struct clk_hw*[]) { 1597 &cam_cc_ife_0_clk_src.clkr.hw, 1598 }, 1599 .num_parents = 1, 1600 .flags = CLK_SET_RATE_PARENT, 1601 .ops = &clk_branch2_ops, 1602 }, 1603 }, 1604 }; 1605 1606 static struct clk_branch cam_cc_ife_0_fast_ahb_clk = { 1607 .halt_reg = 0x11164, 1608 .halt_check = BRANCH_HALT, 1609 .clkr = { 1610 .enable_reg = 0x11164, 1611 .enable_mask = BIT(0), 1612 .hw.init = &(const struct clk_init_data) { 1613 .name = "cam_cc_ife_0_fast_ahb_clk", 1614 .parent_hws = (const struct clk_hw*[]) { 1615 &cam_cc_fast_ahb_clk_src.clkr.hw, 1616 }, 1617 .num_parents = 1, 1618 .flags = CLK_SET_RATE_PARENT, 1619 .ops = &clk_branch2_ops, 1620 }, 1621 }, 1622 }; 1623 1624 static struct clk_branch cam_cc_ife_1_clk = { 1625 .halt_reg = 0x12030, 1626 .halt_check = BRANCH_HALT, 1627 .clkr = { 1628 .enable_reg = 0x12030, 1629 .enable_mask = BIT(0), 1630 .hw.init = &(const struct clk_init_data) { 1631 .name = "cam_cc_ife_1_clk", 1632 .parent_hws = (const struct clk_hw*[]) { 1633 &cam_cc_ife_1_clk_src.clkr.hw, 1634 }, 1635 .num_parents = 1, 1636 .flags = CLK_SET_RATE_PARENT, 1637 .ops = &clk_branch2_ops, 1638 }, 1639 }, 1640 }; 1641 1642 static struct clk_branch cam_cc_ife_1_dsp_clk = { 1643 .halt_reg = 0x12044, 1644 .halt_check = BRANCH_HALT, 1645 .clkr = { 1646 .enable_reg = 0x12044, 1647 .enable_mask = BIT(0), 1648 .hw.init = &(const struct clk_init_data) { 1649 .name = "cam_cc_ife_1_dsp_clk", 1650 .parent_hws = (const struct clk_hw*[]) { 1651 &cam_cc_ife_1_clk_src.clkr.hw, 1652 }, 1653 .num_parents = 1, 1654 .flags = CLK_SET_RATE_PARENT, 1655 .ops = &clk_branch2_ops, 1656 }, 1657 }, 1658 }; 1659 1660 static struct clk_branch cam_cc_ife_1_fast_ahb_clk = { 1661 .halt_reg = 0x12050, 1662 .halt_check = BRANCH_HALT, 1663 .clkr = { 1664 .enable_reg = 0x12050, 1665 .enable_mask = BIT(0), 1666 .hw.init = &(const struct clk_init_data) { 1667 .name = "cam_cc_ife_1_fast_ahb_clk", 1668 .parent_hws = (const struct clk_hw*[]) { 1669 &cam_cc_fast_ahb_clk_src.clkr.hw, 1670 }, 1671 .num_parents = 1, 1672 .flags = CLK_SET_RATE_PARENT, 1673 .ops = &clk_branch2_ops, 1674 }, 1675 }, 1676 }; 1677 1678 static struct clk_branch cam_cc_ife_lite_ahb_clk = { 1679 .halt_reg = 0x13280, 1680 .halt_check = BRANCH_HALT, 1681 .clkr = { 1682 .enable_reg = 0x13280, 1683 .enable_mask = BIT(0), 1684 .hw.init = &(const struct clk_init_data) { 1685 .name = "cam_cc_ife_lite_ahb_clk", 1686 .parent_hws = (const struct clk_hw*[]) { 1687 &cam_cc_slow_ahb_clk_src.clkr.hw, 1688 }, 1689 .num_parents = 1, 1690 .flags = CLK_SET_RATE_PARENT, 1691 .ops = &clk_branch2_ops, 1692 }, 1693 }, 1694 }; 1695 1696 static struct clk_branch cam_cc_ife_lite_clk = { 1697 .halt_reg = 0x1312c, 1698 .halt_check = BRANCH_HALT, 1699 .clkr = { 1700 .enable_reg = 0x1312c, 1701 .enable_mask = BIT(0), 1702 .hw.init = &(const struct clk_init_data) { 1703 .name = "cam_cc_ife_lite_clk", 1704 .parent_hws = (const struct clk_hw*[]) { 1705 &cam_cc_ife_lite_clk_src.clkr.hw, 1706 }, 1707 .num_parents = 1, 1708 .flags = CLK_SET_RATE_PARENT, 1709 .ops = &clk_branch2_ops, 1710 }, 1711 }, 1712 }; 1713 1714 static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { 1715 .halt_reg = 0x1327c, 1716 .halt_check = BRANCH_HALT, 1717 .clkr = { 1718 .enable_reg = 0x1327c, 1719 .enable_mask = BIT(0), 1720 .hw.init = &(const struct clk_init_data) { 1721 .name = "cam_cc_ife_lite_cphy_rx_clk", 1722 .parent_hws = (const struct clk_hw*[]) { 1723 &cam_cc_cphy_rx_clk_src.clkr.hw, 1724 }, 1725 .num_parents = 1, 1726 .flags = CLK_SET_RATE_PARENT, 1727 .ops = &clk_branch2_ops, 1728 }, 1729 }, 1730 }; 1731 1732 static struct clk_branch cam_cc_ife_lite_csid_clk = { 1733 .halt_reg = 0x1326c, 1734 .halt_check = BRANCH_HALT, 1735 .clkr = { 1736 .enable_reg = 0x1326c, 1737 .enable_mask = BIT(0), 1738 .hw.init = &(const struct clk_init_data) { 1739 .name = "cam_cc_ife_lite_csid_clk", 1740 .parent_hws = (const struct clk_hw*[]) { 1741 &cam_cc_ife_lite_csid_clk_src.clkr.hw, 1742 }, 1743 .num_parents = 1, 1744 .flags = CLK_SET_RATE_PARENT, 1745 .ops = &clk_branch2_ops, 1746 }, 1747 }, 1748 }; 1749 1750 static struct clk_branch cam_cc_ipe_nps_ahb_clk = { 1751 .halt_reg = 0x10528, 1752 .halt_check = BRANCH_HALT, 1753 .clkr = { 1754 .enable_reg = 0x10528, 1755 .enable_mask = BIT(0), 1756 .hw.init = &(const struct clk_init_data) { 1757 .name = "cam_cc_ipe_nps_ahb_clk", 1758 .parent_hws = (const struct clk_hw*[]) { 1759 &cam_cc_slow_ahb_clk_src.clkr.hw, 1760 }, 1761 .num_parents = 1, 1762 .flags = CLK_SET_RATE_PARENT, 1763 .ops = &clk_branch2_ops, 1764 }, 1765 }, 1766 }; 1767 1768 static struct clk_branch cam_cc_ipe_nps_clk = { 1769 .halt_reg = 0x104fc, 1770 .halt_check = BRANCH_HALT, 1771 .clkr = { 1772 .enable_reg = 0x104fc, 1773 .enable_mask = BIT(0), 1774 .hw.init = &(const struct clk_init_data) { 1775 .name = "cam_cc_ipe_nps_clk", 1776 .parent_hws = (const struct clk_hw*[]) { 1777 &cam_cc_ipe_nps_clk_src.clkr.hw, 1778 }, 1779 .num_parents = 1, 1780 .flags = CLK_SET_RATE_PARENT, 1781 .ops = &clk_branch2_ops, 1782 }, 1783 }, 1784 }; 1785 1786 static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = { 1787 .halt_reg = 0x1052c, 1788 .halt_check = BRANCH_HALT, 1789 .clkr = { 1790 .enable_reg = 0x1052c, 1791 .enable_mask = BIT(0), 1792 .hw.init = &(const struct clk_init_data) { 1793 .name = "cam_cc_ipe_nps_fast_ahb_clk", 1794 .parent_hws = (const struct clk_hw*[]) { 1795 &cam_cc_fast_ahb_clk_src.clkr.hw, 1796 }, 1797 .num_parents = 1, 1798 .flags = CLK_SET_RATE_PARENT, 1799 .ops = &clk_branch2_ops, 1800 }, 1801 }, 1802 }; 1803 1804 static struct clk_branch cam_cc_ipe_pps_clk = { 1805 .halt_reg = 0x10510, 1806 .halt_check = BRANCH_HALT, 1807 .clkr = { 1808 .enable_reg = 0x10510, 1809 .enable_mask = BIT(0), 1810 .hw.init = &(const struct clk_init_data) { 1811 .name = "cam_cc_ipe_pps_clk", 1812 .parent_hws = (const struct clk_hw*[]) { 1813 &cam_cc_ipe_nps_clk_src.clkr.hw, 1814 }, 1815 .num_parents = 1, 1816 .flags = CLK_SET_RATE_PARENT, 1817 .ops = &clk_branch2_ops, 1818 }, 1819 }, 1820 }; 1821 1822 static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = { 1823 .halt_reg = 0x10530, 1824 .halt_check = BRANCH_HALT, 1825 .clkr = { 1826 .enable_reg = 0x10530, 1827 .enable_mask = BIT(0), 1828 .hw.init = &(const struct clk_init_data) { 1829 .name = "cam_cc_ipe_pps_fast_ahb_clk", 1830 .parent_hws = (const struct clk_hw*[]) { 1831 &cam_cc_fast_ahb_clk_src.clkr.hw, 1832 }, 1833 .num_parents = 1, 1834 .flags = CLK_SET_RATE_PARENT, 1835 .ops = &clk_branch2_ops, 1836 }, 1837 }, 1838 }; 1839 1840 static struct clk_branch cam_cc_jpeg_clk = { 1841 .halt_reg = 0x133b0, 1842 .halt_check = BRANCH_HALT, 1843 .clkr = { 1844 .enable_reg = 0x133b0, 1845 .enable_mask = BIT(0), 1846 .hw.init = &(const struct clk_init_data) { 1847 .name = "cam_cc_jpeg_clk", 1848 .parent_hws = (const struct clk_hw*[]) { 1849 &cam_cc_jpeg_clk_src.clkr.hw, 1850 }, 1851 .num_parents = 1, 1852 .flags = CLK_SET_RATE_PARENT, 1853 .ops = &clk_branch2_ops, 1854 }, 1855 }, 1856 }; 1857 1858 static struct clk_branch cam_cc_mclk0_clk = { 1859 .halt_reg = 0x15018, 1860 .halt_check = BRANCH_HALT, 1861 .clkr = { 1862 .enable_reg = 0x15018, 1863 .enable_mask = BIT(0), 1864 .hw.init = &(const struct clk_init_data) { 1865 .name = "cam_cc_mclk0_clk", 1866 .parent_hws = (const struct clk_hw*[]) { 1867 &cam_cc_mclk0_clk_src.clkr.hw, 1868 }, 1869 .num_parents = 1, 1870 .flags = CLK_SET_RATE_PARENT, 1871 .ops = &clk_branch2_ops, 1872 }, 1873 }, 1874 }; 1875 1876 static struct clk_branch cam_cc_mclk1_clk = { 1877 .halt_reg = 0x15034, 1878 .halt_check = BRANCH_HALT, 1879 .clkr = { 1880 .enable_reg = 0x15034, 1881 .enable_mask = BIT(0), 1882 .hw.init = &(const struct clk_init_data) { 1883 .name = "cam_cc_mclk1_clk", 1884 .parent_hws = (const struct clk_hw*[]) { 1885 &cam_cc_mclk1_clk_src.clkr.hw, 1886 }, 1887 .num_parents = 1, 1888 .flags = CLK_SET_RATE_PARENT, 1889 .ops = &clk_branch2_ops, 1890 }, 1891 }, 1892 }; 1893 1894 static struct clk_branch cam_cc_mclk2_clk = { 1895 .halt_reg = 0x15050, 1896 .halt_check = BRANCH_HALT, 1897 .clkr = { 1898 .enable_reg = 0x15050, 1899 .enable_mask = BIT(0), 1900 .hw.init = &(const struct clk_init_data) { 1901 .name = "cam_cc_mclk2_clk", 1902 .parent_hws = (const struct clk_hw*[]) { 1903 &cam_cc_mclk2_clk_src.clkr.hw, 1904 }, 1905 .num_parents = 1, 1906 .flags = CLK_SET_RATE_PARENT, 1907 .ops = &clk_branch2_ops, 1908 }, 1909 }, 1910 }; 1911 1912 static struct clk_branch cam_cc_mclk3_clk = { 1913 .halt_reg = 0x1506c, 1914 .halt_check = BRANCH_HALT, 1915 .clkr = { 1916 .enable_reg = 0x1506c, 1917 .enable_mask = BIT(0), 1918 .hw.init = &(const struct clk_init_data) { 1919 .name = "cam_cc_mclk3_clk", 1920 .parent_hws = (const struct clk_hw*[]) { 1921 &cam_cc_mclk3_clk_src.clkr.hw, 1922 }, 1923 .num_parents = 1, 1924 .flags = CLK_SET_RATE_PARENT, 1925 .ops = &clk_branch2_ops, 1926 }, 1927 }, 1928 }; 1929 1930 static struct clk_branch cam_cc_mclk4_clk = { 1931 .halt_reg = 0x15088, 1932 .halt_check = BRANCH_HALT, 1933 .clkr = { 1934 .enable_reg = 0x15088, 1935 .enable_mask = BIT(0), 1936 .hw.init = &(const struct clk_init_data) { 1937 .name = "cam_cc_mclk4_clk", 1938 .parent_hws = (const struct clk_hw*[]) { 1939 &cam_cc_mclk4_clk_src.clkr.hw, 1940 }, 1941 .num_parents = 1, 1942 .flags = CLK_SET_RATE_PARENT, 1943 .ops = &clk_branch2_ops, 1944 }, 1945 }, 1946 }; 1947 1948 static struct clk_branch cam_cc_mclk5_clk = { 1949 .halt_reg = 0x150a4, 1950 .halt_check = BRANCH_HALT, 1951 .clkr = { 1952 .enable_reg = 0x150a4, 1953 .enable_mask = BIT(0), 1954 .hw.init = &(const struct clk_init_data) { 1955 .name = "cam_cc_mclk5_clk", 1956 .parent_hws = (const struct clk_hw*[]) { 1957 &cam_cc_mclk5_clk_src.clkr.hw, 1958 }, 1959 .num_parents = 1, 1960 .flags = CLK_SET_RATE_PARENT, 1961 .ops = &clk_branch2_ops, 1962 }, 1963 }, 1964 }; 1965 1966 static struct clk_branch cam_cc_mclk6_clk = { 1967 .halt_reg = 0x150c0, 1968 .halt_check = BRANCH_HALT, 1969 .clkr = { 1970 .enable_reg = 0x150c0, 1971 .enable_mask = BIT(0), 1972 .hw.init = &(const struct clk_init_data) { 1973 .name = "cam_cc_mclk6_clk", 1974 .parent_hws = (const struct clk_hw*[]) { 1975 &cam_cc_mclk6_clk_src.clkr.hw, 1976 }, 1977 .num_parents = 1, 1978 .flags = CLK_SET_RATE_PARENT, 1979 .ops = &clk_branch2_ops, 1980 }, 1981 }, 1982 }; 1983 1984 static struct clk_branch cam_cc_mclk7_clk = { 1985 .halt_reg = 0x150dc, 1986 .halt_check = BRANCH_HALT, 1987 .clkr = { 1988 .enable_reg = 0x150dc, 1989 .enable_mask = BIT(0), 1990 .hw.init = &(const struct clk_init_data) { 1991 .name = "cam_cc_mclk7_clk", 1992 .parent_hws = (const struct clk_hw*[]) { 1993 &cam_cc_mclk7_clk_src.clkr.hw, 1994 }, 1995 .num_parents = 1, 1996 .flags = CLK_SET_RATE_PARENT, 1997 .ops = &clk_branch2_ops, 1998 }, 1999 }, 2000 }; 2001 2002 static struct clk_branch cam_cc_qdss_debug_clk = { 2003 .halt_reg = 0x13928, 2004 .halt_check = BRANCH_HALT, 2005 .clkr = { 2006 .enable_reg = 0x13928, 2007 .enable_mask = BIT(0), 2008 .hw.init = &(const struct clk_init_data) { 2009 .name = "cam_cc_qdss_debug_clk", 2010 .parent_hws = (const struct clk_hw*[]) { 2011 &cam_cc_qdss_debug_clk_src.clkr.hw, 2012 }, 2013 .num_parents = 1, 2014 .flags = CLK_SET_RATE_PARENT, 2015 .ops = &clk_branch2_ops, 2016 }, 2017 }, 2018 }; 2019 2020 static struct clk_branch cam_cc_qdss_debug_xo_clk = { 2021 .halt_reg = 0x1392c, 2022 .halt_check = BRANCH_HALT, 2023 .clkr = { 2024 .enable_reg = 0x1392c, 2025 .enable_mask = BIT(0), 2026 .hw.init = &(const struct clk_init_data) { 2027 .name = "cam_cc_qdss_debug_xo_clk", 2028 .parent_hws = (const struct clk_hw*[]) { 2029 &cam_cc_xo_clk_src.clkr.hw, 2030 }, 2031 .num_parents = 1, 2032 .flags = CLK_SET_RATE_PARENT, 2033 .ops = &clk_branch2_ops, 2034 }, 2035 }, 2036 }; 2037 2038 static struct gdsc cam_cc_titan_top_gdsc = { 2039 .gdscr = 0x13930, 2040 .en_rest_wait_val = 0x2, 2041 .en_few_wait_val = 0x2, 2042 .clk_dis_wait_val = 0xf, 2043 .pd = { 2044 .name = "cam_cc_titan_top_gdsc", 2045 }, 2046 .pwrsts = PWRSTS_OFF_ON, 2047 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2048 }; 2049 2050 static struct gdsc cam_cc_bps_gdsc = { 2051 .gdscr = 0x10004, 2052 .en_rest_wait_val = 0x2, 2053 .en_few_wait_val = 0x2, 2054 .clk_dis_wait_val = 0xf, 2055 .pd = { 2056 .name = "cam_cc_bps_gdsc", 2057 }, 2058 .pwrsts = PWRSTS_OFF_ON, 2059 .parent = &cam_cc_titan_top_gdsc.pd, 2060 .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2061 }; 2062 2063 static struct gdsc cam_cc_ife_0_gdsc = { 2064 .gdscr = 0x11004, 2065 .en_rest_wait_val = 0x2, 2066 .en_few_wait_val = 0x2, 2067 .clk_dis_wait_val = 0xf, 2068 .pd = { 2069 .name = "cam_cc_ife_0_gdsc", 2070 }, 2071 .pwrsts = PWRSTS_OFF_ON, 2072 .parent = &cam_cc_titan_top_gdsc.pd, 2073 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2074 }; 2075 2076 static struct gdsc cam_cc_ife_1_gdsc = { 2077 .gdscr = 0x12004, 2078 .en_rest_wait_val = 0x2, 2079 .en_few_wait_val = 0x2, 2080 .clk_dis_wait_val = 0xf, 2081 .pd = { 2082 .name = "cam_cc_ife_1_gdsc", 2083 }, 2084 .pwrsts = PWRSTS_OFF_ON, 2085 .parent = &cam_cc_titan_top_gdsc.pd, 2086 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2087 }; 2088 2089 static struct gdsc cam_cc_ipe_0_gdsc = { 2090 .gdscr = 0x103bc, 2091 .en_rest_wait_val = 0x2, 2092 .en_few_wait_val = 0x2, 2093 .clk_dis_wait_val = 0xf, 2094 .pd = { 2095 .name = "cam_cc_ipe_0_gdsc", 2096 }, 2097 .pwrsts = PWRSTS_OFF_ON, 2098 .parent = &cam_cc_titan_top_gdsc.pd, 2099 .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2100 }; 2101 2102 static struct clk_regmap *cam_cc_glymur_clocks[] = { 2103 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, 2104 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, 2105 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, 2106 [CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr, 2107 [CAM_CC_CAMNOC_AXI_NRT_CLK] = &cam_cc_camnoc_axi_nrt_clk.clkr, 2108 [CAM_CC_CAMNOC_AXI_RT_CLK] = &cam_cc_camnoc_axi_rt_clk.clkr, 2109 [CAM_CC_CAMNOC_AXI_RT_CLK_SRC] = &cam_cc_camnoc_axi_rt_clk_src.clkr, 2110 [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, 2111 [CAM_CC_CAMNOC_XO_CLK] = &cam_cc_camnoc_xo_clk.clkr, 2112 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, 2113 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, 2114 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, 2115 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, 2116 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 2117 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 2118 [CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr, 2119 [CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr, 2120 [CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr, 2121 [CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr, 2122 [CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr, 2123 [CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr, 2124 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 2125 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 2126 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 2127 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 2128 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 2129 [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr, 2130 [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr, 2131 [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr, 2132 [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr, 2133 [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr, 2134 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 2135 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 2136 [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, 2137 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 2138 [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr, 2139 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 2140 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 2141 [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, 2142 [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, 2143 [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, 2144 [CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr, 2145 [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, 2146 [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, 2147 [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, 2148 [CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr, 2149 [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr, 2150 [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, 2151 [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, 2152 [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, 2153 [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, 2154 [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, 2155 [CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr, 2156 [CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr, 2157 [CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr, 2158 [CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr, 2159 [CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr, 2160 [CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr, 2161 [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, 2162 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, 2163 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 2164 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 2165 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 2166 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 2167 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 2168 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 2169 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 2170 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 2171 [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, 2172 [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, 2173 [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr, 2174 [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr, 2175 [CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr, 2176 [CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr, 2177 [CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr, 2178 [CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr, 2179 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 2180 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, 2181 [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, 2182 [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 2183 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, 2184 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 2185 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 2186 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, 2187 [CAM_CC_PLL4] = &cam_cc_pll4.clkr, 2188 [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, 2189 [CAM_CC_PLL5] = &cam_cc_pll5.clkr, 2190 [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr, 2191 [CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr, 2192 [CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr, 2193 [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr, 2194 [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, 2195 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 2196 [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, 2197 }; 2198 2199 static struct gdsc *cam_cc_glymur_gdscs[] = { 2200 [CAM_CC_BPS_GDSC] = &cam_cc_bps_gdsc, 2201 [CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc, 2202 [CAM_CC_IFE_1_GDSC] = &cam_cc_ife_1_gdsc, 2203 [CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc, 2204 [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc, 2205 }; 2206 2207 static const struct qcom_reset_map cam_cc_glymur_resets[] = { 2208 [CAM_CC_BPS_BCR] = { 0x10000 }, 2209 [CAM_CC_ICP_BCR] = { 0x133c8 }, 2210 [CAM_CC_IFE_0_BCR] = { 0x11000 }, 2211 [CAM_CC_IFE_1_BCR] = { 0x12000 }, 2212 [CAM_CC_IPE_0_BCR] = { 0x103b8 }, 2213 [CAM_CC_QDSS_DEBUG_BCR] = { 0x137f8 }, 2214 }; 2215 2216 static struct clk_alpha_pll *cam_cc_glymur_plls[] = { 2217 &cam_cc_pll0, 2218 &cam_cc_pll1, 2219 &cam_cc_pll2, 2220 &cam_cc_pll3, 2221 &cam_cc_pll4, 2222 &cam_cc_pll5, 2223 }; 2224 2225 static const u32 cam_cc_glymur_critical_cbcrs[] = { 2226 0x13960, /* CAM_CC_GDSC_CLK */ 2227 0x1397c, /* CAM_CC_SLEEP_CLK */ 2228 }; 2229 2230 static const struct regmap_config cam_cc_glymur_regmap_config = { 2231 .reg_bits = 32, 2232 .reg_stride = 4, 2233 .val_bits = 32, 2234 .max_register = 0x1603c, 2235 .fast_io = true, 2236 }; 2237 2238 static const struct qcom_cc_driver_data cam_cc_glymur_driver_data = { 2239 .alpha_plls = cam_cc_glymur_plls, 2240 .num_alpha_plls = ARRAY_SIZE(cam_cc_glymur_plls), 2241 .clk_cbcrs = cam_cc_glymur_critical_cbcrs, 2242 .num_clk_cbcrs = ARRAY_SIZE(cam_cc_glymur_critical_cbcrs), 2243 }; 2244 2245 static const struct qcom_cc_desc cam_cc_glymur_desc = { 2246 .config = &cam_cc_glymur_regmap_config, 2247 .clks = cam_cc_glymur_clocks, 2248 .num_clks = ARRAY_SIZE(cam_cc_glymur_clocks), 2249 .resets = cam_cc_glymur_resets, 2250 .num_resets = ARRAY_SIZE(cam_cc_glymur_resets), 2251 .gdscs = cam_cc_glymur_gdscs, 2252 .num_gdscs = ARRAY_SIZE(cam_cc_glymur_gdscs), 2253 .use_rpm = true, 2254 .driver_data = &cam_cc_glymur_driver_data, 2255 }; 2256 2257 static const struct of_device_id cam_cc_glymur_match_table[] = { 2258 { .compatible = "qcom,glymur-camcc" }, 2259 { } 2260 }; 2261 MODULE_DEVICE_TABLE(of, cam_cc_glymur_match_table); 2262 2263 static int cam_cc_glymur_probe(struct platform_device *pdev) 2264 { 2265 return qcom_cc_probe(pdev, &cam_cc_glymur_desc); 2266 } 2267 2268 static struct platform_driver cam_cc_glymur_driver = { 2269 .probe = cam_cc_glymur_probe, 2270 .driver = { 2271 .name = "camcc-glymur", 2272 .of_match_table = cam_cc_glymur_match_table, 2273 }, 2274 }; 2275 2276 module_platform_driver(cam_cc_glymur_driver); 2277 2278 MODULE_DESCRIPTION("QTI CAMCC GLYMUR Driver"); 2279 MODULE_LICENSE("GPL"); 2280