1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2018, The Linux Foundation. All rights reserved. 3 #include <linux/clk-provider.h> 4 #include <linux/module.h> 5 #include <linux/of.h> 6 #include <linux/platform_device.h> 7 #include <linux/regmap.h> 8 9 #include "clk-alpha-pll.h" 10 11 static struct clk_alpha_pll ipq_pll_huayra = { 12 .offset = 0x0, 13 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_APSS], 14 .flags = SUPPORTS_DYNAMIC_UPDATE, 15 .clkr = { 16 .enable_reg = 0x0, 17 .enable_mask = BIT(0), 18 .hw.init = &(const struct clk_init_data) { 19 .name = "a53pll", 20 .parent_data = &(const struct clk_parent_data) { 21 .fw_name = "xo", 22 }, 23 .num_parents = 1, 24 .ops = &clk_alpha_pll_huayra_ops, 25 }, 26 }, 27 }; 28 29 static struct clk_alpha_pll ipq_pll_stromer = { 30 .offset = 0x0, 31 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER], 32 .flags = SUPPORTS_DYNAMIC_UPDATE, 33 .clkr = { 34 .enable_reg = 0x0, 35 .enable_mask = BIT(0), 36 .hw.init = &(const struct clk_init_data) { 37 .name = "a53pll", 38 .parent_data = &(const struct clk_parent_data) { 39 .fw_name = "xo", 40 }, 41 .num_parents = 1, 42 .ops = &clk_alpha_pll_stromer_ops, 43 }, 44 }, 45 }; 46 47 static struct clk_alpha_pll ipq_pll_stromer_plus = { 48 .offset = 0x0, 49 /* 50 * The register offsets of the Stromer Plus PLL used in IPQ5332 51 * are the same as the Stromer PLL's offsets. 52 */ 53 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER], 54 .flags = SUPPORTS_DYNAMIC_UPDATE, 55 .clkr = { 56 .enable_reg = 0x0, 57 .enable_mask = BIT(0), 58 .hw.init = &(const struct clk_init_data) { 59 .name = "a53pll", 60 .parent_data = &(const struct clk_parent_data) { 61 .fw_name = "xo", 62 }, 63 .num_parents = 1, 64 .ops = &clk_alpha_pll_stromer_plus_ops, 65 }, 66 }, 67 }; 68 69 /* 1.008 GHz configuration */ 70 static const struct alpha_pll_config ipq5018_pll_config = { 71 .l = 0x2a, 72 .config_ctl_val = 0x4001075b, 73 .config_ctl_hi_val = 0x304, 74 .main_output_mask = BIT(0), 75 .aux_output_mask = BIT(1), 76 .early_output_mask = BIT(3), 77 .alpha_en_mask = BIT(24), 78 .status_val = 0x3, 79 .status_mask = GENMASK(10, 8), 80 .lock_det = BIT(2), 81 .test_ctl_hi_val = 0x00400003, 82 }; 83 84 static const struct alpha_pll_config ipq5332_pll_config = { 85 .l = 0x2d, 86 .config_ctl_val = 0x4001075b, 87 .config_ctl_hi_val = 0x304, 88 .main_output_mask = BIT(0), 89 .aux_output_mask = BIT(1), 90 .early_output_mask = BIT(3), 91 .alpha_en_mask = BIT(24), 92 .status_val = 0x3, 93 .status_mask = GENMASK(10, 8), 94 .lock_det = BIT(2), 95 .test_ctl_hi_val = 0x00400003, 96 }; 97 98 static const struct alpha_pll_config ipq6018_pll_config = { 99 .l = 0x37, 100 .config_ctl_val = 0x240d4828, 101 .config_ctl_hi_val = 0x6, 102 .early_output_mask = BIT(3), 103 .aux2_output_mask = BIT(2), 104 .aux_output_mask = BIT(1), 105 .main_output_mask = BIT(0), 106 .test_ctl_val = 0x1c0000C0, 107 .test_ctl_hi_val = 0x4000, 108 }; 109 110 static const struct alpha_pll_config ipq8074_pll_config = { 111 .l = 0x48, 112 .config_ctl_val = 0x200d4828, 113 .config_ctl_hi_val = 0x6, 114 .early_output_mask = BIT(3), 115 .aux2_output_mask = BIT(2), 116 .aux_output_mask = BIT(1), 117 .main_output_mask = BIT(0), 118 .test_ctl_val = 0x1c000000, 119 .test_ctl_hi_val = 0x4000, 120 }; 121 122 static const struct alpha_pll_config ipq9574_pll_config = { 123 .l = 0x3b, 124 .config_ctl_val = 0x200d4828, 125 .config_ctl_hi_val = 0x6, 126 .early_output_mask = BIT(3), 127 .aux2_output_mask = BIT(2), 128 .aux_output_mask = BIT(1), 129 .main_output_mask = BIT(0), 130 .test_ctl_val = 0x0, 131 .test_ctl_hi_val = 0x4000, 132 }; 133 134 struct apss_pll_data { 135 int pll_type; 136 struct clk_alpha_pll *pll; 137 const struct alpha_pll_config *pll_config; 138 }; 139 140 static const struct apss_pll_data ipq5018_pll_data = { 141 .pll_type = CLK_ALPHA_PLL_TYPE_STROMER, 142 .pll = &ipq_pll_stromer, 143 .pll_config = &ipq5018_pll_config, 144 }; 145 146 static const struct apss_pll_data ipq5332_pll_data = { 147 .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS, 148 .pll = &ipq_pll_stromer_plus, 149 .pll_config = &ipq5332_pll_config, 150 }; 151 152 static const struct apss_pll_data ipq8074_pll_data = { 153 .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA, 154 .pll = &ipq_pll_huayra, 155 .pll_config = &ipq8074_pll_config, 156 }; 157 158 static const struct apss_pll_data ipq6018_pll_data = { 159 .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA, 160 .pll = &ipq_pll_huayra, 161 .pll_config = &ipq6018_pll_config, 162 }; 163 164 static const struct apss_pll_data ipq9574_pll_data = { 165 .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA, 166 .pll = &ipq_pll_huayra, 167 .pll_config = &ipq9574_pll_config, 168 }; 169 170 static const struct regmap_config ipq_pll_regmap_config = { 171 .reg_bits = 32, 172 .reg_stride = 4, 173 .val_bits = 32, 174 .max_register = 0x40, 175 .fast_io = true, 176 }; 177 178 static int apss_ipq_pll_probe(struct platform_device *pdev) 179 { 180 const struct apss_pll_data *data; 181 struct device *dev = &pdev->dev; 182 struct regmap *regmap; 183 void __iomem *base; 184 int ret; 185 186 base = devm_platform_ioremap_resource(pdev, 0); 187 if (IS_ERR(base)) 188 return PTR_ERR(base); 189 190 regmap = devm_regmap_init_mmio(dev, base, &ipq_pll_regmap_config); 191 if (IS_ERR(regmap)) 192 return PTR_ERR(regmap); 193 194 data = of_device_get_match_data(&pdev->dev); 195 if (!data) 196 return -ENODEV; 197 198 if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA) 199 clk_alpha_pll_configure(data->pll, regmap, data->pll_config); 200 else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER || 201 data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS) 202 clk_stromer_pll_configure(data->pll, regmap, data->pll_config); 203 204 ret = devm_clk_register_regmap(dev, &data->pll->clkr); 205 if (ret) 206 return ret; 207 208 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 209 &data->pll->clkr.hw); 210 } 211 212 static const struct of_device_id apss_ipq_pll_match_table[] = { 213 { .compatible = "qcom,ipq5018-a53pll", .data = &ipq5018_pll_data }, 214 { .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data }, 215 { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data }, 216 { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data }, 217 { .compatible = "qcom,ipq9574-a73pll", .data = &ipq9574_pll_data }, 218 { } 219 }; 220 MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table); 221 222 static struct platform_driver apss_ipq_pll_driver = { 223 .probe = apss_ipq_pll_probe, 224 .driver = { 225 .name = "qcom-ipq-apss-pll", 226 .of_match_table = apss_ipq_pll_match_table, 227 }, 228 }; 229 module_platform_driver(apss_ipq_pll_driver); 230 231 MODULE_DESCRIPTION("Qualcomm technology Inc APSS ALPHA PLL Driver"); 232 MODULE_LICENSE("GPL v2"); 233