xref: /linux/drivers/clk/qcom/a7-pll.c (revision 8137a49e1567726eb10fcf55ad141ac19804ca6b)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Qualcomm A7 PLL driver
4  *
5  * Copyright (c) 2020, Linaro Limited
6  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
7  */
8 
9 #include <linux/clk-provider.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/regmap.h>
13 
14 #include "clk-alpha-pll.h"
15 
16 #define LUCID_PLL_OFF_L_VAL 0x04
17 
18 static const struct pll_vco lucid_vco[] = {
19 	{ 249600000, 2000000000, 0 },
20 };
21 
22 static struct clk_alpha_pll a7pll = {
23 	.offset = 0x100,
24 	.vco_table = lucid_vco,
25 	.num_vco = ARRAY_SIZE(lucid_vco),
26 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
27 	.clkr = {
28 		.hw.init = &(struct clk_init_data){
29 			.name = "a7pll",
30 			.parent_data =  &(const struct clk_parent_data){
31 				.fw_name = "bi_tcxo",
32 			},
33 			.num_parents = 1,
34 			.ops = &clk_alpha_pll_lucid_ops,
35 		},
36 	},
37 };
38 
39 static const struct alpha_pll_config a7pll_config = {
40 	.l = 0x39,
41 	.config_ctl_val = 0x20485699,
42 	.config_ctl_hi_val = 0x2261,
43 	.config_ctl_hi1_val = 0x029A699C,
44 	.user_ctl_val = 0x1,
45 	.user_ctl_hi_val = 0x805,
46 };
47 
48 static const struct regmap_config a7pll_regmap_config = {
49 	.reg_bits		= 32,
50 	.reg_stride		= 4,
51 	.val_bits		= 32,
52 	.max_register		= 0x1000,
53 	.fast_io		= true,
54 };
55 
56 static int qcom_a7pll_probe(struct platform_device *pdev)
57 {
58 	struct device *dev = &pdev->dev;
59 	struct regmap *regmap;
60 	void __iomem *base;
61 	u32 l_val;
62 	int ret;
63 
64 	base = devm_platform_ioremap_resource(pdev, 0);
65 	if (IS_ERR(base))
66 		return PTR_ERR(base);
67 
68 	regmap = devm_regmap_init_mmio(dev, base, &a7pll_regmap_config);
69 	if (IS_ERR(regmap))
70 		return PTR_ERR(regmap);
71 
72 	/* Configure PLL only if the l_val is zero */
73 	regmap_read(regmap, a7pll.offset + LUCID_PLL_OFF_L_VAL, &l_val);
74 	if (!l_val)
75 		clk_lucid_pll_configure(&a7pll, regmap, &a7pll_config);
76 
77 	ret = devm_clk_register_regmap(dev, &a7pll.clkr);
78 	if (ret)
79 		return ret;
80 
81 	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
82 					   &a7pll.clkr.hw);
83 }
84 
85 static const struct of_device_id qcom_a7pll_match_table[] = {
86 	{ .compatible = "qcom,sdx55-a7pll" },
87 	{ }
88 };
89 MODULE_DEVICE_TABLE(of, qcom_a7pll_match_table);
90 
91 static struct platform_driver qcom_a7pll_driver = {
92 	.probe = qcom_a7pll_probe,
93 	.driver = {
94 		.name = "qcom-a7pll",
95 		.of_match_table = qcom_a7pll_match_table,
96 	},
97 };
98 module_platform_driver(qcom_a7pll_driver);
99 
100 MODULE_DESCRIPTION("Qualcomm A7 PLL Driver");
101 MODULE_LICENSE("GPL v2");
102