1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014 Google, Inc. 4 */ 5 6 #define pr_fmt(fmt) "%s: " fmt, __func__ 7 8 #include <linux/clk-provider.h> 9 #include <linux/io.h> 10 #include <linux/kernel.h> 11 #include <linux/printk.h> 12 #include <linux/slab.h> 13 14 #include "clk.h" 15 16 #define PLL_STATUS 0x0 17 #define PLL_STATUS_LOCK BIT(0) 18 19 #define PLL_CTRL1 0x4 20 #define PLL_CTRL1_REFDIV_SHIFT 0 21 #define PLL_CTRL1_REFDIV_MASK 0x3f 22 #define PLL_CTRL1_FBDIV_SHIFT 6 23 #define PLL_CTRL1_FBDIV_MASK 0xfff 24 #define PLL_INT_CTRL1_POSTDIV1_SHIFT 18 25 #define PLL_INT_CTRL1_POSTDIV1_MASK 0x7 26 #define PLL_INT_CTRL1_POSTDIV2_SHIFT 21 27 #define PLL_INT_CTRL1_POSTDIV2_MASK 0x7 28 #define PLL_INT_CTRL1_PD BIT(24) 29 #define PLL_INT_CTRL1_DSMPD BIT(25) 30 #define PLL_INT_CTRL1_FOUTPOSTDIVPD BIT(26) 31 #define PLL_INT_CTRL1_FOUTVCOPD BIT(27) 32 33 #define PLL_CTRL2 0x8 34 #define PLL_FRAC_CTRL2_FRAC_SHIFT 0 35 #define PLL_FRAC_CTRL2_FRAC_MASK 0xffffff 36 #define PLL_FRAC_CTRL2_POSTDIV1_SHIFT 24 37 #define PLL_FRAC_CTRL2_POSTDIV1_MASK 0x7 38 #define PLL_FRAC_CTRL2_POSTDIV2_SHIFT 27 39 #define PLL_FRAC_CTRL2_POSTDIV2_MASK 0x7 40 #define PLL_INT_CTRL2_BYPASS BIT(28) 41 42 #define PLL_CTRL3 0xc 43 #define PLL_FRAC_CTRL3_PD BIT(0) 44 #define PLL_FRAC_CTRL3_DACPD BIT(1) 45 #define PLL_FRAC_CTRL3_DSMPD BIT(2) 46 #define PLL_FRAC_CTRL3_FOUTPOSTDIVPD BIT(3) 47 #define PLL_FRAC_CTRL3_FOUT4PHASEPD BIT(4) 48 #define PLL_FRAC_CTRL3_FOUTVCOPD BIT(5) 49 50 #define PLL_CTRL4 0x10 51 #define PLL_FRAC_CTRL4_BYPASS BIT(28) 52 53 #define MIN_PFD 9600000UL 54 #define MIN_VCO_LA 400000000UL 55 #define MAX_VCO_LA 1600000000UL 56 #define MIN_VCO_FRAC_INT 600000000UL 57 #define MAX_VCO_FRAC_INT 1600000000UL 58 #define MIN_VCO_FRAC_FRAC 600000000UL 59 #define MAX_VCO_FRAC_FRAC 2400000000UL 60 #define MIN_OUTPUT_LA 8000000UL 61 #define MAX_OUTPUT_LA 1600000000UL 62 #define MIN_OUTPUT_FRAC 12000000UL 63 #define MAX_OUTPUT_FRAC 1600000000UL 64 65 /* Fractional PLL operating modes */ 66 enum pll_mode { 67 PLL_MODE_FRAC, 68 PLL_MODE_INT, 69 }; 70 71 struct pistachio_clk_pll { 72 struct clk_hw hw; 73 void __iomem *base; 74 struct pistachio_pll_rate_table *rates; 75 unsigned int nr_rates; 76 }; 77 78 static inline u32 pll_readl(struct pistachio_clk_pll *pll, u32 reg) 79 { 80 return readl(pll->base + reg); 81 } 82 83 static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg) 84 { 85 writel(val, pll->base + reg); 86 } 87 88 static inline void pll_lock(struct pistachio_clk_pll *pll) 89 { 90 while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK)) 91 cpu_relax(); 92 } 93 94 static inline u64 do_div_round_closest(u64 dividend, u64 divisor) 95 { 96 dividend += divisor / 2; 97 return div64_u64(dividend, divisor); 98 } 99 100 static inline struct pistachio_clk_pll *to_pistachio_pll(struct clk_hw *hw) 101 { 102 return container_of(hw, struct pistachio_clk_pll, hw); 103 } 104 105 static inline enum pll_mode pll_frac_get_mode(struct clk_hw *hw) 106 { 107 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); 108 u32 val; 109 110 val = pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_DSMPD; 111 return val ? PLL_MODE_INT : PLL_MODE_FRAC; 112 } 113 114 static inline void pll_frac_set_mode(struct clk_hw *hw, enum pll_mode mode) 115 { 116 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); 117 u32 val; 118 119 val = pll_readl(pll, PLL_CTRL3); 120 if (mode == PLL_MODE_INT) 121 val |= PLL_FRAC_CTRL3_DSMPD | PLL_FRAC_CTRL3_DACPD; 122 else 123 val &= ~(PLL_FRAC_CTRL3_DSMPD | PLL_FRAC_CTRL3_DACPD); 124 125 pll_writel(pll, val, PLL_CTRL3); 126 } 127 128 static struct pistachio_pll_rate_table * 129 pll_get_params(struct pistachio_clk_pll *pll, unsigned long fref, 130 unsigned long fout) 131 { 132 unsigned int i; 133 134 for (i = 0; i < pll->nr_rates; i++) { 135 if (pll->rates[i].fref == fref && pll->rates[i].fout == fout) 136 return &pll->rates[i]; 137 } 138 139 return NULL; 140 } 141 142 static int pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 143 { 144 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); 145 unsigned int i; 146 147 for (i = 0; i < pll->nr_rates; i++) { 148 if (i > 0 && pll->rates[i].fref == req->best_parent_rate && 149 pll->rates[i].fout <= req->rate) { 150 req->rate = pll->rates[i - 1].fout; 151 152 return 0; 153 } 154 } 155 156 req->rate = pll->rates[0].fout; 157 158 return 0; 159 } 160 161 static int pll_gf40lp_frac_enable(struct clk_hw *hw) 162 { 163 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); 164 u32 val; 165 166 val = pll_readl(pll, PLL_CTRL3); 167 val &= ~(PLL_FRAC_CTRL3_PD | PLL_FRAC_CTRL3_FOUTPOSTDIVPD | 168 PLL_FRAC_CTRL3_FOUT4PHASEPD | PLL_FRAC_CTRL3_FOUTVCOPD); 169 pll_writel(pll, val, PLL_CTRL3); 170 171 val = pll_readl(pll, PLL_CTRL4); 172 val &= ~PLL_FRAC_CTRL4_BYPASS; 173 pll_writel(pll, val, PLL_CTRL4); 174 175 pll_lock(pll); 176 177 return 0; 178 } 179 180 static void pll_gf40lp_frac_disable(struct clk_hw *hw) 181 { 182 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); 183 u32 val; 184 185 val = pll_readl(pll, PLL_CTRL3); 186 val |= PLL_FRAC_CTRL3_PD; 187 pll_writel(pll, val, PLL_CTRL3); 188 } 189 190 static int pll_gf40lp_frac_is_enabled(struct clk_hw *hw) 191 { 192 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); 193 194 return !(pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_PD); 195 } 196 197 static int pll_gf40lp_frac_set_rate(struct clk_hw *hw, unsigned long rate, 198 unsigned long parent_rate) 199 { 200 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); 201 struct pistachio_pll_rate_table *params; 202 int enabled = pll_gf40lp_frac_is_enabled(hw); 203 u64 val, vco, old_postdiv1, old_postdiv2; 204 const char *name = clk_hw_get_name(hw); 205 206 if (rate < MIN_OUTPUT_FRAC || rate > MAX_OUTPUT_FRAC) 207 return -EINVAL; 208 209 params = pll_get_params(pll, parent_rate, rate); 210 if (!params || !params->refdiv) 211 return -EINVAL; 212 213 /* calculate vco */ 214 vco = params->fref; 215 vco *= (params->fbdiv << 24) + params->frac; 216 vco = div64_u64(vco, params->refdiv << 24); 217 218 if (vco < MIN_VCO_FRAC_FRAC || vco > MAX_VCO_FRAC_FRAC) 219 pr_warn("%s: VCO %llu is out of range %lu..%lu\n", name, vco, 220 MIN_VCO_FRAC_FRAC, MAX_VCO_FRAC_FRAC); 221 222 val = div64_u64(params->fref, params->refdiv); 223 if (val < MIN_PFD) 224 pr_warn("%s: PFD %llu is too low (min %lu)\n", 225 name, val, MIN_PFD); 226 if (val > vco / 16) 227 pr_warn("%s: PFD %llu is too high (max %llu)\n", 228 name, val, vco / 16); 229 230 val = pll_readl(pll, PLL_CTRL1); 231 val &= ~((PLL_CTRL1_REFDIV_MASK << PLL_CTRL1_REFDIV_SHIFT) | 232 (PLL_CTRL1_FBDIV_MASK << PLL_CTRL1_FBDIV_SHIFT)); 233 val |= (params->refdiv << PLL_CTRL1_REFDIV_SHIFT) | 234 (params->fbdiv << PLL_CTRL1_FBDIV_SHIFT); 235 pll_writel(pll, val, PLL_CTRL1); 236 237 val = pll_readl(pll, PLL_CTRL2); 238 239 old_postdiv1 = (val >> PLL_FRAC_CTRL2_POSTDIV1_SHIFT) & 240 PLL_FRAC_CTRL2_POSTDIV1_MASK; 241 old_postdiv2 = (val >> PLL_FRAC_CTRL2_POSTDIV2_SHIFT) & 242 PLL_FRAC_CTRL2_POSTDIV2_MASK; 243 if (enabled && 244 (params->postdiv1 != old_postdiv1 || 245 params->postdiv2 != old_postdiv2)) 246 pr_warn("%s: changing postdiv while PLL is enabled\n", name); 247 248 if (params->postdiv2 > params->postdiv1) 249 pr_warn("%s: postdiv2 should not exceed postdiv1\n", name); 250 251 val &= ~((PLL_FRAC_CTRL2_FRAC_MASK << PLL_FRAC_CTRL2_FRAC_SHIFT) | 252 (PLL_FRAC_CTRL2_POSTDIV1_MASK << 253 PLL_FRAC_CTRL2_POSTDIV1_SHIFT) | 254 (PLL_FRAC_CTRL2_POSTDIV2_MASK << 255 PLL_FRAC_CTRL2_POSTDIV2_SHIFT)); 256 val |= (params->frac << PLL_FRAC_CTRL2_FRAC_SHIFT) | 257 (params->postdiv1 << PLL_FRAC_CTRL2_POSTDIV1_SHIFT) | 258 (params->postdiv2 << PLL_FRAC_CTRL2_POSTDIV2_SHIFT); 259 pll_writel(pll, val, PLL_CTRL2); 260 261 /* set operating mode */ 262 if (params->frac) 263 pll_frac_set_mode(hw, PLL_MODE_FRAC); 264 else 265 pll_frac_set_mode(hw, PLL_MODE_INT); 266 267 if (enabled) 268 pll_lock(pll); 269 270 return 0; 271 } 272 273 static unsigned long pll_gf40lp_frac_recalc_rate(struct clk_hw *hw, 274 unsigned long parent_rate) 275 { 276 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); 277 u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate; 278 279 val = pll_readl(pll, PLL_CTRL1); 280 prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK; 281 fbdiv = (val >> PLL_CTRL1_FBDIV_SHIFT) & PLL_CTRL1_FBDIV_MASK; 282 283 val = pll_readl(pll, PLL_CTRL2); 284 postdiv1 = (val >> PLL_FRAC_CTRL2_POSTDIV1_SHIFT) & 285 PLL_FRAC_CTRL2_POSTDIV1_MASK; 286 postdiv2 = (val >> PLL_FRAC_CTRL2_POSTDIV2_SHIFT) & 287 PLL_FRAC_CTRL2_POSTDIV2_MASK; 288 frac = (val >> PLL_FRAC_CTRL2_FRAC_SHIFT) & PLL_FRAC_CTRL2_FRAC_MASK; 289 290 /* get operating mode (int/frac) and calculate rate accordingly */ 291 rate = parent_rate; 292 if (pll_frac_get_mode(hw) == PLL_MODE_FRAC) 293 rate *= (fbdiv << 24) + frac; 294 else 295 rate *= (fbdiv << 24); 296 297 rate = do_div_round_closest(rate, (prediv * postdiv1 * postdiv2) << 24); 298 299 return rate; 300 } 301 302 static const struct clk_ops pll_gf40lp_frac_ops = { 303 .enable = pll_gf40lp_frac_enable, 304 .disable = pll_gf40lp_frac_disable, 305 .is_enabled = pll_gf40lp_frac_is_enabled, 306 .recalc_rate = pll_gf40lp_frac_recalc_rate, 307 .determine_rate = pll_determine_rate, 308 .set_rate = pll_gf40lp_frac_set_rate, 309 }; 310 311 static const struct clk_ops pll_gf40lp_frac_fixed_ops = { 312 .enable = pll_gf40lp_frac_enable, 313 .disable = pll_gf40lp_frac_disable, 314 .is_enabled = pll_gf40lp_frac_is_enabled, 315 .recalc_rate = pll_gf40lp_frac_recalc_rate, 316 }; 317 318 static int pll_gf40lp_laint_enable(struct clk_hw *hw) 319 { 320 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); 321 u32 val; 322 323 val = pll_readl(pll, PLL_CTRL1); 324 val &= ~(PLL_INT_CTRL1_PD | 325 PLL_INT_CTRL1_FOUTPOSTDIVPD | PLL_INT_CTRL1_FOUTVCOPD); 326 pll_writel(pll, val, PLL_CTRL1); 327 328 val = pll_readl(pll, PLL_CTRL2); 329 val &= ~PLL_INT_CTRL2_BYPASS; 330 pll_writel(pll, val, PLL_CTRL2); 331 332 pll_lock(pll); 333 334 return 0; 335 } 336 337 static void pll_gf40lp_laint_disable(struct clk_hw *hw) 338 { 339 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); 340 u32 val; 341 342 val = pll_readl(pll, PLL_CTRL1); 343 val |= PLL_INT_CTRL1_PD; 344 pll_writel(pll, val, PLL_CTRL1); 345 } 346 347 static int pll_gf40lp_laint_is_enabled(struct clk_hw *hw) 348 { 349 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); 350 351 return !(pll_readl(pll, PLL_CTRL1) & PLL_INT_CTRL1_PD); 352 } 353 354 static int pll_gf40lp_laint_set_rate(struct clk_hw *hw, unsigned long rate, 355 unsigned long parent_rate) 356 { 357 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); 358 struct pistachio_pll_rate_table *params; 359 int enabled = pll_gf40lp_laint_is_enabled(hw); 360 u32 val, vco, old_postdiv1, old_postdiv2; 361 const char *name = clk_hw_get_name(hw); 362 363 if (rate < MIN_OUTPUT_LA || rate > MAX_OUTPUT_LA) 364 return -EINVAL; 365 366 params = pll_get_params(pll, parent_rate, rate); 367 if (!params || !params->refdiv) 368 return -EINVAL; 369 370 vco = div_u64(params->fref * params->fbdiv, params->refdiv); 371 if (vco < MIN_VCO_LA || vco > MAX_VCO_LA) 372 pr_warn("%s: VCO %u is out of range %lu..%lu\n", name, vco, 373 MIN_VCO_LA, MAX_VCO_LA); 374 375 val = div_u64(params->fref, params->refdiv); 376 if (val < MIN_PFD) 377 pr_warn("%s: PFD %u is too low (min %lu)\n", 378 name, val, MIN_PFD); 379 if (val > vco / 16) 380 pr_warn("%s: PFD %u is too high (max %u)\n", 381 name, val, vco / 16); 382 383 val = pll_readl(pll, PLL_CTRL1); 384 385 old_postdiv1 = (val >> PLL_INT_CTRL1_POSTDIV1_SHIFT) & 386 PLL_INT_CTRL1_POSTDIV1_MASK; 387 old_postdiv2 = (val >> PLL_INT_CTRL1_POSTDIV2_SHIFT) & 388 PLL_INT_CTRL1_POSTDIV2_MASK; 389 if (enabled && 390 (params->postdiv1 != old_postdiv1 || 391 params->postdiv2 != old_postdiv2)) 392 pr_warn("%s: changing postdiv while PLL is enabled\n", name); 393 394 if (params->postdiv2 > params->postdiv1) 395 pr_warn("%s: postdiv2 should not exceed postdiv1\n", name); 396 397 val &= ~((PLL_CTRL1_REFDIV_MASK << PLL_CTRL1_REFDIV_SHIFT) | 398 (PLL_CTRL1_FBDIV_MASK << PLL_CTRL1_FBDIV_SHIFT) | 399 (PLL_INT_CTRL1_POSTDIV1_MASK << PLL_INT_CTRL1_POSTDIV1_SHIFT) | 400 (PLL_INT_CTRL1_POSTDIV2_MASK << PLL_INT_CTRL1_POSTDIV2_SHIFT)); 401 val |= (params->refdiv << PLL_CTRL1_REFDIV_SHIFT) | 402 (params->fbdiv << PLL_CTRL1_FBDIV_SHIFT) | 403 (params->postdiv1 << PLL_INT_CTRL1_POSTDIV1_SHIFT) | 404 (params->postdiv2 << PLL_INT_CTRL1_POSTDIV2_SHIFT); 405 pll_writel(pll, val, PLL_CTRL1); 406 407 if (enabled) 408 pll_lock(pll); 409 410 return 0; 411 } 412 413 static unsigned long pll_gf40lp_laint_recalc_rate(struct clk_hw *hw, 414 unsigned long parent_rate) 415 { 416 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); 417 u32 val, prediv, fbdiv, postdiv1, postdiv2; 418 u64 rate = parent_rate; 419 420 val = pll_readl(pll, PLL_CTRL1); 421 prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK; 422 fbdiv = (val >> PLL_CTRL1_FBDIV_SHIFT) & PLL_CTRL1_FBDIV_MASK; 423 postdiv1 = (val >> PLL_INT_CTRL1_POSTDIV1_SHIFT) & 424 PLL_INT_CTRL1_POSTDIV1_MASK; 425 postdiv2 = (val >> PLL_INT_CTRL1_POSTDIV2_SHIFT) & 426 PLL_INT_CTRL1_POSTDIV2_MASK; 427 428 rate *= fbdiv; 429 rate = do_div_round_closest(rate, prediv * postdiv1 * postdiv2); 430 431 return rate; 432 } 433 434 static const struct clk_ops pll_gf40lp_laint_ops = { 435 .enable = pll_gf40lp_laint_enable, 436 .disable = pll_gf40lp_laint_disable, 437 .is_enabled = pll_gf40lp_laint_is_enabled, 438 .recalc_rate = pll_gf40lp_laint_recalc_rate, 439 .determine_rate = pll_determine_rate, 440 .set_rate = pll_gf40lp_laint_set_rate, 441 }; 442 443 static const struct clk_ops pll_gf40lp_laint_fixed_ops = { 444 .enable = pll_gf40lp_laint_enable, 445 .disable = pll_gf40lp_laint_disable, 446 .is_enabled = pll_gf40lp_laint_is_enabled, 447 .recalc_rate = pll_gf40lp_laint_recalc_rate, 448 }; 449 450 static struct clk *pll_register(const char *name, const char *parent_name, 451 unsigned long flags, void __iomem *base, 452 enum pistachio_pll_type type, 453 struct pistachio_pll_rate_table *rates, 454 unsigned int nr_rates) 455 { 456 struct pistachio_clk_pll *pll; 457 struct clk_init_data init; 458 struct clk *clk; 459 460 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 461 if (!pll) 462 return ERR_PTR(-ENOMEM); 463 464 init.name = name; 465 init.flags = flags | CLK_GET_RATE_NOCACHE; 466 init.parent_names = &parent_name; 467 init.num_parents = 1; 468 469 switch (type) { 470 case PLL_GF40LP_FRAC: 471 if (rates) 472 init.ops = &pll_gf40lp_frac_ops; 473 else 474 init.ops = &pll_gf40lp_frac_fixed_ops; 475 break; 476 case PLL_GF40LP_LAINT: 477 if (rates) 478 init.ops = &pll_gf40lp_laint_ops; 479 else 480 init.ops = &pll_gf40lp_laint_fixed_ops; 481 break; 482 default: 483 pr_err("Unrecognized PLL type %u\n", type); 484 kfree(pll); 485 return ERR_PTR(-EINVAL); 486 } 487 488 pll->hw.init = &init; 489 pll->base = base; 490 pll->rates = rates; 491 pll->nr_rates = nr_rates; 492 493 clk = clk_register(NULL, &pll->hw); 494 if (IS_ERR(clk)) 495 kfree(pll); 496 497 return clk; 498 } 499 500 void pistachio_clk_register_pll(struct pistachio_clk_provider *p, 501 struct pistachio_pll *pll, 502 unsigned int num) 503 { 504 struct clk *clk; 505 unsigned int i; 506 507 for (i = 0; i < num; i++) { 508 clk = pll_register(pll[i].name, pll[i].parent, 509 0, p->base + pll[i].reg_base, 510 pll[i].type, pll[i].rates, 511 pll[i].nr_rates); 512 p->clk_data.clks[pll[i].id] = clk; 513 } 514 } 515