1 /* 2 * Clk driver for NXP LPC18xx/LPC43xx Clock Control Unit (CCU) 3 * 4 * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com> 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/clk-provider.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/slab.h> 18 #include <linux/string.h> 19 20 #include <dt-bindings/clock/lpc18xx-ccu.h> 21 22 /* Bit defines for CCU branch configuration register */ 23 #define LPC18XX_CCU_RUN BIT(0) 24 #define LPC18XX_CCU_AUTO BIT(1) 25 #define LPC18XX_CCU_DIV BIT(5) 26 #define LPC18XX_CCU_DIVSTAT BIT(27) 27 28 /* CCU branch feature bits */ 29 #define CCU_BRANCH_IS_BUS BIT(0) 30 #define CCU_BRANCH_HAVE_DIV2 BIT(1) 31 32 struct lpc18xx_branch_clk_data { 33 const char **name; 34 int num; 35 }; 36 37 struct lpc18xx_clk_branch { 38 const char *base_name; 39 const char *name; 40 u16 offset; 41 u16 flags; 42 struct clk *clk; 43 struct clk_gate gate; 44 }; 45 46 static struct lpc18xx_clk_branch clk_branches[] = { 47 {"base_apb3_clk", "apb3_bus", CLK_APB3_BUS, CCU_BRANCH_IS_BUS}, 48 {"base_apb3_clk", "apb3_i2c1", CLK_APB3_I2C1, 0}, 49 {"base_apb3_clk", "apb3_dac", CLK_APB3_DAC, 0}, 50 {"base_apb3_clk", "apb3_adc0", CLK_APB3_ADC0, 0}, 51 {"base_apb3_clk", "apb3_adc1", CLK_APB3_ADC1, 0}, 52 {"base_apb3_clk", "apb3_can0", CLK_APB3_CAN0, 0}, 53 54 {"base_apb1_clk", "apb1_bus", CLK_APB1_BUS, CCU_BRANCH_IS_BUS}, 55 {"base_apb1_clk", "apb1_mc_pwm", CLK_APB1_MOTOCON_PWM, 0}, 56 {"base_apb1_clk", "apb1_i2c0", CLK_APB1_I2C0, 0}, 57 {"base_apb1_clk", "apb1_i2s", CLK_APB1_I2S, 0}, 58 {"base_apb1_clk", "apb1_can1", CLK_APB1_CAN1, 0}, 59 60 {"base_spifi_clk", "spifi", CLK_SPIFI, 0}, 61 62 {"base_cpu_clk", "cpu_bus", CLK_CPU_BUS, CCU_BRANCH_IS_BUS}, 63 {"base_cpu_clk", "cpu_spifi", CLK_CPU_SPIFI, 0}, 64 {"base_cpu_clk", "cpu_gpio", CLK_CPU_GPIO, 0}, 65 {"base_cpu_clk", "cpu_lcd", CLK_CPU_LCD, 0}, 66 {"base_cpu_clk", "cpu_ethernet", CLK_CPU_ETHERNET, 0}, 67 {"base_cpu_clk", "cpu_usb0", CLK_CPU_USB0, 0}, 68 {"base_cpu_clk", "cpu_emc", CLK_CPU_EMC, 0}, 69 {"base_cpu_clk", "cpu_sdio", CLK_CPU_SDIO, 0}, 70 {"base_cpu_clk", "cpu_dma", CLK_CPU_DMA, 0}, 71 {"base_cpu_clk", "cpu_core", CLK_CPU_CORE, 0}, 72 {"base_cpu_clk", "cpu_sct", CLK_CPU_SCT, 0}, 73 {"base_cpu_clk", "cpu_usb1", CLK_CPU_USB1, 0}, 74 {"base_cpu_clk", "cpu_emcdiv", CLK_CPU_EMCDIV, CCU_BRANCH_HAVE_DIV2}, 75 {"base_cpu_clk", "cpu_flasha", CLK_CPU_FLASHA, CCU_BRANCH_HAVE_DIV2}, 76 {"base_cpu_clk", "cpu_flashb", CLK_CPU_FLASHB, CCU_BRANCH_HAVE_DIV2}, 77 {"base_cpu_clk", "cpu_m0app", CLK_CPU_M0APP, CCU_BRANCH_HAVE_DIV2}, 78 {"base_cpu_clk", "cpu_adchs", CLK_CPU_ADCHS, CCU_BRANCH_HAVE_DIV2}, 79 {"base_cpu_clk", "cpu_eeprom", CLK_CPU_EEPROM, CCU_BRANCH_HAVE_DIV2}, 80 {"base_cpu_clk", "cpu_wwdt", CLK_CPU_WWDT, 0}, 81 {"base_cpu_clk", "cpu_uart0", CLK_CPU_UART0, 0}, 82 {"base_cpu_clk", "cpu_uart1", CLK_CPU_UART1, 0}, 83 {"base_cpu_clk", "cpu_ssp0", CLK_CPU_SSP0, 0}, 84 {"base_cpu_clk", "cpu_timer0", CLK_CPU_TIMER0, 0}, 85 {"base_cpu_clk", "cpu_timer1", CLK_CPU_TIMER1, 0}, 86 {"base_cpu_clk", "cpu_scu", CLK_CPU_SCU, 0}, 87 {"base_cpu_clk", "cpu_creg", CLK_CPU_CREG, 0}, 88 {"base_cpu_clk", "cpu_ritimer", CLK_CPU_RITIMER, 0}, 89 {"base_cpu_clk", "cpu_uart2", CLK_CPU_UART2, 0}, 90 {"base_cpu_clk", "cpu_uart3", CLK_CPU_UART3, 0}, 91 {"base_cpu_clk", "cpu_timer2", CLK_CPU_TIMER2, 0}, 92 {"base_cpu_clk", "cpu_timer3", CLK_CPU_TIMER3, 0}, 93 {"base_cpu_clk", "cpu_ssp1", CLK_CPU_SSP1, 0}, 94 {"base_cpu_clk", "cpu_qei", CLK_CPU_QEI, 0}, 95 96 {"base_periph_clk", "periph_bus", CLK_PERIPH_BUS, CCU_BRANCH_IS_BUS}, 97 {"base_periph_clk", "periph_core", CLK_PERIPH_CORE, 0}, 98 {"base_periph_clk", "periph_sgpio", CLK_PERIPH_SGPIO, 0}, 99 100 {"base_usb0_clk", "usb0", CLK_USB0, 0}, 101 {"base_usb1_clk", "usb1", CLK_USB1, 0}, 102 {"base_spi_clk", "spi", CLK_SPI, 0}, 103 {"base_adchs_clk", "adchs", CLK_ADCHS, 0}, 104 105 {"base_audio_clk", "audio", CLK_AUDIO, 0}, 106 {"base_uart3_clk", "apb2_uart3", CLK_APB2_UART3, 0}, 107 {"base_uart2_clk", "apb2_uart2", CLK_APB2_UART2, 0}, 108 {"base_uart1_clk", "apb0_uart1", CLK_APB0_UART1, 0}, 109 {"base_uart0_clk", "apb0_uart0", CLK_APB0_UART0, 0}, 110 {"base_ssp1_clk", "apb2_ssp1", CLK_APB2_SSP1, 0}, 111 {"base_ssp0_clk", "apb0_ssp0", CLK_APB0_SSP0, 0}, 112 {"base_sdio_clk", "sdio", CLK_SDIO, 0}, 113 }; 114 115 static struct clk *lpc18xx_ccu_branch_clk_get(struct of_phandle_args *clkspec, 116 void *data) 117 { 118 struct lpc18xx_branch_clk_data *clk_data = data; 119 unsigned int offset = clkspec->args[0]; 120 int i, j; 121 122 for (i = 0; i < ARRAY_SIZE(clk_branches); i++) { 123 if (clk_branches[i].offset != offset) 124 continue; 125 126 for (j = 0; j < clk_data->num; j++) { 127 if (!strcmp(clk_branches[i].base_name, clk_data->name[j])) 128 return clk_branches[i].clk; 129 } 130 } 131 132 pr_err("%s: invalid clock offset %d\n", __func__, offset); 133 134 return ERR_PTR(-EINVAL); 135 } 136 137 static int lpc18xx_ccu_gate_endisable(struct clk_hw *hw, bool enable) 138 { 139 struct clk_gate *gate = to_clk_gate(hw); 140 u32 val; 141 142 /* 143 * Divider field is write only, so divider stat field must 144 * be read so divider field can be set accordingly. 145 */ 146 val = readl(gate->reg); 147 if (val & LPC18XX_CCU_DIVSTAT) 148 val |= LPC18XX_CCU_DIV; 149 150 if (enable) { 151 val |= LPC18XX_CCU_RUN; 152 } else { 153 /* 154 * To safely disable a branch clock a squence of two separate 155 * writes must be used. First write should set the AUTO bit 156 * and the next write should clear the RUN bit. 157 */ 158 val |= LPC18XX_CCU_AUTO; 159 writel(val, gate->reg); 160 161 val &= ~LPC18XX_CCU_RUN; 162 } 163 164 writel(val, gate->reg); 165 166 return 0; 167 } 168 169 static int lpc18xx_ccu_gate_enable(struct clk_hw *hw) 170 { 171 return lpc18xx_ccu_gate_endisable(hw, true); 172 } 173 174 static void lpc18xx_ccu_gate_disable(struct clk_hw *hw) 175 { 176 lpc18xx_ccu_gate_endisable(hw, false); 177 } 178 179 static int lpc18xx_ccu_gate_is_enabled(struct clk_hw *hw) 180 { 181 const struct clk_hw *parent; 182 183 /* 184 * The branch clock registers are only accessible 185 * if the base (parent) clock is enabled. Register 186 * access with a disabled base clock will hang the 187 * system. 188 */ 189 parent = clk_hw_get_parent(hw); 190 if (!parent) 191 return 0; 192 193 if (!clk_hw_is_enabled(parent)) 194 return 0; 195 196 return clk_gate_ops.is_enabled(hw); 197 } 198 199 static const struct clk_ops lpc18xx_ccu_gate_ops = { 200 .enable = lpc18xx_ccu_gate_enable, 201 .disable = lpc18xx_ccu_gate_disable, 202 .is_enabled = lpc18xx_ccu_gate_is_enabled, 203 }; 204 205 static void lpc18xx_ccu_register_branch_gate_div(struct lpc18xx_clk_branch *branch, 206 void __iomem *reg_base, 207 const char *parent) 208 { 209 const struct clk_ops *div_ops = NULL; 210 struct clk_divider *div = NULL; 211 struct clk_hw *div_hw = NULL; 212 213 if (branch->flags & CCU_BRANCH_HAVE_DIV2) { 214 div = kzalloc(sizeof(*div), GFP_KERNEL); 215 if (!div) 216 return; 217 218 div->reg = branch->offset + reg_base; 219 div->flags = CLK_DIVIDER_READ_ONLY; 220 div->shift = 27; 221 div->width = 1; 222 223 div_hw = &div->hw; 224 div_ops = &clk_divider_ro_ops; 225 } 226 227 branch->gate.reg = branch->offset + reg_base; 228 branch->gate.bit_idx = 0; 229 230 branch->clk = clk_register_composite(NULL, branch->name, &parent, 1, 231 NULL, NULL, 232 div_hw, div_ops, 233 &branch->gate.hw, &lpc18xx_ccu_gate_ops, 0); 234 if (IS_ERR(branch->clk)) { 235 kfree(div); 236 pr_warn("%s: failed to register %s\n", __func__, branch->name); 237 return; 238 } 239 240 /* Grab essential branch clocks for CPU and SDRAM */ 241 switch (branch->offset) { 242 case CLK_CPU_EMC: 243 case CLK_CPU_CORE: 244 case CLK_CPU_CREG: 245 case CLK_CPU_EMCDIV: 246 clk_prepare_enable(branch->clk); 247 } 248 } 249 250 static void lpc18xx_ccu_register_branch_clks(void __iomem *reg_base, 251 const char *base_name) 252 { 253 const char *parent = base_name; 254 int i; 255 256 for (i = 0; i < ARRAY_SIZE(clk_branches); i++) { 257 if (strcmp(clk_branches[i].base_name, base_name)) 258 continue; 259 260 lpc18xx_ccu_register_branch_gate_div(&clk_branches[i], reg_base, 261 parent); 262 263 if (clk_branches[i].flags & CCU_BRANCH_IS_BUS) 264 parent = clk_branches[i].name; 265 } 266 } 267 268 static void __init lpc18xx_ccu_init(struct device_node *np) 269 { 270 struct lpc18xx_branch_clk_data *clk_data; 271 void __iomem *reg_base; 272 int i, ret; 273 274 reg_base = of_iomap(np, 0); 275 if (!reg_base) { 276 pr_warn("%s: failed to map address range\n", __func__); 277 return; 278 } 279 280 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); 281 if (!clk_data) { 282 iounmap(reg_base); 283 return; 284 } 285 286 clk_data->num = of_property_count_strings(np, "clock-names"); 287 clk_data->name = kcalloc(clk_data->num, sizeof(char *), GFP_KERNEL); 288 if (!clk_data->name) { 289 iounmap(reg_base); 290 kfree(clk_data); 291 return; 292 } 293 294 for (i = 0; i < clk_data->num; i++) { 295 ret = of_property_read_string_index(np, "clock-names", i, 296 &clk_data->name[i]); 297 if (ret) { 298 pr_warn("%s: failed to get clock name at idx %d\n", 299 __func__, i); 300 continue; 301 } 302 303 lpc18xx_ccu_register_branch_clks(reg_base, clk_data->name[i]); 304 } 305 306 of_clk_add_provider(np, lpc18xx_ccu_branch_clk_get, clk_data); 307 } 308 CLK_OF_DECLARE(lpc18xx_ccu, "nxp,lpc1850-ccu", lpc18xx_ccu_init); 309