1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Marvell EBU SoC common clock handling 4 * 5 * Copyright (C) 2012 Marvell 6 * 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 9 * Andrew Lunn <andrew@lunn.ch> 10 * 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/slab.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/io.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/syscore_ops.h> 21 22 #include "common.h" 23 24 /* 25 * Core Clocks 26 */ 27 28 #define SSCG_CONF_MODE(reg) (((reg) >> 16) & 0x3) 29 #define SSCG_SPREAD_DOWN 0x0 30 #define SSCG_SPREAD_UP 0x1 31 #define SSCG_SPREAD_CENTRAL 0x2 32 #define SSCG_CONF_LOW(reg) (((reg) >> 8) & 0xFF) 33 #define SSCG_CONF_HIGH(reg) ((reg) & 0xFF) 34 35 static struct clk_onecell_data clk_data; 36 37 /* 38 * This function can be used by the Kirkwood, the Armada 370, the 39 * Armada XP and the Armada 375 SoC. The name of the function was 40 * chosen following the dt convention: using the first known SoC 41 * compatible with it. 42 */ 43 u32 kirkwood_fix_sscg_deviation(u32 system_clk) 44 { 45 struct device_node *sscg_np = NULL; 46 void __iomem *sscg_map; 47 u32 sscg_reg; 48 s32 low_bound, high_bound; 49 u64 freq_swing_half; 50 51 sscg_np = of_find_node_by_name(NULL, "sscg"); 52 if (sscg_np == NULL) { 53 pr_err("cannot get SSCG register node\n"); 54 return system_clk; 55 } 56 57 sscg_map = of_iomap(sscg_np, 0); 58 if (sscg_map == NULL) { 59 pr_err("cannot map SSCG register\n"); 60 goto out; 61 } 62 63 sscg_reg = readl(sscg_map); 64 high_bound = SSCG_CONF_HIGH(sscg_reg); 65 low_bound = SSCG_CONF_LOW(sscg_reg); 66 67 if ((high_bound - low_bound) <= 0) 68 goto out; 69 /* 70 * From Marvell engineer we got the following formula (when 71 * this code was written, the datasheet was erroneous) 72 * Spread percentage = 1/96 * (H - L) / H 73 * H = SSCG_High_Boundary 74 * L = SSCG_Low_Boundary 75 * 76 * As the deviation is half of spread then it lead to the 77 * following formula in the code. 78 * 79 * To avoid an overflow and not lose any significant digit in 80 * the same time we have to use a 64 bit integer. 81 */ 82 83 freq_swing_half = (((u64)high_bound - (u64)low_bound) 84 * (u64)system_clk); 85 do_div(freq_swing_half, (2 * 96 * high_bound)); 86 87 switch (SSCG_CONF_MODE(sscg_reg)) { 88 case SSCG_SPREAD_DOWN: 89 system_clk -= freq_swing_half; 90 break; 91 case SSCG_SPREAD_UP: 92 system_clk += freq_swing_half; 93 break; 94 case SSCG_SPREAD_CENTRAL: 95 default: 96 break; 97 } 98 99 iounmap(sscg_map); 100 101 out: 102 of_node_put(sscg_np); 103 104 return system_clk; 105 } 106 107 void __init mvebu_coreclk_setup(struct device_node *np, 108 const struct coreclk_soc_desc *desc) 109 { 110 const char *tclk_name = "tclk"; 111 const char *cpuclk_name = "cpuclk"; 112 void __iomem *base; 113 unsigned long rate; 114 int n; 115 116 base = of_iomap(np, 0); 117 if (WARN_ON(!base)) 118 return; 119 120 /* Allocate struct for TCLK, cpu clk, and core ratio clocks */ 121 clk_data.clk_num = 2 + desc->num_ratios; 122 123 /* One more clock for the optional refclk */ 124 if (desc->get_refclk_freq) 125 clk_data.clk_num += 1; 126 127 clk_data.clks = kzalloc_objs(*clk_data.clks, clk_data.clk_num); 128 if (WARN_ON(!clk_data.clks)) { 129 iounmap(base); 130 return; 131 } 132 133 /* Register TCLK */ 134 of_property_read_string_index(np, "clock-output-names", 0, 135 &tclk_name); 136 rate = desc->get_tclk_freq(base); 137 clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL, 0, 138 rate); 139 WARN_ON(IS_ERR(clk_data.clks[0])); 140 141 /* Register CPU clock */ 142 of_property_read_string_index(np, "clock-output-names", 1, 143 &cpuclk_name); 144 rate = desc->get_cpu_freq(base); 145 146 if (desc->is_sscg_enabled && desc->fix_sscg_deviation 147 && desc->is_sscg_enabled(base)) 148 rate = desc->fix_sscg_deviation(rate); 149 150 clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL, 0, 151 rate); 152 WARN_ON(IS_ERR(clk_data.clks[1])); 153 154 /* Register fixed-factor clocks derived from CPU clock */ 155 for (n = 0; n < desc->num_ratios; n++) { 156 const char *rclk_name = desc->ratios[n].name; 157 int mult, div; 158 159 of_property_read_string_index(np, "clock-output-names", 160 2+n, &rclk_name); 161 desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div); 162 clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name, 163 cpuclk_name, 0, mult, div); 164 WARN_ON(IS_ERR(clk_data.clks[2+n])); 165 } 166 167 /* Register optional refclk */ 168 if (desc->get_refclk_freq) { 169 const char *name = "refclk"; 170 of_property_read_string_index(np, "clock-output-names", 171 2 + desc->num_ratios, &name); 172 rate = desc->get_refclk_freq(base); 173 clk_data.clks[2 + desc->num_ratios] = 174 clk_register_fixed_rate(NULL, name, NULL, 0, rate); 175 WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios])); 176 } 177 178 /* SAR register isn't needed anymore */ 179 iounmap(base); 180 181 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 182 } 183 184 /* 185 * Clock Gating Control 186 */ 187 188 DEFINE_SPINLOCK(ctrl_gating_lock); 189 190 struct clk_gating_ctrl { 191 spinlock_t *lock; 192 struct clk **gates; 193 int num_gates; 194 void __iomem *base; 195 u32 saved_reg; 196 }; 197 198 static struct clk_gating_ctrl *ctrl; 199 200 static struct clk *clk_gating_get_src( 201 struct of_phandle_args *clkspec, void *data) 202 { 203 int n; 204 205 if (clkspec->args_count < 1) 206 return ERR_PTR(-EINVAL); 207 208 for (n = 0; n < ctrl->num_gates; n++) { 209 struct clk_gate *gate = 210 to_clk_gate(__clk_get_hw(ctrl->gates[n])); 211 if (clkspec->args[0] == gate->bit_idx) 212 return ctrl->gates[n]; 213 } 214 return ERR_PTR(-ENODEV); 215 } 216 217 static int mvebu_clk_gating_suspend(void *data) 218 { 219 ctrl->saved_reg = readl(ctrl->base); 220 return 0; 221 } 222 223 static void mvebu_clk_gating_resume(void *data) 224 { 225 writel(ctrl->saved_reg, ctrl->base); 226 } 227 228 static const struct syscore_ops clk_gate_syscore_ops = { 229 .suspend = mvebu_clk_gating_suspend, 230 .resume = mvebu_clk_gating_resume, 231 }; 232 233 static struct syscore clk_gate_syscore = { 234 .ops = &clk_gate_syscore_ops, 235 }; 236 237 void __init mvebu_clk_gating_setup(struct device_node *np, 238 const struct clk_gating_soc_desc *desc) 239 { 240 struct clk *clk; 241 void __iomem *base; 242 const char *default_parent = NULL; 243 int n; 244 245 if (ctrl) { 246 pr_err("mvebu-clk-gating: cannot instantiate more than one gateable clock device\n"); 247 return; 248 } 249 250 base = of_iomap(np, 0); 251 if (WARN_ON(!base)) 252 return; 253 254 clk = of_clk_get(np, 0); 255 if (!IS_ERR(clk)) { 256 default_parent = __clk_get_name(clk); 257 clk_put(clk); 258 } 259 260 ctrl = kzalloc_obj(*ctrl); 261 if (WARN_ON(!ctrl)) 262 goto ctrl_out; 263 264 /* lock must already be initialized */ 265 ctrl->lock = &ctrl_gating_lock; 266 267 ctrl->base = base; 268 269 /* Count, allocate, and register clock gates */ 270 for (n = 0; desc[n].name;) 271 n++; 272 273 ctrl->num_gates = n; 274 ctrl->gates = kzalloc_objs(*ctrl->gates, ctrl->num_gates); 275 if (WARN_ON(!ctrl->gates)) 276 goto gates_out; 277 278 for (n = 0; n < ctrl->num_gates; n++) { 279 const char *parent = 280 (desc[n].parent) ? desc[n].parent : default_parent; 281 ctrl->gates[n] = clk_register_gate(NULL, desc[n].name, parent, 282 desc[n].flags, base, desc[n].bit_idx, 283 0, ctrl->lock); 284 WARN_ON(IS_ERR(ctrl->gates[n])); 285 } 286 287 of_clk_add_provider(np, clk_gating_get_src, ctrl); 288 289 register_syscore(&clk_gate_syscore); 290 291 return; 292 gates_out: 293 kfree(ctrl); 294 ctrl_out: 295 iounmap(base); 296 } 297