1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Marvell MVEBU CPU clock handling. 4 * 5 * Copyright (C) 2012 Marvell 6 * 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * 9 */ 10 #include <linux/kernel.h> 11 #include <linux/slab.h> 12 #include <linux/clk.h> 13 #include <linux/clk-provider.h> 14 #include <linux/of_address.h> 15 #include <linux/io.h> 16 #include <linux/of.h> 17 #include <linux/delay.h> 18 #include <linux/mvebu-pmsu.h> 19 #include <asm/smp_plat.h> 20 21 #define SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET 0x0 22 #define SYS_CTRL_CLK_DIVIDER_CTRL_RESET_ALL 0xff 23 #define SYS_CTRL_CLK_DIVIDER_CTRL_RESET_SHIFT 8 24 #define SYS_CTRL_CLK_DIVIDER_CTRL2_OFFSET 0x8 25 #define SYS_CTRL_CLK_DIVIDER_CTRL2_NBCLK_RATIO_SHIFT 16 26 #define SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET 0xC 27 #define SYS_CTRL_CLK_DIVIDER_MASK 0x3F 28 29 #define PMU_DFS_RATIO_SHIFT 16 30 #define PMU_DFS_RATIO_MASK 0x3F 31 32 #define MAX_CPU 4 33 struct cpu_clk { 34 struct clk_hw hw; 35 int cpu; 36 const char *clk_name; 37 const char *parent_name; 38 void __iomem *reg_base; 39 void __iomem *pmu_dfs; 40 }; 41 42 static struct clk **clks; 43 44 static struct clk_onecell_data clk_data; 45 46 #define to_cpu_clk(p) container_of(p, struct cpu_clk, hw) 47 48 static unsigned long clk_cpu_recalc_rate(struct clk_hw *hwclk, 49 unsigned long parent_rate) 50 { 51 struct cpu_clk *cpuclk = to_cpu_clk(hwclk); 52 u32 reg, div; 53 54 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); 55 div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK; 56 return parent_rate / div; 57 } 58 59 static int clk_cpu_determine_rate(struct clk_hw *hw, 60 struct clk_rate_request *req) 61 { 62 /* Valid ratio are 1:1, 1:2 and 1:3 */ 63 u32 div; 64 65 div = req->best_parent_rate / req->rate; 66 if (div == 0) 67 div = 1; 68 else if (div > 3) 69 div = 3; 70 71 req->rate = req->best_parent_rate / div; 72 73 return 0; 74 } 75 76 static int clk_cpu_off_set_rate(struct clk_hw *hwclk, unsigned long rate, 77 unsigned long parent_rate) 78 79 { 80 struct cpu_clk *cpuclk = to_cpu_clk(hwclk); 81 u32 reg, div; 82 u32 reload_mask; 83 84 div = parent_rate / rate; 85 reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET) 86 & (~(SYS_CTRL_CLK_DIVIDER_MASK << (cpuclk->cpu * 8)))) 87 | (div << (cpuclk->cpu * 8)); 88 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); 89 /* Set clock divider reload smooth bit mask */ 90 reload_mask = 1 << (20 + cpuclk->cpu); 91 92 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET) 93 | reload_mask; 94 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); 95 96 /* Now trigger the clock update */ 97 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET) 98 | 1 << 24; 99 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); 100 101 /* Wait for clocks to settle down then clear reload request */ 102 udelay(1000); 103 reg &= ~(reload_mask | 1 << 24); 104 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); 105 udelay(1000); 106 107 return 0; 108 } 109 110 static int clk_cpu_on_set_rate(struct clk_hw *hwclk, unsigned long rate, 111 unsigned long parent_rate) 112 { 113 u32 reg; 114 unsigned long fabric_div, target_div, cur_rate; 115 struct cpu_clk *cpuclk = to_cpu_clk(hwclk); 116 117 /* 118 * PMU DFS registers are not mapped, Device Tree does not 119 * describes them. We cannot change the frequency dynamically. 120 */ 121 if (!cpuclk->pmu_dfs) 122 return -ENODEV; 123 124 cur_rate = clk_hw_get_rate(hwclk); 125 126 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL2_OFFSET); 127 fabric_div = (reg >> SYS_CTRL_CLK_DIVIDER_CTRL2_NBCLK_RATIO_SHIFT) & 128 SYS_CTRL_CLK_DIVIDER_MASK; 129 130 /* Frequency is going up */ 131 if (rate == 2 * cur_rate) 132 target_div = fabric_div / 2; 133 /* Frequency is going down */ 134 else 135 target_div = fabric_div; 136 137 if (target_div == 0) 138 target_div = 1; 139 140 reg = readl(cpuclk->pmu_dfs); 141 reg &= ~(PMU_DFS_RATIO_MASK << PMU_DFS_RATIO_SHIFT); 142 reg |= (target_div << PMU_DFS_RATIO_SHIFT); 143 writel(reg, cpuclk->pmu_dfs); 144 145 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); 146 reg |= (SYS_CTRL_CLK_DIVIDER_CTRL_RESET_ALL << 147 SYS_CTRL_CLK_DIVIDER_CTRL_RESET_SHIFT); 148 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); 149 150 return mvebu_pmsu_dfs_request(cpuclk->cpu); 151 } 152 153 static int clk_cpu_set_rate(struct clk_hw *hwclk, unsigned long rate, 154 unsigned long parent_rate) 155 { 156 if (__clk_is_enabled(hwclk->clk)) 157 return clk_cpu_on_set_rate(hwclk, rate, parent_rate); 158 else 159 return clk_cpu_off_set_rate(hwclk, rate, parent_rate); 160 } 161 162 static const struct clk_ops cpu_ops = { 163 .recalc_rate = clk_cpu_recalc_rate, 164 .determine_rate = clk_cpu_determine_rate, 165 .set_rate = clk_cpu_set_rate, 166 }; 167 168 static void __init of_cpu_clk_setup(struct device_node *node) 169 { 170 struct cpu_clk *cpuclk; 171 void __iomem *clock_complex_base = of_iomap(node, 0); 172 void __iomem *pmu_dfs_base = of_iomap(node, 1); 173 int ncpus = num_possible_cpus(); 174 int cpu; 175 176 if (clock_complex_base == NULL) { 177 pr_err("%s: clock-complex base register not set\n", 178 __func__); 179 return; 180 } 181 182 if (pmu_dfs_base == NULL) 183 pr_warn("%s: pmu-dfs base register not set, dynamic frequency scaling not available\n", 184 __func__); 185 186 cpuclk = kcalloc(ncpus, sizeof(*cpuclk), GFP_KERNEL); 187 if (WARN_ON(!cpuclk)) 188 goto cpuclk_out; 189 190 clks = kcalloc(ncpus, sizeof(*clks), GFP_KERNEL); 191 if (WARN_ON(!clks)) 192 goto clks_out; 193 194 for_each_possible_cpu(cpu) { 195 struct clk_init_data init; 196 struct clk *clk; 197 char *clk_name = kzalloc(5, GFP_KERNEL); 198 199 if (WARN_ON(!clk_name)) 200 goto bail_out; 201 202 sprintf(clk_name, "cpu%d", cpu); 203 204 cpuclk[cpu].parent_name = of_clk_get_parent_name(node, 0); 205 cpuclk[cpu].clk_name = clk_name; 206 cpuclk[cpu].cpu = cpu; 207 cpuclk[cpu].reg_base = clock_complex_base; 208 if (pmu_dfs_base) 209 cpuclk[cpu].pmu_dfs = pmu_dfs_base + 4 * cpu; 210 cpuclk[cpu].hw.init = &init; 211 212 init.name = cpuclk[cpu].clk_name; 213 init.ops = &cpu_ops; 214 init.flags = 0; 215 init.parent_names = &cpuclk[cpu].parent_name; 216 init.num_parents = 1; 217 218 clk = clk_register(NULL, &cpuclk[cpu].hw); 219 if (WARN_ON(IS_ERR(clk))) 220 goto bail_out; 221 clks[cpu] = clk; 222 } 223 clk_data.clk_num = MAX_CPU; 224 clk_data.clks = clks; 225 of_clk_add_provider(node, of_clk_src_onecell_get, &clk_data); 226 227 return; 228 bail_out: 229 kfree(clks); 230 while(ncpus--) 231 kfree(cpuclk[ncpus].clk_name); 232 clks_out: 233 kfree(cpuclk); 234 cpuclk_out: 235 iounmap(clock_complex_base); 236 } 237 238 CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock", 239 of_cpu_clk_setup); 240 241 static void __init of_mv98dx3236_cpu_clk_setup(struct device_node *node) 242 { 243 of_clk_add_provider(node, of_clk_src_simple_get, NULL); 244 } 245 246 CLK_OF_DECLARE(mv98dx3236_cpu_clock, "marvell,mv98dx3236-cpu-clock", 247 of_mv98dx3236_cpu_clk_setup); 248