1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Marvell Armada XP SoC clocks 4 * 5 * Copyright (C) 2012 Marvell 6 * 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 9 * Andrew Lunn <andrew@lunn.ch> 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/clk-provider.h> 14 #include <linux/io.h> 15 #include <linux/of.h> 16 #include "common.h" 17 18 /* 19 * Core Clocks 20 * 21 * Armada XP Sample At Reset is a 64 bit bitfield split in two 22 * registers of 32 bits 23 */ 24 25 #define SARL 0 /* Low part [0:31] */ 26 #define SARL_AXP_PCLK_FREQ_OPT 21 27 #define SARL_AXP_PCLK_FREQ_OPT_MASK 0x7 28 #define SARL_AXP_FAB_FREQ_OPT 24 29 #define SARL_AXP_FAB_FREQ_OPT_MASK 0xF 30 #define SARH 4 /* High part [32:63] */ 31 #define SARH_AXP_PCLK_FREQ_OPT (52-32) 32 #define SARH_AXP_PCLK_FREQ_OPT_MASK 0x1 33 #define SARH_AXP_PCLK_FREQ_OPT_SHIFT 3 34 #define SARH_AXP_FAB_FREQ_OPT (51-32) 35 #define SARH_AXP_FAB_FREQ_OPT_MASK 0x1 36 #define SARH_AXP_FAB_FREQ_OPT_SHIFT 4 37 38 enum { AXP_CPU_TO_NBCLK, AXP_CPU_TO_HCLK, AXP_CPU_TO_DRAMCLK }; 39 40 static const struct coreclk_ratio axp_coreclk_ratios[] __initconst = { 41 { .id = AXP_CPU_TO_NBCLK, .name = "nbclk" }, 42 { .id = AXP_CPU_TO_HCLK, .name = "hclk" }, 43 { .id = AXP_CPU_TO_DRAMCLK, .name = "dramclk" }, 44 }; 45 46 /* Armada XP TCLK frequency is fixed to 250MHz */ 47 static u32 __init axp_get_tclk_freq(void __iomem *sar) 48 { 49 return 250000000; 50 } 51 52 static const u32 axp_cpu_freqs[] __initconst = { 53 1000000000, 54 1066000000, 55 1200000000, 56 1333000000, 57 1500000000, 58 1666000000, 59 1800000000, 60 2000000000, 61 667000000, 62 0, 63 800000000, 64 1600000000, 65 }; 66 67 static u32 __init axp_get_cpu_freq(void __iomem *sar) 68 { 69 u32 cpu_freq; 70 u8 cpu_freq_select = 0; 71 72 cpu_freq_select = ((readl(sar + SARL) >> SARL_AXP_PCLK_FREQ_OPT) & 73 SARL_AXP_PCLK_FREQ_OPT_MASK); 74 /* 75 * The upper bit is not contiguous to the other ones and 76 * located in the high part of the SAR registers 77 */ 78 cpu_freq_select |= (((readl(sar + SARH) >> SARH_AXP_PCLK_FREQ_OPT) & 79 SARH_AXP_PCLK_FREQ_OPT_MASK) << SARH_AXP_PCLK_FREQ_OPT_SHIFT); 80 if (cpu_freq_select >= ARRAY_SIZE(axp_cpu_freqs)) { 81 pr_err("CPU freq select unsupported: %d\n", cpu_freq_select); 82 cpu_freq = 0; 83 } else 84 cpu_freq = axp_cpu_freqs[cpu_freq_select]; 85 86 return cpu_freq; 87 } 88 89 static const int axp_nbclk_ratios[32][2] __initconst = { 90 {0, 1}, {1, 2}, {2, 2}, {2, 2}, 91 {1, 2}, {1, 2}, {1, 1}, {2, 3}, 92 {0, 1}, {1, 2}, {2, 4}, {0, 1}, 93 {1, 2}, {0, 1}, {0, 1}, {2, 2}, 94 {0, 1}, {0, 1}, {0, 1}, {1, 1}, 95 {2, 3}, {0, 1}, {0, 1}, {0, 1}, 96 {0, 1}, {0, 1}, {0, 1}, {1, 1}, 97 {0, 1}, {0, 1}, {0, 1}, {0, 1}, 98 }; 99 100 static const int axp_hclk_ratios[32][2] __initconst = { 101 {0, 1}, {1, 2}, {2, 6}, {2, 3}, 102 {1, 3}, {1, 4}, {1, 2}, {2, 6}, 103 {0, 1}, {1, 6}, {2, 10}, {0, 1}, 104 {1, 4}, {0, 1}, {0, 1}, {2, 5}, 105 {0, 1}, {0, 1}, {0, 1}, {1, 2}, 106 {2, 6}, {0, 1}, {0, 1}, {0, 1}, 107 {0, 1}, {0, 1}, {0, 1}, {1, 1}, 108 {0, 1}, {0, 1}, {0, 1}, {0, 1}, 109 }; 110 111 static const int axp_dramclk_ratios[32][2] __initconst = { 112 {0, 1}, {1, 2}, {2, 3}, {2, 3}, 113 {1, 3}, {1, 2}, {1, 2}, {2, 6}, 114 {0, 1}, {1, 3}, {2, 5}, {0, 1}, 115 {1, 4}, {0, 1}, {0, 1}, {2, 5}, 116 {0, 1}, {0, 1}, {0, 1}, {1, 1}, 117 {2, 3}, {0, 1}, {0, 1}, {0, 1}, 118 {0, 1}, {0, 1}, {0, 1}, {1, 1}, 119 {0, 1}, {0, 1}, {0, 1}, {0, 1}, 120 }; 121 122 static void __init axp_get_clk_ratio( 123 void __iomem *sar, int id, int *mult, int *div) 124 { 125 u32 opt = ((readl(sar + SARL) >> SARL_AXP_FAB_FREQ_OPT) & 126 SARL_AXP_FAB_FREQ_OPT_MASK); 127 /* 128 * The upper bit is not contiguous to the other ones and 129 * located in the high part of the SAR registers 130 */ 131 opt |= (((readl(sar + SARH) >> SARH_AXP_FAB_FREQ_OPT) & 132 SARH_AXP_FAB_FREQ_OPT_MASK) << SARH_AXP_FAB_FREQ_OPT_SHIFT); 133 134 switch (id) { 135 case AXP_CPU_TO_NBCLK: 136 *mult = axp_nbclk_ratios[opt][0]; 137 *div = axp_nbclk_ratios[opt][1]; 138 break; 139 case AXP_CPU_TO_HCLK: 140 *mult = axp_hclk_ratios[opt][0]; 141 *div = axp_hclk_ratios[opt][1]; 142 break; 143 case AXP_CPU_TO_DRAMCLK: 144 *mult = axp_dramclk_ratios[opt][0]; 145 *div = axp_dramclk_ratios[opt][1]; 146 break; 147 } 148 } 149 150 static const struct coreclk_soc_desc axp_coreclks = { 151 .get_tclk_freq = axp_get_tclk_freq, 152 .get_cpu_freq = axp_get_cpu_freq, 153 .get_clk_ratio = axp_get_clk_ratio, 154 .ratios = axp_coreclk_ratios, 155 .num_ratios = ARRAY_SIZE(axp_coreclk_ratios), 156 }; 157 158 /* 159 * Clock Gating Control 160 */ 161 162 static const struct clk_gating_soc_desc axp_gating_desc[] __initconst = { 163 { "audio", NULL, 0, 0 }, 164 { "ge3", NULL, 1, 0 }, 165 { "ge2", NULL, 2, 0 }, 166 { "ge1", NULL, 3, 0 }, 167 { "ge0", NULL, 4, 0 }, 168 { "pex00", NULL, 5, 0 }, 169 { "pex01", NULL, 6, 0 }, 170 { "pex02", NULL, 7, 0 }, 171 { "pex03", NULL, 8, 0 }, 172 { "pex10", NULL, 9, 0 }, 173 { "pex11", NULL, 10, 0 }, 174 { "pex12", NULL, 11, 0 }, 175 { "pex13", NULL, 12, 0 }, 176 { "bp", NULL, 13, 0 }, 177 { "sata0lnk", NULL, 14, 0 }, 178 { "sata0", "sata0lnk", 15, 0 }, 179 { "lcd", NULL, 16, 0 }, 180 { "sdio", NULL, 17, 0 }, 181 { "usb0", NULL, 18, 0 }, 182 { "usb1", NULL, 19, 0 }, 183 { "usb2", NULL, 20, 0 }, 184 { "xor0", NULL, 22, 0 }, 185 { "crypto", NULL, 23, 0 }, 186 { "tdm", NULL, 25, 0 }, 187 { "pex20", NULL, 26, 0 }, 188 { "pex30", NULL, 27, 0 }, 189 { "xor1", NULL, 28, 0 }, 190 { "sata1lnk", NULL, 29, 0 }, 191 { "sata1", "sata1lnk", 30, 0 }, 192 { } 193 }; 194 195 static void __init axp_clk_init(struct device_node *np) 196 { 197 struct device_node *cgnp = 198 of_find_compatible_node(NULL, NULL, "marvell,armada-xp-gating-clock"); 199 200 mvebu_coreclk_setup(np, &axp_coreclks); 201 202 if (cgnp) { 203 mvebu_clk_gating_setup(cgnp, axp_gating_desc); 204 of_node_put(cgnp); 205 } 206 } 207 CLK_OF_DECLARE(axp_clk, "marvell,armada-xp-core-clock", axp_clk_init); 208