1 // SPDX-License-Identifier: GPL-2.0-only 2 #include <linux/bits.h> 3 #include <linux/clk-provider.h> 4 #include <linux/module.h> 5 #include <linux/platform_device.h> 6 #include <linux/units.h> 7 8 #include <dt-bindings/clock/marvell,pxa1908.h> 9 10 #include "clk.h" 11 12 #define MPMU_UART_PLL 0x14 13 14 #define MPMU_NR_CLKS 39 15 16 struct pxa1908_clk_unit { 17 struct mmp_clk_unit unit; 18 void __iomem *base; 19 }; 20 21 static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = { 22 {PXA1908_CLK_CLK32, "clk32", NULL, 0, 32768}, 23 {PXA1908_CLK_VCTCXO, "vctcxo", NULL, 0, 26 * HZ_PER_MHZ}, 24 {PXA1908_CLK_PLL1_624, "pll1_624", NULL, 0, 624 * HZ_PER_MHZ}, 25 {PXA1908_CLK_PLL1_416, "pll1_416", NULL, 0, 416 * HZ_PER_MHZ}, 26 {PXA1908_CLK_PLL1_499, "pll1_499", NULL, 0, 499 * HZ_PER_MHZ}, 27 {PXA1908_CLK_PLL1_832, "pll1_832", NULL, 0, 832 * HZ_PER_MHZ}, 28 {PXA1908_CLK_PLL1_1248, "pll1_1248", NULL, 0, 1248 * HZ_PER_MHZ}, 29 }; 30 31 static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = { 32 {PXA1908_CLK_PLL1_D2, "pll1_d2", "pll1_624", 1, 2, 0}, 33 {PXA1908_CLK_PLL1_D4, "pll1_d4", "pll1_d2", 1, 2, 0}, 34 {PXA1908_CLK_PLL1_D6, "pll1_d6", "pll1_d2", 1, 3, 0}, 35 {PXA1908_CLK_PLL1_D8, "pll1_d8", "pll1_d4", 1, 2, 0}, 36 {PXA1908_CLK_PLL1_D12, "pll1_d12", "pll1_d6", 1, 2, 0}, 37 {PXA1908_CLK_PLL1_D13, "pll1_d13", "pll1_624", 1, 13, 0}, 38 {PXA1908_CLK_PLL1_D16, "pll1_d16", "pll1_d8", 1, 2, 0}, 39 {PXA1908_CLK_PLL1_D24, "pll1_d24", "pll1_d12", 1, 2, 0}, 40 {PXA1908_CLK_PLL1_D48, "pll1_d48", "pll1_d24", 1, 2, 0}, 41 {PXA1908_CLK_PLL1_D96, "pll1_d96", "pll1_d48", 1, 2, 0}, 42 {PXA1908_CLK_PLL1_32, "pll1_32", "pll1_d13", 2, 3, 0}, 43 {PXA1908_CLK_PLL1_208, "pll1_208", "pll1_d2", 2, 3, 0}, 44 {PXA1908_CLK_PLL1_117, "pll1_117", "pll1_624", 3, 16, 0}, 45 }; 46 47 static struct u32_fract uart_factor_tbl[] = { 48 {.numerator = 8125, .denominator = 1536}, /* 14.745MHz */ 49 }; 50 51 static struct mmp_clk_factor_masks uart_factor_masks = { 52 .factor = 2, 53 .num_mask = GENMASK(12, 0), 54 .den_mask = GENMASK(12, 0), 55 .num_shift = 16, 56 .den_shift = 0, 57 }; 58 59 static void pxa1908_pll_init(struct pxa1908_clk_unit *pxa_unit) 60 { 61 struct mmp_clk_unit *unit = &pxa_unit->unit; 62 63 mmp_register_fixed_rate_clks(unit, fixed_rate_clks, 64 ARRAY_SIZE(fixed_rate_clks)); 65 66 mmp_register_fixed_factor_clks(unit, fixed_factor_clks, 67 ARRAY_SIZE(fixed_factor_clks)); 68 69 mmp_clk_register_factor("uart_pll", "pll1_d4", 70 CLK_SET_RATE_PARENT, 71 pxa_unit->base + MPMU_UART_PLL, 72 &uart_factor_masks, uart_factor_tbl, 73 ARRAY_SIZE(uart_factor_tbl), NULL); 74 } 75 76 static int pxa1908_mpmu_probe(struct platform_device *pdev) 77 { 78 struct pxa1908_clk_unit *pxa_unit; 79 80 pxa_unit = devm_kzalloc(&pdev->dev, sizeof(*pxa_unit), GFP_KERNEL); 81 if (IS_ERR(pxa_unit)) 82 return PTR_ERR(pxa_unit); 83 84 pxa_unit->base = devm_platform_ioremap_resource(pdev, 0); 85 if (IS_ERR(pxa_unit->base)) 86 return PTR_ERR(pxa_unit->base); 87 88 mmp_clk_init(pdev->dev.of_node, &pxa_unit->unit, MPMU_NR_CLKS); 89 90 pxa1908_pll_init(pxa_unit); 91 92 return 0; 93 } 94 95 static const struct of_device_id pxa1908_mpmu_match_table[] = { 96 { .compatible = "marvell,pxa1908-mpmu" }, 97 { } 98 }; 99 MODULE_DEVICE_TABLE(of, pxa1908_mpmu_match_table); 100 101 static struct platform_driver pxa1908_mpmu_driver = { 102 .probe = pxa1908_mpmu_probe, 103 .driver = { 104 .name = "pxa1908-mpmu", 105 .of_match_table = pxa1908_mpmu_match_table 106 } 107 }; 108 module_platform_driver(pxa1908_mpmu_driver); 109 110 MODULE_AUTHOR("Duje Mihanović <duje.mihanovic@skole.hr>"); 111 MODULE_DESCRIPTION("Marvell PXA1908 MPMU Clock Driver"); 112 MODULE_LICENSE("GPL"); 113