1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * mmp factor clock operation source file 4 * 5 * Copyright (C) 2012 Marvell 6 * Chao Xie <xiechao.mail@gmail.com> 7 */ 8 9 #include <linux/clk-provider.h> 10 #include <linux/slab.h> 11 #include <linux/io.h> 12 #include <linux/err.h> 13 14 #include "clk.h" 15 /* 16 * It is M/N clock 17 * 18 * Fout from synthesizer can be given from two equations: 19 * numerator/denominator = Fin / (Fout * factor) 20 */ 21 22 #define to_clk_factor(hw) container_of(hw, struct mmp_clk_factor, hw) 23 24 static int clk_factor_determine_rate(struct clk_hw *hw, 25 struct clk_rate_request *req) 26 { 27 struct mmp_clk_factor *factor = to_clk_factor(hw); 28 u64 rate = 0, prev_rate; 29 struct u32_fract *d; 30 int i; 31 32 for (i = 0; i < factor->ftbl_cnt; i++) { 33 d = &factor->ftbl[i]; 34 35 prev_rate = rate; 36 rate = (u64)(req->best_parent_rate) * d->denominator; 37 do_div(rate, d->numerator * factor->masks->factor); 38 if (rate > req->rate) 39 break; 40 } 41 42 if ((i == 0) || (i == factor->ftbl_cnt)) 43 req->rate = rate; 44 else if ((req->rate - prev_rate) > (rate - req->rate)) 45 req->rate = rate; 46 else 47 req->rate = prev_rate; 48 49 return 0; 50 } 51 52 static unsigned long clk_factor_recalc_rate(struct clk_hw *hw, 53 unsigned long parent_rate) 54 { 55 struct mmp_clk_factor *factor = to_clk_factor(hw); 56 struct mmp_clk_factor_masks *masks = factor->masks; 57 struct u32_fract d; 58 unsigned int val; 59 u64 rate; 60 61 val = readl_relaxed(factor->base); 62 63 /* calculate numerator */ 64 d.numerator = (val >> masks->num_shift) & masks->num_mask; 65 66 /* calculate denominator */ 67 d.denominator = (val >> masks->den_shift) & masks->den_mask; 68 if (!d.denominator) 69 return 0; 70 71 rate = (u64)parent_rate * d.denominator; 72 do_div(rate, d.numerator * factor->masks->factor); 73 74 return rate; 75 } 76 77 /* Configures new clock rate*/ 78 static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate, 79 unsigned long prate) 80 { 81 struct mmp_clk_factor *factor = to_clk_factor(hw); 82 struct mmp_clk_factor_masks *masks = factor->masks; 83 int i; 84 unsigned long val; 85 unsigned long flags = 0; 86 struct u32_fract *d; 87 u64 rate = 0; 88 89 for (i = 0; i < factor->ftbl_cnt; i++) { 90 d = &factor->ftbl[i]; 91 92 rate = (u64)prate * d->denominator; 93 do_div(rate, d->numerator * factor->masks->factor); 94 if (rate > drate) 95 break; 96 } 97 d = i ? &factor->ftbl[i - 1] : &factor->ftbl[0]; 98 99 if (factor->lock) 100 spin_lock_irqsave(factor->lock, flags); 101 102 val = readl_relaxed(factor->base); 103 104 val &= ~(masks->num_mask << masks->num_shift); 105 val |= (d->numerator & masks->num_mask) << masks->num_shift; 106 107 val &= ~(masks->den_mask << masks->den_shift); 108 val |= (d->denominator & masks->den_mask) << masks->den_shift; 109 110 writel_relaxed(val, factor->base); 111 112 if (factor->lock) 113 spin_unlock_irqrestore(factor->lock, flags); 114 115 return 0; 116 } 117 118 static int clk_factor_init(struct clk_hw *hw) 119 { 120 struct mmp_clk_factor *factor = to_clk_factor(hw); 121 struct mmp_clk_factor_masks *masks = factor->masks; 122 struct u32_fract d; 123 u32 val; 124 int i; 125 unsigned long flags = 0; 126 127 if (factor->lock) 128 spin_lock_irqsave(factor->lock, flags); 129 130 val = readl(factor->base); 131 132 /* calculate numerator */ 133 d.numerator = (val >> masks->num_shift) & masks->num_mask; 134 135 /* calculate denominator */ 136 d.denominator = (val >> masks->den_shift) & masks->den_mask; 137 138 for (i = 0; i < factor->ftbl_cnt; i++) 139 if (d.denominator == factor->ftbl[i].denominator && 140 d.numerator == factor->ftbl[i].numerator) 141 break; 142 143 if (i >= factor->ftbl_cnt) { 144 val &= ~(masks->num_mask << masks->num_shift); 145 val |= (factor->ftbl[0].numerator & masks->num_mask) << masks->num_shift; 146 147 val &= ~(masks->den_mask << masks->den_shift); 148 val |= (factor->ftbl[0].denominator & masks->den_mask) << masks->den_shift; 149 } 150 151 if (!(val & masks->enable_mask) || i >= factor->ftbl_cnt) { 152 val |= masks->enable_mask; 153 writel(val, factor->base); 154 } 155 156 if (factor->lock) 157 spin_unlock_irqrestore(factor->lock, flags); 158 159 return 0; 160 } 161 162 static const struct clk_ops clk_factor_ops = { 163 .recalc_rate = clk_factor_recalc_rate, 164 .determine_rate = clk_factor_determine_rate, 165 .set_rate = clk_factor_set_rate, 166 .init = clk_factor_init, 167 }; 168 169 struct clk *mmp_clk_register_factor(const char *name, const char *parent_name, 170 unsigned long flags, void __iomem *base, 171 struct mmp_clk_factor_masks *masks, 172 struct u32_fract *ftbl, unsigned int ftbl_cnt, spinlock_t *lock) 173 { 174 struct mmp_clk_factor *factor; 175 struct clk_init_data init; 176 struct clk *clk; 177 178 if (!masks) { 179 pr_err("%s: must pass a clk_factor_mask\n", __func__); 180 return ERR_PTR(-EINVAL); 181 } 182 183 factor = kzalloc(sizeof(*factor), GFP_KERNEL); 184 if (!factor) 185 return ERR_PTR(-ENOMEM); 186 187 /* struct clk_aux assignments */ 188 factor->base = base; 189 factor->masks = masks; 190 factor->ftbl = ftbl; 191 factor->ftbl_cnt = ftbl_cnt; 192 factor->hw.init = &init; 193 factor->lock = lock; 194 195 init.name = name; 196 init.ops = &clk_factor_ops; 197 init.flags = flags; 198 init.parent_names = &parent_name; 199 init.num_parents = 1; 200 201 clk = clk_register(NULL, &factor->hw); 202 if (IS_ERR_OR_NULL(clk)) 203 kfree(factor); 204 205 return clk; 206 } 207