1 /* 2 * Purna Chandra Mandal,<purna.mandal@microchip.com> 3 * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. 4 * 5 * This program is free software; you can distribute it and/or modify it 6 * under the terms of the GNU General Public License (Version 2) as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 */ 14 #include <dt-bindings/clock/microchip,pic32-clock.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/clkdev.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/of_address.h> 21 #include <linux/of_platform.h> 22 #include <linux/platform_device.h> 23 #include <asm/traps.h> 24 25 #include "clk-core.h" 26 27 /* FRC Postscaler */ 28 #define OSC_FRCDIV_MASK 0x07 29 #define OSC_FRCDIV_SHIFT 24 30 31 /* SPLL fields */ 32 #define PLL_ICLK_MASK 0x01 33 #define PLL_ICLK_SHIFT 7 34 35 #define DECLARE_PERIPHERAL_CLOCK(__clk_name, __reg, __flags) \ 36 { \ 37 .ctrl_reg = (__reg), \ 38 .init_data = { \ 39 .name = (__clk_name), \ 40 .parent_names = (const char *[]) { \ 41 "sys_clk" \ 42 }, \ 43 .num_parents = 1, \ 44 .ops = &pic32_pbclk_ops, \ 45 .flags = (__flags), \ 46 }, \ 47 } 48 49 #define DECLARE_REFO_CLOCK(__clkid, __reg) \ 50 { \ 51 .ctrl_reg = (__reg), \ 52 .init_data = { \ 53 .name = "refo" #__clkid "_clk", \ 54 .parent_names = (const char *[]) { \ 55 "sys_clk", "pb1_clk", "posc_clk", \ 56 "frc_clk", "lprc_clk", "sosc_clk", \ 57 "sys_pll", "refi" #__clkid "_clk", \ 58 "bfrc_clk", \ 59 }, \ 60 .num_parents = 9, \ 61 .flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE,\ 62 .ops = &pic32_roclk_ops, \ 63 }, \ 64 .parent_map = (const u32[]) { \ 65 0, 1, 2, 3, 4, 5, 7, 8, 9 \ 66 }, \ 67 } 68 69 static const struct pic32_ref_osc_data ref_clks[] = { 70 DECLARE_REFO_CLOCK(1, 0x80), 71 DECLARE_REFO_CLOCK(2, 0xa0), 72 DECLARE_REFO_CLOCK(3, 0xc0), 73 DECLARE_REFO_CLOCK(4, 0xe0), 74 DECLARE_REFO_CLOCK(5, 0x100), 75 }; 76 77 static const struct pic32_periph_clk_data periph_clocks[] = { 78 DECLARE_PERIPHERAL_CLOCK("pb1_clk", 0x140, 0), 79 DECLARE_PERIPHERAL_CLOCK("pb2_clk", 0x150, CLK_IGNORE_UNUSED), 80 DECLARE_PERIPHERAL_CLOCK("pb3_clk", 0x160, 0), 81 DECLARE_PERIPHERAL_CLOCK("pb4_clk", 0x170, 0), 82 DECLARE_PERIPHERAL_CLOCK("pb5_clk", 0x180, 0), 83 DECLARE_PERIPHERAL_CLOCK("pb6_clk", 0x190, 0), 84 DECLARE_PERIPHERAL_CLOCK("cpu_clk", 0x1a0, CLK_IGNORE_UNUSED), 85 }; 86 87 static const struct pic32_sys_clk_data sys_mux_clk = { 88 .slew_reg = 0x1c0, 89 .slew_div = 2, /* step of div_4 -> div_2 -> no_div */ 90 .init_data = { 91 .name = "sys_clk", 92 .parent_names = (const char *[]) { 93 "frcdiv_clk", "sys_pll", "posc_clk", 94 "sosc_clk", "lprc_clk", "frcdiv_clk", 95 }, 96 .num_parents = 6, 97 .ops = &pic32_sclk_ops, 98 }, 99 .parent_map = (const u32[]) { 100 0, 1, 2, 4, 5, 7, 101 }, 102 }; 103 104 static const struct pic32_sys_pll_data sys_pll = { 105 .ctrl_reg = 0x020, 106 .status_reg = 0x1d0, 107 .lock_mask = BIT(7), 108 .init_data = { 109 .name = "sys_pll", 110 .parent_names = (const char *[]) { 111 "spll_mux_clk" 112 }, 113 .num_parents = 1, 114 .ops = &pic32_spll_ops, 115 }, 116 }; 117 118 static const struct pic32_sec_osc_data sosc_clk = { 119 .status_reg = 0x1d0, 120 .enable_mask = BIT(1), 121 .status_mask = BIT(4), 122 .fixed_rate = 32768, 123 .init_data = { 124 .name = "sosc_clk", 125 .parent_names = NULL, 126 .ops = &pic32_sosc_ops, 127 }, 128 }; 129 130 static int pic32mzda_critical_clks[] = { 131 PB2CLK, PB7CLK 132 }; 133 134 /* PIC32MZDA clock data */ 135 struct pic32mzda_clk_data { 136 struct clk *clks[MAXCLKS]; 137 struct pic32_clk_common core; 138 struct clk_onecell_data onecell_data; 139 struct notifier_block failsafe_notifier; 140 }; 141 142 static int pic32_fscm_nmi(struct notifier_block *nb, 143 unsigned long action, void *data) 144 { 145 struct pic32mzda_clk_data *cd; 146 147 cd = container_of(nb, struct pic32mzda_clk_data, failsafe_notifier); 148 149 /* SYSCLK is now running from BFRCCLK. Report clock failure. */ 150 if (readl(cd->core.iobase) & BIT(2)) 151 pr_alert("pic32-clk: FSCM detected clk failure.\n"); 152 153 /* TODO: detect reason of failure and recover accordingly */ 154 155 return NOTIFY_OK; 156 } 157 158 static int pic32mzda_clk_probe(struct platform_device *pdev) 159 { 160 const char *const pll_mux_parents[] = {"posc_clk", "frc_clk"}; 161 struct device_node *np = pdev->dev.of_node; 162 struct pic32mzda_clk_data *cd; 163 struct pic32_clk_common *core; 164 struct clk *pll_mux_clk, *clk; 165 struct clk **clks; 166 int nr_clks, i, ret; 167 168 cd = devm_kzalloc(&pdev->dev, sizeof(*cd), GFP_KERNEL); 169 if (!cd) 170 return -ENOMEM; 171 172 core = &cd->core; 173 core->iobase = of_io_request_and_map(np, 0, of_node_full_name(np)); 174 if (IS_ERR(core->iobase)) { 175 dev_err(&pdev->dev, "pic32-clk: failed to map registers\n"); 176 return PTR_ERR(core->iobase); 177 } 178 179 spin_lock_init(&core->reg_lock); 180 core->dev = &pdev->dev; 181 clks = &cd->clks[0]; 182 183 /* register fixed rate clocks */ 184 clks[POSCCLK] = clk_register_fixed_rate(&pdev->dev, "posc_clk", NULL, 185 0, 24000000); 186 clks[FRCCLK] = clk_register_fixed_rate(&pdev->dev, "frc_clk", NULL, 187 0, 8000000); 188 clks[BFRCCLK] = clk_register_fixed_rate(&pdev->dev, "bfrc_clk", NULL, 189 0, 8000000); 190 clks[LPRCCLK] = clk_register_fixed_rate(&pdev->dev, "lprc_clk", NULL, 191 0, 32000); 192 clks[UPLLCLK] = clk_register_fixed_rate(&pdev->dev, "usbphy_clk", NULL, 193 0, 24000000); 194 /* fixed rate (optional) clock */ 195 if (of_find_property(np, "microchip,pic32mzda-sosc", NULL)) { 196 pr_info("pic32-clk: dt requests SOSC.\n"); 197 clks[SOSCCLK] = pic32_sosc_clk_register(&sosc_clk, core); 198 } 199 /* divider clock */ 200 clks[FRCDIVCLK] = clk_register_divider(&pdev->dev, "frcdiv_clk", 201 "frc_clk", 0, 202 core->iobase, 203 OSC_FRCDIV_SHIFT, 204 OSC_FRCDIV_MASK, 205 CLK_DIVIDER_POWER_OF_TWO, 206 &core->reg_lock); 207 /* PLL ICLK mux */ 208 pll_mux_clk = clk_register_mux(&pdev->dev, "spll_mux_clk", 209 pll_mux_parents, 2, 0, 210 core->iobase + 0x020, 211 PLL_ICLK_SHIFT, 1, 0, &core->reg_lock); 212 if (IS_ERR(pll_mux_clk)) 213 pr_err("spll_mux_clk: clk register failed\n"); 214 215 /* PLL */ 216 clks[PLLCLK] = pic32_spll_clk_register(&sys_pll, core); 217 /* SYSTEM clock */ 218 clks[SCLK] = pic32_sys_clk_register(&sys_mux_clk, core); 219 /* Peripheral bus clocks */ 220 for (nr_clks = PB1CLK, i = 0; nr_clks <= PB7CLK; i++, nr_clks++) 221 clks[nr_clks] = pic32_periph_clk_register(&periph_clocks[i], 222 core); 223 /* Reference oscillator clock */ 224 for (nr_clks = REF1CLK, i = 0; nr_clks <= REF5CLK; i++, nr_clks++) 225 clks[nr_clks] = pic32_refo_clk_register(&ref_clks[i], core); 226 227 /* register clkdev */ 228 for (i = 0; i < MAXCLKS; i++) { 229 if (IS_ERR(clks[i])) 230 continue; 231 clk_register_clkdev(clks[i], NULL, __clk_get_name(clks[i])); 232 } 233 234 /* register clock provider */ 235 cd->onecell_data.clks = clks; 236 cd->onecell_data.clk_num = MAXCLKS; 237 ret = of_clk_add_provider(np, of_clk_src_onecell_get, 238 &cd->onecell_data); 239 if (ret) 240 return ret; 241 242 /* force enable critical clocks */ 243 for (i = 0; i < ARRAY_SIZE(pic32mzda_critical_clks); i++) { 244 clk = clks[pic32mzda_critical_clks[i]]; 245 if (clk_prepare_enable(clk)) 246 dev_err(&pdev->dev, "clk_prepare_enable(%s) failed\n", 247 __clk_get_name(clk)); 248 } 249 250 /* register NMI for failsafe clock monitor */ 251 cd->failsafe_notifier.notifier_call = pic32_fscm_nmi; 252 return register_nmi_notifier(&cd->failsafe_notifier); 253 } 254 255 static const struct of_device_id pic32mzda_clk_match_table[] = { 256 { .compatible = "microchip,pic32mzda-clk", }, 257 { } 258 }; 259 MODULE_DEVICE_TABLE(of, pic32mzda_clk_match_table); 260 261 static struct platform_driver pic32mzda_clk_driver = { 262 .probe = pic32mzda_clk_probe, 263 .driver = { 264 .name = "clk-pic32mzda", 265 .of_match_table = pic32mzda_clk_match_table, 266 }, 267 }; 268 269 static int __init microchip_pic32mzda_clk_init(void) 270 { 271 return platform_driver_register(&pic32mzda_clk_driver); 272 } 273 core_initcall(microchip_pic32mzda_clk_init); 274 275 MODULE_DESCRIPTION("Microchip PIC32MZDA Clock Driver"); 276 MODULE_LICENSE("GPL v2"); 277 MODULE_ALIAS("platform:clk-pic32mzda"); 278