1*b82e98bfSConor Dooley /* SPDX-License-Identifier: GPL-2.0-only */ 2*b82e98bfSConor Dooley /* 3*b82e98bfSConor Dooley * Purna Chandra Mandal,<purna.mandal@microchip.com> 4*b82e98bfSConor Dooley * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. 5*b82e98bfSConor Dooley */ 6*b82e98bfSConor Dooley #ifndef __MICROCHIP_CLK_PIC32_H_ 7*b82e98bfSConor Dooley #define __MICROCHIP_CLK_PIC32_H_ 8*b82e98bfSConor Dooley 9*b82e98bfSConor Dooley #include <linux/clk-provider.h> 10*b82e98bfSConor Dooley 11*b82e98bfSConor Dooley /* PIC32 clock data */ 12*b82e98bfSConor Dooley struct pic32_clk_common { 13*b82e98bfSConor Dooley struct device *dev; 14*b82e98bfSConor Dooley void __iomem *iobase; 15*b82e98bfSConor Dooley spinlock_t reg_lock; /* clock lock */ 16*b82e98bfSConor Dooley }; 17*b82e98bfSConor Dooley 18*b82e98bfSConor Dooley /* System PLL clock */ 19*b82e98bfSConor Dooley struct pic32_sys_pll_data { 20*b82e98bfSConor Dooley struct clk_init_data init_data; 21*b82e98bfSConor Dooley const u32 ctrl_reg; 22*b82e98bfSConor Dooley const u32 status_reg; 23*b82e98bfSConor Dooley const u32 lock_mask; 24*b82e98bfSConor Dooley }; 25*b82e98bfSConor Dooley 26*b82e98bfSConor Dooley /* System clock */ 27*b82e98bfSConor Dooley struct pic32_sys_clk_data { 28*b82e98bfSConor Dooley struct clk_init_data init_data; 29*b82e98bfSConor Dooley const u32 mux_reg; 30*b82e98bfSConor Dooley const u32 slew_reg; 31*b82e98bfSConor Dooley const u32 *parent_map; 32*b82e98bfSConor Dooley const u32 slew_div; 33*b82e98bfSConor Dooley }; 34*b82e98bfSConor Dooley 35*b82e98bfSConor Dooley /* Reference Oscillator clock */ 36*b82e98bfSConor Dooley struct pic32_ref_osc_data { 37*b82e98bfSConor Dooley struct clk_init_data init_data; 38*b82e98bfSConor Dooley const u32 ctrl_reg; 39*b82e98bfSConor Dooley const u32 *parent_map; 40*b82e98bfSConor Dooley }; 41*b82e98bfSConor Dooley 42*b82e98bfSConor Dooley /* Peripheral Bus clock */ 43*b82e98bfSConor Dooley struct pic32_periph_clk_data { 44*b82e98bfSConor Dooley struct clk_init_data init_data; 45*b82e98bfSConor Dooley const u32 ctrl_reg; 46*b82e98bfSConor Dooley }; 47*b82e98bfSConor Dooley 48*b82e98bfSConor Dooley /* External Secondary Oscillator clock */ 49*b82e98bfSConor Dooley struct pic32_sec_osc_data { 50*b82e98bfSConor Dooley struct clk_init_data init_data; 51*b82e98bfSConor Dooley const u32 enable_reg; 52*b82e98bfSConor Dooley const u32 status_reg; 53*b82e98bfSConor Dooley const u32 enable_mask; 54*b82e98bfSConor Dooley const u32 status_mask; 55*b82e98bfSConor Dooley const unsigned long fixed_rate; 56*b82e98bfSConor Dooley }; 57*b82e98bfSConor Dooley 58*b82e98bfSConor Dooley extern const struct clk_ops pic32_pbclk_ops; 59*b82e98bfSConor Dooley extern const struct clk_ops pic32_sclk_ops; 60*b82e98bfSConor Dooley extern const struct clk_ops pic32_sclk_no_div_ops; 61*b82e98bfSConor Dooley extern const struct clk_ops pic32_spll_ops; 62*b82e98bfSConor Dooley extern const struct clk_ops pic32_roclk_ops; 63*b82e98bfSConor Dooley extern const struct clk_ops pic32_sosc_ops; 64*b82e98bfSConor Dooley 65*b82e98bfSConor Dooley struct clk *pic32_periph_clk_register(const struct pic32_periph_clk_data *data, 66*b82e98bfSConor Dooley struct pic32_clk_common *core); 67*b82e98bfSConor Dooley struct clk *pic32_refo_clk_register(const struct pic32_ref_osc_data *data, 68*b82e98bfSConor Dooley struct pic32_clk_common *core); 69*b82e98bfSConor Dooley struct clk *pic32_sys_clk_register(const struct pic32_sys_clk_data *data, 70*b82e98bfSConor Dooley struct pic32_clk_common *core); 71*b82e98bfSConor Dooley struct clk *pic32_spll_clk_register(const struct pic32_sys_pll_data *data, 72*b82e98bfSConor Dooley struct pic32_clk_common *core); 73*b82e98bfSConor Dooley struct clk *pic32_sosc_clk_register(const struct pic32_sec_osc_data *data, 74*b82e98bfSConor Dooley struct pic32_clk_common *core); 75*b82e98bfSConor Dooley 76*b82e98bfSConor Dooley #endif /* __MICROCHIP_CLK_PIC32_H_*/ 77