1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Purna Chandra Mandal,<purna.mandal@microchip.com> 4 * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. 5 */ 6 #include <linux/clk-provider.h> 7 #include <linux/delay.h> 8 #include <linux/device.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <asm/mach-pic32/pic32.h> 13 #include <asm/traps.h> 14 15 #include "clk-core.h" 16 17 /* OSCCON Reg fields */ 18 #define OSC_CUR_MASK 0x07 19 #define OSC_CUR_SHIFT 12 20 #define OSC_NEW_MASK 0x07 21 #define OSC_NEW_SHIFT 8 22 #define OSC_SWEN BIT(0) 23 24 /* SPLLCON Reg fields */ 25 #define PLL_RANGE_MASK 0x07 26 #define PLL_RANGE_SHIFT 0 27 #define PLL_ICLK_MASK 0x01 28 #define PLL_ICLK_SHIFT 7 29 #define PLL_IDIV_MASK 0x07 30 #define PLL_IDIV_SHIFT 8 31 #define PLL_ODIV_MASK 0x07 32 #define PLL_ODIV_SHIFT 24 33 #define PLL_MULT_MASK 0x7F 34 #define PLL_MULT_SHIFT 16 35 #define PLL_MULT_MAX 128 36 #define PLL_ODIV_MIN 1 37 #define PLL_ODIV_MAX 5 38 39 /* Peripheral Bus Clock Reg Fields */ 40 #define PB_DIV_MASK 0x7f 41 #define PB_DIV_SHIFT 0 42 #define PB_DIV_READY BIT(11) 43 #define PB_DIV_ENABLE BIT(15) 44 #define PB_DIV_MAX 128 45 #define PB_DIV_MIN 0 46 47 /* Reference Oscillator Control Reg fields */ 48 #define REFO_SEL_MASK 0x0f 49 #define REFO_SEL_SHIFT 0 50 #define REFO_ACTIVE BIT(8) 51 #define REFO_DIVSW_EN BIT(9) 52 #define REFO_OE BIT(12) 53 #define REFO_ON BIT(15) 54 #define REFO_DIV_SHIFT 16 55 #define REFO_DIV_MASK 0x7fff 56 57 /* Reference Oscillator Trim Register Fields */ 58 #define REFO_TRIM_REG 0x10 59 #define REFO_TRIM_MASK 0x1ff 60 #define REFO_TRIM_SHIFT 23 61 #define REFO_TRIM_MAX 511 62 63 /* Mux Slew Control Register fields */ 64 #define SLEW_BUSY BIT(0) 65 #define SLEW_DOWNEN BIT(1) 66 #define SLEW_UPEN BIT(2) 67 #define SLEW_DIV 0x07 68 #define SLEW_DIV_SHIFT 8 69 #define SLEW_SYSDIV 0x0f 70 #define SLEW_SYSDIV_SHIFT 20 71 72 /* Clock Poll Timeout */ 73 #define LOCK_TIMEOUT_US USEC_PER_MSEC 74 75 /* SoC specific clock needed during SPLL clock rate switch */ 76 static struct clk_hw *pic32_sclk_hw; 77 78 /* add instruction pipeline delay while CPU clock is in-transition. */ 79 #define cpu_nop5() \ 80 do { \ 81 __asm__ __volatile__("nop"); \ 82 __asm__ __volatile__("nop"); \ 83 __asm__ __volatile__("nop"); \ 84 __asm__ __volatile__("nop"); \ 85 __asm__ __volatile__("nop"); \ 86 } while (0) 87 88 /* Perpheral bus clocks */ 89 struct pic32_periph_clk { 90 struct clk_hw hw; 91 void __iomem *ctrl_reg; 92 struct pic32_clk_common *core; 93 }; 94 95 #define clkhw_to_pbclk(_hw) container_of(_hw, struct pic32_periph_clk, hw) 96 97 static int pbclk_is_enabled(struct clk_hw *hw) 98 { 99 struct pic32_periph_clk *pb = clkhw_to_pbclk(hw); 100 101 return readl(pb->ctrl_reg) & PB_DIV_ENABLE; 102 } 103 104 static int pbclk_enable(struct clk_hw *hw) 105 { 106 struct pic32_periph_clk *pb = clkhw_to_pbclk(hw); 107 108 writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg)); 109 return 0; 110 } 111 112 static void pbclk_disable(struct clk_hw *hw) 113 { 114 struct pic32_periph_clk *pb = clkhw_to_pbclk(hw); 115 116 writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg)); 117 } 118 119 static unsigned long calc_best_divided_rate(unsigned long rate, 120 unsigned long parent_rate, 121 u32 divider_max, 122 u32 divider_min) 123 { 124 unsigned long divided_rate, divided_rate_down, best_rate; 125 unsigned long div, div_up; 126 127 /* eq. clk_rate = parent_rate / divider. 128 * 129 * Find best divider to produce closest of target divided rate. 130 */ 131 div = parent_rate / rate; 132 div = clamp_val(div, divider_min, divider_max); 133 div_up = clamp_val(div + 1, divider_min, divider_max); 134 135 divided_rate = parent_rate / div; 136 divided_rate_down = parent_rate / div_up; 137 if (abs(rate - divided_rate_down) < abs(rate - divided_rate)) 138 best_rate = divided_rate_down; 139 else 140 best_rate = divided_rate; 141 142 return best_rate; 143 } 144 145 static inline u32 pbclk_read_pbdiv(struct pic32_periph_clk *pb) 146 { 147 return ((readl(pb->ctrl_reg) >> PB_DIV_SHIFT) & PB_DIV_MASK) + 1; 148 } 149 150 static unsigned long pbclk_recalc_rate(struct clk_hw *hw, 151 unsigned long parent_rate) 152 { 153 struct pic32_periph_clk *pb = clkhw_to_pbclk(hw); 154 155 return parent_rate / pbclk_read_pbdiv(pb); 156 } 157 158 static int pbclk_determine_rate(struct clk_hw *hw, 159 struct clk_rate_request *req) 160 { 161 req->rate = calc_best_divided_rate(req->rate, req->best_parent_rate, 162 PB_DIV_MAX, PB_DIV_MIN); 163 164 return 0; 165 } 166 167 static int pbclk_set_rate(struct clk_hw *hw, unsigned long rate, 168 unsigned long parent_rate) 169 { 170 struct pic32_periph_clk *pb = clkhw_to_pbclk(hw); 171 unsigned long flags; 172 u32 v, div; 173 int err; 174 175 /* check & wait for DIV_READY */ 176 err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY, 177 1, LOCK_TIMEOUT_US); 178 if (err) 179 return err; 180 181 /* calculate clkdiv and best rate */ 182 div = DIV_ROUND_CLOSEST(parent_rate, rate); 183 184 spin_lock_irqsave(&pb->core->reg_lock, flags); 185 186 /* apply new div */ 187 v = readl(pb->ctrl_reg); 188 v &= ~PB_DIV_MASK; 189 v |= (div - 1); 190 191 pic32_syskey_unlock(); 192 193 writel(v, pb->ctrl_reg); 194 195 spin_unlock_irqrestore(&pb->core->reg_lock, flags); 196 197 /* wait again for DIV_READY */ 198 err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY, 199 1, LOCK_TIMEOUT_US); 200 if (err) 201 return err; 202 203 /* confirm that new div is applied correctly */ 204 return (pbclk_read_pbdiv(pb) == div) ? 0 : -EBUSY; 205 } 206 207 const struct clk_ops pic32_pbclk_ops = { 208 .enable = pbclk_enable, 209 .disable = pbclk_disable, 210 .is_enabled = pbclk_is_enabled, 211 .recalc_rate = pbclk_recalc_rate, 212 .determine_rate = pbclk_determine_rate, 213 .set_rate = pbclk_set_rate, 214 }; 215 216 struct clk *pic32_periph_clk_register(const struct pic32_periph_clk_data *desc, 217 struct pic32_clk_common *core) 218 { 219 struct pic32_periph_clk *pbclk; 220 struct clk *clk; 221 222 pbclk = devm_kzalloc(core->dev, sizeof(*pbclk), GFP_KERNEL); 223 if (!pbclk) 224 return ERR_PTR(-ENOMEM); 225 226 pbclk->hw.init = &desc->init_data; 227 pbclk->core = core; 228 pbclk->ctrl_reg = desc->ctrl_reg + core->iobase; 229 230 clk = devm_clk_register(core->dev, &pbclk->hw); 231 if (IS_ERR(clk)) { 232 dev_err(core->dev, "%s: clk_register() failed\n", __func__); 233 devm_kfree(core->dev, pbclk); 234 } 235 236 return clk; 237 } 238 239 /* Reference oscillator operations */ 240 struct pic32_ref_osc { 241 struct clk_hw hw; 242 void __iomem *ctrl_reg; 243 const u32 *parent_map; 244 struct pic32_clk_common *core; 245 }; 246 247 #define clkhw_to_refosc(_hw) container_of(_hw, struct pic32_ref_osc, hw) 248 249 static int roclk_is_enabled(struct clk_hw *hw) 250 { 251 struct pic32_ref_osc *refo = clkhw_to_refosc(hw); 252 253 return readl(refo->ctrl_reg) & REFO_ON; 254 } 255 256 static int roclk_enable(struct clk_hw *hw) 257 { 258 struct pic32_ref_osc *refo = clkhw_to_refosc(hw); 259 260 writel(REFO_ON | REFO_OE, PIC32_SET(refo->ctrl_reg)); 261 return 0; 262 } 263 264 static void roclk_disable(struct clk_hw *hw) 265 { 266 struct pic32_ref_osc *refo = clkhw_to_refosc(hw); 267 268 writel(REFO_ON | REFO_OE, PIC32_CLR(refo->ctrl_reg)); 269 } 270 271 static int roclk_init(struct clk_hw *hw) 272 { 273 /* initialize clock in disabled state */ 274 roclk_disable(hw); 275 276 return 0; 277 } 278 279 static u8 roclk_get_parent(struct clk_hw *hw) 280 { 281 struct pic32_ref_osc *refo = clkhw_to_refosc(hw); 282 u32 v, i; 283 284 v = (readl(refo->ctrl_reg) >> REFO_SEL_SHIFT) & REFO_SEL_MASK; 285 286 if (!refo->parent_map) 287 return v; 288 289 for (i = 0; i < clk_hw_get_num_parents(hw); i++) 290 if (refo->parent_map[i] == v) 291 return i; 292 293 return -EINVAL; 294 } 295 296 static unsigned long roclk_calc_rate(unsigned long parent_rate, 297 u32 rodiv, u32 rotrim) 298 { 299 u64 rate64; 300 301 /* fout = fin / [2 * {div + (trim / 512)}] 302 * = fin * 512 / [1024 * div + 2 * trim] 303 * = fin * 256 / (512 * div + trim) 304 * = (fin << 8) / ((div << 9) + trim) 305 */ 306 if (rotrim) { 307 rodiv = (rodiv << 9) + rotrim; 308 rate64 = parent_rate; 309 rate64 <<= 8; 310 do_div(rate64, rodiv); 311 } else if (rodiv) { 312 rate64 = parent_rate / (rodiv << 1); 313 } else { 314 rate64 = parent_rate; 315 } 316 return rate64; 317 } 318 319 static void roclk_calc_div_trim(unsigned long rate, 320 unsigned long parent_rate, 321 u32 *rodiv_p, u32 *rotrim_p) 322 { 323 u32 div, rotrim, rodiv; 324 u64 frac; 325 326 /* Find integer approximation of floating-point arithmetic. 327 * fout = fin / [2 * {rodiv + (rotrim / 512)}] ... (1) 328 * i.e. fout = fin / 2 * DIV 329 * whereas DIV = rodiv + (rotrim / 512) 330 * 331 * Since kernel does not perform floating-point arithmetic so 332 * (rotrim/512) will be zero. And DIV & rodiv will result same. 333 * 334 * ie. fout = (fin * 256) / [(512 * rodiv) + rotrim] ... from (1) 335 * ie. rotrim = ((fin * 256) / fout) - (512 * DIV) 336 */ 337 if (parent_rate <= rate) { 338 div = 0; 339 frac = 0; 340 rodiv = 0; 341 rotrim = 0; 342 } else { 343 div = parent_rate / (rate << 1); 344 frac = parent_rate; 345 frac <<= 8; 346 do_div(frac, rate); 347 frac -= (u64)(div << 9); 348 349 rodiv = (div > REFO_DIV_MASK) ? REFO_DIV_MASK : div; 350 rotrim = (frac >= REFO_TRIM_MAX) ? REFO_TRIM_MAX : frac; 351 } 352 353 if (rodiv_p) 354 *rodiv_p = rodiv; 355 356 if (rotrim_p) 357 *rotrim_p = rotrim; 358 } 359 360 static unsigned long roclk_recalc_rate(struct clk_hw *hw, 361 unsigned long parent_rate) 362 { 363 struct pic32_ref_osc *refo = clkhw_to_refosc(hw); 364 u32 v, rodiv, rotrim; 365 366 /* get rodiv */ 367 v = readl(refo->ctrl_reg); 368 rodiv = (v >> REFO_DIV_SHIFT) & REFO_DIV_MASK; 369 370 /* get trim */ 371 v = readl(refo->ctrl_reg + REFO_TRIM_REG); 372 rotrim = (v >> REFO_TRIM_SHIFT) & REFO_TRIM_MASK; 373 374 return roclk_calc_rate(parent_rate, rodiv, rotrim); 375 } 376 377 static int roclk_determine_rate(struct clk_hw *hw, 378 struct clk_rate_request *req) 379 { 380 u32 rotrim, rodiv; 381 382 /* calculate dividers for new rate */ 383 roclk_calc_div_trim(req->rate, req->best_parent_rate, &rodiv, &rotrim); 384 385 /* caclulate new rate (rounding) based on new rodiv & rotrim */ 386 req->rate = roclk_calc_rate(req->best_parent_rate, rodiv, rotrim); 387 388 return 0; 389 } 390 391 static int roclk_determine_rate(struct clk_hw *hw, 392 struct clk_rate_request *req) 393 { 394 struct clk_hw *parent_clk, *best_parent_clk = NULL; 395 unsigned int i, delta, best_delta = -1; 396 unsigned long parent_rate, best_parent_rate = 0; 397 unsigned long best = 0, nearest_rate; 398 399 /* find a parent which can generate nearest clkrate >= rate */ 400 for (i = 0; i < clk_hw_get_num_parents(hw); i++) { 401 /* get parent */ 402 parent_clk = clk_hw_get_parent_by_index(hw, i); 403 if (!parent_clk) 404 continue; 405 406 /* skip if parent runs slower than target rate */ 407 parent_rate = clk_hw_get_rate(parent_clk); 408 if (req->rate > parent_rate) 409 continue; 410 411 nearest_rate = roclk_round_rate(hw, req->rate, &parent_rate); 412 delta = abs(nearest_rate - req->rate); 413 if ((nearest_rate >= req->rate) && (delta < best_delta)) { 414 best_parent_clk = parent_clk; 415 best_parent_rate = parent_rate; 416 best = nearest_rate; 417 best_delta = delta; 418 419 if (delta == 0) 420 break; 421 } 422 } 423 424 /* if no match found, retain old rate */ 425 if (!best_parent_clk) { 426 pr_err("%s:%s, no parent found for rate %lu.\n", 427 __func__, clk_hw_get_name(hw), req->rate); 428 return clk_hw_get_rate(hw); 429 } 430 431 pr_debug("%s,rate %lu, best_parent(%s, %lu), best %lu, delta %d\n", 432 clk_hw_get_name(hw), req->rate, 433 clk_hw_get_name(best_parent_clk), best_parent_rate, 434 best, best_delta); 435 436 if (req->best_parent_rate) 437 req->best_parent_rate = best_parent_rate; 438 439 if (req->best_parent_hw) 440 req->best_parent_hw = best_parent_clk; 441 442 return best; 443 } 444 445 static int roclk_set_parent(struct clk_hw *hw, u8 index) 446 { 447 struct pic32_ref_osc *refo = clkhw_to_refosc(hw); 448 unsigned long flags; 449 u32 v; 450 int err; 451 452 if (refo->parent_map) 453 index = refo->parent_map[index]; 454 455 /* wait until ACTIVE bit is zero or timeout */ 456 err = readl_poll_timeout(refo->ctrl_reg, v, !(v & REFO_ACTIVE), 457 1, LOCK_TIMEOUT_US); 458 if (err) { 459 pr_err("%s: poll failed, clk active\n", clk_hw_get_name(hw)); 460 return err; 461 } 462 463 spin_lock_irqsave(&refo->core->reg_lock, flags); 464 465 pic32_syskey_unlock(); 466 467 /* calculate & apply new */ 468 v = readl(refo->ctrl_reg); 469 v &= ~(REFO_SEL_MASK << REFO_SEL_SHIFT); 470 v |= index << REFO_SEL_SHIFT; 471 472 writel(v, refo->ctrl_reg); 473 474 spin_unlock_irqrestore(&refo->core->reg_lock, flags); 475 476 return 0; 477 } 478 479 static int roclk_set_rate_and_parent(struct clk_hw *hw, 480 unsigned long rate, 481 unsigned long parent_rate, 482 u8 index) 483 { 484 struct pic32_ref_osc *refo = clkhw_to_refosc(hw); 485 unsigned long flags; 486 u32 trim, rodiv, v; 487 int err; 488 489 /* calculate new rodiv & rotrim for new rate */ 490 roclk_calc_div_trim(rate, parent_rate, &rodiv, &trim); 491 492 pr_debug("parent_rate = %lu, rate = %lu, div = %d, trim = %d\n", 493 parent_rate, rate, rodiv, trim); 494 495 /* wait till source change is active */ 496 err = readl_poll_timeout(refo->ctrl_reg, v, 497 !(v & (REFO_ACTIVE | REFO_DIVSW_EN)), 498 1, LOCK_TIMEOUT_US); 499 if (err) { 500 pr_err("%s: poll timedout, clock is still active\n", __func__); 501 return err; 502 } 503 504 spin_lock_irqsave(&refo->core->reg_lock, flags); 505 v = readl(refo->ctrl_reg); 506 507 pic32_syskey_unlock(); 508 509 /* apply parent, if required */ 510 if (refo->parent_map) 511 index = refo->parent_map[index]; 512 513 v &= ~(REFO_SEL_MASK << REFO_SEL_SHIFT); 514 v |= index << REFO_SEL_SHIFT; 515 516 /* apply RODIV */ 517 v &= ~(REFO_DIV_MASK << REFO_DIV_SHIFT); 518 v |= rodiv << REFO_DIV_SHIFT; 519 writel(v, refo->ctrl_reg); 520 521 /* apply ROTRIM */ 522 v = readl(refo->ctrl_reg + REFO_TRIM_REG); 523 v &= ~(REFO_TRIM_MASK << REFO_TRIM_SHIFT); 524 v |= trim << REFO_TRIM_SHIFT; 525 writel(v, refo->ctrl_reg + REFO_TRIM_REG); 526 527 /* enable & activate divider switching */ 528 writel(REFO_ON | REFO_DIVSW_EN, PIC32_SET(refo->ctrl_reg)); 529 530 /* wait till divswen is in-progress */ 531 err = readl_poll_timeout_atomic(refo->ctrl_reg, v, !(v & REFO_DIVSW_EN), 532 1, LOCK_TIMEOUT_US); 533 /* leave the clk gated as it was */ 534 writel(REFO_ON, PIC32_CLR(refo->ctrl_reg)); 535 536 spin_unlock_irqrestore(&refo->core->reg_lock, flags); 537 538 return err; 539 } 540 541 static int roclk_set_rate(struct clk_hw *hw, unsigned long rate, 542 unsigned long parent_rate) 543 { 544 u8 index = roclk_get_parent(hw); 545 546 return roclk_set_rate_and_parent(hw, rate, parent_rate, index); 547 } 548 549 const struct clk_ops pic32_roclk_ops = { 550 .enable = roclk_enable, 551 .disable = roclk_disable, 552 .is_enabled = roclk_is_enabled, 553 .get_parent = roclk_get_parent, 554 .set_parent = roclk_set_parent, 555 .determine_rate = roclk_determine_rate, 556 .recalc_rate = roclk_recalc_rate, 557 .set_rate_and_parent = roclk_set_rate_and_parent, 558 .set_rate = roclk_set_rate, 559 .init = roclk_init, 560 }; 561 562 struct clk *pic32_refo_clk_register(const struct pic32_ref_osc_data *data, 563 struct pic32_clk_common *core) 564 { 565 struct pic32_ref_osc *refo; 566 struct clk *clk; 567 568 refo = devm_kzalloc(core->dev, sizeof(*refo), GFP_KERNEL); 569 if (!refo) 570 return ERR_PTR(-ENOMEM); 571 572 refo->core = core; 573 refo->hw.init = &data->init_data; 574 refo->ctrl_reg = data->ctrl_reg + core->iobase; 575 refo->parent_map = data->parent_map; 576 577 clk = devm_clk_register(core->dev, &refo->hw); 578 if (IS_ERR(clk)) 579 dev_err(core->dev, "%s: clk_register() failed\n", __func__); 580 581 return clk; 582 } 583 584 struct pic32_sys_pll { 585 struct clk_hw hw; 586 void __iomem *ctrl_reg; 587 void __iomem *status_reg; 588 u32 lock_mask; 589 u32 idiv; /* PLL iclk divider, treated fixed */ 590 struct pic32_clk_common *core; 591 }; 592 593 #define clkhw_to_spll(_hw) container_of(_hw, struct pic32_sys_pll, hw) 594 595 static inline u32 spll_odiv_to_divider(u32 odiv) 596 { 597 odiv = clamp_val(odiv, PLL_ODIV_MIN, PLL_ODIV_MAX); 598 599 return 1 << odiv; 600 } 601 602 static unsigned long spll_calc_mult_div(struct pic32_sys_pll *pll, 603 unsigned long rate, 604 unsigned long parent_rate, 605 u32 *mult_p, u32 *odiv_p) 606 { 607 u32 mul, div, best_mul = 1, best_div = 1; 608 unsigned long new_rate, best_rate = rate; 609 unsigned int best_delta = -1, delta, match_found = 0; 610 u64 rate64; 611 612 parent_rate /= pll->idiv; 613 614 for (mul = 1; mul <= PLL_MULT_MAX; mul++) { 615 for (div = PLL_ODIV_MIN; div <= PLL_ODIV_MAX; div++) { 616 rate64 = parent_rate; 617 rate64 *= mul; 618 do_div(rate64, 1 << div); 619 new_rate = rate64; 620 delta = abs(rate - new_rate); 621 if ((new_rate >= rate) && (delta < best_delta)) { 622 best_delta = delta; 623 best_rate = new_rate; 624 best_mul = mul; 625 best_div = div; 626 match_found = 1; 627 } 628 } 629 } 630 631 if (!match_found) { 632 pr_warn("spll: no match found\n"); 633 return 0; 634 } 635 636 pr_debug("rate %lu, par_rate %lu/mult %u, div %u, best_rate %lu\n", 637 rate, parent_rate, best_mul, best_div, best_rate); 638 639 if (mult_p) 640 *mult_p = best_mul - 1; 641 642 if (odiv_p) 643 *odiv_p = best_div; 644 645 return best_rate; 646 } 647 648 static unsigned long spll_clk_recalc_rate(struct clk_hw *hw, 649 unsigned long parent_rate) 650 { 651 struct pic32_sys_pll *pll = clkhw_to_spll(hw); 652 unsigned long pll_in_rate; 653 u32 mult, odiv, div, v; 654 u64 rate64; 655 656 v = readl(pll->ctrl_reg); 657 odiv = ((v >> PLL_ODIV_SHIFT) & PLL_ODIV_MASK); 658 mult = ((v >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1; 659 div = spll_odiv_to_divider(odiv); 660 661 /* pll_in_rate = parent_rate / idiv 662 * pll_out_rate = pll_in_rate * mult / div; 663 */ 664 pll_in_rate = parent_rate / pll->idiv; 665 rate64 = pll_in_rate; 666 rate64 *= mult; 667 do_div(rate64, div); 668 669 return rate64; 670 } 671 672 static int spll_clk_determine_rate(struct clk_hw *hw, 673 struct clk_rate_request *req) 674 { 675 struct pic32_sys_pll *pll = clkhw_to_spll(hw); 676 677 req->rate = spll_calc_mult_div(pll, req->rate, req->best_parent_rate, 678 NULL, NULL); 679 680 return 0; 681 } 682 683 static int spll_clk_set_rate(struct clk_hw *hw, unsigned long rate, 684 unsigned long parent_rate) 685 { 686 struct pic32_sys_pll *pll = clkhw_to_spll(hw); 687 unsigned long ret, flags; 688 u32 mult, odiv, v; 689 int err; 690 691 ret = spll_calc_mult_div(pll, rate, parent_rate, &mult, &odiv); 692 if (!ret) 693 return -EINVAL; 694 695 /* 696 * We can't change SPLL counters when it is in-active use 697 * by SYSCLK. So check before applying new counters/rate. 698 */ 699 700 /* Is spll_clk active parent of sys_clk ? */ 701 if (unlikely(clk_hw_get_parent(pic32_sclk_hw) == hw)) { 702 pr_err("%s: failed, clk in-use\n", __func__); 703 return -EBUSY; 704 } 705 706 spin_lock_irqsave(&pll->core->reg_lock, flags); 707 708 /* apply new multiplier & divisor */ 709 v = readl(pll->ctrl_reg); 710 v &= ~(PLL_MULT_MASK << PLL_MULT_SHIFT); 711 v &= ~(PLL_ODIV_MASK << PLL_ODIV_SHIFT); 712 v |= (mult << PLL_MULT_SHIFT) | (odiv << PLL_ODIV_SHIFT); 713 714 /* sys unlock before write */ 715 pic32_syskey_unlock(); 716 717 writel(v, pll->ctrl_reg); 718 cpu_relax(); 719 720 /* insert few nops (5-stage) to ensure CPU does not hang */ 721 cpu_nop5(); 722 cpu_nop5(); 723 724 /* Wait until PLL is locked (maximum 100 usecs). */ 725 err = readl_poll_timeout_atomic(pll->status_reg, v, 726 v & pll->lock_mask, 1, 100); 727 spin_unlock_irqrestore(&pll->core->reg_lock, flags); 728 729 return err; 730 } 731 732 /* SPLL clock operation */ 733 const struct clk_ops pic32_spll_ops = { 734 .recalc_rate = spll_clk_recalc_rate, 735 .determine_rate = spll_clk_determine_rate, 736 .set_rate = spll_clk_set_rate, 737 }; 738 739 struct clk *pic32_spll_clk_register(const struct pic32_sys_pll_data *data, 740 struct pic32_clk_common *core) 741 { 742 struct pic32_sys_pll *spll; 743 struct clk *clk; 744 745 spll = devm_kzalloc(core->dev, sizeof(*spll), GFP_KERNEL); 746 if (!spll) 747 return ERR_PTR(-ENOMEM); 748 749 spll->core = core; 750 spll->hw.init = &data->init_data; 751 spll->ctrl_reg = data->ctrl_reg + core->iobase; 752 spll->status_reg = data->status_reg + core->iobase; 753 spll->lock_mask = data->lock_mask; 754 755 /* cache PLL idiv; PLL driver uses it as constant.*/ 756 spll->idiv = (readl(spll->ctrl_reg) >> PLL_IDIV_SHIFT) & PLL_IDIV_MASK; 757 spll->idiv += 1; 758 759 clk = devm_clk_register(core->dev, &spll->hw); 760 if (IS_ERR(clk)) 761 dev_err(core->dev, "sys_pll: clk_register() failed\n"); 762 763 return clk; 764 } 765 766 /* System mux clock(aka SCLK) */ 767 768 struct pic32_sys_clk { 769 struct clk_hw hw; 770 void __iomem *mux_reg; 771 void __iomem *slew_reg; 772 u32 slew_div; 773 const u32 *parent_map; 774 struct pic32_clk_common *core; 775 }; 776 777 #define clkhw_to_sys_clk(_hw) container_of(_hw, struct pic32_sys_clk, hw) 778 779 static unsigned long sclk_get_rate(struct clk_hw *hw, unsigned long parent_rate) 780 { 781 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); 782 u32 div; 783 784 div = (readl(sclk->slew_reg) >> SLEW_SYSDIV_SHIFT) & SLEW_SYSDIV; 785 div += 1; /* sys-div to divider */ 786 787 return parent_rate / div; 788 } 789 790 static int sclk_determine_rate(struct clk_hw *hw, 791 struct clk_rate_request *req) 792 { 793 req->rate = calc_best_divided_rate(req->rate, req->best_parent_rate, 794 SLEW_SYSDIV, 1); 795 796 return 0; 797 } 798 799 static int sclk_set_rate(struct clk_hw *hw, 800 unsigned long rate, unsigned long parent_rate) 801 { 802 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); 803 unsigned long flags; 804 u32 v, div; 805 int err; 806 807 div = parent_rate / rate; 808 809 spin_lock_irqsave(&sclk->core->reg_lock, flags); 810 811 /* apply new div */ 812 v = readl(sclk->slew_reg); 813 v &= ~(SLEW_SYSDIV << SLEW_SYSDIV_SHIFT); 814 v |= (div - 1) << SLEW_SYSDIV_SHIFT; 815 816 pic32_syskey_unlock(); 817 818 writel(v, sclk->slew_reg); 819 820 /* wait until BUSY is cleared */ 821 err = readl_poll_timeout_atomic(sclk->slew_reg, v, 822 !(v & SLEW_BUSY), 1, LOCK_TIMEOUT_US); 823 824 spin_unlock_irqrestore(&sclk->core->reg_lock, flags); 825 826 return err; 827 } 828 829 static u8 sclk_get_parent(struct clk_hw *hw) 830 { 831 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); 832 u32 i, v; 833 834 v = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK; 835 836 if (!sclk->parent_map) 837 return v; 838 839 for (i = 0; i < clk_hw_get_num_parents(hw); i++) 840 if (sclk->parent_map[i] == v) 841 return i; 842 return -EINVAL; 843 } 844 845 static int sclk_set_parent(struct clk_hw *hw, u8 index) 846 { 847 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); 848 unsigned long flags; 849 u32 nosc, cosc, v; 850 int err; 851 852 spin_lock_irqsave(&sclk->core->reg_lock, flags); 853 854 /* find new_osc */ 855 nosc = sclk->parent_map ? sclk->parent_map[index] : index; 856 857 /* set new parent */ 858 v = readl(sclk->mux_reg); 859 v &= ~(OSC_NEW_MASK << OSC_NEW_SHIFT); 860 v |= nosc << OSC_NEW_SHIFT; 861 862 pic32_syskey_unlock(); 863 864 writel(v, sclk->mux_reg); 865 866 /* initate switch */ 867 writel(OSC_SWEN, PIC32_SET(sclk->mux_reg)); 868 cpu_relax(); 869 870 /* add nop to flush pipeline (as cpu_clk is in-flux) */ 871 cpu_nop5(); 872 873 /* wait for SWEN bit to clear */ 874 err = readl_poll_timeout_atomic(sclk->slew_reg, v, 875 !(v & OSC_SWEN), 1, LOCK_TIMEOUT_US); 876 877 spin_unlock_irqrestore(&sclk->core->reg_lock, flags); 878 879 /* 880 * SCLK clock-switching logic might reject a clock switching request 881 * if pre-requisites (like new clk_src not present or unstable) are 882 * not met. 883 * So confirm before claiming success. 884 */ 885 cosc = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK; 886 if (cosc != nosc) { 887 pr_err("%s: err, failed to set_parent() to %d, current %d\n", 888 clk_hw_get_name(hw), nosc, cosc); 889 err = -EBUSY; 890 } 891 892 return err; 893 } 894 895 static int sclk_init(struct clk_hw *hw) 896 { 897 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); 898 unsigned long flags; 899 u32 v; 900 901 /* Maintain reference to this clk, required in spll_clk_set_rate() */ 902 pic32_sclk_hw = hw; 903 904 /* apply slew divider on both up and down scaling */ 905 if (sclk->slew_div) { 906 spin_lock_irqsave(&sclk->core->reg_lock, flags); 907 v = readl(sclk->slew_reg); 908 v &= ~(SLEW_DIV << SLEW_DIV_SHIFT); 909 v |= sclk->slew_div << SLEW_DIV_SHIFT; 910 v |= SLEW_DOWNEN | SLEW_UPEN; 911 writel(v, sclk->slew_reg); 912 spin_unlock_irqrestore(&sclk->core->reg_lock, flags); 913 } 914 915 return 0; 916 } 917 918 /* sclk with post-divider */ 919 const struct clk_ops pic32_sclk_ops = { 920 .get_parent = sclk_get_parent, 921 .set_parent = sclk_set_parent, 922 .determine_rate = sclk_determine_rate, 923 .set_rate = sclk_set_rate, 924 .recalc_rate = sclk_get_rate, 925 .init = sclk_init, 926 .determine_rate = __clk_mux_determine_rate, 927 }; 928 929 /* sclk with no slew and no post-divider */ 930 const struct clk_ops pic32_sclk_no_div_ops = { 931 .get_parent = sclk_get_parent, 932 .set_parent = sclk_set_parent, 933 .init = sclk_init, 934 .determine_rate = __clk_mux_determine_rate, 935 }; 936 937 struct clk *pic32_sys_clk_register(const struct pic32_sys_clk_data *data, 938 struct pic32_clk_common *core) 939 { 940 struct pic32_sys_clk *sclk; 941 struct clk *clk; 942 943 sclk = devm_kzalloc(core->dev, sizeof(*sclk), GFP_KERNEL); 944 if (!sclk) 945 return ERR_PTR(-ENOMEM); 946 947 sclk->core = core; 948 sclk->hw.init = &data->init_data; 949 sclk->mux_reg = data->mux_reg + core->iobase; 950 sclk->slew_reg = data->slew_reg + core->iobase; 951 sclk->slew_div = data->slew_div; 952 sclk->parent_map = data->parent_map; 953 954 clk = devm_clk_register(core->dev, &sclk->hw); 955 if (IS_ERR(clk)) 956 dev_err(core->dev, "%s: clk register failed\n", __func__); 957 958 return clk; 959 } 960 961 /* secondary oscillator */ 962 struct pic32_sec_osc { 963 struct clk_hw hw; 964 void __iomem *enable_reg; 965 void __iomem *status_reg; 966 u32 enable_mask; 967 u32 status_mask; 968 unsigned long fixed_rate; 969 struct pic32_clk_common *core; 970 }; 971 972 #define clkhw_to_sosc(_hw) container_of(_hw, struct pic32_sec_osc, hw) 973 static int sosc_clk_enable(struct clk_hw *hw) 974 { 975 struct pic32_sec_osc *sosc = clkhw_to_sosc(hw); 976 u32 v; 977 978 /* enable SOSC */ 979 pic32_syskey_unlock(); 980 writel(sosc->enable_mask, PIC32_SET(sosc->enable_reg)); 981 982 /* wait till warm-up period expires or ready-status is updated */ 983 return readl_poll_timeout_atomic(sosc->status_reg, v, 984 v & sosc->status_mask, 1, 100); 985 } 986 987 static void sosc_clk_disable(struct clk_hw *hw) 988 { 989 struct pic32_sec_osc *sosc = clkhw_to_sosc(hw); 990 991 pic32_syskey_unlock(); 992 writel(sosc->enable_mask, PIC32_CLR(sosc->enable_reg)); 993 } 994 995 static int sosc_clk_is_enabled(struct clk_hw *hw) 996 { 997 struct pic32_sec_osc *sosc = clkhw_to_sosc(hw); 998 u32 enabled, ready; 999 1000 /* check enabled and ready status */ 1001 enabled = readl(sosc->enable_reg) & sosc->enable_mask; 1002 ready = readl(sosc->status_reg) & sosc->status_mask; 1003 1004 return enabled && ready; 1005 } 1006 1007 static unsigned long sosc_clk_calc_rate(struct clk_hw *hw, 1008 unsigned long parent_rate) 1009 { 1010 return clkhw_to_sosc(hw)->fixed_rate; 1011 } 1012 1013 const struct clk_ops pic32_sosc_ops = { 1014 .enable = sosc_clk_enable, 1015 .disable = sosc_clk_disable, 1016 .is_enabled = sosc_clk_is_enabled, 1017 .recalc_rate = sosc_clk_calc_rate, 1018 }; 1019 1020 struct clk *pic32_sosc_clk_register(const struct pic32_sec_osc_data *data, 1021 struct pic32_clk_common *core) 1022 { 1023 struct pic32_sec_osc *sosc; 1024 1025 sosc = devm_kzalloc(core->dev, sizeof(*sosc), GFP_KERNEL); 1026 if (!sosc) 1027 return ERR_PTR(-ENOMEM); 1028 1029 sosc->core = core; 1030 sosc->hw.init = &data->init_data; 1031 sosc->fixed_rate = data->fixed_rate; 1032 sosc->enable_mask = data->enable_mask; 1033 sosc->status_mask = data->status_mask; 1034 sosc->enable_reg = data->enable_reg + core->iobase; 1035 sosc->status_reg = data->status_reg + core->iobase; 1036 1037 return devm_clk_register(core->dev, &sosc->hw); 1038 } 1039