1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Purna Chandra Mandal,<purna.mandal@microchip.com> 4 * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. 5 */ 6 #include <linux/clk-provider.h> 7 #include <linux/delay.h> 8 #include <linux/device.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <asm/mach-pic32/pic32.h> 13 #include <asm/traps.h> 14 15 #include "clk-core.h" 16 17 /* OSCCON Reg fields */ 18 #define OSC_CUR_MASK 0x07 19 #define OSC_CUR_SHIFT 12 20 #define OSC_NEW_MASK 0x07 21 #define OSC_NEW_SHIFT 8 22 #define OSC_SWEN BIT(0) 23 24 /* SPLLCON Reg fields */ 25 #define PLL_RANGE_MASK 0x07 26 #define PLL_RANGE_SHIFT 0 27 #define PLL_ICLK_MASK 0x01 28 #define PLL_ICLK_SHIFT 7 29 #define PLL_IDIV_MASK 0x07 30 #define PLL_IDIV_SHIFT 8 31 #define PLL_ODIV_MASK 0x07 32 #define PLL_ODIV_SHIFT 24 33 #define PLL_MULT_MASK 0x7F 34 #define PLL_MULT_SHIFT 16 35 #define PLL_MULT_MAX 128 36 #define PLL_ODIV_MIN 1 37 #define PLL_ODIV_MAX 5 38 39 /* Peripheral Bus Clock Reg Fields */ 40 #define PB_DIV_MASK 0x7f 41 #define PB_DIV_SHIFT 0 42 #define PB_DIV_READY BIT(11) 43 #define PB_DIV_ENABLE BIT(15) 44 #define PB_DIV_MAX 128 45 #define PB_DIV_MIN 0 46 47 /* Reference Oscillator Control Reg fields */ 48 #define REFO_SEL_MASK 0x0f 49 #define REFO_SEL_SHIFT 0 50 #define REFO_ACTIVE BIT(8) 51 #define REFO_DIVSW_EN BIT(9) 52 #define REFO_OE BIT(12) 53 #define REFO_ON BIT(15) 54 #define REFO_DIV_SHIFT 16 55 #define REFO_DIV_MASK 0x7fff 56 57 /* Reference Oscillator Trim Register Fields */ 58 #define REFO_TRIM_REG 0x10 59 #define REFO_TRIM_MASK 0x1ff 60 #define REFO_TRIM_SHIFT 23 61 #define REFO_TRIM_MAX 511 62 63 /* Mux Slew Control Register fields */ 64 #define SLEW_BUSY BIT(0) 65 #define SLEW_DOWNEN BIT(1) 66 #define SLEW_UPEN BIT(2) 67 #define SLEW_DIV 0x07 68 #define SLEW_DIV_SHIFT 8 69 #define SLEW_SYSDIV 0x0f 70 #define SLEW_SYSDIV_SHIFT 20 71 72 /* Clock Poll Timeout */ 73 #define LOCK_TIMEOUT_US USEC_PER_MSEC 74 75 /* SoC specific clock needed during SPLL clock rate switch */ 76 static struct clk_hw *pic32_sclk_hw; 77 78 /* add instruction pipeline delay while CPU clock is in-transition. */ 79 #define cpu_nop5() \ 80 do { \ 81 __asm__ __volatile__("nop"); \ 82 __asm__ __volatile__("nop"); \ 83 __asm__ __volatile__("nop"); \ 84 __asm__ __volatile__("nop"); \ 85 __asm__ __volatile__("nop"); \ 86 } while (0) 87 88 /* Perpheral bus clocks */ 89 struct pic32_periph_clk { 90 struct clk_hw hw; 91 void __iomem *ctrl_reg; 92 struct pic32_clk_common *core; 93 }; 94 95 #define clkhw_to_pbclk(_hw) container_of(_hw, struct pic32_periph_clk, hw) 96 97 static int pbclk_is_enabled(struct clk_hw *hw) 98 { 99 struct pic32_periph_clk *pb = clkhw_to_pbclk(hw); 100 101 return readl(pb->ctrl_reg) & PB_DIV_ENABLE; 102 } 103 104 static int pbclk_enable(struct clk_hw *hw) 105 { 106 struct pic32_periph_clk *pb = clkhw_to_pbclk(hw); 107 108 writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg)); 109 return 0; 110 } 111 112 static void pbclk_disable(struct clk_hw *hw) 113 { 114 struct pic32_periph_clk *pb = clkhw_to_pbclk(hw); 115 116 writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg)); 117 } 118 119 static unsigned long calc_best_divided_rate(unsigned long rate, 120 unsigned long parent_rate, 121 u32 divider_max, 122 u32 divider_min) 123 { 124 unsigned long divided_rate, divided_rate_down, best_rate; 125 unsigned long div, div_up; 126 127 /* eq. clk_rate = parent_rate / divider. 128 * 129 * Find best divider to produce closest of target divided rate. 130 */ 131 div = parent_rate / rate; 132 div = clamp_val(div, divider_min, divider_max); 133 div_up = clamp_val(div + 1, divider_min, divider_max); 134 135 divided_rate = parent_rate / div; 136 divided_rate_down = parent_rate / div_up; 137 if (abs(rate - divided_rate_down) < abs(rate - divided_rate)) 138 best_rate = divided_rate_down; 139 else 140 best_rate = divided_rate; 141 142 return best_rate; 143 } 144 145 static inline u32 pbclk_read_pbdiv(struct pic32_periph_clk *pb) 146 { 147 return ((readl(pb->ctrl_reg) >> PB_DIV_SHIFT) & PB_DIV_MASK) + 1; 148 } 149 150 static unsigned long pbclk_recalc_rate(struct clk_hw *hw, 151 unsigned long parent_rate) 152 { 153 struct pic32_periph_clk *pb = clkhw_to_pbclk(hw); 154 155 return parent_rate / pbclk_read_pbdiv(pb); 156 } 157 158 static int pbclk_determine_rate(struct clk_hw *hw, 159 struct clk_rate_request *req) 160 { 161 req->rate = calc_best_divided_rate(req->rate, req->best_parent_rate, 162 PB_DIV_MAX, PB_DIV_MIN); 163 164 return 0; 165 } 166 167 static int pbclk_set_rate(struct clk_hw *hw, unsigned long rate, 168 unsigned long parent_rate) 169 { 170 struct pic32_periph_clk *pb = clkhw_to_pbclk(hw); 171 unsigned long flags; 172 u32 v, div; 173 int err; 174 175 /* check & wait for DIV_READY */ 176 err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY, 177 1, LOCK_TIMEOUT_US); 178 if (err) 179 return err; 180 181 /* calculate clkdiv and best rate */ 182 div = DIV_ROUND_CLOSEST(parent_rate, rate); 183 184 spin_lock_irqsave(&pb->core->reg_lock, flags); 185 186 /* apply new div */ 187 v = readl(pb->ctrl_reg); 188 v &= ~PB_DIV_MASK; 189 v |= (div - 1); 190 191 pic32_syskey_unlock(); 192 193 writel(v, pb->ctrl_reg); 194 195 spin_unlock_irqrestore(&pb->core->reg_lock, flags); 196 197 /* wait again for DIV_READY */ 198 err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY, 199 1, LOCK_TIMEOUT_US); 200 if (err) 201 return err; 202 203 /* confirm that new div is applied correctly */ 204 return (pbclk_read_pbdiv(pb) == div) ? 0 : -EBUSY; 205 } 206 207 const struct clk_ops pic32_pbclk_ops = { 208 .enable = pbclk_enable, 209 .disable = pbclk_disable, 210 .is_enabled = pbclk_is_enabled, 211 .recalc_rate = pbclk_recalc_rate, 212 .determine_rate = pbclk_determine_rate, 213 .set_rate = pbclk_set_rate, 214 }; 215 216 struct clk *pic32_periph_clk_register(const struct pic32_periph_clk_data *desc, 217 struct pic32_clk_common *core) 218 { 219 struct pic32_periph_clk *pbclk; 220 struct clk *clk; 221 222 pbclk = devm_kzalloc(core->dev, sizeof(*pbclk), GFP_KERNEL); 223 if (!pbclk) 224 return ERR_PTR(-ENOMEM); 225 226 pbclk->hw.init = &desc->init_data; 227 pbclk->core = core; 228 pbclk->ctrl_reg = desc->ctrl_reg + core->iobase; 229 230 clk = devm_clk_register(core->dev, &pbclk->hw); 231 if (IS_ERR(clk)) { 232 dev_err(core->dev, "%s: clk_register() failed\n", __func__); 233 devm_kfree(core->dev, pbclk); 234 } 235 236 return clk; 237 } 238 239 /* Reference oscillator operations */ 240 struct pic32_ref_osc { 241 struct clk_hw hw; 242 void __iomem *ctrl_reg; 243 const u32 *parent_map; 244 struct pic32_clk_common *core; 245 }; 246 247 #define clkhw_to_refosc(_hw) container_of(_hw, struct pic32_ref_osc, hw) 248 249 static int roclk_is_enabled(struct clk_hw *hw) 250 { 251 struct pic32_ref_osc *refo = clkhw_to_refosc(hw); 252 253 return readl(refo->ctrl_reg) & REFO_ON; 254 } 255 256 static int roclk_enable(struct clk_hw *hw) 257 { 258 struct pic32_ref_osc *refo = clkhw_to_refosc(hw); 259 260 writel(REFO_ON | REFO_OE, PIC32_SET(refo->ctrl_reg)); 261 return 0; 262 } 263 264 static void roclk_disable(struct clk_hw *hw) 265 { 266 struct pic32_ref_osc *refo = clkhw_to_refosc(hw); 267 268 writel(REFO_ON | REFO_OE, PIC32_CLR(refo->ctrl_reg)); 269 } 270 271 static int roclk_init(struct clk_hw *hw) 272 { 273 /* initialize clock in disabled state */ 274 roclk_disable(hw); 275 276 return 0; 277 } 278 279 static u8 roclk_get_parent(struct clk_hw *hw) 280 { 281 struct pic32_ref_osc *refo = clkhw_to_refosc(hw); 282 u32 v, i; 283 284 v = (readl(refo->ctrl_reg) >> REFO_SEL_SHIFT) & REFO_SEL_MASK; 285 286 if (!refo->parent_map) 287 return v; 288 289 for (i = 0; i < clk_hw_get_num_parents(hw); i++) 290 if (refo->parent_map[i] == v) 291 return i; 292 293 return -EINVAL; 294 } 295 296 static unsigned long roclk_calc_rate(unsigned long parent_rate, 297 u32 rodiv, u32 rotrim) 298 { 299 u64 rate64; 300 301 /* fout = fin / [2 * {div + (trim / 512)}] 302 * = fin * 512 / [1024 * div + 2 * trim] 303 * = fin * 256 / (512 * div + trim) 304 * = (fin << 8) / ((div << 9) + trim) 305 */ 306 if (rotrim) { 307 rodiv = (rodiv << 9) + rotrim; 308 rate64 = parent_rate; 309 rate64 <<= 8; 310 do_div(rate64, rodiv); 311 } else if (rodiv) { 312 rate64 = parent_rate / (rodiv << 1); 313 } else { 314 rate64 = parent_rate; 315 } 316 return rate64; 317 } 318 319 static void roclk_calc_div_trim(unsigned long rate, 320 unsigned long parent_rate, 321 u32 *rodiv_p, u32 *rotrim_p) 322 { 323 u32 div, rotrim, rodiv; 324 u64 frac; 325 326 /* Find integer approximation of floating-point arithmetic. 327 * fout = fin / [2 * {rodiv + (rotrim / 512)}] ... (1) 328 * i.e. fout = fin / 2 * DIV 329 * whereas DIV = rodiv + (rotrim / 512) 330 * 331 * Since kernel does not perform floating-point arithmetic so 332 * (rotrim/512) will be zero. And DIV & rodiv will result same. 333 * 334 * ie. fout = (fin * 256) / [(512 * rodiv) + rotrim] ... from (1) 335 * ie. rotrim = ((fin * 256) / fout) - (512 * DIV) 336 */ 337 if (parent_rate <= rate) { 338 div = 0; 339 frac = 0; 340 rodiv = 0; 341 rotrim = 0; 342 } else { 343 div = parent_rate / (rate << 1); 344 frac = parent_rate; 345 frac <<= 8; 346 do_div(frac, rate); 347 frac -= (u64)(div << 9); 348 349 rodiv = (div > REFO_DIV_MASK) ? REFO_DIV_MASK : div; 350 rotrim = (frac >= REFO_TRIM_MAX) ? REFO_TRIM_MAX : frac; 351 } 352 353 if (rodiv_p) 354 *rodiv_p = rodiv; 355 356 if (rotrim_p) 357 *rotrim_p = rotrim; 358 } 359 360 static unsigned long roclk_recalc_rate(struct clk_hw *hw, 361 unsigned long parent_rate) 362 { 363 struct pic32_ref_osc *refo = clkhw_to_refosc(hw); 364 u32 v, rodiv, rotrim; 365 366 /* get rodiv */ 367 v = readl(refo->ctrl_reg); 368 rodiv = (v >> REFO_DIV_SHIFT) & REFO_DIV_MASK; 369 370 /* get trim */ 371 v = readl(refo->ctrl_reg + REFO_TRIM_REG); 372 rotrim = (v >> REFO_TRIM_SHIFT) & REFO_TRIM_MASK; 373 374 return roclk_calc_rate(parent_rate, rodiv, rotrim); 375 } 376 377 static int roclk_determine_rate(struct clk_hw *hw, 378 struct clk_rate_request *req) 379 { 380 struct clk_hw *parent_clk, *best_parent_clk = NULL; 381 unsigned int i, delta, best_delta = -1; 382 unsigned long parent_rate, best_parent_rate = 0; 383 unsigned long best = 0, nearest_rate; 384 385 /* find a parent which can generate nearest clkrate >= rate */ 386 for (i = 0; i < clk_hw_get_num_parents(hw); i++) { 387 u32 rotrim, rodiv; 388 389 /* get parent */ 390 parent_clk = clk_hw_get_parent_by_index(hw, i); 391 if (!parent_clk) 392 continue; 393 394 /* skip if parent runs slower than target rate */ 395 parent_rate = clk_hw_get_rate(parent_clk); 396 if (req->rate > parent_rate) 397 continue; 398 399 /* calculate dividers for new rate */ 400 roclk_calc_div_trim(req->rate, req->best_parent_rate, &rodiv, &rotrim); 401 402 /* caclulate new rate (rounding) based on new rodiv & rotrim */ 403 nearest_rate = roclk_calc_rate(req->best_parent_rate, rodiv, rotrim); 404 405 delta = abs(nearest_rate - req->rate); 406 if ((nearest_rate >= req->rate) && (delta < best_delta)) { 407 best_parent_clk = parent_clk; 408 best_parent_rate = parent_rate; 409 best = nearest_rate; 410 best_delta = delta; 411 412 if (delta == 0) 413 break; 414 } 415 } 416 417 /* if no match found, retain old rate */ 418 if (!best_parent_clk) { 419 pr_err("%s:%s, no parent found for rate %lu.\n", 420 __func__, clk_hw_get_name(hw), req->rate); 421 return clk_hw_get_rate(hw); 422 } 423 424 pr_debug("%s,rate %lu, best_parent(%s, %lu), best %lu, delta %d\n", 425 clk_hw_get_name(hw), req->rate, 426 clk_hw_get_name(best_parent_clk), best_parent_rate, 427 best, best_delta); 428 429 if (req->best_parent_rate) 430 req->best_parent_rate = best_parent_rate; 431 432 if (req->best_parent_hw) 433 req->best_parent_hw = best_parent_clk; 434 435 return best; 436 } 437 438 static int roclk_set_parent(struct clk_hw *hw, u8 index) 439 { 440 struct pic32_ref_osc *refo = clkhw_to_refosc(hw); 441 unsigned long flags; 442 u32 v; 443 int err; 444 445 if (refo->parent_map) 446 index = refo->parent_map[index]; 447 448 /* wait until ACTIVE bit is zero or timeout */ 449 err = readl_poll_timeout(refo->ctrl_reg, v, !(v & REFO_ACTIVE), 450 1, LOCK_TIMEOUT_US); 451 if (err) { 452 pr_err("%s: poll failed, clk active\n", clk_hw_get_name(hw)); 453 return err; 454 } 455 456 spin_lock_irqsave(&refo->core->reg_lock, flags); 457 458 pic32_syskey_unlock(); 459 460 /* calculate & apply new */ 461 v = readl(refo->ctrl_reg); 462 v &= ~(REFO_SEL_MASK << REFO_SEL_SHIFT); 463 v |= index << REFO_SEL_SHIFT; 464 465 writel(v, refo->ctrl_reg); 466 467 spin_unlock_irqrestore(&refo->core->reg_lock, flags); 468 469 return 0; 470 } 471 472 static int roclk_set_rate_and_parent(struct clk_hw *hw, 473 unsigned long rate, 474 unsigned long parent_rate, 475 u8 index) 476 { 477 struct pic32_ref_osc *refo = clkhw_to_refosc(hw); 478 unsigned long flags; 479 u32 trim, rodiv, v; 480 int err; 481 482 /* calculate new rodiv & rotrim for new rate */ 483 roclk_calc_div_trim(rate, parent_rate, &rodiv, &trim); 484 485 pr_debug("parent_rate = %lu, rate = %lu, div = %d, trim = %d\n", 486 parent_rate, rate, rodiv, trim); 487 488 /* wait till source change is active */ 489 err = readl_poll_timeout(refo->ctrl_reg, v, 490 !(v & (REFO_ACTIVE | REFO_DIVSW_EN)), 491 1, LOCK_TIMEOUT_US); 492 if (err) { 493 pr_err("%s: poll timedout, clock is still active\n", __func__); 494 return err; 495 } 496 497 spin_lock_irqsave(&refo->core->reg_lock, flags); 498 v = readl(refo->ctrl_reg); 499 500 pic32_syskey_unlock(); 501 502 /* apply parent, if required */ 503 if (refo->parent_map) 504 index = refo->parent_map[index]; 505 506 v &= ~(REFO_SEL_MASK << REFO_SEL_SHIFT); 507 v |= index << REFO_SEL_SHIFT; 508 509 /* apply RODIV */ 510 v &= ~(REFO_DIV_MASK << REFO_DIV_SHIFT); 511 v |= rodiv << REFO_DIV_SHIFT; 512 writel(v, refo->ctrl_reg); 513 514 /* apply ROTRIM */ 515 v = readl(refo->ctrl_reg + REFO_TRIM_REG); 516 v &= ~(REFO_TRIM_MASK << REFO_TRIM_SHIFT); 517 v |= trim << REFO_TRIM_SHIFT; 518 writel(v, refo->ctrl_reg + REFO_TRIM_REG); 519 520 /* enable & activate divider switching */ 521 writel(REFO_ON | REFO_DIVSW_EN, PIC32_SET(refo->ctrl_reg)); 522 523 /* wait till divswen is in-progress */ 524 err = readl_poll_timeout_atomic(refo->ctrl_reg, v, !(v & REFO_DIVSW_EN), 525 1, LOCK_TIMEOUT_US); 526 /* leave the clk gated as it was */ 527 writel(REFO_ON, PIC32_CLR(refo->ctrl_reg)); 528 529 spin_unlock_irqrestore(&refo->core->reg_lock, flags); 530 531 return err; 532 } 533 534 static int roclk_set_rate(struct clk_hw *hw, unsigned long rate, 535 unsigned long parent_rate) 536 { 537 u8 index = roclk_get_parent(hw); 538 539 return roclk_set_rate_and_parent(hw, rate, parent_rate, index); 540 } 541 542 const struct clk_ops pic32_roclk_ops = { 543 .enable = roclk_enable, 544 .disable = roclk_disable, 545 .is_enabled = roclk_is_enabled, 546 .get_parent = roclk_get_parent, 547 .set_parent = roclk_set_parent, 548 .determine_rate = roclk_determine_rate, 549 .recalc_rate = roclk_recalc_rate, 550 .set_rate_and_parent = roclk_set_rate_and_parent, 551 .set_rate = roclk_set_rate, 552 .init = roclk_init, 553 }; 554 555 struct clk *pic32_refo_clk_register(const struct pic32_ref_osc_data *data, 556 struct pic32_clk_common *core) 557 { 558 struct pic32_ref_osc *refo; 559 struct clk *clk; 560 561 refo = devm_kzalloc(core->dev, sizeof(*refo), GFP_KERNEL); 562 if (!refo) 563 return ERR_PTR(-ENOMEM); 564 565 refo->core = core; 566 refo->hw.init = &data->init_data; 567 refo->ctrl_reg = data->ctrl_reg + core->iobase; 568 refo->parent_map = data->parent_map; 569 570 clk = devm_clk_register(core->dev, &refo->hw); 571 if (IS_ERR(clk)) 572 dev_err(core->dev, "%s: clk_register() failed\n", __func__); 573 574 return clk; 575 } 576 577 struct pic32_sys_pll { 578 struct clk_hw hw; 579 void __iomem *ctrl_reg; 580 void __iomem *status_reg; 581 u32 lock_mask; 582 u32 idiv; /* PLL iclk divider, treated fixed */ 583 struct pic32_clk_common *core; 584 }; 585 586 #define clkhw_to_spll(_hw) container_of(_hw, struct pic32_sys_pll, hw) 587 588 static inline u32 spll_odiv_to_divider(u32 odiv) 589 { 590 odiv = clamp_val(odiv, PLL_ODIV_MIN, PLL_ODIV_MAX); 591 592 return 1 << odiv; 593 } 594 595 static unsigned long spll_calc_mult_div(struct pic32_sys_pll *pll, 596 unsigned long rate, 597 unsigned long parent_rate, 598 u32 *mult_p, u32 *odiv_p) 599 { 600 u32 mul, div, best_mul = 1, best_div = 1; 601 unsigned long new_rate, best_rate = rate; 602 unsigned int best_delta = -1, delta, match_found = 0; 603 u64 rate64; 604 605 parent_rate /= pll->idiv; 606 607 for (mul = 1; mul <= PLL_MULT_MAX; mul++) { 608 for (div = PLL_ODIV_MIN; div <= PLL_ODIV_MAX; div++) { 609 rate64 = parent_rate; 610 rate64 *= mul; 611 do_div(rate64, 1 << div); 612 new_rate = rate64; 613 delta = abs(rate - new_rate); 614 if ((new_rate >= rate) && (delta < best_delta)) { 615 best_delta = delta; 616 best_rate = new_rate; 617 best_mul = mul; 618 best_div = div; 619 match_found = 1; 620 } 621 } 622 } 623 624 if (!match_found) { 625 pr_warn("spll: no match found\n"); 626 return 0; 627 } 628 629 pr_debug("rate %lu, par_rate %lu/mult %u, div %u, best_rate %lu\n", 630 rate, parent_rate, best_mul, best_div, best_rate); 631 632 if (mult_p) 633 *mult_p = best_mul - 1; 634 635 if (odiv_p) 636 *odiv_p = best_div; 637 638 return best_rate; 639 } 640 641 static unsigned long spll_clk_recalc_rate(struct clk_hw *hw, 642 unsigned long parent_rate) 643 { 644 struct pic32_sys_pll *pll = clkhw_to_spll(hw); 645 unsigned long pll_in_rate; 646 u32 mult, odiv, div, v; 647 u64 rate64; 648 649 v = readl(pll->ctrl_reg); 650 odiv = ((v >> PLL_ODIV_SHIFT) & PLL_ODIV_MASK); 651 mult = ((v >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1; 652 div = spll_odiv_to_divider(odiv); 653 654 /* pll_in_rate = parent_rate / idiv 655 * pll_out_rate = pll_in_rate * mult / div; 656 */ 657 pll_in_rate = parent_rate / pll->idiv; 658 rate64 = pll_in_rate; 659 rate64 *= mult; 660 do_div(rate64, div); 661 662 return rate64; 663 } 664 665 static int spll_clk_determine_rate(struct clk_hw *hw, 666 struct clk_rate_request *req) 667 { 668 struct pic32_sys_pll *pll = clkhw_to_spll(hw); 669 670 req->rate = spll_calc_mult_div(pll, req->rate, req->best_parent_rate, 671 NULL, NULL); 672 673 return 0; 674 } 675 676 static int spll_clk_set_rate(struct clk_hw *hw, unsigned long rate, 677 unsigned long parent_rate) 678 { 679 struct pic32_sys_pll *pll = clkhw_to_spll(hw); 680 unsigned long ret, flags; 681 u32 mult, odiv, v; 682 int err; 683 684 ret = spll_calc_mult_div(pll, rate, parent_rate, &mult, &odiv); 685 if (!ret) 686 return -EINVAL; 687 688 /* 689 * We can't change SPLL counters when it is in-active use 690 * by SYSCLK. So check before applying new counters/rate. 691 */ 692 693 /* Is spll_clk active parent of sys_clk ? */ 694 if (unlikely(clk_hw_get_parent(pic32_sclk_hw) == hw)) { 695 pr_err("%s: failed, clk in-use\n", __func__); 696 return -EBUSY; 697 } 698 699 spin_lock_irqsave(&pll->core->reg_lock, flags); 700 701 /* apply new multiplier & divisor */ 702 v = readl(pll->ctrl_reg); 703 v &= ~(PLL_MULT_MASK << PLL_MULT_SHIFT); 704 v &= ~(PLL_ODIV_MASK << PLL_ODIV_SHIFT); 705 v |= (mult << PLL_MULT_SHIFT) | (odiv << PLL_ODIV_SHIFT); 706 707 /* sys unlock before write */ 708 pic32_syskey_unlock(); 709 710 writel(v, pll->ctrl_reg); 711 cpu_relax(); 712 713 /* insert few nops (5-stage) to ensure CPU does not hang */ 714 cpu_nop5(); 715 cpu_nop5(); 716 717 /* Wait until PLL is locked (maximum 100 usecs). */ 718 err = readl_poll_timeout_atomic(pll->status_reg, v, 719 v & pll->lock_mask, 1, 100); 720 spin_unlock_irqrestore(&pll->core->reg_lock, flags); 721 722 return err; 723 } 724 725 /* SPLL clock operation */ 726 const struct clk_ops pic32_spll_ops = { 727 .recalc_rate = spll_clk_recalc_rate, 728 .determine_rate = spll_clk_determine_rate, 729 .set_rate = spll_clk_set_rate, 730 }; 731 732 struct clk *pic32_spll_clk_register(const struct pic32_sys_pll_data *data, 733 struct pic32_clk_common *core) 734 { 735 struct pic32_sys_pll *spll; 736 struct clk *clk; 737 738 spll = devm_kzalloc(core->dev, sizeof(*spll), GFP_KERNEL); 739 if (!spll) 740 return ERR_PTR(-ENOMEM); 741 742 spll->core = core; 743 spll->hw.init = &data->init_data; 744 spll->ctrl_reg = data->ctrl_reg + core->iobase; 745 spll->status_reg = data->status_reg + core->iobase; 746 spll->lock_mask = data->lock_mask; 747 748 /* cache PLL idiv; PLL driver uses it as constant.*/ 749 spll->idiv = (readl(spll->ctrl_reg) >> PLL_IDIV_SHIFT) & PLL_IDIV_MASK; 750 spll->idiv += 1; 751 752 clk = devm_clk_register(core->dev, &spll->hw); 753 if (IS_ERR(clk)) 754 dev_err(core->dev, "sys_pll: clk_register() failed\n"); 755 756 return clk; 757 } 758 759 /* System mux clock(aka SCLK) */ 760 761 struct pic32_sys_clk { 762 struct clk_hw hw; 763 void __iomem *mux_reg; 764 void __iomem *slew_reg; 765 u32 slew_div; 766 const u32 *parent_map; 767 struct pic32_clk_common *core; 768 }; 769 770 #define clkhw_to_sys_clk(_hw) container_of(_hw, struct pic32_sys_clk, hw) 771 772 static unsigned long sclk_get_rate(struct clk_hw *hw, unsigned long parent_rate) 773 { 774 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); 775 u32 div; 776 777 div = (readl(sclk->slew_reg) >> SLEW_SYSDIV_SHIFT) & SLEW_SYSDIV; 778 div += 1; /* sys-div to divider */ 779 780 return parent_rate / div; 781 } 782 783 static int sclk_determine_rate(struct clk_hw *hw, 784 struct clk_rate_request *req) 785 { 786 req->rate = calc_best_divided_rate(req->rate, req->best_parent_rate, 787 SLEW_SYSDIV, 1); 788 789 return 0; 790 } 791 792 static int sclk_set_rate(struct clk_hw *hw, 793 unsigned long rate, unsigned long parent_rate) 794 { 795 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); 796 unsigned long flags; 797 u32 v, div; 798 int err; 799 800 div = parent_rate / rate; 801 802 spin_lock_irqsave(&sclk->core->reg_lock, flags); 803 804 /* apply new div */ 805 v = readl(sclk->slew_reg); 806 v &= ~(SLEW_SYSDIV << SLEW_SYSDIV_SHIFT); 807 v |= (div - 1) << SLEW_SYSDIV_SHIFT; 808 809 pic32_syskey_unlock(); 810 811 writel(v, sclk->slew_reg); 812 813 /* wait until BUSY is cleared */ 814 err = readl_poll_timeout_atomic(sclk->slew_reg, v, 815 !(v & SLEW_BUSY), 1, LOCK_TIMEOUT_US); 816 817 spin_unlock_irqrestore(&sclk->core->reg_lock, flags); 818 819 return err; 820 } 821 822 static u8 sclk_get_parent(struct clk_hw *hw) 823 { 824 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); 825 u32 i, v; 826 827 v = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK; 828 829 if (!sclk->parent_map) 830 return v; 831 832 for (i = 0; i < clk_hw_get_num_parents(hw); i++) 833 if (sclk->parent_map[i] == v) 834 return i; 835 return -EINVAL; 836 } 837 838 static int sclk_set_parent(struct clk_hw *hw, u8 index) 839 { 840 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); 841 unsigned long flags; 842 u32 nosc, cosc, v; 843 int err; 844 845 spin_lock_irqsave(&sclk->core->reg_lock, flags); 846 847 /* find new_osc */ 848 nosc = sclk->parent_map ? sclk->parent_map[index] : index; 849 850 /* set new parent */ 851 v = readl(sclk->mux_reg); 852 v &= ~(OSC_NEW_MASK << OSC_NEW_SHIFT); 853 v |= nosc << OSC_NEW_SHIFT; 854 855 pic32_syskey_unlock(); 856 857 writel(v, sclk->mux_reg); 858 859 /* initate switch */ 860 writel(OSC_SWEN, PIC32_SET(sclk->mux_reg)); 861 cpu_relax(); 862 863 /* add nop to flush pipeline (as cpu_clk is in-flux) */ 864 cpu_nop5(); 865 866 /* wait for SWEN bit to clear */ 867 err = readl_poll_timeout_atomic(sclk->slew_reg, v, 868 !(v & OSC_SWEN), 1, LOCK_TIMEOUT_US); 869 870 spin_unlock_irqrestore(&sclk->core->reg_lock, flags); 871 872 /* 873 * SCLK clock-switching logic might reject a clock switching request 874 * if pre-requisites (like new clk_src not present or unstable) are 875 * not met. 876 * So confirm before claiming success. 877 */ 878 cosc = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK; 879 if (cosc != nosc) { 880 pr_err("%s: err, failed to set_parent() to %d, current %d\n", 881 clk_hw_get_name(hw), nosc, cosc); 882 err = -EBUSY; 883 } 884 885 return err; 886 } 887 888 static int sclk_init(struct clk_hw *hw) 889 { 890 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); 891 unsigned long flags; 892 u32 v; 893 894 /* Maintain reference to this clk, required in spll_clk_set_rate() */ 895 pic32_sclk_hw = hw; 896 897 /* apply slew divider on both up and down scaling */ 898 if (sclk->slew_div) { 899 spin_lock_irqsave(&sclk->core->reg_lock, flags); 900 v = readl(sclk->slew_reg); 901 v &= ~(SLEW_DIV << SLEW_DIV_SHIFT); 902 v |= sclk->slew_div << SLEW_DIV_SHIFT; 903 v |= SLEW_DOWNEN | SLEW_UPEN; 904 writel(v, sclk->slew_reg); 905 spin_unlock_irqrestore(&sclk->core->reg_lock, flags); 906 } 907 908 return 0; 909 } 910 911 /* sclk with post-divider */ 912 const struct clk_ops pic32_sclk_ops = { 913 .get_parent = sclk_get_parent, 914 .set_parent = sclk_set_parent, 915 .determine_rate = sclk_determine_rate, 916 .set_rate = sclk_set_rate, 917 .recalc_rate = sclk_get_rate, 918 .init = sclk_init, 919 .determine_rate = __clk_mux_determine_rate, 920 }; 921 922 /* sclk with no slew and no post-divider */ 923 const struct clk_ops pic32_sclk_no_div_ops = { 924 .get_parent = sclk_get_parent, 925 .set_parent = sclk_set_parent, 926 .init = sclk_init, 927 .determine_rate = __clk_mux_determine_rate, 928 }; 929 930 struct clk *pic32_sys_clk_register(const struct pic32_sys_clk_data *data, 931 struct pic32_clk_common *core) 932 { 933 struct pic32_sys_clk *sclk; 934 struct clk *clk; 935 936 sclk = devm_kzalloc(core->dev, sizeof(*sclk), GFP_KERNEL); 937 if (!sclk) 938 return ERR_PTR(-ENOMEM); 939 940 sclk->core = core; 941 sclk->hw.init = &data->init_data; 942 sclk->mux_reg = data->mux_reg + core->iobase; 943 sclk->slew_reg = data->slew_reg + core->iobase; 944 sclk->slew_div = data->slew_div; 945 sclk->parent_map = data->parent_map; 946 947 clk = devm_clk_register(core->dev, &sclk->hw); 948 if (IS_ERR(clk)) 949 dev_err(core->dev, "%s: clk register failed\n", __func__); 950 951 return clk; 952 } 953 954 /* secondary oscillator */ 955 struct pic32_sec_osc { 956 struct clk_hw hw; 957 void __iomem *enable_reg; 958 void __iomem *status_reg; 959 u32 enable_mask; 960 u32 status_mask; 961 unsigned long fixed_rate; 962 struct pic32_clk_common *core; 963 }; 964 965 #define clkhw_to_sosc(_hw) container_of(_hw, struct pic32_sec_osc, hw) 966 static int sosc_clk_enable(struct clk_hw *hw) 967 { 968 struct pic32_sec_osc *sosc = clkhw_to_sosc(hw); 969 u32 v; 970 971 /* enable SOSC */ 972 pic32_syskey_unlock(); 973 writel(sosc->enable_mask, PIC32_SET(sosc->enable_reg)); 974 975 /* wait till warm-up period expires or ready-status is updated */ 976 return readl_poll_timeout_atomic(sosc->status_reg, v, 977 v & sosc->status_mask, 1, 100); 978 } 979 980 static void sosc_clk_disable(struct clk_hw *hw) 981 { 982 struct pic32_sec_osc *sosc = clkhw_to_sosc(hw); 983 984 pic32_syskey_unlock(); 985 writel(sosc->enable_mask, PIC32_CLR(sosc->enable_reg)); 986 } 987 988 static int sosc_clk_is_enabled(struct clk_hw *hw) 989 { 990 struct pic32_sec_osc *sosc = clkhw_to_sosc(hw); 991 u32 enabled, ready; 992 993 /* check enabled and ready status */ 994 enabled = readl(sosc->enable_reg) & sosc->enable_mask; 995 ready = readl(sosc->status_reg) & sosc->status_mask; 996 997 return enabled && ready; 998 } 999 1000 static unsigned long sosc_clk_calc_rate(struct clk_hw *hw, 1001 unsigned long parent_rate) 1002 { 1003 return clkhw_to_sosc(hw)->fixed_rate; 1004 } 1005 1006 const struct clk_ops pic32_sosc_ops = { 1007 .enable = sosc_clk_enable, 1008 .disable = sosc_clk_disable, 1009 .is_enabled = sosc_clk_is_enabled, 1010 .recalc_rate = sosc_clk_calc_rate, 1011 }; 1012 1013 struct clk *pic32_sosc_clk_register(const struct pic32_sec_osc_data *data, 1014 struct pic32_clk_common *core) 1015 { 1016 struct pic32_sec_osc *sosc; 1017 1018 sosc = devm_kzalloc(core->dev, sizeof(*sosc), GFP_KERNEL); 1019 if (!sosc) 1020 return ERR_PTR(-ENOMEM); 1021 1022 sosc->core = core; 1023 sosc->hw.init = &data->init_data; 1024 sosc->fixed_rate = data->fixed_rate; 1025 sosc->enable_mask = data->enable_mask; 1026 sosc->status_mask = data->status_mask; 1027 sosc->enable_reg = data->enable_reg + core->iobase; 1028 sosc->status_reg = data->status_reg + core->iobase; 1029 1030 return devm_clk_register(core->dev, &sosc->hw); 1031 } 1032