1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2015 Endless Mobile, Inc. 4 * Author: Carlo Caione <carlo@endlessm.com> 5 * 6 * Copyright (c) 2016 BayLibre, Inc. 7 * Michael Turquette <mturquette@baylibre.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/init.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/of_address.h> 15 #include <linux/reset-controller.h> 16 #include <linux/slab.h> 17 #include <linux/regmap.h> 18 19 #include "clk-regmap.h" 20 #include "meson-clkc-utils.h" 21 #include "clk-pll.h" 22 #include "clk-mpll.h" 23 24 #include <dt-bindings/clock/meson8b-clkc.h> 25 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> 26 27 /* 28 * Clock controller register offsets 29 * 30 * Register offsets from the HardKernel[0] data sheet must be multiplied 31 * by 4 before adding them to the base address to get the right value 32 * 33 * [0] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf 34 */ 35 #define HHI_GP_PLL_CNTL 0x40 36 #define HHI_GP_PLL_CNTL2 0x44 37 #define HHI_GP_PLL_CNTL3 0x48 38 #define HHI_GP_PLL_CNTL4 0x4C 39 #define HHI_GP_PLL_CNTL5 0x50 40 #define HHI_VIID_CLK_DIV 0x128 41 #define HHI_VIID_CLK_CNTL 0x12c 42 #define HHI_GCLK_MPEG0 0x140 43 #define HHI_GCLK_MPEG1 0x144 44 #define HHI_GCLK_MPEG2 0x148 45 #define HHI_GCLK_OTHER 0x150 46 #define HHI_GCLK_AO 0x154 47 #define HHI_SYS_CPU_CLK_CNTL1 0x15c 48 #define HHI_VID_CLK_DIV 0x164 49 #define HHI_MPEG_CLK_CNTL 0x174 50 #define HHI_AUD_CLK_CNTL 0x178 51 #define HHI_VID_CLK_CNTL 0x17c 52 #define HHI_AUD_CLK_CNTL2 0x190 53 #define HHI_VID_CLK_CNTL2 0x194 54 #define HHI_VID_DIVIDER_CNTL 0x198 55 #define HHI_SYS_CPU_CLK_CNTL0 0x19c 56 #define HHI_MALI_CLK_CNTL 0x1b0 57 #define HHI_VPU_CLK_CNTL 0x1bc 58 #define HHI_HDMI_CLK_CNTL 0x1cc 59 #define HHI_VDEC_CLK_CNTL 0x1e0 60 #define HHI_VDEC2_CLK_CNTL 0x1e4 61 #define HHI_VDEC3_CLK_CNTL 0x1e8 62 #define HHI_NAND_CLK_CNTL 0x25c 63 #define HHI_MPLL_CNTL 0x280 64 #define HHI_SYS_PLL_CNTL 0x300 65 #define HHI_VID_PLL_CNTL 0x320 66 #define HHI_VID_PLL_CNTL2 0x324 67 #define HHI_VID_PLL_CNTL3 0x328 68 #define HHI_VID_PLL_CNTL4 0x32c 69 #define HHI_VID_PLL_CNTL5 0x330 70 #define HHI_VID_PLL_CNTL6 0x334 71 #define HHI_VID2_PLL_CNTL 0x380 72 #define HHI_VID2_PLL_CNTL2 0x384 73 #define HHI_VID2_PLL_CNTL3 0x388 74 #define HHI_VID2_PLL_CNTL4 0x38c 75 #define HHI_VID2_PLL_CNTL5 0x390 76 #define HHI_VID2_PLL_CNTL6 0x394 77 78 /* 79 * MPLL register offeset taken from the S905 datasheet. Vendor kernel source 80 * confirm these are the same for the S805. 81 */ 82 #define HHI_MPLL_CNTL 0x280 83 #define HHI_MPLL_CNTL2 0x284 84 #define HHI_MPLL_CNTL3 0x288 85 #define HHI_MPLL_CNTL4 0x28c 86 #define HHI_MPLL_CNTL5 0x290 87 #define HHI_MPLL_CNTL6 0x294 88 #define HHI_MPLL_CNTL7 0x298 89 #define HHI_MPLL_CNTL8 0x29c 90 #define HHI_MPLL_CNTL9 0x2a0 91 #define HHI_MPLL_CNTL10 0x2a4 92 93 struct meson8b_clk_reset { 94 struct reset_controller_dev reset; 95 struct regmap *regmap; 96 }; 97 98 static const struct pll_params_table sys_pll_params_table[] = { 99 PLL_PARAMS(50, 1), 100 PLL_PARAMS(51, 1), 101 PLL_PARAMS(52, 1), 102 PLL_PARAMS(53, 1), 103 PLL_PARAMS(54, 1), 104 PLL_PARAMS(55, 1), 105 PLL_PARAMS(56, 1), 106 PLL_PARAMS(57, 1), 107 PLL_PARAMS(58, 1), 108 PLL_PARAMS(59, 1), 109 PLL_PARAMS(60, 1), 110 PLL_PARAMS(61, 1), 111 PLL_PARAMS(62, 1), 112 PLL_PARAMS(63, 1), 113 PLL_PARAMS(64, 1), 114 PLL_PARAMS(65, 1), 115 PLL_PARAMS(66, 1), 116 PLL_PARAMS(67, 1), 117 PLL_PARAMS(68, 1), 118 PLL_PARAMS(84, 1), 119 { /* sentinel */ }, 120 }; 121 122 static struct clk_regmap meson8b_fixed_pll_dco = { 123 .data = &(struct meson_clk_pll_data){ 124 .en = { 125 .reg_off = HHI_MPLL_CNTL, 126 .shift = 30, 127 .width = 1, 128 }, 129 .m = { 130 .reg_off = HHI_MPLL_CNTL, 131 .shift = 0, 132 .width = 9, 133 }, 134 .n = { 135 .reg_off = HHI_MPLL_CNTL, 136 .shift = 9, 137 .width = 5, 138 }, 139 .frac = { 140 .reg_off = HHI_MPLL_CNTL2, 141 .shift = 0, 142 .width = 12, 143 }, 144 .l = { 145 .reg_off = HHI_MPLL_CNTL, 146 .shift = 31, 147 .width = 1, 148 }, 149 .rst = { 150 .reg_off = HHI_MPLL_CNTL, 151 .shift = 29, 152 .width = 1, 153 }, 154 }, 155 .hw.init = &(struct clk_init_data){ 156 .name = "fixed_pll_dco", 157 .ops = &meson_clk_pll_ro_ops, 158 .parent_data = &(const struct clk_parent_data) { 159 .fw_name = "xtal", 160 .name = "xtal", 161 .index = -1, 162 }, 163 .num_parents = 1, 164 }, 165 }; 166 167 static struct clk_regmap meson8b_fixed_pll = { 168 .data = &(struct clk_regmap_div_data){ 169 .offset = HHI_MPLL_CNTL, 170 .shift = 16, 171 .width = 2, 172 .flags = CLK_DIVIDER_POWER_OF_TWO, 173 }, 174 .hw.init = &(struct clk_init_data){ 175 .name = "fixed_pll", 176 .ops = &clk_regmap_divider_ro_ops, 177 .parent_hws = (const struct clk_hw *[]) { 178 &meson8b_fixed_pll_dco.hw 179 }, 180 .num_parents = 1, 181 /* 182 * This clock won't ever change at runtime so 183 * CLK_SET_RATE_PARENT is not required 184 */ 185 }, 186 }; 187 188 static struct clk_fixed_factor hdmi_pll_dco_in = { 189 .mult = 2, 190 .div = 1, 191 .hw.init = &(struct clk_init_data){ 192 .name = "hdmi_pll_dco_in", 193 .ops = &clk_fixed_factor_ops, 194 .parent_data = &(const struct clk_parent_data) { 195 .fw_name = "xtal", 196 .index = -1, 197 }, 198 .num_parents = 1, 199 }, 200 }; 201 202 /* 203 * Taken from the vendor driver for the 2970/2975MHz (both only differ in the 204 * FRAC part in HHI_VID_PLL_CNTL2) where these values are identical for Meson8, 205 * Meson8b and Meson8m2. This doubles the input (or output - it's not clear 206 * which one but the result is the same) clock. The vendor driver additionally 207 * has the following comment about: "optimise HPLL VCO 2.97GHz performance". 208 */ 209 static const struct reg_sequence meson8b_hdmi_pll_init_regs[] = { 210 { .reg = HHI_VID_PLL_CNTL2, .def = 0x69c84000 }, 211 { .reg = HHI_VID_PLL_CNTL3, .def = 0x8a46c023 }, 212 { .reg = HHI_VID_PLL_CNTL4, .def = 0x4123b100 }, 213 { .reg = HHI_VID_PLL_CNTL5, .def = 0x00012385 }, 214 { .reg = HHI_VID2_PLL_CNTL2, .def = 0x0430a800 }, 215 }; 216 217 static const struct pll_params_table meson8b_hdmi_pll_params_table[] = { 218 PLL_PARAMS(40, 1), 219 PLL_PARAMS(42, 1), 220 PLL_PARAMS(44, 1), 221 PLL_PARAMS(45, 1), 222 PLL_PARAMS(49, 1), 223 PLL_PARAMS(52, 1), 224 PLL_PARAMS(54, 1), 225 PLL_PARAMS(56, 1), 226 PLL_PARAMS(59, 1), 227 PLL_PARAMS(60, 1), 228 PLL_PARAMS(61, 1), 229 PLL_PARAMS(62, 1), 230 PLL_PARAMS(64, 1), 231 PLL_PARAMS(66, 1), 232 PLL_PARAMS(68, 1), 233 PLL_PARAMS(71, 1), 234 PLL_PARAMS(82, 1), 235 { /* sentinel */ } 236 }; 237 238 static struct clk_regmap meson8b_hdmi_pll_dco = { 239 .data = &(struct meson_clk_pll_data){ 240 .en = { 241 .reg_off = HHI_VID_PLL_CNTL, 242 .shift = 30, 243 .width = 1, 244 }, 245 .m = { 246 .reg_off = HHI_VID_PLL_CNTL, 247 .shift = 0, 248 .width = 9, 249 }, 250 .n = { 251 .reg_off = HHI_VID_PLL_CNTL, 252 .shift = 10, 253 .width = 5, 254 }, 255 .frac = { 256 .reg_off = HHI_VID_PLL_CNTL2, 257 .shift = 0, 258 .width = 12, 259 }, 260 .l = { 261 .reg_off = HHI_VID_PLL_CNTL, 262 .shift = 31, 263 .width = 1, 264 }, 265 .rst = { 266 .reg_off = HHI_VID_PLL_CNTL, 267 .shift = 29, 268 .width = 1, 269 }, 270 .table = meson8b_hdmi_pll_params_table, 271 .init_regs = meson8b_hdmi_pll_init_regs, 272 .init_count = ARRAY_SIZE(meson8b_hdmi_pll_init_regs), 273 }, 274 .hw.init = &(struct clk_init_data){ 275 /* sometimes also called "HPLL" or "HPLL PLL" */ 276 .name = "hdmi_pll_dco", 277 .ops = &meson_clk_pll_ops, 278 .parent_hws = (const struct clk_hw *[]) { 279 &hdmi_pll_dco_in.hw 280 }, 281 .num_parents = 1, 282 }, 283 }; 284 285 static struct clk_regmap meson8b_hdmi_pll_lvds_out = { 286 .data = &(struct clk_regmap_div_data){ 287 .offset = HHI_VID_PLL_CNTL, 288 .shift = 16, 289 .width = 2, 290 .flags = CLK_DIVIDER_POWER_OF_TWO, 291 }, 292 .hw.init = &(struct clk_init_data){ 293 .name = "hdmi_pll_lvds_out", 294 .ops = &clk_regmap_divider_ops, 295 .parent_hws = (const struct clk_hw *[]) { 296 &meson8b_hdmi_pll_dco.hw 297 }, 298 .num_parents = 1, 299 .flags = CLK_SET_RATE_PARENT, 300 }, 301 }; 302 303 static struct clk_regmap meson8b_hdmi_pll_hdmi_out = { 304 .data = &(struct clk_regmap_div_data){ 305 .offset = HHI_VID_PLL_CNTL, 306 .shift = 18, 307 .width = 2, 308 .flags = CLK_DIVIDER_POWER_OF_TWO, 309 }, 310 .hw.init = &(struct clk_init_data){ 311 .name = "hdmi_pll_hdmi_out", 312 .ops = &clk_regmap_divider_ops, 313 .parent_hws = (const struct clk_hw *[]) { 314 &meson8b_hdmi_pll_dco.hw 315 }, 316 .num_parents = 1, 317 .flags = CLK_SET_RATE_PARENT, 318 }, 319 }; 320 321 static struct clk_regmap meson8b_sys_pll_dco = { 322 .data = &(struct meson_clk_pll_data){ 323 .en = { 324 .reg_off = HHI_SYS_PLL_CNTL, 325 .shift = 30, 326 .width = 1, 327 }, 328 .m = { 329 .reg_off = HHI_SYS_PLL_CNTL, 330 .shift = 0, 331 .width = 9, 332 }, 333 .n = { 334 .reg_off = HHI_SYS_PLL_CNTL, 335 .shift = 9, 336 .width = 5, 337 }, 338 .l = { 339 .reg_off = HHI_SYS_PLL_CNTL, 340 .shift = 31, 341 .width = 1, 342 }, 343 .rst = { 344 .reg_off = HHI_SYS_PLL_CNTL, 345 .shift = 29, 346 .width = 1, 347 }, 348 .table = sys_pll_params_table, 349 }, 350 .hw.init = &(struct clk_init_data){ 351 .name = "sys_pll_dco", 352 .ops = &meson_clk_pll_ops, 353 .parent_data = &(const struct clk_parent_data) { 354 .fw_name = "xtal", 355 .name = "xtal", 356 .index = -1, 357 }, 358 .num_parents = 1, 359 }, 360 }; 361 362 static struct clk_regmap meson8b_sys_pll = { 363 .data = &(struct clk_regmap_div_data){ 364 .offset = HHI_SYS_PLL_CNTL, 365 .shift = 16, 366 .width = 2, 367 .flags = CLK_DIVIDER_POWER_OF_TWO, 368 }, 369 .hw.init = &(struct clk_init_data){ 370 .name = "sys_pll", 371 .ops = &clk_regmap_divider_ops, 372 .parent_hws = (const struct clk_hw *[]) { 373 &meson8b_sys_pll_dco.hw 374 }, 375 .num_parents = 1, 376 .flags = CLK_SET_RATE_PARENT, 377 }, 378 }; 379 380 static struct clk_fixed_factor meson8b_fclk_div2_div = { 381 .mult = 1, 382 .div = 2, 383 .hw.init = &(struct clk_init_data){ 384 .name = "fclk_div2_div", 385 .ops = &clk_fixed_factor_ops, 386 .parent_hws = (const struct clk_hw *[]) { 387 &meson8b_fixed_pll.hw 388 }, 389 .num_parents = 1, 390 }, 391 }; 392 393 static struct clk_regmap meson8b_fclk_div2 = { 394 .data = &(struct clk_regmap_gate_data){ 395 .offset = HHI_MPLL_CNTL6, 396 .bit_idx = 27, 397 }, 398 .hw.init = &(struct clk_init_data){ 399 .name = "fclk_div2", 400 .ops = &clk_regmap_gate_ops, 401 .parent_hws = (const struct clk_hw *[]) { 402 &meson8b_fclk_div2_div.hw 403 }, 404 .num_parents = 1, 405 }, 406 }; 407 408 static struct clk_fixed_factor meson8b_fclk_div3_div = { 409 .mult = 1, 410 .div = 3, 411 .hw.init = &(struct clk_init_data){ 412 .name = "fclk_div3_div", 413 .ops = &clk_fixed_factor_ops, 414 .parent_hws = (const struct clk_hw *[]) { 415 &meson8b_fixed_pll.hw 416 }, 417 .num_parents = 1, 418 }, 419 }; 420 421 static struct clk_regmap meson8b_fclk_div3 = { 422 .data = &(struct clk_regmap_gate_data){ 423 .offset = HHI_MPLL_CNTL6, 424 .bit_idx = 28, 425 }, 426 .hw.init = &(struct clk_init_data){ 427 .name = "fclk_div3", 428 .ops = &clk_regmap_gate_ops, 429 .parent_hws = (const struct clk_hw *[]) { 430 &meson8b_fclk_div3_div.hw 431 }, 432 .num_parents = 1, 433 }, 434 }; 435 436 static struct clk_fixed_factor meson8b_fclk_div4_div = { 437 .mult = 1, 438 .div = 4, 439 .hw.init = &(struct clk_init_data){ 440 .name = "fclk_div4_div", 441 .ops = &clk_fixed_factor_ops, 442 .parent_hws = (const struct clk_hw *[]) { 443 &meson8b_fixed_pll.hw 444 }, 445 .num_parents = 1, 446 }, 447 }; 448 449 static struct clk_regmap meson8b_fclk_div4 = { 450 .data = &(struct clk_regmap_gate_data){ 451 .offset = HHI_MPLL_CNTL6, 452 .bit_idx = 29, 453 }, 454 .hw.init = &(struct clk_init_data){ 455 .name = "fclk_div4", 456 .ops = &clk_regmap_gate_ops, 457 .parent_hws = (const struct clk_hw *[]) { 458 &meson8b_fclk_div4_div.hw 459 }, 460 .num_parents = 1, 461 }, 462 }; 463 464 static struct clk_fixed_factor meson8b_fclk_div5_div = { 465 .mult = 1, 466 .div = 5, 467 .hw.init = &(struct clk_init_data){ 468 .name = "fclk_div5_div", 469 .ops = &clk_fixed_factor_ops, 470 .parent_hws = (const struct clk_hw *[]) { 471 &meson8b_fixed_pll.hw 472 }, 473 .num_parents = 1, 474 }, 475 }; 476 477 static struct clk_regmap meson8b_fclk_div5 = { 478 .data = &(struct clk_regmap_gate_data){ 479 .offset = HHI_MPLL_CNTL6, 480 .bit_idx = 30, 481 }, 482 .hw.init = &(struct clk_init_data){ 483 .name = "fclk_div5", 484 .ops = &clk_regmap_gate_ops, 485 .parent_hws = (const struct clk_hw *[]) { 486 &meson8b_fclk_div5_div.hw 487 }, 488 .num_parents = 1, 489 }, 490 }; 491 492 static struct clk_fixed_factor meson8b_fclk_div7_div = { 493 .mult = 1, 494 .div = 7, 495 .hw.init = &(struct clk_init_data){ 496 .name = "fclk_div7_div", 497 .ops = &clk_fixed_factor_ops, 498 .parent_hws = (const struct clk_hw *[]) { 499 &meson8b_fixed_pll.hw 500 }, 501 .num_parents = 1, 502 }, 503 }; 504 505 static struct clk_regmap meson8b_fclk_div7 = { 506 .data = &(struct clk_regmap_gate_data){ 507 .offset = HHI_MPLL_CNTL6, 508 .bit_idx = 31, 509 }, 510 .hw.init = &(struct clk_init_data){ 511 .name = "fclk_div7", 512 .ops = &clk_regmap_gate_ops, 513 .parent_hws = (const struct clk_hw *[]) { 514 &meson8b_fclk_div7_div.hw 515 }, 516 .num_parents = 1, 517 }, 518 }; 519 520 static struct clk_regmap meson8b_mpll_prediv = { 521 .data = &(struct clk_regmap_div_data){ 522 .offset = HHI_MPLL_CNTL5, 523 .shift = 12, 524 .width = 1, 525 }, 526 .hw.init = &(struct clk_init_data){ 527 .name = "mpll_prediv", 528 .ops = &clk_regmap_divider_ro_ops, 529 .parent_hws = (const struct clk_hw *[]) { 530 &meson8b_fixed_pll.hw 531 }, 532 .num_parents = 1, 533 }, 534 }; 535 536 static struct clk_regmap meson8b_mpll0_div = { 537 .data = &(struct meson_clk_mpll_data){ 538 .sdm = { 539 .reg_off = HHI_MPLL_CNTL7, 540 .shift = 0, 541 .width = 14, 542 }, 543 .sdm_en = { 544 .reg_off = HHI_MPLL_CNTL7, 545 .shift = 15, 546 .width = 1, 547 }, 548 .n2 = { 549 .reg_off = HHI_MPLL_CNTL7, 550 .shift = 16, 551 .width = 9, 552 }, 553 .ssen = { 554 .reg_off = HHI_MPLL_CNTL, 555 .shift = 25, 556 .width = 1, 557 }, 558 }, 559 .hw.init = &(struct clk_init_data){ 560 .name = "mpll0_div", 561 .ops = &meson_clk_mpll_ops, 562 .parent_hws = (const struct clk_hw *[]) { 563 &meson8b_mpll_prediv.hw 564 }, 565 .num_parents = 1, 566 }, 567 }; 568 569 static struct clk_regmap meson8b_mpll0 = { 570 .data = &(struct clk_regmap_gate_data){ 571 .offset = HHI_MPLL_CNTL7, 572 .bit_idx = 14, 573 }, 574 .hw.init = &(struct clk_init_data){ 575 .name = "mpll0", 576 .ops = &clk_regmap_gate_ops, 577 .parent_hws = (const struct clk_hw *[]) { 578 &meson8b_mpll0_div.hw 579 }, 580 .num_parents = 1, 581 .flags = CLK_SET_RATE_PARENT, 582 }, 583 }; 584 585 static struct clk_regmap meson8b_mpll1_div = { 586 .data = &(struct meson_clk_mpll_data){ 587 .sdm = { 588 .reg_off = HHI_MPLL_CNTL8, 589 .shift = 0, 590 .width = 14, 591 }, 592 .sdm_en = { 593 .reg_off = HHI_MPLL_CNTL8, 594 .shift = 15, 595 .width = 1, 596 }, 597 .n2 = { 598 .reg_off = HHI_MPLL_CNTL8, 599 .shift = 16, 600 .width = 9, 601 }, 602 }, 603 .hw.init = &(struct clk_init_data){ 604 .name = "mpll1_div", 605 .ops = &meson_clk_mpll_ops, 606 .parent_hws = (const struct clk_hw *[]) { 607 &meson8b_mpll_prediv.hw 608 }, 609 .num_parents = 1, 610 }, 611 }; 612 613 static struct clk_regmap meson8b_mpll1 = { 614 .data = &(struct clk_regmap_gate_data){ 615 .offset = HHI_MPLL_CNTL8, 616 .bit_idx = 14, 617 }, 618 .hw.init = &(struct clk_init_data){ 619 .name = "mpll1", 620 .ops = &clk_regmap_gate_ops, 621 .parent_hws = (const struct clk_hw *[]) { 622 &meson8b_mpll1_div.hw 623 }, 624 .num_parents = 1, 625 .flags = CLK_SET_RATE_PARENT, 626 }, 627 }; 628 629 static struct clk_regmap meson8b_mpll2_div = { 630 .data = &(struct meson_clk_mpll_data){ 631 .sdm = { 632 .reg_off = HHI_MPLL_CNTL9, 633 .shift = 0, 634 .width = 14, 635 }, 636 .sdm_en = { 637 .reg_off = HHI_MPLL_CNTL9, 638 .shift = 15, 639 .width = 1, 640 }, 641 .n2 = { 642 .reg_off = HHI_MPLL_CNTL9, 643 .shift = 16, 644 .width = 9, 645 }, 646 }, 647 .hw.init = &(struct clk_init_data){ 648 .name = "mpll2_div", 649 .ops = &meson_clk_mpll_ops, 650 .parent_hws = (const struct clk_hw *[]) { 651 &meson8b_mpll_prediv.hw 652 }, 653 .num_parents = 1, 654 }, 655 }; 656 657 static struct clk_regmap meson8b_mpll2 = { 658 .data = &(struct clk_regmap_gate_data){ 659 .offset = HHI_MPLL_CNTL9, 660 .bit_idx = 14, 661 }, 662 .hw.init = &(struct clk_init_data){ 663 .name = "mpll2", 664 .ops = &clk_regmap_gate_ops, 665 .parent_hws = (const struct clk_hw *[]) { 666 &meson8b_mpll2_div.hw 667 }, 668 .num_parents = 1, 669 .flags = CLK_SET_RATE_PARENT, 670 }, 671 }; 672 673 /* clk81 is often referred as "mpeg_clk" */ 674 static u32 meson8b_clk81_parents_val_table[] = { 6, 5, 7 }; 675 static struct clk_regmap meson8b_clk81_sel = { 676 .data = &(struct clk_regmap_mux_data){ 677 .offset = HHI_MPEG_CLK_CNTL, 678 .mask = 0x7, 679 .shift = 12, 680 .table = meson8b_clk81_parents_val_table, 681 }, 682 .hw.init = &(struct clk_init_data){ 683 .name = "clk81_sel", 684 .ops = &clk_regmap_mux_ro_ops, 685 /* 686 * FIXME bits 14:12 selects from 8 possible parents: 687 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, 688 * fclk_div4, fclk_div3, fclk_div5 689 */ 690 .parent_hws = (const struct clk_hw *[]) { 691 &meson8b_fclk_div3.hw, 692 &meson8b_fclk_div4.hw, 693 &meson8b_fclk_div5.hw, 694 }, 695 .num_parents = 3, 696 }, 697 }; 698 699 static struct clk_regmap meson8b_clk81_div = { 700 .data = &(struct clk_regmap_div_data){ 701 .offset = HHI_MPEG_CLK_CNTL, 702 .shift = 0, 703 .width = 7, 704 }, 705 .hw.init = &(struct clk_init_data){ 706 .name = "clk81_div", 707 .ops = &clk_regmap_divider_ro_ops, 708 .parent_hws = (const struct clk_hw *[]) { 709 &meson8b_clk81_sel.hw 710 }, 711 .num_parents = 1, 712 }, 713 }; 714 715 static struct clk_regmap meson8b_clk81 = { 716 .data = &(struct clk_regmap_gate_data){ 717 .offset = HHI_MPEG_CLK_CNTL, 718 .bit_idx = 7, 719 }, 720 .hw.init = &(struct clk_init_data){ 721 .name = "clk81", 722 .ops = &clk_regmap_gate_ops, 723 .parent_hws = (const struct clk_hw *[]) { 724 &meson8b_clk81_div.hw 725 }, 726 .num_parents = 1, 727 .flags = CLK_IS_CRITICAL, 728 }, 729 }; 730 731 static struct clk_regmap meson8b_cpu_in_sel = { 732 .data = &(struct clk_regmap_mux_data){ 733 .offset = HHI_SYS_CPU_CLK_CNTL0, 734 .mask = 0x1, 735 .shift = 0, 736 }, 737 .hw.init = &(struct clk_init_data){ 738 .name = "cpu_in_sel", 739 .ops = &clk_regmap_mux_ops, 740 .parent_data = (const struct clk_parent_data[]) { 741 { .fw_name = "xtal", .name = "xtal", .index = -1, }, 742 { .hw = &meson8b_sys_pll.hw, }, 743 }, 744 .num_parents = 2, 745 .flags = (CLK_SET_RATE_PARENT | 746 CLK_SET_RATE_NO_REPARENT), 747 }, 748 }; 749 750 static struct clk_fixed_factor meson8b_cpu_in_div2 = { 751 .mult = 1, 752 .div = 2, 753 .hw.init = &(struct clk_init_data){ 754 .name = "cpu_in_div2", 755 .ops = &clk_fixed_factor_ops, 756 .parent_hws = (const struct clk_hw *[]) { 757 &meson8b_cpu_in_sel.hw 758 }, 759 .num_parents = 1, 760 .flags = CLK_SET_RATE_PARENT, 761 }, 762 }; 763 764 static struct clk_fixed_factor meson8b_cpu_in_div3 = { 765 .mult = 1, 766 .div = 3, 767 .hw.init = &(struct clk_init_data){ 768 .name = "cpu_in_div3", 769 .ops = &clk_fixed_factor_ops, 770 .parent_hws = (const struct clk_hw *[]) { 771 &meson8b_cpu_in_sel.hw 772 }, 773 .num_parents = 1, 774 .flags = CLK_SET_RATE_PARENT, 775 }, 776 }; 777 778 static const struct clk_div_table meson8b_cpu_scale_div_table[] = { 779 { .val = 1, .div = 4 }, 780 { .val = 2, .div = 6 }, 781 { .val = 3, .div = 8 }, 782 { .val = 4, .div = 10 }, 783 { .val = 5, .div = 12 }, 784 { .val = 6, .div = 14 }, 785 { .val = 7, .div = 16 }, 786 { .val = 8, .div = 18 }, 787 { /* sentinel */ }, 788 }; 789 790 static struct clk_regmap meson8b_cpu_scale_div = { 791 .data = &(struct clk_regmap_div_data){ 792 .offset = HHI_SYS_CPU_CLK_CNTL1, 793 .shift = 20, 794 .width = 10, 795 .table = meson8b_cpu_scale_div_table, 796 .flags = CLK_DIVIDER_ALLOW_ZERO, 797 }, 798 .hw.init = &(struct clk_init_data){ 799 .name = "cpu_scale_div", 800 .ops = &clk_regmap_divider_ops, 801 .parent_hws = (const struct clk_hw *[]) { 802 &meson8b_cpu_in_sel.hw 803 }, 804 .num_parents = 1, 805 .flags = CLK_SET_RATE_PARENT, 806 }, 807 }; 808 809 static u32 meson8b_cpu_scale_out_parents_val_table[] = { 0, 1, 3 }; 810 static struct clk_regmap meson8b_cpu_scale_out_sel = { 811 .data = &(struct clk_regmap_mux_data){ 812 .offset = HHI_SYS_CPU_CLK_CNTL0, 813 .mask = 0x3, 814 .shift = 2, 815 .table = meson8b_cpu_scale_out_parents_val_table, 816 }, 817 .hw.init = &(struct clk_init_data){ 818 .name = "cpu_scale_out_sel", 819 .ops = &clk_regmap_mux_ops, 820 /* 821 * NOTE: We are skipping the parent with value 0x2 (which is 822 * meson8b_cpu_in_div3) because it results in a duty cycle of 823 * 33% which makes the system unstable and can result in a 824 * lockup of the whole system. 825 */ 826 .parent_hws = (const struct clk_hw *[]) { 827 &meson8b_cpu_in_sel.hw, 828 &meson8b_cpu_in_div2.hw, 829 &meson8b_cpu_scale_div.hw, 830 }, 831 .num_parents = 3, 832 .flags = CLK_SET_RATE_PARENT, 833 }, 834 }; 835 836 static struct clk_regmap meson8b_cpu_clk = { 837 .data = &(struct clk_regmap_mux_data){ 838 .offset = HHI_SYS_CPU_CLK_CNTL0, 839 .mask = 0x1, 840 .shift = 7, 841 }, 842 .hw.init = &(struct clk_init_data){ 843 .name = "cpu_clk", 844 .ops = &clk_regmap_mux_ops, 845 .parent_data = (const struct clk_parent_data[]) { 846 { .fw_name = "xtal", .name = "xtal", .index = -1, }, 847 { .hw = &meson8b_cpu_scale_out_sel.hw, }, 848 }, 849 .num_parents = 2, 850 .flags = (CLK_SET_RATE_PARENT | 851 CLK_SET_RATE_NO_REPARENT | 852 CLK_IS_CRITICAL), 853 }, 854 }; 855 856 static struct clk_regmap meson8b_nand_clk_sel = { 857 .data = &(struct clk_regmap_mux_data){ 858 .offset = HHI_NAND_CLK_CNTL, 859 .mask = 0x7, 860 .shift = 9, 861 .flags = CLK_MUX_ROUND_CLOSEST, 862 }, 863 .hw.init = &(struct clk_init_data){ 864 .name = "nand_clk_sel", 865 .ops = &clk_regmap_mux_ops, 866 /* FIXME all other parents are unknown: */ 867 .parent_data = (const struct clk_parent_data[]) { 868 { .hw = &meson8b_fclk_div4.hw, }, 869 { .hw = &meson8b_fclk_div3.hw, }, 870 { .hw = &meson8b_fclk_div5.hw, }, 871 { .hw = &meson8b_fclk_div7.hw, }, 872 { .fw_name = "xtal", .name = "xtal", .index = -1, }, 873 }, 874 .num_parents = 5, 875 .flags = CLK_SET_RATE_PARENT, 876 }, 877 }; 878 879 static struct clk_regmap meson8b_nand_clk_div = { 880 .data = &(struct clk_regmap_div_data){ 881 .offset = HHI_NAND_CLK_CNTL, 882 .shift = 0, 883 .width = 7, 884 .flags = CLK_DIVIDER_ROUND_CLOSEST, 885 }, 886 .hw.init = &(struct clk_init_data){ 887 .name = "nand_clk_div", 888 .ops = &clk_regmap_divider_ops, 889 .parent_hws = (const struct clk_hw *[]) { 890 &meson8b_nand_clk_sel.hw 891 }, 892 .num_parents = 1, 893 .flags = CLK_SET_RATE_PARENT, 894 }, 895 }; 896 897 static struct clk_regmap meson8b_nand_clk = { 898 .data = &(struct clk_regmap_gate_data){ 899 .offset = HHI_NAND_CLK_CNTL, 900 .bit_idx = 8, 901 }, 902 .hw.init = &(struct clk_init_data){ 903 .name = "nand_clk", 904 .ops = &clk_regmap_gate_ops, 905 .parent_hws = (const struct clk_hw *[]) { 906 &meson8b_nand_clk_div.hw 907 }, 908 .num_parents = 1, 909 .flags = CLK_SET_RATE_PARENT, 910 }, 911 }; 912 913 static struct clk_fixed_factor meson8b_cpu_clk_div2 = { 914 .mult = 1, 915 .div = 2, 916 .hw.init = &(struct clk_init_data){ 917 .name = "cpu_clk_div2", 918 .ops = &clk_fixed_factor_ops, 919 .parent_hws = (const struct clk_hw *[]) { 920 &meson8b_cpu_clk.hw 921 }, 922 .num_parents = 1, 923 }, 924 }; 925 926 static struct clk_fixed_factor meson8b_cpu_clk_div3 = { 927 .mult = 1, 928 .div = 3, 929 .hw.init = &(struct clk_init_data){ 930 .name = "cpu_clk_div3", 931 .ops = &clk_fixed_factor_ops, 932 .parent_hws = (const struct clk_hw *[]) { 933 &meson8b_cpu_clk.hw 934 }, 935 .num_parents = 1, 936 }, 937 }; 938 939 static struct clk_fixed_factor meson8b_cpu_clk_div4 = { 940 .mult = 1, 941 .div = 4, 942 .hw.init = &(struct clk_init_data){ 943 .name = "cpu_clk_div4", 944 .ops = &clk_fixed_factor_ops, 945 .parent_hws = (const struct clk_hw *[]) { 946 &meson8b_cpu_clk.hw 947 }, 948 .num_parents = 1, 949 }, 950 }; 951 952 static struct clk_fixed_factor meson8b_cpu_clk_div5 = { 953 .mult = 1, 954 .div = 5, 955 .hw.init = &(struct clk_init_data){ 956 .name = "cpu_clk_div5", 957 .ops = &clk_fixed_factor_ops, 958 .parent_hws = (const struct clk_hw *[]) { 959 &meson8b_cpu_clk.hw 960 }, 961 .num_parents = 1, 962 }, 963 }; 964 965 static struct clk_fixed_factor meson8b_cpu_clk_div6 = { 966 .mult = 1, 967 .div = 6, 968 .hw.init = &(struct clk_init_data){ 969 .name = "cpu_clk_div6", 970 .ops = &clk_fixed_factor_ops, 971 .parent_hws = (const struct clk_hw *[]) { 972 &meson8b_cpu_clk.hw 973 }, 974 .num_parents = 1, 975 }, 976 }; 977 978 static struct clk_fixed_factor meson8b_cpu_clk_div7 = { 979 .mult = 1, 980 .div = 7, 981 .hw.init = &(struct clk_init_data){ 982 .name = "cpu_clk_div7", 983 .ops = &clk_fixed_factor_ops, 984 .parent_hws = (const struct clk_hw *[]) { 985 &meson8b_cpu_clk.hw 986 }, 987 .num_parents = 1, 988 }, 989 }; 990 991 static struct clk_fixed_factor meson8b_cpu_clk_div8 = { 992 .mult = 1, 993 .div = 8, 994 .hw.init = &(struct clk_init_data){ 995 .name = "cpu_clk_div8", 996 .ops = &clk_fixed_factor_ops, 997 .parent_hws = (const struct clk_hw *[]) { 998 &meson8b_cpu_clk.hw 999 }, 1000 .num_parents = 1, 1001 }, 1002 }; 1003 1004 static u32 meson8b_cpu_if_parents_val_table[] = { 1, 2, 3, 4, 5, 6, 7 }; 1005 static const struct clk_hw *meson8b_cpu_if_parents[] = { 1006 &meson8b_cpu_clk_div2.hw, 1007 &meson8b_cpu_clk_div3.hw, 1008 &meson8b_cpu_clk_div4.hw, 1009 &meson8b_cpu_clk_div5.hw, 1010 &meson8b_cpu_clk_div6.hw, 1011 &meson8b_cpu_clk_div7.hw, 1012 &meson8b_cpu_clk_div8.hw, 1013 }; 1014 1015 static struct clk_regmap meson8b_apb_sel = { 1016 .data = &(struct clk_regmap_mux_data){ 1017 .offset = HHI_SYS_CPU_CLK_CNTL1, 1018 .mask = 0x7, 1019 .shift = 3, 1020 .table = meson8b_cpu_if_parents_val_table, 1021 }, 1022 .hw.init = &(struct clk_init_data){ 1023 .name = "apb_sel", 1024 .ops = &clk_regmap_mux_ops, 1025 .parent_hws = meson8b_cpu_if_parents, 1026 .num_parents = ARRAY_SIZE(meson8b_cpu_if_parents), 1027 }, 1028 }; 1029 1030 static struct clk_regmap meson8b_apb = { 1031 .data = &(struct clk_regmap_gate_data){ 1032 .offset = HHI_SYS_CPU_CLK_CNTL1, 1033 .bit_idx = 16, 1034 .flags = CLK_GATE_SET_TO_DISABLE, 1035 }, 1036 .hw.init = &(struct clk_init_data){ 1037 .name = "apb", 1038 .ops = &clk_regmap_gate_ro_ops, 1039 .parent_hws = (const struct clk_hw *[]) { 1040 &meson8b_apb_sel.hw 1041 }, 1042 .num_parents = 1, 1043 .flags = CLK_SET_RATE_PARENT, 1044 }, 1045 }; 1046 1047 static struct clk_regmap meson8b_periph_sel = { 1048 .data = &(struct clk_regmap_mux_data){ 1049 .offset = HHI_SYS_CPU_CLK_CNTL1, 1050 .mask = 0x7, 1051 .shift = 6, 1052 }, 1053 .hw.init = &(struct clk_init_data){ 1054 .name = "periph_sel", 1055 .ops = &clk_regmap_mux_ops, 1056 .parent_hws = meson8b_cpu_if_parents, 1057 .num_parents = ARRAY_SIZE(meson8b_cpu_if_parents), 1058 }, 1059 }; 1060 1061 static struct clk_regmap meson8b_periph = { 1062 .data = &(struct clk_regmap_gate_data){ 1063 .offset = HHI_SYS_CPU_CLK_CNTL1, 1064 .bit_idx = 17, 1065 .flags = CLK_GATE_SET_TO_DISABLE, 1066 }, 1067 .hw.init = &(struct clk_init_data){ 1068 .name = "periph", 1069 .ops = &clk_regmap_gate_ro_ops, 1070 .parent_hws = (const struct clk_hw *[]) { 1071 &meson8b_periph_sel.hw 1072 }, 1073 .num_parents = 1, 1074 .flags = CLK_SET_RATE_PARENT, 1075 }, 1076 }; 1077 1078 static struct clk_regmap meson8b_axi_sel = { 1079 .data = &(struct clk_regmap_mux_data){ 1080 .offset = HHI_SYS_CPU_CLK_CNTL1, 1081 .mask = 0x7, 1082 .shift = 9, 1083 .table = meson8b_cpu_if_parents_val_table, 1084 }, 1085 .hw.init = &(struct clk_init_data){ 1086 .name = "axi_sel", 1087 .ops = &clk_regmap_mux_ops, 1088 .parent_hws = meson8b_cpu_if_parents, 1089 .num_parents = ARRAY_SIZE(meson8b_cpu_if_parents), 1090 }, 1091 }; 1092 1093 static struct clk_regmap meson8b_axi = { 1094 .data = &(struct clk_regmap_gate_data){ 1095 .offset = HHI_SYS_CPU_CLK_CNTL1, 1096 .bit_idx = 18, 1097 .flags = CLK_GATE_SET_TO_DISABLE, 1098 }, 1099 .hw.init = &(struct clk_init_data){ 1100 .name = "axi", 1101 .ops = &clk_regmap_gate_ro_ops, 1102 .parent_hws = (const struct clk_hw *[]) { 1103 &meson8b_axi_sel.hw 1104 }, 1105 .num_parents = 1, 1106 .flags = CLK_SET_RATE_PARENT, 1107 }, 1108 }; 1109 1110 static struct clk_regmap meson8b_l2_dram_sel = { 1111 .data = &(struct clk_regmap_mux_data){ 1112 .offset = HHI_SYS_CPU_CLK_CNTL1, 1113 .mask = 0x7, 1114 .shift = 12, 1115 }, 1116 .hw.init = &(struct clk_init_data){ 1117 .name = "l2_dram_sel", 1118 .ops = &clk_regmap_mux_ops, 1119 .parent_hws = meson8b_cpu_if_parents, 1120 .num_parents = ARRAY_SIZE(meson8b_cpu_if_parents), 1121 }, 1122 }; 1123 1124 static struct clk_regmap meson8b_l2_dram = { 1125 .data = &(struct clk_regmap_gate_data){ 1126 .offset = HHI_SYS_CPU_CLK_CNTL1, 1127 .bit_idx = 19, 1128 .flags = CLK_GATE_SET_TO_DISABLE, 1129 }, 1130 .hw.init = &(struct clk_init_data){ 1131 .name = "l2_dram", 1132 .ops = &clk_regmap_gate_ro_ops, 1133 .parent_hws = (const struct clk_hw *[]) { 1134 &meson8b_l2_dram_sel.hw 1135 }, 1136 .num_parents = 1, 1137 .flags = CLK_SET_RATE_PARENT, 1138 }, 1139 }; 1140 1141 /* also called LVDS_CLK_EN */ 1142 static struct clk_regmap meson8b_vid_pll_lvds_en = { 1143 .data = &(struct clk_regmap_gate_data){ 1144 .offset = HHI_VID_DIVIDER_CNTL, 1145 .bit_idx = 11, 1146 }, 1147 .hw.init = &(struct clk_init_data){ 1148 .name = "vid_pll_lvds_en", 1149 .ops = &clk_regmap_gate_ops, 1150 .parent_hws = (const struct clk_hw *[]) { 1151 &meson8b_hdmi_pll_lvds_out.hw 1152 }, 1153 .num_parents = 1, 1154 .flags = CLK_SET_RATE_PARENT, 1155 }, 1156 }; 1157 1158 static struct clk_regmap meson8b_vid_pll_in_sel = { 1159 .data = &(struct clk_regmap_mux_data){ 1160 .offset = HHI_VID_DIVIDER_CNTL, 1161 .mask = 0x1, 1162 .shift = 15, 1163 }, 1164 .hw.init = &(struct clk_init_data){ 1165 .name = "vid_pll_in_sel", 1166 .ops = &clk_regmap_mux_ops, 1167 /* 1168 * TODO: depending on the SoC there is also a second parent: 1169 * Meson8: unknown 1170 * Meson8b: hdmi_pll_dco 1171 * Meson8m2: vid2_pll 1172 */ 1173 .parent_hws = (const struct clk_hw *[]) { 1174 &meson8b_vid_pll_lvds_en.hw 1175 }, 1176 .num_parents = 1, 1177 .flags = CLK_SET_RATE_PARENT, 1178 }, 1179 }; 1180 1181 static struct clk_regmap meson8b_vid_pll_in_en = { 1182 .data = &(struct clk_regmap_gate_data){ 1183 .offset = HHI_VID_DIVIDER_CNTL, 1184 .bit_idx = 16, 1185 }, 1186 .hw.init = &(struct clk_init_data){ 1187 .name = "vid_pll_in_en", 1188 .ops = &clk_regmap_gate_ops, 1189 .parent_hws = (const struct clk_hw *[]) { 1190 &meson8b_vid_pll_in_sel.hw 1191 }, 1192 .num_parents = 1, 1193 .flags = CLK_SET_RATE_PARENT, 1194 }, 1195 }; 1196 1197 static struct clk_regmap meson8b_vid_pll_pre_div = { 1198 .data = &(struct clk_regmap_div_data){ 1199 .offset = HHI_VID_DIVIDER_CNTL, 1200 .shift = 4, 1201 .width = 3, 1202 }, 1203 .hw.init = &(struct clk_init_data){ 1204 .name = "vid_pll_pre_div", 1205 .ops = &clk_regmap_divider_ops, 1206 .parent_hws = (const struct clk_hw *[]) { 1207 &meson8b_vid_pll_in_en.hw 1208 }, 1209 .num_parents = 1, 1210 .flags = CLK_SET_RATE_PARENT, 1211 }, 1212 }; 1213 1214 static struct clk_regmap meson8b_vid_pll_post_div = { 1215 .data = &(struct clk_regmap_div_data){ 1216 .offset = HHI_VID_DIVIDER_CNTL, 1217 .shift = 12, 1218 .width = 3, 1219 }, 1220 .hw.init = &(struct clk_init_data){ 1221 .name = "vid_pll_post_div", 1222 .ops = &clk_regmap_divider_ops, 1223 .parent_hws = (const struct clk_hw *[]) { 1224 &meson8b_vid_pll_pre_div.hw 1225 }, 1226 .num_parents = 1, 1227 .flags = CLK_SET_RATE_PARENT, 1228 }, 1229 }; 1230 1231 static struct clk_regmap meson8b_vid_pll = { 1232 .data = &(struct clk_regmap_mux_data){ 1233 .offset = HHI_VID_DIVIDER_CNTL, 1234 .mask = 0x3, 1235 .shift = 8, 1236 }, 1237 .hw.init = &(struct clk_init_data){ 1238 .name = "vid_pll", 1239 .ops = &clk_regmap_mux_ops, 1240 /* TODO: parent 0x2 is vid_pll_pre_div_mult7_div2 */ 1241 .parent_hws = (const struct clk_hw *[]) { 1242 &meson8b_vid_pll_pre_div.hw, 1243 &meson8b_vid_pll_post_div.hw, 1244 }, 1245 .num_parents = 2, 1246 .flags = CLK_SET_RATE_PARENT, 1247 }, 1248 }; 1249 1250 static struct clk_regmap meson8b_vid_pll_final_div = { 1251 .data = &(struct clk_regmap_div_data){ 1252 .offset = HHI_VID_CLK_DIV, 1253 .shift = 0, 1254 .width = 8, 1255 }, 1256 .hw.init = &(struct clk_init_data){ 1257 .name = "vid_pll_final_div", 1258 .ops = &clk_regmap_divider_ops, 1259 .parent_hws = (const struct clk_hw *[]) { 1260 &meson8b_vid_pll.hw 1261 }, 1262 .num_parents = 1, 1263 .flags = CLK_SET_RATE_PARENT, 1264 }, 1265 }; 1266 1267 static const struct clk_hw *meson8b_vclk_parents[] = { 1268 &meson8b_vid_pll_final_div.hw, 1269 &meson8b_fclk_div4.hw, 1270 &meson8b_fclk_div3.hw, 1271 &meson8b_fclk_div5.hw, 1272 &meson8b_vid_pll_final_div.hw, 1273 &meson8b_fclk_div7.hw, 1274 &meson8b_mpll1.hw, 1275 }; 1276 1277 static struct clk_regmap meson8b_vclk_in_sel = { 1278 .data = &(struct clk_regmap_mux_data){ 1279 .offset = HHI_VID_CLK_CNTL, 1280 .mask = 0x7, 1281 .shift = 16, 1282 }, 1283 .hw.init = &(struct clk_init_data){ 1284 .name = "vclk_in_sel", 1285 .ops = &clk_regmap_mux_ops, 1286 .parent_hws = meson8b_vclk_parents, 1287 .num_parents = ARRAY_SIZE(meson8b_vclk_parents), 1288 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 1289 }, 1290 }; 1291 1292 static struct clk_regmap meson8b_vclk_in_en = { 1293 .data = &(struct clk_regmap_gate_data){ 1294 .offset = HHI_VID_CLK_DIV, 1295 .bit_idx = 16, 1296 }, 1297 .hw.init = &(struct clk_init_data){ 1298 .name = "vclk_in_en", 1299 .ops = &clk_regmap_gate_ops, 1300 .parent_hws = (const struct clk_hw *[]) { 1301 &meson8b_vclk_in_sel.hw 1302 }, 1303 .num_parents = 1, 1304 .flags = CLK_SET_RATE_PARENT, 1305 }, 1306 }; 1307 1308 static struct clk_regmap meson8b_vclk_en = { 1309 .data = &(struct clk_regmap_gate_data){ 1310 .offset = HHI_VID_CLK_CNTL, 1311 .bit_idx = 19, 1312 }, 1313 .hw.init = &(struct clk_init_data){ 1314 .name = "vclk_en", 1315 .ops = &clk_regmap_gate_ops, 1316 .parent_hws = (const struct clk_hw *[]) { 1317 &meson8b_vclk_in_en.hw 1318 }, 1319 .num_parents = 1, 1320 .flags = CLK_SET_RATE_PARENT, 1321 }, 1322 }; 1323 1324 static struct clk_regmap meson8b_vclk_div1 = { 1325 .data = &(struct clk_regmap_gate_data){ 1326 .offset = HHI_VID_CLK_CNTL, 1327 .bit_idx = 0, 1328 }, 1329 .hw.init = &(struct clk_init_data){ 1330 .name = "vclk_div1", 1331 .ops = &clk_regmap_gate_ops, 1332 .parent_hws = (const struct clk_hw *[]) { 1333 &meson8b_vclk_en.hw 1334 }, 1335 .num_parents = 1, 1336 .flags = CLK_SET_RATE_PARENT, 1337 }, 1338 }; 1339 1340 static struct clk_fixed_factor meson8b_vclk_div2_div = { 1341 .mult = 1, 1342 .div = 2, 1343 .hw.init = &(struct clk_init_data){ 1344 .name = "vclk_div2_div", 1345 .ops = &clk_fixed_factor_ops, 1346 .parent_hws = (const struct clk_hw *[]) { 1347 &meson8b_vclk_en.hw 1348 }, 1349 .num_parents = 1, 1350 .flags = CLK_SET_RATE_PARENT, 1351 } 1352 }; 1353 1354 static struct clk_regmap meson8b_vclk_div2 = { 1355 .data = &(struct clk_regmap_gate_data){ 1356 .offset = HHI_VID_CLK_CNTL, 1357 .bit_idx = 1, 1358 }, 1359 .hw.init = &(struct clk_init_data){ 1360 .name = "vclk_div2", 1361 .ops = &clk_regmap_gate_ops, 1362 .parent_hws = (const struct clk_hw *[]) { 1363 &meson8b_vclk_div2_div.hw 1364 }, 1365 .num_parents = 1, 1366 .flags = CLK_SET_RATE_PARENT, 1367 }, 1368 }; 1369 1370 static struct clk_fixed_factor meson8b_vclk_div4_div = { 1371 .mult = 1, 1372 .div = 4, 1373 .hw.init = &(struct clk_init_data){ 1374 .name = "vclk_div4_div", 1375 .ops = &clk_fixed_factor_ops, 1376 .parent_hws = (const struct clk_hw *[]) { 1377 &meson8b_vclk_en.hw 1378 }, 1379 .num_parents = 1, 1380 .flags = CLK_SET_RATE_PARENT, 1381 } 1382 }; 1383 1384 static struct clk_regmap meson8b_vclk_div4 = { 1385 .data = &(struct clk_regmap_gate_data){ 1386 .offset = HHI_VID_CLK_CNTL, 1387 .bit_idx = 2, 1388 }, 1389 .hw.init = &(struct clk_init_data){ 1390 .name = "vclk_div4", 1391 .ops = &clk_regmap_gate_ops, 1392 .parent_hws = (const struct clk_hw *[]) { 1393 &meson8b_vclk_div4_div.hw 1394 }, 1395 .num_parents = 1, 1396 .flags = CLK_SET_RATE_PARENT, 1397 }, 1398 }; 1399 1400 static struct clk_fixed_factor meson8b_vclk_div6_div = { 1401 .mult = 1, 1402 .div = 6, 1403 .hw.init = &(struct clk_init_data){ 1404 .name = "vclk_div6_div", 1405 .ops = &clk_fixed_factor_ops, 1406 .parent_hws = (const struct clk_hw *[]) { 1407 &meson8b_vclk_en.hw 1408 }, 1409 .num_parents = 1, 1410 .flags = CLK_SET_RATE_PARENT, 1411 } 1412 }; 1413 1414 static struct clk_regmap meson8b_vclk_div6 = { 1415 .data = &(struct clk_regmap_gate_data){ 1416 .offset = HHI_VID_CLK_CNTL, 1417 .bit_idx = 3, 1418 }, 1419 .hw.init = &(struct clk_init_data){ 1420 .name = "vclk_div6", 1421 .ops = &clk_regmap_gate_ops, 1422 .parent_hws = (const struct clk_hw *[]) { 1423 &meson8b_vclk_div6_div.hw 1424 }, 1425 .num_parents = 1, 1426 .flags = CLK_SET_RATE_PARENT, 1427 }, 1428 }; 1429 1430 static struct clk_fixed_factor meson8b_vclk_div12_div = { 1431 .mult = 1, 1432 .div = 12, 1433 .hw.init = &(struct clk_init_data){ 1434 .name = "vclk_div12_div", 1435 .ops = &clk_fixed_factor_ops, 1436 .parent_hws = (const struct clk_hw *[]) { 1437 &meson8b_vclk_en.hw 1438 }, 1439 .num_parents = 1, 1440 .flags = CLK_SET_RATE_PARENT, 1441 } 1442 }; 1443 1444 static struct clk_regmap meson8b_vclk_div12 = { 1445 .data = &(struct clk_regmap_gate_data){ 1446 .offset = HHI_VID_CLK_CNTL, 1447 .bit_idx = 4, 1448 }, 1449 .hw.init = &(struct clk_init_data){ 1450 .name = "vclk_div12", 1451 .ops = &clk_regmap_gate_ops, 1452 .parent_hws = (const struct clk_hw *[]) { 1453 &meson8b_vclk_div12_div.hw 1454 }, 1455 .num_parents = 1, 1456 .flags = CLK_SET_RATE_PARENT, 1457 }, 1458 }; 1459 1460 static struct clk_regmap meson8b_vclk2_in_sel = { 1461 .data = &(struct clk_regmap_mux_data){ 1462 .offset = HHI_VIID_CLK_CNTL, 1463 .mask = 0x7, 1464 .shift = 16, 1465 }, 1466 .hw.init = &(struct clk_init_data){ 1467 .name = "vclk2_in_sel", 1468 .ops = &clk_regmap_mux_ops, 1469 .parent_hws = meson8b_vclk_parents, 1470 .num_parents = ARRAY_SIZE(meson8b_vclk_parents), 1471 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 1472 }, 1473 }; 1474 1475 static struct clk_regmap meson8b_vclk2_in_en = { 1476 .data = &(struct clk_regmap_gate_data){ 1477 .offset = HHI_VIID_CLK_DIV, 1478 .bit_idx = 16, 1479 }, 1480 .hw.init = &(struct clk_init_data){ 1481 .name = "vclk2_in_en", 1482 .ops = &clk_regmap_gate_ops, 1483 .parent_hws = (const struct clk_hw *[]) { 1484 &meson8b_vclk2_in_sel.hw 1485 }, 1486 .num_parents = 1, 1487 .flags = CLK_SET_RATE_PARENT, 1488 }, 1489 }; 1490 1491 static struct clk_regmap meson8b_vclk2_en = { 1492 .data = &(struct clk_regmap_gate_data){ 1493 .offset = HHI_VIID_CLK_DIV, 1494 .bit_idx = 19, 1495 }, 1496 .hw.init = &(struct clk_init_data){ 1497 .name = "vclk2_en", 1498 .ops = &clk_regmap_gate_ops, 1499 .parent_hws = (const struct clk_hw *[]) { 1500 &meson8b_vclk2_in_en.hw 1501 }, 1502 .num_parents = 1, 1503 .flags = CLK_SET_RATE_PARENT, 1504 }, 1505 }; 1506 1507 static struct clk_regmap meson8b_vclk2_div1 = { 1508 .data = &(struct clk_regmap_gate_data){ 1509 .offset = HHI_VIID_CLK_DIV, 1510 .bit_idx = 0, 1511 }, 1512 .hw.init = &(struct clk_init_data){ 1513 .name = "vclk2_div1", 1514 .ops = &clk_regmap_gate_ops, 1515 .parent_hws = (const struct clk_hw *[]) { 1516 &meson8b_vclk2_en.hw 1517 }, 1518 .num_parents = 1, 1519 .flags = CLK_SET_RATE_PARENT, 1520 }, 1521 }; 1522 1523 static struct clk_fixed_factor meson8b_vclk2_div2_div = { 1524 .mult = 1, 1525 .div = 2, 1526 .hw.init = &(struct clk_init_data){ 1527 .name = "vclk2_div2_div", 1528 .ops = &clk_fixed_factor_ops, 1529 .parent_hws = (const struct clk_hw *[]) { 1530 &meson8b_vclk2_en.hw 1531 }, 1532 .num_parents = 1, 1533 .flags = CLK_SET_RATE_PARENT, 1534 } 1535 }; 1536 1537 static struct clk_regmap meson8b_vclk2_div2 = { 1538 .data = &(struct clk_regmap_gate_data){ 1539 .offset = HHI_VIID_CLK_DIV, 1540 .bit_idx = 1, 1541 }, 1542 .hw.init = &(struct clk_init_data){ 1543 .name = "vclk2_div2", 1544 .ops = &clk_regmap_gate_ops, 1545 .parent_hws = (const struct clk_hw *[]) { 1546 &meson8b_vclk2_div2_div.hw 1547 }, 1548 .num_parents = 1, 1549 .flags = CLK_SET_RATE_PARENT, 1550 }, 1551 }; 1552 1553 static struct clk_fixed_factor meson8b_vclk2_div4_div = { 1554 .mult = 1, 1555 .div = 4, 1556 .hw.init = &(struct clk_init_data){ 1557 .name = "vclk2_div4_div", 1558 .ops = &clk_fixed_factor_ops, 1559 .parent_hws = (const struct clk_hw *[]) { 1560 &meson8b_vclk2_en.hw 1561 }, 1562 .num_parents = 1, 1563 .flags = CLK_SET_RATE_PARENT, 1564 } 1565 }; 1566 1567 static struct clk_regmap meson8b_vclk2_div4 = { 1568 .data = &(struct clk_regmap_gate_data){ 1569 .offset = HHI_VIID_CLK_DIV, 1570 .bit_idx = 2, 1571 }, 1572 .hw.init = &(struct clk_init_data){ 1573 .name = "vclk2_div4", 1574 .ops = &clk_regmap_gate_ops, 1575 .parent_hws = (const struct clk_hw *[]) { 1576 &meson8b_vclk2_div4_div.hw 1577 }, 1578 .num_parents = 1, 1579 .flags = CLK_SET_RATE_PARENT, 1580 }, 1581 }; 1582 1583 static struct clk_fixed_factor meson8b_vclk2_div6_div = { 1584 .mult = 1, 1585 .div = 6, 1586 .hw.init = &(struct clk_init_data){ 1587 .name = "vclk2_div6_div", 1588 .ops = &clk_fixed_factor_ops, 1589 .parent_hws = (const struct clk_hw *[]) { 1590 &meson8b_vclk2_en.hw 1591 }, 1592 .num_parents = 1, 1593 .flags = CLK_SET_RATE_PARENT, 1594 } 1595 }; 1596 1597 static struct clk_regmap meson8b_vclk2_div6 = { 1598 .data = &(struct clk_regmap_gate_data){ 1599 .offset = HHI_VIID_CLK_DIV, 1600 .bit_idx = 3, 1601 }, 1602 .hw.init = &(struct clk_init_data){ 1603 .name = "vclk2_div6", 1604 .ops = &clk_regmap_gate_ops, 1605 .parent_hws = (const struct clk_hw *[]) { 1606 &meson8b_vclk2_div6_div.hw 1607 }, 1608 .num_parents = 1, 1609 .flags = CLK_SET_RATE_PARENT, 1610 }, 1611 }; 1612 1613 static struct clk_fixed_factor meson8b_vclk2_div12_div = { 1614 .mult = 1, 1615 .div = 12, 1616 .hw.init = &(struct clk_init_data){ 1617 .name = "vclk2_div12_div", 1618 .ops = &clk_fixed_factor_ops, 1619 .parent_hws = (const struct clk_hw *[]) { 1620 &meson8b_vclk2_en.hw 1621 }, 1622 .num_parents = 1, 1623 .flags = CLK_SET_RATE_PARENT, 1624 } 1625 }; 1626 1627 static struct clk_regmap meson8b_vclk2_div12 = { 1628 .data = &(struct clk_regmap_gate_data){ 1629 .offset = HHI_VIID_CLK_DIV, 1630 .bit_idx = 4, 1631 }, 1632 .hw.init = &(struct clk_init_data){ 1633 .name = "vclk2_div12", 1634 .ops = &clk_regmap_gate_ops, 1635 .parent_hws = (const struct clk_hw *[]) { 1636 &meson8b_vclk2_div12_div.hw 1637 }, 1638 .num_parents = 1, 1639 .flags = CLK_SET_RATE_PARENT, 1640 }, 1641 }; 1642 1643 static const struct clk_hw *meson8b_vclk_enc_parents[] = { 1644 &meson8b_vclk_div1.hw, 1645 &meson8b_vclk_div2.hw, 1646 &meson8b_vclk_div4.hw, 1647 &meson8b_vclk_div6.hw, 1648 &meson8b_vclk_div12.hw, 1649 }; 1650 1651 static struct clk_regmap meson8b_cts_enct_sel = { 1652 .data = &(struct clk_regmap_mux_data){ 1653 .offset = HHI_VID_CLK_DIV, 1654 .mask = 0xf, 1655 .shift = 20, 1656 }, 1657 .hw.init = &(struct clk_init_data){ 1658 .name = "cts_enct_sel", 1659 .ops = &clk_regmap_mux_ops, 1660 .parent_hws = meson8b_vclk_enc_parents, 1661 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_parents), 1662 .flags = CLK_SET_RATE_PARENT, 1663 }, 1664 }; 1665 1666 static struct clk_regmap meson8b_cts_enct = { 1667 .data = &(struct clk_regmap_gate_data){ 1668 .offset = HHI_VID_CLK_CNTL2, 1669 .bit_idx = 1, 1670 }, 1671 .hw.init = &(struct clk_init_data){ 1672 .name = "cts_enct", 1673 .ops = &clk_regmap_gate_ops, 1674 .parent_hws = (const struct clk_hw *[]) { 1675 &meson8b_cts_enct_sel.hw 1676 }, 1677 .num_parents = 1, 1678 .flags = CLK_SET_RATE_PARENT, 1679 }, 1680 }; 1681 1682 static struct clk_regmap meson8b_cts_encp_sel = { 1683 .data = &(struct clk_regmap_mux_data){ 1684 .offset = HHI_VID_CLK_DIV, 1685 .mask = 0xf, 1686 .shift = 24, 1687 }, 1688 .hw.init = &(struct clk_init_data){ 1689 .name = "cts_encp_sel", 1690 .ops = &clk_regmap_mux_ops, 1691 .parent_hws = meson8b_vclk_enc_parents, 1692 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_parents), 1693 .flags = CLK_SET_RATE_PARENT, 1694 }, 1695 }; 1696 1697 static struct clk_regmap meson8b_cts_encp = { 1698 .data = &(struct clk_regmap_gate_data){ 1699 .offset = HHI_VID_CLK_CNTL2, 1700 .bit_idx = 2, 1701 }, 1702 .hw.init = &(struct clk_init_data){ 1703 .name = "cts_encp", 1704 .ops = &clk_regmap_gate_ops, 1705 .parent_hws = (const struct clk_hw *[]) { 1706 &meson8b_cts_encp_sel.hw 1707 }, 1708 .num_parents = 1, 1709 .flags = CLK_SET_RATE_PARENT, 1710 }, 1711 }; 1712 1713 static struct clk_regmap meson8b_cts_enci_sel = { 1714 .data = &(struct clk_regmap_mux_data){ 1715 .offset = HHI_VID_CLK_DIV, 1716 .mask = 0xf, 1717 .shift = 28, 1718 }, 1719 .hw.init = &(struct clk_init_data){ 1720 .name = "cts_enci_sel", 1721 .ops = &clk_regmap_mux_ops, 1722 .parent_hws = meson8b_vclk_enc_parents, 1723 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_parents), 1724 .flags = CLK_SET_RATE_PARENT, 1725 }, 1726 }; 1727 1728 static struct clk_regmap meson8b_cts_enci = { 1729 .data = &(struct clk_regmap_gate_data){ 1730 .offset = HHI_VID_CLK_CNTL2, 1731 .bit_idx = 0, 1732 }, 1733 .hw.init = &(struct clk_init_data){ 1734 .name = "cts_enci", 1735 .ops = &clk_regmap_gate_ops, 1736 .parent_hws = (const struct clk_hw *[]) { 1737 &meson8b_cts_enci_sel.hw 1738 }, 1739 .num_parents = 1, 1740 .flags = CLK_SET_RATE_PARENT, 1741 }, 1742 }; 1743 1744 static struct clk_regmap meson8b_hdmi_tx_pixel_sel = { 1745 .data = &(struct clk_regmap_mux_data){ 1746 .offset = HHI_HDMI_CLK_CNTL, 1747 .mask = 0xf, 1748 .shift = 16, 1749 }, 1750 .hw.init = &(struct clk_init_data){ 1751 .name = "hdmi_tx_pixel_sel", 1752 .ops = &clk_regmap_mux_ops, 1753 .parent_hws = meson8b_vclk_enc_parents, 1754 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_parents), 1755 .flags = CLK_SET_RATE_PARENT, 1756 }, 1757 }; 1758 1759 static struct clk_regmap meson8b_hdmi_tx_pixel = { 1760 .data = &(struct clk_regmap_gate_data){ 1761 .offset = HHI_VID_CLK_CNTL2, 1762 .bit_idx = 5, 1763 }, 1764 .hw.init = &(struct clk_init_data){ 1765 .name = "hdmi_tx_pixel", 1766 .ops = &clk_regmap_gate_ops, 1767 .parent_hws = (const struct clk_hw *[]) { 1768 &meson8b_hdmi_tx_pixel_sel.hw 1769 }, 1770 .num_parents = 1, 1771 .flags = CLK_SET_RATE_PARENT, 1772 }, 1773 }; 1774 1775 static struct clk_regmap meson8b_cts_encl_sel = { 1776 .data = &(struct clk_regmap_mux_data){ 1777 .offset = HHI_VIID_CLK_DIV, 1778 .mask = 0xf, 1779 .shift = 12, 1780 }, 1781 .hw.init = &(struct clk_init_data){ 1782 .name = "cts_encl_sel", 1783 .ops = &clk_regmap_mux_ops, 1784 .parent_hws = meson8b_vclk_enc_parents, 1785 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_parents), 1786 .flags = CLK_SET_RATE_PARENT, 1787 }, 1788 }; 1789 1790 static struct clk_regmap meson8b_cts_encl = { 1791 .data = &(struct clk_regmap_gate_data){ 1792 .offset = HHI_VID_CLK_CNTL2, 1793 .bit_idx = 3, 1794 }, 1795 .hw.init = &(struct clk_init_data){ 1796 .name = "cts_encl", 1797 .ops = &clk_regmap_gate_ops, 1798 .parent_hws = (const struct clk_hw *[]) { 1799 &meson8b_cts_encl_sel.hw 1800 }, 1801 .num_parents = 1, 1802 .flags = CLK_SET_RATE_PARENT, 1803 }, 1804 }; 1805 1806 static struct clk_regmap meson8b_cts_vdac0_sel = { 1807 .data = &(struct clk_regmap_mux_data){ 1808 .offset = HHI_VIID_CLK_DIV, 1809 .mask = 0xf, 1810 .shift = 28, 1811 }, 1812 .hw.init = &(struct clk_init_data){ 1813 .name = "cts_vdac0_sel", 1814 .ops = &clk_regmap_mux_ops, 1815 .parent_hws = meson8b_vclk_enc_parents, 1816 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_parents), 1817 .flags = CLK_SET_RATE_PARENT, 1818 }, 1819 }; 1820 1821 static struct clk_regmap meson8b_cts_vdac0 = { 1822 .data = &(struct clk_regmap_gate_data){ 1823 .offset = HHI_VID_CLK_CNTL2, 1824 .bit_idx = 4, 1825 }, 1826 .hw.init = &(struct clk_init_data){ 1827 .name = "cts_vdac0", 1828 .ops = &clk_regmap_gate_ops, 1829 .parent_hws = (const struct clk_hw *[]) { 1830 &meson8b_cts_vdac0_sel.hw 1831 }, 1832 .num_parents = 1, 1833 .flags = CLK_SET_RATE_PARENT, 1834 }, 1835 }; 1836 1837 static struct clk_regmap meson8b_hdmi_sys_sel = { 1838 .data = &(struct clk_regmap_mux_data){ 1839 .offset = HHI_HDMI_CLK_CNTL, 1840 .mask = 0x3, 1841 .shift = 9, 1842 .flags = CLK_MUX_ROUND_CLOSEST, 1843 }, 1844 .hw.init = &(struct clk_init_data){ 1845 .name = "hdmi_sys_sel", 1846 .ops = &clk_regmap_mux_ops, 1847 /* FIXME: all other parents are unknown */ 1848 .parent_data = &(const struct clk_parent_data) { 1849 .fw_name = "xtal", 1850 .name = "xtal", 1851 .index = -1, 1852 }, 1853 .num_parents = 1, 1854 .flags = CLK_SET_RATE_NO_REPARENT, 1855 }, 1856 }; 1857 1858 static struct clk_regmap meson8b_hdmi_sys_div = { 1859 .data = &(struct clk_regmap_div_data){ 1860 .offset = HHI_HDMI_CLK_CNTL, 1861 .shift = 0, 1862 .width = 7, 1863 }, 1864 .hw.init = &(struct clk_init_data){ 1865 .name = "hdmi_sys_div", 1866 .ops = &clk_regmap_divider_ops, 1867 .parent_hws = (const struct clk_hw *[]) { 1868 &meson8b_hdmi_sys_sel.hw 1869 }, 1870 .num_parents = 1, 1871 .flags = CLK_SET_RATE_PARENT, 1872 }, 1873 }; 1874 1875 static struct clk_regmap meson8b_hdmi_sys = { 1876 .data = &(struct clk_regmap_gate_data){ 1877 .offset = HHI_HDMI_CLK_CNTL, 1878 .bit_idx = 8, 1879 }, 1880 .hw.init = &(struct clk_init_data) { 1881 .name = "hdmi_sys", 1882 .ops = &clk_regmap_gate_ops, 1883 .parent_hws = (const struct clk_hw *[]) { 1884 &meson8b_hdmi_sys_div.hw 1885 }, 1886 .num_parents = 1, 1887 .flags = CLK_SET_RATE_PARENT, 1888 }, 1889 }; 1890 1891 /* 1892 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) 1893 * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can 1894 * actually manage this glitch-free mux because it does top-to-bottom 1895 * updates the each clock tree and switches to the "inactive" one when 1896 * CLK_SET_RATE_GATE is set. 1897 * Meson8 only has mali_0 and no glitch-free mux. 1898 */ 1899 static u32 meson8b_mali_parents_val_table[] = { 0, 2, 3, 4, 5, 6, 7 }; 1900 static const struct clk_parent_data meson8b_mali_parents[] = { 1901 { .fw_name = "xtal", .name = "xtal", .index = -1, }, 1902 { .hw = &meson8b_mpll2.hw, }, 1903 { .hw = &meson8b_mpll1.hw, }, 1904 { .hw = &meson8b_fclk_div7.hw, }, 1905 { .hw = &meson8b_fclk_div4.hw, }, 1906 { .hw = &meson8b_fclk_div3.hw, }, 1907 { .hw = &meson8b_fclk_div5.hw, }, 1908 }; 1909 1910 static struct clk_regmap meson8b_mali_0_sel = { 1911 .data = &(struct clk_regmap_mux_data){ 1912 .offset = HHI_MALI_CLK_CNTL, 1913 .mask = 0x7, 1914 .shift = 9, 1915 .table = meson8b_mali_parents_val_table, 1916 }, 1917 .hw.init = &(struct clk_init_data){ 1918 .name = "mali_0_sel", 1919 .ops = &clk_regmap_mux_ops, 1920 .parent_data = meson8b_mali_parents, 1921 .num_parents = ARRAY_SIZE(meson8b_mali_parents), 1922 /* 1923 * Don't propagate rate changes up because the only changeable 1924 * parents are mpll1 and mpll2 but we need those for audio and 1925 * RGMII (Ethernet). We don't want to change the audio or 1926 * Ethernet clocks when setting the GPU frequency. 1927 */ 1928 .flags = 0, 1929 }, 1930 }; 1931 1932 static struct clk_regmap meson8b_mali_0_div = { 1933 .data = &(struct clk_regmap_div_data){ 1934 .offset = HHI_MALI_CLK_CNTL, 1935 .shift = 0, 1936 .width = 7, 1937 }, 1938 .hw.init = &(struct clk_init_data){ 1939 .name = "mali_0_div", 1940 .ops = &clk_regmap_divider_ops, 1941 .parent_hws = (const struct clk_hw *[]) { 1942 &meson8b_mali_0_sel.hw 1943 }, 1944 .num_parents = 1, 1945 .flags = CLK_SET_RATE_PARENT, 1946 }, 1947 }; 1948 1949 static struct clk_regmap meson8b_mali_0 = { 1950 .data = &(struct clk_regmap_gate_data){ 1951 .offset = HHI_MALI_CLK_CNTL, 1952 .bit_idx = 8, 1953 }, 1954 .hw.init = &(struct clk_init_data){ 1955 .name = "mali_0", 1956 .ops = &clk_regmap_gate_ops, 1957 .parent_hws = (const struct clk_hw *[]) { 1958 &meson8b_mali_0_div.hw 1959 }, 1960 .num_parents = 1, 1961 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, 1962 }, 1963 }; 1964 1965 static struct clk_regmap meson8b_mali_1_sel = { 1966 .data = &(struct clk_regmap_mux_data){ 1967 .offset = HHI_MALI_CLK_CNTL, 1968 .mask = 0x7, 1969 .shift = 25, 1970 .table = meson8b_mali_parents_val_table, 1971 }, 1972 .hw.init = &(struct clk_init_data){ 1973 .name = "mali_1_sel", 1974 .ops = &clk_regmap_mux_ops, 1975 .parent_data = meson8b_mali_parents, 1976 .num_parents = ARRAY_SIZE(meson8b_mali_parents), 1977 /* 1978 * Don't propagate rate changes up because the only changeable 1979 * parents are mpll1 and mpll2 but we need those for audio and 1980 * RGMII (Ethernet). We don't want to change the audio or 1981 * Ethernet clocks when setting the GPU frequency. 1982 */ 1983 .flags = 0, 1984 }, 1985 }; 1986 1987 static struct clk_regmap meson8b_mali_1_div = { 1988 .data = &(struct clk_regmap_div_data){ 1989 .offset = HHI_MALI_CLK_CNTL, 1990 .shift = 16, 1991 .width = 7, 1992 }, 1993 .hw.init = &(struct clk_init_data){ 1994 .name = "mali_1_div", 1995 .ops = &clk_regmap_divider_ops, 1996 .parent_hws = (const struct clk_hw *[]) { 1997 &meson8b_mali_1_sel.hw 1998 }, 1999 .num_parents = 1, 2000 .flags = CLK_SET_RATE_PARENT, 2001 }, 2002 }; 2003 2004 static struct clk_regmap meson8b_mali_1 = { 2005 .data = &(struct clk_regmap_gate_data){ 2006 .offset = HHI_MALI_CLK_CNTL, 2007 .bit_idx = 24, 2008 }, 2009 .hw.init = &(struct clk_init_data){ 2010 .name = "mali_1", 2011 .ops = &clk_regmap_gate_ops, 2012 .parent_hws = (const struct clk_hw *[]) { 2013 &meson8b_mali_1_div.hw 2014 }, 2015 .num_parents = 1, 2016 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, 2017 }, 2018 }; 2019 2020 static struct clk_regmap meson8b_mali = { 2021 .data = &(struct clk_regmap_mux_data){ 2022 .offset = HHI_MALI_CLK_CNTL, 2023 .mask = 1, 2024 .shift = 31, 2025 }, 2026 .hw.init = &(struct clk_init_data){ 2027 .name = "mali", 2028 .ops = &clk_regmap_mux_ops, 2029 .parent_hws = (const struct clk_hw *[]) { 2030 &meson8b_mali_0.hw, 2031 &meson8b_mali_1.hw, 2032 }, 2033 .num_parents = 2, 2034 .flags = CLK_SET_RATE_PARENT, 2035 }, 2036 }; 2037 2038 static const struct reg_sequence meson8m2_gp_pll_init_regs[] = { 2039 { .reg = HHI_GP_PLL_CNTL2, .def = 0x59c88000 }, 2040 { .reg = HHI_GP_PLL_CNTL3, .def = 0xca463823 }, 2041 { .reg = HHI_GP_PLL_CNTL4, .def = 0x0286a027 }, 2042 { .reg = HHI_GP_PLL_CNTL5, .def = 0x00003000 }, 2043 }; 2044 2045 static const struct pll_params_table meson8m2_gp_pll_params_table[] = { 2046 PLL_PARAMS(182, 3), 2047 { /* sentinel */ }, 2048 }; 2049 2050 static struct clk_regmap meson8m2_gp_pll_dco = { 2051 .data = &(struct meson_clk_pll_data){ 2052 .en = { 2053 .reg_off = HHI_GP_PLL_CNTL, 2054 .shift = 30, 2055 .width = 1, 2056 }, 2057 .m = { 2058 .reg_off = HHI_GP_PLL_CNTL, 2059 .shift = 0, 2060 .width = 9, 2061 }, 2062 .n = { 2063 .reg_off = HHI_GP_PLL_CNTL, 2064 .shift = 9, 2065 .width = 5, 2066 }, 2067 .l = { 2068 .reg_off = HHI_GP_PLL_CNTL, 2069 .shift = 31, 2070 .width = 1, 2071 }, 2072 .rst = { 2073 .reg_off = HHI_GP_PLL_CNTL, 2074 .shift = 29, 2075 .width = 1, 2076 }, 2077 .table = meson8m2_gp_pll_params_table, 2078 .init_regs = meson8m2_gp_pll_init_regs, 2079 .init_count = ARRAY_SIZE(meson8m2_gp_pll_init_regs), 2080 }, 2081 .hw.init = &(struct clk_init_data){ 2082 .name = "gp_pll_dco", 2083 .ops = &meson_clk_pll_ops, 2084 .parent_data = &(const struct clk_parent_data) { 2085 .fw_name = "xtal", 2086 .name = "xtal", 2087 .index = -1, 2088 }, 2089 .num_parents = 1, 2090 }, 2091 }; 2092 2093 static struct clk_regmap meson8m2_gp_pll = { 2094 .data = &(struct clk_regmap_div_data){ 2095 .offset = HHI_GP_PLL_CNTL, 2096 .shift = 16, 2097 .width = 2, 2098 .flags = CLK_DIVIDER_POWER_OF_TWO, 2099 }, 2100 .hw.init = &(struct clk_init_data){ 2101 .name = "gp_pll", 2102 .ops = &clk_regmap_divider_ops, 2103 .parent_hws = (const struct clk_hw *[]) { 2104 &meson8m2_gp_pll_dco.hw 2105 }, 2106 .num_parents = 1, 2107 .flags = CLK_SET_RATE_PARENT, 2108 }, 2109 }; 2110 2111 static const struct clk_hw *meson8b_vpu_parents[] = { 2112 &meson8b_fclk_div4.hw, 2113 &meson8b_fclk_div3.hw, 2114 &meson8b_fclk_div5.hw, 2115 &meson8b_fclk_div7.hw, 2116 }; 2117 2118 static struct clk_regmap meson8b_vpu_0_sel = { 2119 .data = &(struct clk_regmap_mux_data){ 2120 .offset = HHI_VPU_CLK_CNTL, 2121 .mask = 0x3, 2122 .shift = 9, 2123 }, 2124 .hw.init = &(struct clk_init_data){ 2125 .name = "vpu_0_sel", 2126 .ops = &clk_regmap_mux_ops, 2127 .parent_hws = meson8b_vpu_parents, 2128 .num_parents = ARRAY_SIZE(meson8b_vpu_parents), 2129 .flags = CLK_SET_RATE_PARENT, 2130 }, 2131 }; 2132 2133 static const struct clk_hw *mmeson8m2_vpu_parents[] = { 2134 &meson8b_fclk_div4.hw, 2135 &meson8b_fclk_div3.hw, 2136 &meson8b_fclk_div5.hw, 2137 &meson8m2_gp_pll.hw, 2138 }; 2139 2140 static struct clk_regmap meson8m2_vpu_0_sel = { 2141 .data = &(struct clk_regmap_mux_data){ 2142 .offset = HHI_VPU_CLK_CNTL, 2143 .mask = 0x3, 2144 .shift = 9, 2145 }, 2146 .hw.init = &(struct clk_init_data){ 2147 .name = "vpu_0_sel", 2148 .ops = &clk_regmap_mux_ops, 2149 .parent_hws = mmeson8m2_vpu_parents, 2150 .num_parents = ARRAY_SIZE(mmeson8m2_vpu_parents), 2151 .flags = CLK_SET_RATE_PARENT, 2152 }, 2153 }; 2154 2155 static struct clk_regmap meson8b_vpu_0_div = { 2156 .data = &(struct clk_regmap_div_data){ 2157 .offset = HHI_VPU_CLK_CNTL, 2158 .shift = 0, 2159 .width = 7, 2160 }, 2161 .hw.init = &(struct clk_init_data){ 2162 .name = "vpu_0_div", 2163 .ops = &clk_regmap_divider_ops, 2164 .parent_data = &(const struct clk_parent_data) { 2165 /* 2166 * Note: 2167 * meson8b and meson8m2 have different vpu_0_sels (with 2168 * different struct clk_hw). We fallback to the global 2169 * naming string mechanism so vpu_0_div picks up the 2170 * appropriate one. 2171 */ 2172 .name = "vpu_0_sel", 2173 .index = -1, 2174 }, 2175 .num_parents = 1, 2176 .flags = CLK_SET_RATE_PARENT, 2177 }, 2178 }; 2179 2180 static struct clk_regmap meson8b_vpu_0 = { 2181 .data = &(struct clk_regmap_gate_data){ 2182 .offset = HHI_VPU_CLK_CNTL, 2183 .bit_idx = 8, 2184 }, 2185 .hw.init = &(struct clk_init_data) { 2186 .name = "vpu_0", 2187 .ops = &clk_regmap_gate_ops, 2188 .parent_hws = (const struct clk_hw *[]) { 2189 &meson8b_vpu_0_div.hw 2190 }, 2191 .num_parents = 1, 2192 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, 2193 }, 2194 }; 2195 2196 static struct clk_regmap meson8b_vpu_1_sel = { 2197 .data = &(struct clk_regmap_mux_data){ 2198 .offset = HHI_VPU_CLK_CNTL, 2199 .mask = 0x3, 2200 .shift = 25, 2201 }, 2202 .hw.init = &(struct clk_init_data){ 2203 .name = "vpu_1_sel", 2204 .ops = &clk_regmap_mux_ops, 2205 .parent_hws = meson8b_vpu_parents, 2206 .num_parents = ARRAY_SIZE(meson8b_vpu_parents), 2207 .flags = CLK_SET_RATE_PARENT, 2208 }, 2209 }; 2210 2211 static struct clk_regmap meson8m2_vpu_1_sel = { 2212 .data = &(struct clk_regmap_mux_data){ 2213 .offset = HHI_VPU_CLK_CNTL, 2214 .mask = 0x3, 2215 .shift = 25, 2216 }, 2217 .hw.init = &(struct clk_init_data){ 2218 .name = "vpu_1_sel", 2219 .ops = &clk_regmap_mux_ops, 2220 .parent_hws = mmeson8m2_vpu_parents, 2221 .num_parents = ARRAY_SIZE(mmeson8m2_vpu_parents), 2222 .flags = CLK_SET_RATE_PARENT, 2223 }, 2224 }; 2225 2226 static struct clk_regmap meson8b_vpu_1_div = { 2227 .data = &(struct clk_regmap_div_data){ 2228 .offset = HHI_VPU_CLK_CNTL, 2229 .shift = 16, 2230 .width = 7, 2231 }, 2232 .hw.init = &(struct clk_init_data){ 2233 .name = "vpu_1_div", 2234 .ops = &clk_regmap_divider_ops, 2235 .parent_data = &(const struct clk_parent_data) { 2236 /* 2237 * Note: 2238 * meson8b and meson8m2 have different vpu_1_sels (with 2239 * different struct clk_hw). We fallback to the global 2240 * naming string mechanism so vpu_1_div picks up the 2241 * appropriate one. 2242 */ 2243 .name = "vpu_1_sel", 2244 .index = -1, 2245 }, 2246 .num_parents = 1, 2247 .flags = CLK_SET_RATE_PARENT, 2248 }, 2249 }; 2250 2251 static struct clk_regmap meson8b_vpu_1 = { 2252 .data = &(struct clk_regmap_gate_data){ 2253 .offset = HHI_VPU_CLK_CNTL, 2254 .bit_idx = 24, 2255 }, 2256 .hw.init = &(struct clk_init_data) { 2257 .name = "vpu_1", 2258 .ops = &clk_regmap_gate_ops, 2259 .parent_hws = (const struct clk_hw *[]) { 2260 &meson8b_vpu_1_div.hw 2261 }, 2262 .num_parents = 1, 2263 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, 2264 }, 2265 }; 2266 2267 /* 2268 * The VPU clock has two identical clock trees (vpu_0 and vpu_1) 2269 * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can 2270 * actually manage this glitch-free mux because it does top-to-bottom 2271 * updates the each clock tree and switches to the "inactive" one when 2272 * CLK_SET_RATE_GATE is set. 2273 * Meson8 only has vpu_0 and no glitch-free mux. 2274 */ 2275 static struct clk_regmap meson8b_vpu = { 2276 .data = &(struct clk_regmap_mux_data){ 2277 .offset = HHI_VPU_CLK_CNTL, 2278 .mask = 1, 2279 .shift = 31, 2280 }, 2281 .hw.init = &(struct clk_init_data){ 2282 .name = "vpu", 2283 .ops = &clk_regmap_mux_ops, 2284 .parent_hws = (const struct clk_hw *[]) { 2285 &meson8b_vpu_0.hw, 2286 &meson8b_vpu_1.hw, 2287 }, 2288 .num_parents = 2, 2289 .flags = CLK_SET_RATE_PARENT, 2290 }, 2291 }; 2292 2293 static const struct clk_hw *meson8b_vdec_parents[] = { 2294 &meson8b_fclk_div4.hw, 2295 &meson8b_fclk_div3.hw, 2296 &meson8b_fclk_div5.hw, 2297 &meson8b_fclk_div7.hw, 2298 &meson8b_mpll2.hw, 2299 &meson8b_mpll1.hw, 2300 }; 2301 2302 static struct clk_regmap meson8b_vdec_1_sel = { 2303 .data = &(struct clk_regmap_mux_data){ 2304 .offset = HHI_VDEC_CLK_CNTL, 2305 .mask = 0x3, 2306 .shift = 9, 2307 .flags = CLK_MUX_ROUND_CLOSEST, 2308 }, 2309 .hw.init = &(struct clk_init_data){ 2310 .name = "vdec_1_sel", 2311 .ops = &clk_regmap_mux_ops, 2312 .parent_hws = meson8b_vdec_parents, 2313 .num_parents = ARRAY_SIZE(meson8b_vdec_parents), 2314 .flags = CLK_SET_RATE_PARENT, 2315 }, 2316 }; 2317 2318 static struct clk_regmap meson8b_vdec_1_1_div = { 2319 .data = &(struct clk_regmap_div_data){ 2320 .offset = HHI_VDEC_CLK_CNTL, 2321 .shift = 0, 2322 .width = 7, 2323 .flags = CLK_DIVIDER_ROUND_CLOSEST, 2324 }, 2325 .hw.init = &(struct clk_init_data){ 2326 .name = "vdec_1_1_div", 2327 .ops = &clk_regmap_divider_ops, 2328 .parent_hws = (const struct clk_hw *[]) { 2329 &meson8b_vdec_1_sel.hw 2330 }, 2331 .num_parents = 1, 2332 .flags = CLK_SET_RATE_PARENT, 2333 }, 2334 }; 2335 2336 static struct clk_regmap meson8b_vdec_1_1 = { 2337 .data = &(struct clk_regmap_gate_data){ 2338 .offset = HHI_VDEC_CLK_CNTL, 2339 .bit_idx = 8, 2340 }, 2341 .hw.init = &(struct clk_init_data) { 2342 .name = "vdec_1_1", 2343 .ops = &clk_regmap_gate_ops, 2344 .parent_hws = (const struct clk_hw *[]) { 2345 &meson8b_vdec_1_1_div.hw 2346 }, 2347 .num_parents = 1, 2348 .flags = CLK_SET_RATE_PARENT, 2349 }, 2350 }; 2351 2352 static struct clk_regmap meson8b_vdec_1_2_div = { 2353 .data = &(struct clk_regmap_div_data){ 2354 .offset = HHI_VDEC3_CLK_CNTL, 2355 .shift = 0, 2356 .width = 7, 2357 .flags = CLK_DIVIDER_ROUND_CLOSEST, 2358 }, 2359 .hw.init = &(struct clk_init_data){ 2360 .name = "vdec_1_2_div", 2361 .ops = &clk_regmap_divider_ops, 2362 .parent_hws = (const struct clk_hw *[]) { 2363 &meson8b_vdec_1_sel.hw 2364 }, 2365 .num_parents = 1, 2366 .flags = CLK_SET_RATE_PARENT, 2367 }, 2368 }; 2369 2370 static struct clk_regmap meson8b_vdec_1_2 = { 2371 .data = &(struct clk_regmap_gate_data){ 2372 .offset = HHI_VDEC3_CLK_CNTL, 2373 .bit_idx = 8, 2374 }, 2375 .hw.init = &(struct clk_init_data) { 2376 .name = "vdec_1_2", 2377 .ops = &clk_regmap_gate_ops, 2378 .parent_hws = (const struct clk_hw *[]) { 2379 &meson8b_vdec_1_2_div.hw 2380 }, 2381 .num_parents = 1, 2382 .flags = CLK_SET_RATE_PARENT, 2383 }, 2384 }; 2385 2386 static struct clk_regmap meson8b_vdec_1 = { 2387 .data = &(struct clk_regmap_mux_data){ 2388 .offset = HHI_VDEC3_CLK_CNTL, 2389 .mask = 0x1, 2390 .shift = 15, 2391 .flags = CLK_MUX_ROUND_CLOSEST, 2392 }, 2393 .hw.init = &(struct clk_init_data){ 2394 .name = "vdec_1", 2395 .ops = &clk_regmap_mux_ops, 2396 .parent_hws = (const struct clk_hw *[]) { 2397 &meson8b_vdec_1_1.hw, 2398 &meson8b_vdec_1_2.hw, 2399 }, 2400 .num_parents = 2, 2401 .flags = CLK_SET_RATE_PARENT, 2402 }, 2403 }; 2404 2405 static struct clk_regmap meson8b_vdec_hcodec_sel = { 2406 .data = &(struct clk_regmap_mux_data){ 2407 .offset = HHI_VDEC_CLK_CNTL, 2408 .mask = 0x3, 2409 .shift = 25, 2410 .flags = CLK_MUX_ROUND_CLOSEST, 2411 }, 2412 .hw.init = &(struct clk_init_data){ 2413 .name = "vdec_hcodec_sel", 2414 .ops = &clk_regmap_mux_ops, 2415 .parent_hws = meson8b_vdec_parents, 2416 .num_parents = ARRAY_SIZE(meson8b_vdec_parents), 2417 .flags = CLK_SET_RATE_PARENT, 2418 }, 2419 }; 2420 2421 static struct clk_regmap meson8b_vdec_hcodec_div = { 2422 .data = &(struct clk_regmap_div_data){ 2423 .offset = HHI_VDEC_CLK_CNTL, 2424 .shift = 16, 2425 .width = 7, 2426 .flags = CLK_DIVIDER_ROUND_CLOSEST, 2427 }, 2428 .hw.init = &(struct clk_init_data){ 2429 .name = "vdec_hcodec_div", 2430 .ops = &clk_regmap_divider_ops, 2431 .parent_hws = (const struct clk_hw *[]) { 2432 &meson8b_vdec_hcodec_sel.hw 2433 }, 2434 .num_parents = 1, 2435 .flags = CLK_SET_RATE_PARENT, 2436 }, 2437 }; 2438 2439 static struct clk_regmap meson8b_vdec_hcodec = { 2440 .data = &(struct clk_regmap_gate_data){ 2441 .offset = HHI_VDEC_CLK_CNTL, 2442 .bit_idx = 24, 2443 }, 2444 .hw.init = &(struct clk_init_data) { 2445 .name = "vdec_hcodec", 2446 .ops = &clk_regmap_gate_ops, 2447 .parent_hws = (const struct clk_hw *[]) { 2448 &meson8b_vdec_hcodec_div.hw 2449 }, 2450 .num_parents = 1, 2451 .flags = CLK_SET_RATE_PARENT, 2452 }, 2453 }; 2454 2455 static struct clk_regmap meson8b_vdec_2_sel = { 2456 .data = &(struct clk_regmap_mux_data){ 2457 .offset = HHI_VDEC2_CLK_CNTL, 2458 .mask = 0x3, 2459 .shift = 9, 2460 .flags = CLK_MUX_ROUND_CLOSEST, 2461 }, 2462 .hw.init = &(struct clk_init_data){ 2463 .name = "vdec_2_sel", 2464 .ops = &clk_regmap_mux_ops, 2465 .parent_hws = meson8b_vdec_parents, 2466 .num_parents = ARRAY_SIZE(meson8b_vdec_parents), 2467 .flags = CLK_SET_RATE_PARENT, 2468 }, 2469 }; 2470 2471 static struct clk_regmap meson8b_vdec_2_div = { 2472 .data = &(struct clk_regmap_div_data){ 2473 .offset = HHI_VDEC2_CLK_CNTL, 2474 .shift = 0, 2475 .width = 7, 2476 .flags = CLK_DIVIDER_ROUND_CLOSEST, 2477 }, 2478 .hw.init = &(struct clk_init_data){ 2479 .name = "vdec_2_div", 2480 .ops = &clk_regmap_divider_ops, 2481 .parent_hws = (const struct clk_hw *[]) { 2482 &meson8b_vdec_2_sel.hw 2483 }, 2484 .num_parents = 1, 2485 .flags = CLK_SET_RATE_PARENT, 2486 }, 2487 }; 2488 2489 static struct clk_regmap meson8b_vdec_2 = { 2490 .data = &(struct clk_regmap_gate_data){ 2491 .offset = HHI_VDEC2_CLK_CNTL, 2492 .bit_idx = 8, 2493 }, 2494 .hw.init = &(struct clk_init_data) { 2495 .name = "vdec_2", 2496 .ops = &clk_regmap_gate_ops, 2497 .parent_hws = (const struct clk_hw *[]) { 2498 &meson8b_vdec_2_div.hw 2499 }, 2500 .num_parents = 1, 2501 .flags = CLK_SET_RATE_PARENT, 2502 }, 2503 }; 2504 2505 static struct clk_regmap meson8b_vdec_hevc_sel = { 2506 .data = &(struct clk_regmap_mux_data){ 2507 .offset = HHI_VDEC2_CLK_CNTL, 2508 .mask = 0x3, 2509 .shift = 25, 2510 .flags = CLK_MUX_ROUND_CLOSEST, 2511 }, 2512 .hw.init = &(struct clk_init_data){ 2513 .name = "vdec_hevc_sel", 2514 .ops = &clk_regmap_mux_ops, 2515 .parent_hws = meson8b_vdec_parents, 2516 .num_parents = ARRAY_SIZE(meson8b_vdec_parents), 2517 .flags = CLK_SET_RATE_PARENT, 2518 }, 2519 }; 2520 2521 static struct clk_regmap meson8b_vdec_hevc_div = { 2522 .data = &(struct clk_regmap_div_data){ 2523 .offset = HHI_VDEC2_CLK_CNTL, 2524 .shift = 16, 2525 .width = 7, 2526 .flags = CLK_DIVIDER_ROUND_CLOSEST, 2527 }, 2528 .hw.init = &(struct clk_init_data){ 2529 .name = "vdec_hevc_div", 2530 .ops = &clk_regmap_divider_ops, 2531 .parent_hws = (const struct clk_hw *[]) { 2532 &meson8b_vdec_hevc_sel.hw 2533 }, 2534 .num_parents = 1, 2535 .flags = CLK_SET_RATE_PARENT, 2536 }, 2537 }; 2538 2539 static struct clk_regmap meson8b_vdec_hevc_en = { 2540 .data = &(struct clk_regmap_gate_data){ 2541 .offset = HHI_VDEC2_CLK_CNTL, 2542 .bit_idx = 24, 2543 }, 2544 .hw.init = &(struct clk_init_data) { 2545 .name = "vdec_hevc_en", 2546 .ops = &clk_regmap_gate_ops, 2547 .parent_hws = (const struct clk_hw *[]) { 2548 &meson8b_vdec_hevc_div.hw 2549 }, 2550 .num_parents = 1, 2551 .flags = CLK_SET_RATE_PARENT, 2552 }, 2553 }; 2554 2555 static struct clk_regmap meson8b_vdec_hevc = { 2556 .data = &(struct clk_regmap_mux_data){ 2557 .offset = HHI_VDEC2_CLK_CNTL, 2558 .mask = 0x1, 2559 .shift = 31, 2560 .flags = CLK_MUX_ROUND_CLOSEST, 2561 }, 2562 .hw.init = &(struct clk_init_data){ 2563 .name = "vdec_hevc", 2564 .ops = &clk_regmap_mux_ops, 2565 /* TODO: The second parent is currently unknown */ 2566 .parent_hws = (const struct clk_hw *[]) { 2567 &meson8b_vdec_hevc_en.hw 2568 }, 2569 .num_parents = 1, 2570 .flags = CLK_SET_RATE_PARENT, 2571 }, 2572 }; 2573 2574 /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */ 2575 static u32 meson8b_cts_mclk_parents_val_table[] = { 1, 2, 3 }; 2576 static const struct clk_hw *meson8b_cts_mclk_parents[] = { 2577 &meson8b_mpll0.hw, 2578 &meson8b_mpll1.hw, 2579 &meson8b_mpll2.hw 2580 }; 2581 2582 static struct clk_regmap meson8b_cts_amclk_sel = { 2583 .data = &(struct clk_regmap_mux_data){ 2584 .offset = HHI_AUD_CLK_CNTL, 2585 .mask = 0x3, 2586 .shift = 9, 2587 .table = meson8b_cts_mclk_parents_val_table, 2588 .flags = CLK_MUX_ROUND_CLOSEST, 2589 }, 2590 .hw.init = &(struct clk_init_data){ 2591 .name = "cts_amclk_sel", 2592 .ops = &clk_regmap_mux_ops, 2593 .parent_hws = meson8b_cts_mclk_parents, 2594 .num_parents = ARRAY_SIZE(meson8b_cts_mclk_parents), 2595 }, 2596 }; 2597 2598 static struct clk_regmap meson8b_cts_amclk_div = { 2599 .data = &(struct clk_regmap_div_data) { 2600 .offset = HHI_AUD_CLK_CNTL, 2601 .shift = 0, 2602 .width = 8, 2603 .flags = CLK_DIVIDER_ROUND_CLOSEST, 2604 }, 2605 .hw.init = &(struct clk_init_data){ 2606 .name = "cts_amclk_div", 2607 .ops = &clk_regmap_divider_ops, 2608 .parent_hws = (const struct clk_hw *[]) { 2609 &meson8b_cts_amclk_sel.hw 2610 }, 2611 .num_parents = 1, 2612 .flags = CLK_SET_RATE_PARENT, 2613 }, 2614 }; 2615 2616 static struct clk_regmap meson8b_cts_amclk = { 2617 .data = &(struct clk_regmap_gate_data){ 2618 .offset = HHI_AUD_CLK_CNTL, 2619 .bit_idx = 8, 2620 }, 2621 .hw.init = &(struct clk_init_data){ 2622 .name = "cts_amclk", 2623 .ops = &clk_regmap_gate_ops, 2624 .parent_hws = (const struct clk_hw *[]) { 2625 &meson8b_cts_amclk_div.hw 2626 }, 2627 .num_parents = 1, 2628 .flags = CLK_SET_RATE_PARENT, 2629 }, 2630 }; 2631 2632 static struct clk_regmap meson8b_cts_mclk_i958_sel = { 2633 .data = &(struct clk_regmap_mux_data){ 2634 .offset = HHI_AUD_CLK_CNTL2, 2635 .mask = 0x3, 2636 .shift = 25, 2637 .table = meson8b_cts_mclk_parents_val_table, 2638 .flags = CLK_MUX_ROUND_CLOSEST, 2639 }, 2640 .hw.init = &(struct clk_init_data) { 2641 .name = "cts_mclk_i958_sel", 2642 .ops = &clk_regmap_mux_ops, 2643 .parent_hws = meson8b_cts_mclk_parents, 2644 .num_parents = ARRAY_SIZE(meson8b_cts_mclk_parents), 2645 }, 2646 }; 2647 2648 static struct clk_regmap meson8b_cts_mclk_i958_div = { 2649 .data = &(struct clk_regmap_div_data){ 2650 .offset = HHI_AUD_CLK_CNTL2, 2651 .shift = 16, 2652 .width = 8, 2653 .flags = CLK_DIVIDER_ROUND_CLOSEST, 2654 }, 2655 .hw.init = &(struct clk_init_data) { 2656 .name = "cts_mclk_i958_div", 2657 .ops = &clk_regmap_divider_ops, 2658 .parent_hws = (const struct clk_hw *[]) { 2659 &meson8b_cts_mclk_i958_sel.hw 2660 }, 2661 .num_parents = 1, 2662 .flags = CLK_SET_RATE_PARENT, 2663 }, 2664 }; 2665 2666 static struct clk_regmap meson8b_cts_mclk_i958 = { 2667 .data = &(struct clk_regmap_gate_data){ 2668 .offset = HHI_AUD_CLK_CNTL2, 2669 .bit_idx = 24, 2670 }, 2671 .hw.init = &(struct clk_init_data){ 2672 .name = "cts_mclk_i958", 2673 .ops = &clk_regmap_gate_ops, 2674 .parent_hws = (const struct clk_hw *[]) { 2675 &meson8b_cts_mclk_i958_div.hw 2676 }, 2677 .num_parents = 1, 2678 .flags = CLK_SET_RATE_PARENT, 2679 }, 2680 }; 2681 2682 static struct clk_regmap meson8b_cts_i958 = { 2683 .data = &(struct clk_regmap_mux_data){ 2684 .offset = HHI_AUD_CLK_CNTL2, 2685 .mask = 0x1, 2686 .shift = 27, 2687 }, 2688 .hw.init = &(struct clk_init_data){ 2689 .name = "cts_i958", 2690 .ops = &clk_regmap_mux_ops, 2691 .parent_hws = (const struct clk_hw *[]) { 2692 &meson8b_cts_amclk.hw, 2693 &meson8b_cts_mclk_i958.hw 2694 }, 2695 .num_parents = 2, 2696 /* 2697 * The parent is specific to origin of the audio data. Let the 2698 * consumer choose the appropriate parent. 2699 */ 2700 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2701 }, 2702 }; 2703 2704 static const struct clk_parent_data meson8b_pclk_parents = { .hw = &meson8b_clk81.hw }; 2705 2706 #define MESON8B_PCLK(_name, _reg, _bit, _flags) \ 2707 MESON_PCLK(_name, _reg, _bit, &meson8b_pclk_parents, _flags) 2708 2709 /* 2710 * Everything Else (EE) domain gates 2711 * 2712 * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons 2713 * Users are encouraged to test without it and submit changes to: 2714 * - remove the flag if not necessary 2715 * - replace the flag with something more adequate, such as CLK_IS_CRITICAL, 2716 * if appropriate. 2717 * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirable 2718 * for a particular clock. 2719 */ 2720 static MESON8B_PCLK(meson8b_ddr, HHI_GCLK_MPEG0, 0, CLK_IGNORE_UNUSED); 2721 static MESON8B_PCLK(meson8b_dos, HHI_GCLK_MPEG0, 1, CLK_IGNORE_UNUSED); 2722 static MESON8B_PCLK(meson8b_isa, HHI_GCLK_MPEG0, 5, CLK_IGNORE_UNUSED); 2723 static MESON8B_PCLK(meson8b_pl301, HHI_GCLK_MPEG0, 6, CLK_IGNORE_UNUSED); 2724 static MESON8B_PCLK(meson8b_periphs, HHI_GCLK_MPEG0, 7, CLK_IGNORE_UNUSED); 2725 static MESON8B_PCLK(meson8b_spicc, HHI_GCLK_MPEG0, 8, CLK_IGNORE_UNUSED); 2726 static MESON8B_PCLK(meson8b_i2c, HHI_GCLK_MPEG0, 9, CLK_IGNORE_UNUSED); 2727 static MESON8B_PCLK(meson8b_sar_adc, HHI_GCLK_MPEG0, 10, CLK_IGNORE_UNUSED); 2728 static MESON8B_PCLK(meson8b_smart_card, HHI_GCLK_MPEG0, 11, CLK_IGNORE_UNUSED); 2729 static MESON8B_PCLK(meson8b_rng0, HHI_GCLK_MPEG0, 12, CLK_IGNORE_UNUSED); 2730 static MESON8B_PCLK(meson8b_uart0, HHI_GCLK_MPEG0, 13, CLK_IGNORE_UNUSED); 2731 static MESON8B_PCLK(meson8b_sdhc, HHI_GCLK_MPEG0, 14, CLK_IGNORE_UNUSED); 2732 static MESON8B_PCLK(meson8b_stream, HHI_GCLK_MPEG0, 15, CLK_IGNORE_UNUSED); 2733 static MESON8B_PCLK(meson8b_async_fifo, HHI_GCLK_MPEG0, 16, CLK_IGNORE_UNUSED); 2734 static MESON8B_PCLK(meson8b_sdio, HHI_GCLK_MPEG0, 17, CLK_IGNORE_UNUSED); 2735 static MESON8B_PCLK(meson8b_abuf, HHI_GCLK_MPEG0, 18, CLK_IGNORE_UNUSED); 2736 static MESON8B_PCLK(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19, CLK_IGNORE_UNUSED); 2737 static MESON8B_PCLK(meson8b_assist_misc, HHI_GCLK_MPEG0, 23, CLK_IGNORE_UNUSED); 2738 static MESON8B_PCLK(meson8b_spi, HHI_GCLK_MPEG0, 30, CLK_IGNORE_UNUSED); 2739 2740 static MESON8B_PCLK(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2, CLK_IGNORE_UNUSED); 2741 static MESON8B_PCLK(meson8b_eth, HHI_GCLK_MPEG1, 3, CLK_IGNORE_UNUSED); 2742 static MESON8B_PCLK(meson8b_demux, HHI_GCLK_MPEG1, 4, CLK_IGNORE_UNUSED); 2743 static MESON8B_PCLK(meson8b_blkmv, HHI_GCLK_MPEG1, 14, CLK_IGNORE_UNUSED); 2744 static MESON8B_PCLK(meson8b_aiu, HHI_GCLK_MPEG1, 15, CLK_IGNORE_UNUSED); 2745 static MESON8B_PCLK(meson8b_uart1, HHI_GCLK_MPEG1, 16, CLK_IGNORE_UNUSED); 2746 static MESON8B_PCLK(meson8b_g2d, HHI_GCLK_MPEG1, 20, CLK_IGNORE_UNUSED); 2747 static MESON8B_PCLK(meson8b_usb0, HHI_GCLK_MPEG1, 21, CLK_IGNORE_UNUSED); 2748 static MESON8B_PCLK(meson8b_usb1, HHI_GCLK_MPEG1, 22, CLK_IGNORE_UNUSED); 2749 static MESON8B_PCLK(meson8b_reset, HHI_GCLK_MPEG1, 23, CLK_IGNORE_UNUSED); 2750 static MESON8B_PCLK(meson8b_nand, HHI_GCLK_MPEG1, 24, CLK_IGNORE_UNUSED); 2751 static MESON8B_PCLK(meson8b_dos_parser, HHI_GCLK_MPEG1, 25, CLK_IGNORE_UNUSED); 2752 static MESON8B_PCLK(meson8b_usb, HHI_GCLK_MPEG1, 26, CLK_IGNORE_UNUSED); 2753 static MESON8B_PCLK(meson8b_vdin1, HHI_GCLK_MPEG1, 28, CLK_IGNORE_UNUSED); 2754 static MESON8B_PCLK(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29, CLK_IGNORE_UNUSED); 2755 static MESON8B_PCLK(meson8b_efuse, HHI_GCLK_MPEG1, 30, CLK_IGNORE_UNUSED); 2756 static MESON8B_PCLK(meson8b_boot_rom, HHI_GCLK_MPEG1, 31, CLK_IGNORE_UNUSED); 2757 2758 static MESON8B_PCLK(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1, CLK_IGNORE_UNUSED); 2759 static MESON8B_PCLK(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2, CLK_IGNORE_UNUSED); 2760 static MESON8B_PCLK(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3, CLK_IGNORE_UNUSED); 2761 static MESON8B_PCLK(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4, CLK_IGNORE_UNUSED); 2762 static MESON8B_PCLK(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8, CLK_IGNORE_UNUSED); 2763 static MESON8B_PCLK(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9, CLK_IGNORE_UNUSED); 2764 static MESON8B_PCLK(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11, CLK_IGNORE_UNUSED); 2765 static MESON8B_PCLK(meson8b_dvin, HHI_GCLK_MPEG2, 12, CLK_IGNORE_UNUSED); 2766 static MESON8B_PCLK(meson8b_uart2, HHI_GCLK_MPEG2, 15, CLK_IGNORE_UNUSED); 2767 static MESON8B_PCLK(meson8b_sana, HHI_GCLK_MPEG2, 22, CLK_IGNORE_UNUSED); 2768 static MESON8B_PCLK(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25, CLK_IGNORE_UNUSED); 2769 static MESON8B_PCLK(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26, CLK_IGNORE_UNUSED); 2770 static MESON8B_PCLK(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29, CLK_IGNORE_UNUSED); 2771 2772 static MESON8B_PCLK(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1, CLK_IGNORE_UNUSED); 2773 static MESON8B_PCLK(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2, CLK_IGNORE_UNUSED); 2774 static MESON8B_PCLK(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3, CLK_IGNORE_UNUSED); 2775 static MESON8B_PCLK(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4, CLK_IGNORE_UNUSED); 2776 static MESON8B_PCLK(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8, CLK_IGNORE_UNUSED); 2777 static MESON8B_PCLK(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9, CLK_IGNORE_UNUSED); 2778 static MESON8B_PCLK(meson8b_dac_clk, HHI_GCLK_OTHER, 10, CLK_IGNORE_UNUSED); 2779 static MESON8B_PCLK(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14, CLK_IGNORE_UNUSED); 2780 static MESON8B_PCLK(meson8b_iec958_gate, HHI_GCLK_OTHER, 16, CLK_IGNORE_UNUSED); 2781 static MESON8B_PCLK(meson8b_enc480p, HHI_GCLK_OTHER, 20, CLK_IGNORE_UNUSED); 2782 static MESON8B_PCLK(meson8b_rng1, HHI_GCLK_OTHER, 21, CLK_IGNORE_UNUSED); 2783 static MESON8B_PCLK(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22, CLK_IGNORE_UNUSED); 2784 static MESON8B_PCLK(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24, CLK_IGNORE_UNUSED); 2785 static MESON8B_PCLK(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25, CLK_IGNORE_UNUSED); 2786 static MESON8B_PCLK(meson8b_vclk2_other, HHI_GCLK_OTHER, 26, CLK_IGNORE_UNUSED); 2787 static MESON8B_PCLK(meson8b_edp, HHI_GCLK_OTHER, 31, CLK_IGNORE_UNUSED); 2788 2789 /* AIU gates */ 2790 static const struct clk_parent_data meson8b_aiu_glue_parents = { .hw = &meson8b_aiu.hw }; 2791 static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, 2792 &meson8b_aiu_glue_parents, CLK_IGNORE_UNUSED); 2793 2794 static const struct clk_parent_data meson8b_aiu_pclk_parents = { .hw = &meson8b_aiu_glue.hw }; 2795 #define MESON8B_AIU_PCLK(_name, _bit, _flags) \ 2796 MESON_PCLK(_name, HHI_GCLK_MPEG1, _bit, &meson8b_aiu_pclk_parents, _flags) 2797 2798 static MESON8B_AIU_PCLK(meson8b_iec958, 7, CLK_IGNORE_UNUSED); 2799 static MESON8B_AIU_PCLK(meson8b_i2s_out, 8, CLK_IGNORE_UNUSED); 2800 static MESON8B_AIU_PCLK(meson8b_amclk, 9, CLK_IGNORE_UNUSED); 2801 static MESON8B_AIU_PCLK(meson8b_aififo2, 10, CLK_IGNORE_UNUSED); 2802 static MESON8B_AIU_PCLK(meson8b_mixer, 11, CLK_IGNORE_UNUSED); 2803 static MESON8B_AIU_PCLK(meson8b_mixer_iface, 12, CLK_IGNORE_UNUSED); 2804 static MESON8B_AIU_PCLK(meson8b_adc, 13, CLK_IGNORE_UNUSED); 2805 2806 /* Always On (AO) domain gates */ 2807 2808 static MESON8B_PCLK(meson8b_ao_media_cpu, HHI_GCLK_AO, 0, CLK_IGNORE_UNUSED); 2809 static MESON8B_PCLK(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1, CLK_IGNORE_UNUSED); 2810 static MESON8B_PCLK(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2, CLK_IGNORE_UNUSED); 2811 static MESON8B_PCLK(meson8b_ao_iface, HHI_GCLK_AO, 3, CLK_IGNORE_UNUSED); 2812 2813 static struct clk_hw *meson8_hw_clks[] = { 2814 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw, 2815 [CLKID_PLL_VID] = &meson8b_vid_pll.hw, 2816 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw, 2817 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw, 2818 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw, 2819 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw, 2820 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw, 2821 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw, 2822 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw, 2823 [CLKID_MPEG_SEL] = &meson8b_clk81_sel.hw, 2824 [CLKID_MPEG_DIV] = &meson8b_clk81_div.hw, 2825 [CLKID_CLK81] = &meson8b_clk81.hw, 2826 [CLKID_DDR] = &meson8b_ddr.hw, 2827 [CLKID_DOS] = &meson8b_dos.hw, 2828 [CLKID_ISA] = &meson8b_isa.hw, 2829 [CLKID_PL301] = &meson8b_pl301.hw, 2830 [CLKID_PERIPHS] = &meson8b_periphs.hw, 2831 [CLKID_SPICC] = &meson8b_spicc.hw, 2832 [CLKID_I2C] = &meson8b_i2c.hw, 2833 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw, 2834 [CLKID_SMART_CARD] = &meson8b_smart_card.hw, 2835 [CLKID_RNG0] = &meson8b_rng0.hw, 2836 [CLKID_UART0] = &meson8b_uart0.hw, 2837 [CLKID_SDHC] = &meson8b_sdhc.hw, 2838 [CLKID_STREAM] = &meson8b_stream.hw, 2839 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw, 2840 [CLKID_SDIO] = &meson8b_sdio.hw, 2841 [CLKID_ABUF] = &meson8b_abuf.hw, 2842 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw, 2843 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw, 2844 [CLKID_SPI] = &meson8b_spi.hw, 2845 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw, 2846 [CLKID_ETH] = &meson8b_eth.hw, 2847 [CLKID_DEMUX] = &meson8b_demux.hw, 2848 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw, 2849 [CLKID_IEC958] = &meson8b_iec958.hw, 2850 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw, 2851 [CLKID_AMCLK] = &meson8b_amclk.hw, 2852 [CLKID_AIFIFO2] = &meson8b_aififo2.hw, 2853 [CLKID_MIXER] = &meson8b_mixer.hw, 2854 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw, 2855 [CLKID_ADC] = &meson8b_adc.hw, 2856 [CLKID_BLKMV] = &meson8b_blkmv.hw, 2857 [CLKID_AIU] = &meson8b_aiu.hw, 2858 [CLKID_UART1] = &meson8b_uart1.hw, 2859 [CLKID_G2D] = &meson8b_g2d.hw, 2860 [CLKID_USB0] = &meson8b_usb0.hw, 2861 [CLKID_USB1] = &meson8b_usb1.hw, 2862 [CLKID_RESET] = &meson8b_reset.hw, 2863 [CLKID_NAND] = &meson8b_nand.hw, 2864 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw, 2865 [CLKID_USB] = &meson8b_usb.hw, 2866 [CLKID_VDIN1] = &meson8b_vdin1.hw, 2867 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw, 2868 [CLKID_EFUSE] = &meson8b_efuse.hw, 2869 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw, 2870 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw, 2871 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw, 2872 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw, 2873 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw, 2874 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw, 2875 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw, 2876 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw, 2877 [CLKID_DVIN] = &meson8b_dvin.hw, 2878 [CLKID_UART2] = &meson8b_uart2.hw, 2879 [CLKID_SANA] = &meson8b_sana.hw, 2880 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw, 2881 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw, 2882 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw, 2883 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw, 2884 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw, 2885 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw, 2886 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw, 2887 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw, 2888 [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw, 2889 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw, 2890 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw, 2891 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw, 2892 [CLKID_ENC480P] = &meson8b_enc480p.hw, 2893 [CLKID_RNG1] = &meson8b_rng1.hw, 2894 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw, 2895 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw, 2896 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw, 2897 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw, 2898 [CLKID_EDP] = &meson8b_edp.hw, 2899 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw, 2900 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw, 2901 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw, 2902 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw, 2903 [CLKID_MPLL0] = &meson8b_mpll0.hw, 2904 [CLKID_MPLL1] = &meson8b_mpll1.hw, 2905 [CLKID_MPLL2] = &meson8b_mpll2.hw, 2906 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw, 2907 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw, 2908 [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw, 2909 [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw, 2910 [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw, 2911 [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw, 2912 [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw, 2913 [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw, 2914 [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw, 2915 [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw, 2916 [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw, 2917 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw, 2918 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw, 2919 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw, 2920 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw, 2921 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw, 2922 [CLKID_NAND_CLK] = &meson8b_nand_clk.hw, 2923 [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw, 2924 [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw, 2925 [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw, 2926 [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw, 2927 [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw, 2928 [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw, 2929 [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw, 2930 [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw, 2931 [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw, 2932 [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw, 2933 [CLKID_APB_SEL] = &meson8b_apb_sel.hw, 2934 [CLKID_APB] = &meson8b_apb.hw, 2935 [CLKID_PERIPH_SEL] = &meson8b_periph_sel.hw, 2936 [CLKID_PERIPH] = &meson8b_periph.hw, 2937 [CLKID_AXI_SEL] = &meson8b_axi_sel.hw, 2938 [CLKID_AXI] = &meson8b_axi.hw, 2939 [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_sel.hw, 2940 [CLKID_L2_DRAM] = &meson8b_l2_dram.hw, 2941 [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw, 2942 [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw, 2943 [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw, 2944 [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw, 2945 [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw, 2946 [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw, 2947 [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw, 2948 [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw, 2949 [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw, 2950 [CLKID_VCLK_EN] = &meson8b_vclk_en.hw, 2951 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1.hw, 2952 [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw, 2953 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2.hw, 2954 [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw, 2955 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4.hw, 2956 [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw, 2957 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6.hw, 2958 [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw, 2959 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12.hw, 2960 [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw, 2961 [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_in_en.hw, 2962 [CLKID_VCLK2_EN] = &meson8b_vclk2_en.hw, 2963 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1.hw, 2964 [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw, 2965 [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2.hw, 2966 [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw, 2967 [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4.hw, 2968 [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw, 2969 [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6.hw, 2970 [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw, 2971 [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12.hw, 2972 [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw, 2973 [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw, 2974 [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw, 2975 [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw, 2976 [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw, 2977 [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw, 2978 [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw, 2979 [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw, 2980 [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw, 2981 [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw, 2982 [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw, 2983 [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw, 2984 [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw, 2985 [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw, 2986 [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw, 2987 [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw, 2988 [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw, 2989 [CLKID_MALI] = &meson8b_mali_0.hw, 2990 [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw, 2991 [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw, 2992 [CLKID_VPU] = &meson8b_vpu_0.hw, 2993 [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw, 2994 [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw, 2995 [CLKID_VDEC_1] = &meson8b_vdec_1_1.hw, 2996 [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw, 2997 [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw, 2998 [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw, 2999 [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw, 3000 [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw, 3001 [CLKID_VDEC_2] = &meson8b_vdec_2.hw, 3002 [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw, 3003 [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw, 3004 [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw, 3005 [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw, 3006 [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw, 3007 [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw, 3008 [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw, 3009 [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw, 3010 [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw, 3011 [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw, 3012 [CLKID_CTS_I958] = &meson8b_cts_i958.hw, 3013 [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, 3014 [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw, 3015 }; 3016 3017 static struct clk_hw *meson8b_hw_clks[] = { 3018 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw, 3019 [CLKID_PLL_VID] = &meson8b_vid_pll.hw, 3020 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw, 3021 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw, 3022 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw, 3023 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw, 3024 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw, 3025 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw, 3026 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw, 3027 [CLKID_MPEG_SEL] = &meson8b_clk81_sel.hw, 3028 [CLKID_MPEG_DIV] = &meson8b_clk81_div.hw, 3029 [CLKID_CLK81] = &meson8b_clk81.hw, 3030 [CLKID_DDR] = &meson8b_ddr.hw, 3031 [CLKID_DOS] = &meson8b_dos.hw, 3032 [CLKID_ISA] = &meson8b_isa.hw, 3033 [CLKID_PL301] = &meson8b_pl301.hw, 3034 [CLKID_PERIPHS] = &meson8b_periphs.hw, 3035 [CLKID_SPICC] = &meson8b_spicc.hw, 3036 [CLKID_I2C] = &meson8b_i2c.hw, 3037 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw, 3038 [CLKID_SMART_CARD] = &meson8b_smart_card.hw, 3039 [CLKID_RNG0] = &meson8b_rng0.hw, 3040 [CLKID_UART0] = &meson8b_uart0.hw, 3041 [CLKID_SDHC] = &meson8b_sdhc.hw, 3042 [CLKID_STREAM] = &meson8b_stream.hw, 3043 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw, 3044 [CLKID_SDIO] = &meson8b_sdio.hw, 3045 [CLKID_ABUF] = &meson8b_abuf.hw, 3046 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw, 3047 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw, 3048 [CLKID_SPI] = &meson8b_spi.hw, 3049 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw, 3050 [CLKID_ETH] = &meson8b_eth.hw, 3051 [CLKID_DEMUX] = &meson8b_demux.hw, 3052 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw, 3053 [CLKID_IEC958] = &meson8b_iec958.hw, 3054 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw, 3055 [CLKID_AMCLK] = &meson8b_amclk.hw, 3056 [CLKID_AIFIFO2] = &meson8b_aififo2.hw, 3057 [CLKID_MIXER] = &meson8b_mixer.hw, 3058 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw, 3059 [CLKID_ADC] = &meson8b_adc.hw, 3060 [CLKID_BLKMV] = &meson8b_blkmv.hw, 3061 [CLKID_AIU] = &meson8b_aiu.hw, 3062 [CLKID_UART1] = &meson8b_uart1.hw, 3063 [CLKID_G2D] = &meson8b_g2d.hw, 3064 [CLKID_USB0] = &meson8b_usb0.hw, 3065 [CLKID_USB1] = &meson8b_usb1.hw, 3066 [CLKID_RESET] = &meson8b_reset.hw, 3067 [CLKID_NAND] = &meson8b_nand.hw, 3068 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw, 3069 [CLKID_USB] = &meson8b_usb.hw, 3070 [CLKID_VDIN1] = &meson8b_vdin1.hw, 3071 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw, 3072 [CLKID_EFUSE] = &meson8b_efuse.hw, 3073 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw, 3074 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw, 3075 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw, 3076 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw, 3077 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw, 3078 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw, 3079 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw, 3080 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw, 3081 [CLKID_DVIN] = &meson8b_dvin.hw, 3082 [CLKID_UART2] = &meson8b_uart2.hw, 3083 [CLKID_SANA] = &meson8b_sana.hw, 3084 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw, 3085 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw, 3086 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw, 3087 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw, 3088 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw, 3089 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw, 3090 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw, 3091 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw, 3092 [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw, 3093 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw, 3094 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw, 3095 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw, 3096 [CLKID_ENC480P] = &meson8b_enc480p.hw, 3097 [CLKID_RNG1] = &meson8b_rng1.hw, 3098 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw, 3099 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw, 3100 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw, 3101 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw, 3102 [CLKID_EDP] = &meson8b_edp.hw, 3103 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw, 3104 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw, 3105 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw, 3106 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw, 3107 [CLKID_MPLL0] = &meson8b_mpll0.hw, 3108 [CLKID_MPLL1] = &meson8b_mpll1.hw, 3109 [CLKID_MPLL2] = &meson8b_mpll2.hw, 3110 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw, 3111 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw, 3112 [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw, 3113 [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw, 3114 [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw, 3115 [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw, 3116 [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw, 3117 [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw, 3118 [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw, 3119 [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw, 3120 [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw, 3121 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw, 3122 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw, 3123 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw, 3124 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw, 3125 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw, 3126 [CLKID_NAND_CLK] = &meson8b_nand_clk.hw, 3127 [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw, 3128 [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw, 3129 [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw, 3130 [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw, 3131 [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw, 3132 [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw, 3133 [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw, 3134 [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw, 3135 [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw, 3136 [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw, 3137 [CLKID_APB_SEL] = &meson8b_apb_sel.hw, 3138 [CLKID_APB] = &meson8b_apb.hw, 3139 [CLKID_PERIPH_SEL] = &meson8b_periph_sel.hw, 3140 [CLKID_PERIPH] = &meson8b_periph.hw, 3141 [CLKID_AXI_SEL] = &meson8b_axi_sel.hw, 3142 [CLKID_AXI] = &meson8b_axi.hw, 3143 [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_sel.hw, 3144 [CLKID_L2_DRAM] = &meson8b_l2_dram.hw, 3145 [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw, 3146 [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw, 3147 [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw, 3148 [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw, 3149 [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw, 3150 [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw, 3151 [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw, 3152 [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw, 3153 [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw, 3154 [CLKID_VCLK_EN] = &meson8b_vclk_en.hw, 3155 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1.hw, 3156 [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw, 3157 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2.hw, 3158 [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw, 3159 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4.hw, 3160 [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw, 3161 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6.hw, 3162 [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw, 3163 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12.hw, 3164 [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw, 3165 [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_in_en.hw, 3166 [CLKID_VCLK2_EN] = &meson8b_vclk2_en.hw, 3167 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1.hw, 3168 [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw, 3169 [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2.hw, 3170 [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw, 3171 [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4.hw, 3172 [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw, 3173 [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6.hw, 3174 [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw, 3175 [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12.hw, 3176 [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw, 3177 [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw, 3178 [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw, 3179 [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw, 3180 [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw, 3181 [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw, 3182 [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw, 3183 [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw, 3184 [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw, 3185 [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw, 3186 [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw, 3187 [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw, 3188 [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw, 3189 [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw, 3190 [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw, 3191 [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw, 3192 [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw, 3193 [CLKID_MALI_0] = &meson8b_mali_0.hw, 3194 [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw, 3195 [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw, 3196 [CLKID_MALI_1] = &meson8b_mali_1.hw, 3197 [CLKID_MALI] = &meson8b_mali.hw, 3198 [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw, 3199 [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw, 3200 [CLKID_VPU_0] = &meson8b_vpu_0.hw, 3201 [CLKID_VPU_1_SEL] = &meson8b_vpu_1_sel.hw, 3202 [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw, 3203 [CLKID_VPU_1] = &meson8b_vpu_1.hw, 3204 [CLKID_VPU] = &meson8b_vpu.hw, 3205 [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw, 3206 [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw, 3207 [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw, 3208 [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw, 3209 [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw, 3210 [CLKID_VDEC_1] = &meson8b_vdec_1.hw, 3211 [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw, 3212 [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw, 3213 [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw, 3214 [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw, 3215 [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw, 3216 [CLKID_VDEC_2] = &meson8b_vdec_2.hw, 3217 [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw, 3218 [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw, 3219 [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw, 3220 [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw, 3221 [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw, 3222 [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw, 3223 [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw, 3224 [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw, 3225 [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw, 3226 [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw, 3227 [CLKID_CTS_I958] = &meson8b_cts_i958.hw, 3228 [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, 3229 [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw, 3230 }; 3231 3232 static struct clk_hw *meson8m2_hw_clks[] = { 3233 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw, 3234 [CLKID_PLL_VID] = &meson8b_vid_pll.hw, 3235 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw, 3236 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw, 3237 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw, 3238 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw, 3239 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw, 3240 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw, 3241 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw, 3242 [CLKID_MPEG_SEL] = &meson8b_clk81_sel.hw, 3243 [CLKID_MPEG_DIV] = &meson8b_clk81_div.hw, 3244 [CLKID_CLK81] = &meson8b_clk81.hw, 3245 [CLKID_DDR] = &meson8b_ddr.hw, 3246 [CLKID_DOS] = &meson8b_dos.hw, 3247 [CLKID_ISA] = &meson8b_isa.hw, 3248 [CLKID_PL301] = &meson8b_pl301.hw, 3249 [CLKID_PERIPHS] = &meson8b_periphs.hw, 3250 [CLKID_SPICC] = &meson8b_spicc.hw, 3251 [CLKID_I2C] = &meson8b_i2c.hw, 3252 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw, 3253 [CLKID_SMART_CARD] = &meson8b_smart_card.hw, 3254 [CLKID_RNG0] = &meson8b_rng0.hw, 3255 [CLKID_UART0] = &meson8b_uart0.hw, 3256 [CLKID_SDHC] = &meson8b_sdhc.hw, 3257 [CLKID_STREAM] = &meson8b_stream.hw, 3258 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw, 3259 [CLKID_SDIO] = &meson8b_sdio.hw, 3260 [CLKID_ABUF] = &meson8b_abuf.hw, 3261 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw, 3262 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw, 3263 [CLKID_SPI] = &meson8b_spi.hw, 3264 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw, 3265 [CLKID_ETH] = &meson8b_eth.hw, 3266 [CLKID_DEMUX] = &meson8b_demux.hw, 3267 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw, 3268 [CLKID_IEC958] = &meson8b_iec958.hw, 3269 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw, 3270 [CLKID_AMCLK] = &meson8b_amclk.hw, 3271 [CLKID_AIFIFO2] = &meson8b_aififo2.hw, 3272 [CLKID_MIXER] = &meson8b_mixer.hw, 3273 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw, 3274 [CLKID_ADC] = &meson8b_adc.hw, 3275 [CLKID_BLKMV] = &meson8b_blkmv.hw, 3276 [CLKID_AIU] = &meson8b_aiu.hw, 3277 [CLKID_UART1] = &meson8b_uart1.hw, 3278 [CLKID_G2D] = &meson8b_g2d.hw, 3279 [CLKID_USB0] = &meson8b_usb0.hw, 3280 [CLKID_USB1] = &meson8b_usb1.hw, 3281 [CLKID_RESET] = &meson8b_reset.hw, 3282 [CLKID_NAND] = &meson8b_nand.hw, 3283 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw, 3284 [CLKID_USB] = &meson8b_usb.hw, 3285 [CLKID_VDIN1] = &meson8b_vdin1.hw, 3286 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw, 3287 [CLKID_EFUSE] = &meson8b_efuse.hw, 3288 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw, 3289 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw, 3290 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw, 3291 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw, 3292 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw, 3293 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw, 3294 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw, 3295 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw, 3296 [CLKID_DVIN] = &meson8b_dvin.hw, 3297 [CLKID_UART2] = &meson8b_uart2.hw, 3298 [CLKID_SANA] = &meson8b_sana.hw, 3299 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw, 3300 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw, 3301 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw, 3302 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw, 3303 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw, 3304 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw, 3305 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw, 3306 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw, 3307 [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw, 3308 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw, 3309 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw, 3310 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw, 3311 [CLKID_ENC480P] = &meson8b_enc480p.hw, 3312 [CLKID_RNG1] = &meson8b_rng1.hw, 3313 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw, 3314 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw, 3315 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw, 3316 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw, 3317 [CLKID_EDP] = &meson8b_edp.hw, 3318 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw, 3319 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw, 3320 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw, 3321 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw, 3322 [CLKID_MPLL0] = &meson8b_mpll0.hw, 3323 [CLKID_MPLL1] = &meson8b_mpll1.hw, 3324 [CLKID_MPLL2] = &meson8b_mpll2.hw, 3325 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw, 3326 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw, 3327 [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw, 3328 [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw, 3329 [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw, 3330 [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw, 3331 [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw, 3332 [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw, 3333 [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw, 3334 [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw, 3335 [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw, 3336 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw, 3337 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw, 3338 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw, 3339 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw, 3340 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw, 3341 [CLKID_NAND_CLK] = &meson8b_nand_clk.hw, 3342 [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw, 3343 [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw, 3344 [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw, 3345 [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw, 3346 [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw, 3347 [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw, 3348 [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw, 3349 [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw, 3350 [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw, 3351 [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw, 3352 [CLKID_APB_SEL] = &meson8b_apb_sel.hw, 3353 [CLKID_APB] = &meson8b_apb.hw, 3354 [CLKID_PERIPH_SEL] = &meson8b_periph_sel.hw, 3355 [CLKID_PERIPH] = &meson8b_periph.hw, 3356 [CLKID_AXI_SEL] = &meson8b_axi_sel.hw, 3357 [CLKID_AXI] = &meson8b_axi.hw, 3358 [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_sel.hw, 3359 [CLKID_L2_DRAM] = &meson8b_l2_dram.hw, 3360 [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw, 3361 [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw, 3362 [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw, 3363 [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw, 3364 [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw, 3365 [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw, 3366 [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw, 3367 [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw, 3368 [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw, 3369 [CLKID_VCLK_EN] = &meson8b_vclk_en.hw, 3370 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1.hw, 3371 [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw, 3372 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2.hw, 3373 [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw, 3374 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4.hw, 3375 [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw, 3376 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6.hw, 3377 [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw, 3378 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12.hw, 3379 [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw, 3380 [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_in_en.hw, 3381 [CLKID_VCLK2_EN] = &meson8b_vclk2_en.hw, 3382 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1.hw, 3383 [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw, 3384 [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2.hw, 3385 [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw, 3386 [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4.hw, 3387 [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw, 3388 [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6.hw, 3389 [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw, 3390 [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12.hw, 3391 [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw, 3392 [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw, 3393 [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw, 3394 [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw, 3395 [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw, 3396 [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw, 3397 [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw, 3398 [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw, 3399 [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw, 3400 [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw, 3401 [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw, 3402 [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw, 3403 [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw, 3404 [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw, 3405 [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw, 3406 [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw, 3407 [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw, 3408 [CLKID_MALI_0] = &meson8b_mali_0.hw, 3409 [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw, 3410 [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw, 3411 [CLKID_MALI_1] = &meson8b_mali_1.hw, 3412 [CLKID_MALI] = &meson8b_mali.hw, 3413 [CLKID_GP_PLL_DCO] = &meson8m2_gp_pll_dco.hw, 3414 [CLKID_GP_PLL] = &meson8m2_gp_pll.hw, 3415 [CLKID_VPU_0_SEL] = &meson8m2_vpu_0_sel.hw, 3416 [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw, 3417 [CLKID_VPU_0] = &meson8b_vpu_0.hw, 3418 [CLKID_VPU_1_SEL] = &meson8m2_vpu_1_sel.hw, 3419 [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw, 3420 [CLKID_VPU_1] = &meson8b_vpu_1.hw, 3421 [CLKID_VPU] = &meson8b_vpu.hw, 3422 [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw, 3423 [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw, 3424 [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw, 3425 [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw, 3426 [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw, 3427 [CLKID_VDEC_1] = &meson8b_vdec_1.hw, 3428 [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw, 3429 [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw, 3430 [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw, 3431 [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw, 3432 [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw, 3433 [CLKID_VDEC_2] = &meson8b_vdec_2.hw, 3434 [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw, 3435 [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw, 3436 [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw, 3437 [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw, 3438 [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw, 3439 [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw, 3440 [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw, 3441 [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw, 3442 [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw, 3443 [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw, 3444 [CLKID_CTS_I958] = &meson8b_cts_i958.hw, 3445 [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, 3446 [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw, 3447 }; 3448 3449 static const struct meson8b_clk_reset_line { 3450 u32 reg; 3451 u8 bit_idx; 3452 bool active_low; 3453 } meson8b_clk_reset_bits[] = { 3454 [CLKC_RESET_L2_CACHE_SOFT_RESET] = { 3455 .reg = HHI_SYS_CPU_CLK_CNTL0, 3456 .bit_idx = 30, 3457 .active_low = false, 3458 }, 3459 [CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET] = { 3460 .reg = HHI_SYS_CPU_CLK_CNTL0, 3461 .bit_idx = 29, 3462 .active_low = false, 3463 }, 3464 [CLKC_RESET_SCU_SOFT_RESET] = { 3465 .reg = HHI_SYS_CPU_CLK_CNTL0, 3466 .bit_idx = 28, 3467 .active_low = false, 3468 }, 3469 [CLKC_RESET_CPU3_SOFT_RESET] = { 3470 .reg = HHI_SYS_CPU_CLK_CNTL0, 3471 .bit_idx = 27, 3472 .active_low = false, 3473 }, 3474 [CLKC_RESET_CPU2_SOFT_RESET] = { 3475 .reg = HHI_SYS_CPU_CLK_CNTL0, 3476 .bit_idx = 26, 3477 .active_low = false, 3478 }, 3479 [CLKC_RESET_CPU1_SOFT_RESET] = { 3480 .reg = HHI_SYS_CPU_CLK_CNTL0, 3481 .bit_idx = 25, 3482 .active_low = false, 3483 }, 3484 [CLKC_RESET_CPU0_SOFT_RESET] = { 3485 .reg = HHI_SYS_CPU_CLK_CNTL0, 3486 .bit_idx = 24, 3487 .active_low = false, 3488 }, 3489 [CLKC_RESET_A5_GLOBAL_RESET] = { 3490 .reg = HHI_SYS_CPU_CLK_CNTL0, 3491 .bit_idx = 18, 3492 .active_low = false, 3493 }, 3494 [CLKC_RESET_A5_AXI_SOFT_RESET] = { 3495 .reg = HHI_SYS_CPU_CLK_CNTL0, 3496 .bit_idx = 17, 3497 .active_low = false, 3498 }, 3499 [CLKC_RESET_A5_ABP_SOFT_RESET] = { 3500 .reg = HHI_SYS_CPU_CLK_CNTL0, 3501 .bit_idx = 16, 3502 .active_low = false, 3503 }, 3504 [CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET] = { 3505 .reg = HHI_SYS_CPU_CLK_CNTL1, 3506 .bit_idx = 30, 3507 .active_low = false, 3508 }, 3509 [CLKC_RESET_VID_CLK_CNTL_SOFT_RESET] = { 3510 .reg = HHI_VID_CLK_CNTL, 3511 .bit_idx = 15, 3512 .active_low = false, 3513 }, 3514 [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST] = { 3515 .reg = HHI_VID_DIVIDER_CNTL, 3516 .bit_idx = 7, 3517 .active_low = false, 3518 }, 3519 [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE] = { 3520 .reg = HHI_VID_DIVIDER_CNTL, 3521 .bit_idx = 3, 3522 .active_low = false, 3523 }, 3524 [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST] = { 3525 .reg = HHI_VID_DIVIDER_CNTL, 3526 .bit_idx = 1, 3527 .active_low = true, 3528 }, 3529 [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE] = { 3530 .reg = HHI_VID_DIVIDER_CNTL, 3531 .bit_idx = 0, 3532 .active_low = true, 3533 }, 3534 }; 3535 3536 static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev, 3537 unsigned long id, bool assert) 3538 { 3539 struct meson8b_clk_reset *meson8b_clk_reset = 3540 container_of(rcdev, struct meson8b_clk_reset, reset); 3541 const struct meson8b_clk_reset_line *reset; 3542 unsigned int value = 0; 3543 3544 if (id >= ARRAY_SIZE(meson8b_clk_reset_bits)) 3545 return -EINVAL; 3546 3547 reset = &meson8b_clk_reset_bits[id]; 3548 3549 if (assert != reset->active_low) 3550 value = BIT(reset->bit_idx); 3551 3552 regmap_update_bits(meson8b_clk_reset->regmap, reset->reg, 3553 BIT(reset->bit_idx), value); 3554 3555 return 0; 3556 } 3557 3558 static int meson8b_clk_reset_assert(struct reset_controller_dev *rcdev, 3559 unsigned long id) 3560 { 3561 return meson8b_clk_reset_update(rcdev, id, true); 3562 } 3563 3564 static int meson8b_clk_reset_deassert(struct reset_controller_dev *rcdev, 3565 unsigned long id) 3566 { 3567 return meson8b_clk_reset_update(rcdev, id, false); 3568 } 3569 3570 static const struct reset_control_ops meson8b_clk_reset_ops = { 3571 .assert = meson8b_clk_reset_assert, 3572 .deassert = meson8b_clk_reset_deassert, 3573 }; 3574 3575 struct meson8b_nb_data { 3576 struct notifier_block nb; 3577 struct clk_hw *cpu_clk; 3578 }; 3579 3580 static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb, 3581 unsigned long event, void *data) 3582 { 3583 struct meson8b_nb_data *nb_data = 3584 container_of(nb, struct meson8b_nb_data, nb); 3585 struct clk_hw *parent_clk; 3586 int ret; 3587 3588 switch (event) { 3589 case PRE_RATE_CHANGE: 3590 /* xtal */ 3591 parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 0); 3592 break; 3593 3594 case POST_RATE_CHANGE: 3595 /* cpu_scale_out_sel */ 3596 parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 1); 3597 break; 3598 3599 default: 3600 return NOTIFY_DONE; 3601 } 3602 3603 ret = clk_hw_set_parent(nb_data->cpu_clk, parent_clk); 3604 if (ret) 3605 return notifier_from_errno(ret); 3606 3607 udelay(100); 3608 3609 return NOTIFY_OK; 3610 } 3611 3612 static struct meson8b_nb_data meson8b_cpu_nb_data = { 3613 .nb.notifier_call = meson8b_cpu_clk_notifier_cb, 3614 }; 3615 3616 static struct meson_clk_hw_data meson8_clks = { 3617 .hws = meson8_hw_clks, 3618 .num = ARRAY_SIZE(meson8_hw_clks), 3619 }; 3620 3621 static struct meson_clk_hw_data meson8b_clks = { 3622 .hws = meson8b_hw_clks, 3623 .num = ARRAY_SIZE(meson8b_hw_clks), 3624 }; 3625 3626 static struct meson_clk_hw_data meson8m2_clks = { 3627 .hws = meson8m2_hw_clks, 3628 .num = ARRAY_SIZE(meson8m2_hw_clks), 3629 }; 3630 3631 static void __init meson8b_clkc_init_common(struct device_node *np, 3632 struct meson_clk_hw_data *hw_clks) 3633 { 3634 struct meson8b_clk_reset *rstc; 3635 struct device_node *parent_np; 3636 const char *notifier_clk_name; 3637 struct clk *notifier_clk; 3638 struct regmap *map; 3639 int i, ret; 3640 3641 parent_np = of_get_parent(np); 3642 map = syscon_node_to_regmap(parent_np); 3643 of_node_put(parent_np); 3644 if (IS_ERR(map)) { 3645 pr_err("failed to get HHI regmap - Trying obsolete regs\n"); 3646 return; 3647 } 3648 3649 rstc = kzalloc(sizeof(*rstc), GFP_KERNEL); 3650 if (!rstc) 3651 return; 3652 3653 /* Reset Controller */ 3654 rstc->regmap = map; 3655 rstc->reset.ops = &meson8b_clk_reset_ops; 3656 rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits); 3657 rstc->reset.of_node = np; 3658 ret = reset_controller_register(&rstc->reset); 3659 if (ret) { 3660 pr_err("%s: Failed to register clkc reset controller: %d\n", 3661 __func__, ret); 3662 return; 3663 } 3664 3665 /* 3666 * register all clks and start with the first used ID (which is 3667 * CLKID_PLL_FIXED) 3668 */ 3669 for (i = CLKID_PLL_FIXED; i < hw_clks->num; i++) { 3670 /* array might be sparse */ 3671 if (!hw_clks->hws[i]) 3672 continue; 3673 3674 ret = of_clk_hw_register(np, hw_clks->hws[i]); 3675 if (ret) 3676 return; 3677 } 3678 3679 meson8b_cpu_nb_data.cpu_clk = hw_clks->hws[CLKID_CPUCLK]; 3680 3681 /* 3682 * FIXME we shouldn't program the muxes in notifier handlers. The 3683 * tricky programming sequence will be handled by the forthcoming 3684 * coordinated clock rates mechanism once that feature is released. 3685 */ 3686 notifier_clk_name = clk_hw_get_name(&meson8b_cpu_scale_out_sel.hw); 3687 notifier_clk = __clk_lookup(notifier_clk_name); 3688 ret = clk_notifier_register(notifier_clk, &meson8b_cpu_nb_data.nb); 3689 if (ret) { 3690 pr_err("%s: failed to register the CPU clock notifier\n", 3691 __func__); 3692 return; 3693 } 3694 3695 ret = of_clk_add_hw_provider(np, meson_clk_hw_get, hw_clks); 3696 if (ret) 3697 pr_err("%s: failed to register clock provider\n", __func__); 3698 } 3699 3700 static void __init meson8_clkc_init(struct device_node *np) 3701 { 3702 return meson8b_clkc_init_common(np, &meson8_clks); 3703 } 3704 3705 static void __init meson8b_clkc_init(struct device_node *np) 3706 { 3707 return meson8b_clkc_init_common(np, &meson8b_clks); 3708 } 3709 3710 static void __init meson8m2_clkc_init(struct device_node *np) 3711 { 3712 return meson8b_clkc_init_common(np, &meson8m2_clks); 3713 } 3714 3715 CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc", 3716 meson8_clkc_init); 3717 CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc", 3718 meson8b_clkc_init); 3719 CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc", 3720 meson8m2_clkc_init); 3721