1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2015 Endless Mobile, Inc. 4 * Author: Carlo Caione <carlo@endlessm.com> 5 * 6 * Copyright (c) 2016 BayLibre, Inc. 7 * Michael Turquette <mturquette@baylibre.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/init.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/of_address.h> 15 #include <linux/reset-controller.h> 16 #include <linux/slab.h> 17 #include <linux/regmap.h> 18 19 #include "clk-regmap.h" 20 #include "meson-clkc-utils.h" 21 #include "clk-pll.h" 22 #include "clk-mpll.h" 23 24 #include <dt-bindings/clock/meson8b-clkc.h> 25 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> 26 27 /* 28 * Clock controller register offsets 29 * 30 * Register offsets from the HardKernel[0] data sheet must be multiplied 31 * by 4 before adding them to the base address to get the right value 32 * 33 * [0] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf 34 */ 35 #define HHI_GP_PLL_CNTL 0x40 36 #define HHI_GP_PLL_CNTL2 0x44 37 #define HHI_GP_PLL_CNTL3 0x48 38 #define HHI_GP_PLL_CNTL4 0x4C 39 #define HHI_GP_PLL_CNTL5 0x50 40 #define HHI_VIID_CLK_DIV 0x128 41 #define HHI_VIID_CLK_CNTL 0x12c 42 #define HHI_GCLK_MPEG0 0x140 43 #define HHI_GCLK_MPEG1 0x144 44 #define HHI_GCLK_MPEG2 0x148 45 #define HHI_GCLK_OTHER 0x150 46 #define HHI_GCLK_AO 0x154 47 #define HHI_SYS_CPU_CLK_CNTL1 0x15c 48 #define HHI_VID_CLK_DIV 0x164 49 #define HHI_MPEG_CLK_CNTL 0x174 50 #define HHI_AUD_CLK_CNTL 0x178 51 #define HHI_VID_CLK_CNTL 0x17c 52 #define HHI_AUD_CLK_CNTL2 0x190 53 #define HHI_VID_CLK_CNTL2 0x194 54 #define HHI_VID_DIVIDER_CNTL 0x198 55 #define HHI_SYS_CPU_CLK_CNTL0 0x19c 56 #define HHI_MALI_CLK_CNTL 0x1b0 57 #define HHI_VPU_CLK_CNTL 0x1bc 58 #define HHI_HDMI_CLK_CNTL 0x1cc 59 #define HHI_VDEC_CLK_CNTL 0x1e0 60 #define HHI_VDEC2_CLK_CNTL 0x1e4 61 #define HHI_VDEC3_CLK_CNTL 0x1e8 62 #define HHI_NAND_CLK_CNTL 0x25c 63 #define HHI_MPLL_CNTL 0x280 64 #define HHI_SYS_PLL_CNTL 0x300 65 #define HHI_VID_PLL_CNTL 0x320 66 #define HHI_VID_PLL_CNTL2 0x324 67 #define HHI_VID_PLL_CNTL3 0x328 68 #define HHI_VID_PLL_CNTL4 0x32c 69 #define HHI_VID_PLL_CNTL5 0x330 70 #define HHI_VID_PLL_CNTL6 0x334 71 #define HHI_VID2_PLL_CNTL 0x380 72 #define HHI_VID2_PLL_CNTL2 0x384 73 #define HHI_VID2_PLL_CNTL3 0x388 74 #define HHI_VID2_PLL_CNTL4 0x38c 75 #define HHI_VID2_PLL_CNTL5 0x390 76 #define HHI_VID2_PLL_CNTL6 0x394 77 78 /* 79 * MPLL register offeset taken from the S905 datasheet. Vendor kernel source 80 * confirm these are the same for the S805. 81 */ 82 #define HHI_MPLL_CNTL 0x280 83 #define HHI_MPLL_CNTL2 0x284 84 #define HHI_MPLL_CNTL3 0x288 85 #define HHI_MPLL_CNTL4 0x28c 86 #define HHI_MPLL_CNTL5 0x290 87 #define HHI_MPLL_CNTL6 0x294 88 #define HHI_MPLL_CNTL7 0x298 89 #define HHI_MPLL_CNTL8 0x29c 90 #define HHI_MPLL_CNTL9 0x2a0 91 #define HHI_MPLL_CNTL10 0x2a4 92 93 struct meson8b_clk_reset { 94 struct reset_controller_dev reset; 95 struct regmap *regmap; 96 }; 97 98 static const struct pll_params_table sys_pll_params_table[] = { 99 PLL_PARAMS(50, 1), 100 PLL_PARAMS(51, 1), 101 PLL_PARAMS(52, 1), 102 PLL_PARAMS(53, 1), 103 PLL_PARAMS(54, 1), 104 PLL_PARAMS(55, 1), 105 PLL_PARAMS(56, 1), 106 PLL_PARAMS(57, 1), 107 PLL_PARAMS(58, 1), 108 PLL_PARAMS(59, 1), 109 PLL_PARAMS(60, 1), 110 PLL_PARAMS(61, 1), 111 PLL_PARAMS(62, 1), 112 PLL_PARAMS(63, 1), 113 PLL_PARAMS(64, 1), 114 PLL_PARAMS(65, 1), 115 PLL_PARAMS(66, 1), 116 PLL_PARAMS(67, 1), 117 PLL_PARAMS(68, 1), 118 PLL_PARAMS(84, 1), 119 { /* sentinel */ }, 120 }; 121 122 static struct clk_regmap meson8b_fixed_pll_dco = { 123 .data = &(struct meson_clk_pll_data){ 124 .en = { 125 .reg_off = HHI_MPLL_CNTL, 126 .shift = 30, 127 .width = 1, 128 }, 129 .m = { 130 .reg_off = HHI_MPLL_CNTL, 131 .shift = 0, 132 .width = 9, 133 }, 134 .n = { 135 .reg_off = HHI_MPLL_CNTL, 136 .shift = 9, 137 .width = 5, 138 }, 139 .frac = { 140 .reg_off = HHI_MPLL_CNTL2, 141 .shift = 0, 142 .width = 12, 143 }, 144 .l = { 145 .reg_off = HHI_MPLL_CNTL, 146 .shift = 31, 147 .width = 1, 148 }, 149 .rst = { 150 .reg_off = HHI_MPLL_CNTL, 151 .shift = 29, 152 .width = 1, 153 }, 154 }, 155 .hw.init = &(struct clk_init_data){ 156 .name = "fixed_pll_dco", 157 .ops = &meson_clk_pll_ro_ops, 158 .parent_data = &(const struct clk_parent_data) { 159 .fw_name = "xtal", 160 .name = "xtal", 161 .index = -1, 162 }, 163 .num_parents = 1, 164 }, 165 }; 166 167 static struct clk_regmap meson8b_fixed_pll = { 168 .data = &(struct clk_regmap_div_data){ 169 .offset = HHI_MPLL_CNTL, 170 .shift = 16, 171 .width = 2, 172 .flags = CLK_DIVIDER_POWER_OF_TWO, 173 }, 174 .hw.init = &(struct clk_init_data){ 175 .name = "fixed_pll", 176 .ops = &clk_regmap_divider_ro_ops, 177 .parent_hws = (const struct clk_hw *[]) { 178 &meson8b_fixed_pll_dco.hw 179 }, 180 .num_parents = 1, 181 /* 182 * This clock won't ever change at runtime so 183 * CLK_SET_RATE_PARENT is not required 184 */ 185 }, 186 }; 187 188 static struct clk_fixed_factor hdmi_pll_dco_in = { 189 .mult = 2, 190 .div = 1, 191 .hw.init = &(struct clk_init_data){ 192 .name = "hdmi_pll_dco_in", 193 .ops = &clk_fixed_factor_ops, 194 .parent_data = &(const struct clk_parent_data) { 195 .fw_name = "xtal", 196 .index = -1, 197 }, 198 .num_parents = 1, 199 }, 200 }; 201 202 /* 203 * Taken from the vendor driver for the 2970/2975MHz (both only differ in the 204 * FRAC part in HHI_VID_PLL_CNTL2) where these values are identical for Meson8, 205 * Meson8b and Meson8m2. This doubles the input (or output - it's not clear 206 * which one but the result is the same) clock. The vendor driver additionally 207 * has the following comment about: "optimise HPLL VCO 2.97GHz performance". 208 */ 209 static const struct reg_sequence meson8b_hdmi_pll_init_regs[] = { 210 { .reg = HHI_VID_PLL_CNTL2, .def = 0x69c84000 }, 211 { .reg = HHI_VID_PLL_CNTL3, .def = 0x8a46c023 }, 212 { .reg = HHI_VID_PLL_CNTL4, .def = 0x4123b100 }, 213 { .reg = HHI_VID_PLL_CNTL5, .def = 0x00012385 }, 214 { .reg = HHI_VID2_PLL_CNTL2, .def = 0x0430a800 }, 215 }; 216 217 static const struct pll_params_table hdmi_pll_params_table[] = { 218 PLL_PARAMS(40, 1), 219 PLL_PARAMS(42, 1), 220 PLL_PARAMS(44, 1), 221 PLL_PARAMS(45, 1), 222 PLL_PARAMS(49, 1), 223 PLL_PARAMS(52, 1), 224 PLL_PARAMS(54, 1), 225 PLL_PARAMS(56, 1), 226 PLL_PARAMS(59, 1), 227 PLL_PARAMS(60, 1), 228 PLL_PARAMS(61, 1), 229 PLL_PARAMS(62, 1), 230 PLL_PARAMS(64, 1), 231 PLL_PARAMS(66, 1), 232 PLL_PARAMS(68, 1), 233 PLL_PARAMS(71, 1), 234 PLL_PARAMS(82, 1), 235 { /* sentinel */ } 236 }; 237 238 static struct clk_regmap meson8b_hdmi_pll_dco = { 239 .data = &(struct meson_clk_pll_data){ 240 .en = { 241 .reg_off = HHI_VID_PLL_CNTL, 242 .shift = 30, 243 .width = 1, 244 }, 245 .m = { 246 .reg_off = HHI_VID_PLL_CNTL, 247 .shift = 0, 248 .width = 9, 249 }, 250 .n = { 251 .reg_off = HHI_VID_PLL_CNTL, 252 .shift = 10, 253 .width = 5, 254 }, 255 .frac = { 256 .reg_off = HHI_VID_PLL_CNTL2, 257 .shift = 0, 258 .width = 12, 259 }, 260 .l = { 261 .reg_off = HHI_VID_PLL_CNTL, 262 .shift = 31, 263 .width = 1, 264 }, 265 .rst = { 266 .reg_off = HHI_VID_PLL_CNTL, 267 .shift = 29, 268 .width = 1, 269 }, 270 .table = hdmi_pll_params_table, 271 .init_regs = meson8b_hdmi_pll_init_regs, 272 .init_count = ARRAY_SIZE(meson8b_hdmi_pll_init_regs), 273 }, 274 .hw.init = &(struct clk_init_data){ 275 /* sometimes also called "HPLL" or "HPLL PLL" */ 276 .name = "hdmi_pll_dco", 277 .ops = &meson_clk_pll_ops, 278 .parent_hws = (const struct clk_hw *[]) { 279 &hdmi_pll_dco_in.hw 280 }, 281 .num_parents = 1, 282 }, 283 }; 284 285 static struct clk_regmap meson8b_hdmi_pll_lvds_out = { 286 .data = &(struct clk_regmap_div_data){ 287 .offset = HHI_VID_PLL_CNTL, 288 .shift = 16, 289 .width = 2, 290 .flags = CLK_DIVIDER_POWER_OF_TWO, 291 }, 292 .hw.init = &(struct clk_init_data){ 293 .name = "hdmi_pll_lvds_out", 294 .ops = &clk_regmap_divider_ops, 295 .parent_hws = (const struct clk_hw *[]) { 296 &meson8b_hdmi_pll_dco.hw 297 }, 298 .num_parents = 1, 299 .flags = CLK_SET_RATE_PARENT, 300 }, 301 }; 302 303 static struct clk_regmap meson8b_hdmi_pll_hdmi_out = { 304 .data = &(struct clk_regmap_div_data){ 305 .offset = HHI_VID_PLL_CNTL, 306 .shift = 18, 307 .width = 2, 308 .flags = CLK_DIVIDER_POWER_OF_TWO, 309 }, 310 .hw.init = &(struct clk_init_data){ 311 .name = "hdmi_pll_hdmi_out", 312 .ops = &clk_regmap_divider_ops, 313 .parent_hws = (const struct clk_hw *[]) { 314 &meson8b_hdmi_pll_dco.hw 315 }, 316 .num_parents = 1, 317 .flags = CLK_SET_RATE_PARENT, 318 }, 319 }; 320 321 static struct clk_regmap meson8b_sys_pll_dco = { 322 .data = &(struct meson_clk_pll_data){ 323 .en = { 324 .reg_off = HHI_SYS_PLL_CNTL, 325 .shift = 30, 326 .width = 1, 327 }, 328 .m = { 329 .reg_off = HHI_SYS_PLL_CNTL, 330 .shift = 0, 331 .width = 9, 332 }, 333 .n = { 334 .reg_off = HHI_SYS_PLL_CNTL, 335 .shift = 9, 336 .width = 5, 337 }, 338 .l = { 339 .reg_off = HHI_SYS_PLL_CNTL, 340 .shift = 31, 341 .width = 1, 342 }, 343 .rst = { 344 .reg_off = HHI_SYS_PLL_CNTL, 345 .shift = 29, 346 .width = 1, 347 }, 348 .table = sys_pll_params_table, 349 }, 350 .hw.init = &(struct clk_init_data){ 351 .name = "sys_pll_dco", 352 .ops = &meson_clk_pll_ops, 353 .parent_data = &(const struct clk_parent_data) { 354 .fw_name = "xtal", 355 .name = "xtal", 356 .index = -1, 357 }, 358 .num_parents = 1, 359 }, 360 }; 361 362 static struct clk_regmap meson8b_sys_pll = { 363 .data = &(struct clk_regmap_div_data){ 364 .offset = HHI_SYS_PLL_CNTL, 365 .shift = 16, 366 .width = 2, 367 .flags = CLK_DIVIDER_POWER_OF_TWO, 368 }, 369 .hw.init = &(struct clk_init_data){ 370 .name = "sys_pll", 371 .ops = &clk_regmap_divider_ops, 372 .parent_hws = (const struct clk_hw *[]) { 373 &meson8b_sys_pll_dco.hw 374 }, 375 .num_parents = 1, 376 .flags = CLK_SET_RATE_PARENT, 377 }, 378 }; 379 380 static struct clk_fixed_factor meson8b_fclk_div2_div = { 381 .mult = 1, 382 .div = 2, 383 .hw.init = &(struct clk_init_data){ 384 .name = "fclk_div2_div", 385 .ops = &clk_fixed_factor_ops, 386 .parent_hws = (const struct clk_hw *[]) { 387 &meson8b_fixed_pll.hw 388 }, 389 .num_parents = 1, 390 }, 391 }; 392 393 static struct clk_regmap meson8b_fclk_div2 = { 394 .data = &(struct clk_regmap_gate_data){ 395 .offset = HHI_MPLL_CNTL6, 396 .bit_idx = 27, 397 }, 398 .hw.init = &(struct clk_init_data){ 399 .name = "fclk_div2", 400 .ops = &clk_regmap_gate_ops, 401 .parent_hws = (const struct clk_hw *[]) { 402 &meson8b_fclk_div2_div.hw 403 }, 404 .num_parents = 1, 405 }, 406 }; 407 408 static struct clk_fixed_factor meson8b_fclk_div3_div = { 409 .mult = 1, 410 .div = 3, 411 .hw.init = &(struct clk_init_data){ 412 .name = "fclk_div3_div", 413 .ops = &clk_fixed_factor_ops, 414 .parent_hws = (const struct clk_hw *[]) { 415 &meson8b_fixed_pll.hw 416 }, 417 .num_parents = 1, 418 }, 419 }; 420 421 static struct clk_regmap meson8b_fclk_div3 = { 422 .data = &(struct clk_regmap_gate_data){ 423 .offset = HHI_MPLL_CNTL6, 424 .bit_idx = 28, 425 }, 426 .hw.init = &(struct clk_init_data){ 427 .name = "fclk_div3", 428 .ops = &clk_regmap_gate_ops, 429 .parent_hws = (const struct clk_hw *[]) { 430 &meson8b_fclk_div3_div.hw 431 }, 432 .num_parents = 1, 433 }, 434 }; 435 436 static struct clk_fixed_factor meson8b_fclk_div4_div = { 437 .mult = 1, 438 .div = 4, 439 .hw.init = &(struct clk_init_data){ 440 .name = "fclk_div4_div", 441 .ops = &clk_fixed_factor_ops, 442 .parent_hws = (const struct clk_hw *[]) { 443 &meson8b_fixed_pll.hw 444 }, 445 .num_parents = 1, 446 }, 447 }; 448 449 static struct clk_regmap meson8b_fclk_div4 = { 450 .data = &(struct clk_regmap_gate_data){ 451 .offset = HHI_MPLL_CNTL6, 452 .bit_idx = 29, 453 }, 454 .hw.init = &(struct clk_init_data){ 455 .name = "fclk_div4", 456 .ops = &clk_regmap_gate_ops, 457 .parent_hws = (const struct clk_hw *[]) { 458 &meson8b_fclk_div4_div.hw 459 }, 460 .num_parents = 1, 461 }, 462 }; 463 464 static struct clk_fixed_factor meson8b_fclk_div5_div = { 465 .mult = 1, 466 .div = 5, 467 .hw.init = &(struct clk_init_data){ 468 .name = "fclk_div5_div", 469 .ops = &clk_fixed_factor_ops, 470 .parent_hws = (const struct clk_hw *[]) { 471 &meson8b_fixed_pll.hw 472 }, 473 .num_parents = 1, 474 }, 475 }; 476 477 static struct clk_regmap meson8b_fclk_div5 = { 478 .data = &(struct clk_regmap_gate_data){ 479 .offset = HHI_MPLL_CNTL6, 480 .bit_idx = 30, 481 }, 482 .hw.init = &(struct clk_init_data){ 483 .name = "fclk_div5", 484 .ops = &clk_regmap_gate_ops, 485 .parent_hws = (const struct clk_hw *[]) { 486 &meson8b_fclk_div5_div.hw 487 }, 488 .num_parents = 1, 489 }, 490 }; 491 492 static struct clk_fixed_factor meson8b_fclk_div7_div = { 493 .mult = 1, 494 .div = 7, 495 .hw.init = &(struct clk_init_data){ 496 .name = "fclk_div7_div", 497 .ops = &clk_fixed_factor_ops, 498 .parent_hws = (const struct clk_hw *[]) { 499 &meson8b_fixed_pll.hw 500 }, 501 .num_parents = 1, 502 }, 503 }; 504 505 static struct clk_regmap meson8b_fclk_div7 = { 506 .data = &(struct clk_regmap_gate_data){ 507 .offset = HHI_MPLL_CNTL6, 508 .bit_idx = 31, 509 }, 510 .hw.init = &(struct clk_init_data){ 511 .name = "fclk_div7", 512 .ops = &clk_regmap_gate_ops, 513 .parent_hws = (const struct clk_hw *[]) { 514 &meson8b_fclk_div7_div.hw 515 }, 516 .num_parents = 1, 517 }, 518 }; 519 520 static struct clk_regmap meson8b_mpll_prediv = { 521 .data = &(struct clk_regmap_div_data){ 522 .offset = HHI_MPLL_CNTL5, 523 .shift = 12, 524 .width = 1, 525 }, 526 .hw.init = &(struct clk_init_data){ 527 .name = "mpll_prediv", 528 .ops = &clk_regmap_divider_ro_ops, 529 .parent_hws = (const struct clk_hw *[]) { 530 &meson8b_fixed_pll.hw 531 }, 532 .num_parents = 1, 533 }, 534 }; 535 536 static struct clk_regmap meson8b_mpll0_div = { 537 .data = &(struct meson_clk_mpll_data){ 538 .sdm = { 539 .reg_off = HHI_MPLL_CNTL7, 540 .shift = 0, 541 .width = 14, 542 }, 543 .sdm_en = { 544 .reg_off = HHI_MPLL_CNTL7, 545 .shift = 15, 546 .width = 1, 547 }, 548 .n2 = { 549 .reg_off = HHI_MPLL_CNTL7, 550 .shift = 16, 551 .width = 9, 552 }, 553 .ssen = { 554 .reg_off = HHI_MPLL_CNTL, 555 .shift = 25, 556 .width = 1, 557 }, 558 }, 559 .hw.init = &(struct clk_init_data){ 560 .name = "mpll0_div", 561 .ops = &meson_clk_mpll_ops, 562 .parent_hws = (const struct clk_hw *[]) { 563 &meson8b_mpll_prediv.hw 564 }, 565 .num_parents = 1, 566 }, 567 }; 568 569 static struct clk_regmap meson8b_mpll0 = { 570 .data = &(struct clk_regmap_gate_data){ 571 .offset = HHI_MPLL_CNTL7, 572 .bit_idx = 14, 573 }, 574 .hw.init = &(struct clk_init_data){ 575 .name = "mpll0", 576 .ops = &clk_regmap_gate_ops, 577 .parent_hws = (const struct clk_hw *[]) { 578 &meson8b_mpll0_div.hw 579 }, 580 .num_parents = 1, 581 .flags = CLK_SET_RATE_PARENT, 582 }, 583 }; 584 585 static struct clk_regmap meson8b_mpll1_div = { 586 .data = &(struct meson_clk_mpll_data){ 587 .sdm = { 588 .reg_off = HHI_MPLL_CNTL8, 589 .shift = 0, 590 .width = 14, 591 }, 592 .sdm_en = { 593 .reg_off = HHI_MPLL_CNTL8, 594 .shift = 15, 595 .width = 1, 596 }, 597 .n2 = { 598 .reg_off = HHI_MPLL_CNTL8, 599 .shift = 16, 600 .width = 9, 601 }, 602 }, 603 .hw.init = &(struct clk_init_data){ 604 .name = "mpll1_div", 605 .ops = &meson_clk_mpll_ops, 606 .parent_hws = (const struct clk_hw *[]) { 607 &meson8b_mpll_prediv.hw 608 }, 609 .num_parents = 1, 610 }, 611 }; 612 613 static struct clk_regmap meson8b_mpll1 = { 614 .data = &(struct clk_regmap_gate_data){ 615 .offset = HHI_MPLL_CNTL8, 616 .bit_idx = 14, 617 }, 618 .hw.init = &(struct clk_init_data){ 619 .name = "mpll1", 620 .ops = &clk_regmap_gate_ops, 621 .parent_hws = (const struct clk_hw *[]) { 622 &meson8b_mpll1_div.hw 623 }, 624 .num_parents = 1, 625 .flags = CLK_SET_RATE_PARENT, 626 }, 627 }; 628 629 static struct clk_regmap meson8b_mpll2_div = { 630 .data = &(struct meson_clk_mpll_data){ 631 .sdm = { 632 .reg_off = HHI_MPLL_CNTL9, 633 .shift = 0, 634 .width = 14, 635 }, 636 .sdm_en = { 637 .reg_off = HHI_MPLL_CNTL9, 638 .shift = 15, 639 .width = 1, 640 }, 641 .n2 = { 642 .reg_off = HHI_MPLL_CNTL9, 643 .shift = 16, 644 .width = 9, 645 }, 646 }, 647 .hw.init = &(struct clk_init_data){ 648 .name = "mpll2_div", 649 .ops = &meson_clk_mpll_ops, 650 .parent_hws = (const struct clk_hw *[]) { 651 &meson8b_mpll_prediv.hw 652 }, 653 .num_parents = 1, 654 }, 655 }; 656 657 static struct clk_regmap meson8b_mpll2 = { 658 .data = &(struct clk_regmap_gate_data){ 659 .offset = HHI_MPLL_CNTL9, 660 .bit_idx = 14, 661 }, 662 .hw.init = &(struct clk_init_data){ 663 .name = "mpll2", 664 .ops = &clk_regmap_gate_ops, 665 .parent_hws = (const struct clk_hw *[]) { 666 &meson8b_mpll2_div.hw 667 }, 668 .num_parents = 1, 669 .flags = CLK_SET_RATE_PARENT, 670 }, 671 }; 672 673 static u32 mux_table_clk81[] = { 6, 5, 7 }; 674 static struct clk_regmap meson8b_mpeg_clk_sel = { 675 .data = &(struct clk_regmap_mux_data){ 676 .offset = HHI_MPEG_CLK_CNTL, 677 .mask = 0x7, 678 .shift = 12, 679 .table = mux_table_clk81, 680 }, 681 .hw.init = &(struct clk_init_data){ 682 .name = "mpeg_clk_sel", 683 .ops = &clk_regmap_mux_ro_ops, 684 /* 685 * FIXME bits 14:12 selects from 8 possible parents: 686 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, 687 * fclk_div4, fclk_div3, fclk_div5 688 */ 689 .parent_hws = (const struct clk_hw *[]) { 690 &meson8b_fclk_div3.hw, 691 &meson8b_fclk_div4.hw, 692 &meson8b_fclk_div5.hw, 693 }, 694 .num_parents = 3, 695 }, 696 }; 697 698 static struct clk_regmap meson8b_mpeg_clk_div = { 699 .data = &(struct clk_regmap_div_data){ 700 .offset = HHI_MPEG_CLK_CNTL, 701 .shift = 0, 702 .width = 7, 703 }, 704 .hw.init = &(struct clk_init_data){ 705 .name = "mpeg_clk_div", 706 .ops = &clk_regmap_divider_ro_ops, 707 .parent_hws = (const struct clk_hw *[]) { 708 &meson8b_mpeg_clk_sel.hw 709 }, 710 .num_parents = 1, 711 }, 712 }; 713 714 static struct clk_regmap meson8b_clk81 = { 715 .data = &(struct clk_regmap_gate_data){ 716 .offset = HHI_MPEG_CLK_CNTL, 717 .bit_idx = 7, 718 }, 719 .hw.init = &(struct clk_init_data){ 720 .name = "clk81", 721 .ops = &clk_regmap_gate_ops, 722 .parent_hws = (const struct clk_hw *[]) { 723 &meson8b_mpeg_clk_div.hw 724 }, 725 .num_parents = 1, 726 .flags = CLK_IS_CRITICAL, 727 }, 728 }; 729 730 static struct clk_regmap meson8b_cpu_in_sel = { 731 .data = &(struct clk_regmap_mux_data){ 732 .offset = HHI_SYS_CPU_CLK_CNTL0, 733 .mask = 0x1, 734 .shift = 0, 735 }, 736 .hw.init = &(struct clk_init_data){ 737 .name = "cpu_in_sel", 738 .ops = &clk_regmap_mux_ops, 739 .parent_data = (const struct clk_parent_data[]) { 740 { .fw_name = "xtal", .name = "xtal", .index = -1, }, 741 { .hw = &meson8b_sys_pll.hw, }, 742 }, 743 .num_parents = 2, 744 .flags = (CLK_SET_RATE_PARENT | 745 CLK_SET_RATE_NO_REPARENT), 746 }, 747 }; 748 749 static struct clk_fixed_factor meson8b_cpu_in_div2 = { 750 .mult = 1, 751 .div = 2, 752 .hw.init = &(struct clk_init_data){ 753 .name = "cpu_in_div2", 754 .ops = &clk_fixed_factor_ops, 755 .parent_hws = (const struct clk_hw *[]) { 756 &meson8b_cpu_in_sel.hw 757 }, 758 .num_parents = 1, 759 .flags = CLK_SET_RATE_PARENT, 760 }, 761 }; 762 763 static struct clk_fixed_factor meson8b_cpu_in_div3 = { 764 .mult = 1, 765 .div = 3, 766 .hw.init = &(struct clk_init_data){ 767 .name = "cpu_in_div3", 768 .ops = &clk_fixed_factor_ops, 769 .parent_hws = (const struct clk_hw *[]) { 770 &meson8b_cpu_in_sel.hw 771 }, 772 .num_parents = 1, 773 .flags = CLK_SET_RATE_PARENT, 774 }, 775 }; 776 777 static const struct clk_div_table cpu_scale_table[] = { 778 { .val = 1, .div = 4 }, 779 { .val = 2, .div = 6 }, 780 { .val = 3, .div = 8 }, 781 { .val = 4, .div = 10 }, 782 { .val = 5, .div = 12 }, 783 { .val = 6, .div = 14 }, 784 { .val = 7, .div = 16 }, 785 { .val = 8, .div = 18 }, 786 { /* sentinel */ }, 787 }; 788 789 static struct clk_regmap meson8b_cpu_scale_div = { 790 .data = &(struct clk_regmap_div_data){ 791 .offset = HHI_SYS_CPU_CLK_CNTL1, 792 .shift = 20, 793 .width = 10, 794 .table = cpu_scale_table, 795 .flags = CLK_DIVIDER_ALLOW_ZERO, 796 }, 797 .hw.init = &(struct clk_init_data){ 798 .name = "cpu_scale_div", 799 .ops = &clk_regmap_divider_ops, 800 .parent_hws = (const struct clk_hw *[]) { 801 &meson8b_cpu_in_sel.hw 802 }, 803 .num_parents = 1, 804 .flags = CLK_SET_RATE_PARENT, 805 }, 806 }; 807 808 static u32 mux_table_cpu_scale_out_sel[] = { 0, 1, 3 }; 809 static struct clk_regmap meson8b_cpu_scale_out_sel = { 810 .data = &(struct clk_regmap_mux_data){ 811 .offset = HHI_SYS_CPU_CLK_CNTL0, 812 .mask = 0x3, 813 .shift = 2, 814 .table = mux_table_cpu_scale_out_sel, 815 }, 816 .hw.init = &(struct clk_init_data){ 817 .name = "cpu_scale_out_sel", 818 .ops = &clk_regmap_mux_ops, 819 /* 820 * NOTE: We are skipping the parent with value 0x2 (which is 821 * meson8b_cpu_in_div3) because it results in a duty cycle of 822 * 33% which makes the system unstable and can result in a 823 * lockup of the whole system. 824 */ 825 .parent_hws = (const struct clk_hw *[]) { 826 &meson8b_cpu_in_sel.hw, 827 &meson8b_cpu_in_div2.hw, 828 &meson8b_cpu_scale_div.hw, 829 }, 830 .num_parents = 3, 831 .flags = CLK_SET_RATE_PARENT, 832 }, 833 }; 834 835 static struct clk_regmap meson8b_cpu_clk = { 836 .data = &(struct clk_regmap_mux_data){ 837 .offset = HHI_SYS_CPU_CLK_CNTL0, 838 .mask = 0x1, 839 .shift = 7, 840 }, 841 .hw.init = &(struct clk_init_data){ 842 .name = "cpu_clk", 843 .ops = &clk_regmap_mux_ops, 844 .parent_data = (const struct clk_parent_data[]) { 845 { .fw_name = "xtal", .name = "xtal", .index = -1, }, 846 { .hw = &meson8b_cpu_scale_out_sel.hw, }, 847 }, 848 .num_parents = 2, 849 .flags = (CLK_SET_RATE_PARENT | 850 CLK_SET_RATE_NO_REPARENT | 851 CLK_IS_CRITICAL), 852 }, 853 }; 854 855 static struct clk_regmap meson8b_nand_clk_sel = { 856 .data = &(struct clk_regmap_mux_data){ 857 .offset = HHI_NAND_CLK_CNTL, 858 .mask = 0x7, 859 .shift = 9, 860 .flags = CLK_MUX_ROUND_CLOSEST, 861 }, 862 .hw.init = &(struct clk_init_data){ 863 .name = "nand_clk_sel", 864 .ops = &clk_regmap_mux_ops, 865 /* FIXME all other parents are unknown: */ 866 .parent_data = (const struct clk_parent_data[]) { 867 { .hw = &meson8b_fclk_div4.hw, }, 868 { .hw = &meson8b_fclk_div3.hw, }, 869 { .hw = &meson8b_fclk_div5.hw, }, 870 { .hw = &meson8b_fclk_div7.hw, }, 871 { .fw_name = "xtal", .name = "xtal", .index = -1, }, 872 }, 873 .num_parents = 5, 874 .flags = CLK_SET_RATE_PARENT, 875 }, 876 }; 877 878 static struct clk_regmap meson8b_nand_clk_div = { 879 .data = &(struct clk_regmap_div_data){ 880 .offset = HHI_NAND_CLK_CNTL, 881 .shift = 0, 882 .width = 7, 883 .flags = CLK_DIVIDER_ROUND_CLOSEST, 884 }, 885 .hw.init = &(struct clk_init_data){ 886 .name = "nand_clk_div", 887 .ops = &clk_regmap_divider_ops, 888 .parent_hws = (const struct clk_hw *[]) { 889 &meson8b_nand_clk_sel.hw 890 }, 891 .num_parents = 1, 892 .flags = CLK_SET_RATE_PARENT, 893 }, 894 }; 895 896 static struct clk_regmap meson8b_nand_clk_gate = { 897 .data = &(struct clk_regmap_gate_data){ 898 .offset = HHI_NAND_CLK_CNTL, 899 .bit_idx = 8, 900 }, 901 .hw.init = &(struct clk_init_data){ 902 .name = "nand_clk_gate", 903 .ops = &clk_regmap_gate_ops, 904 .parent_hws = (const struct clk_hw *[]) { 905 &meson8b_nand_clk_div.hw 906 }, 907 .num_parents = 1, 908 .flags = CLK_SET_RATE_PARENT, 909 }, 910 }; 911 912 static struct clk_fixed_factor meson8b_cpu_clk_div2 = { 913 .mult = 1, 914 .div = 2, 915 .hw.init = &(struct clk_init_data){ 916 .name = "cpu_clk_div2", 917 .ops = &clk_fixed_factor_ops, 918 .parent_hws = (const struct clk_hw *[]) { 919 &meson8b_cpu_clk.hw 920 }, 921 .num_parents = 1, 922 }, 923 }; 924 925 static struct clk_fixed_factor meson8b_cpu_clk_div3 = { 926 .mult = 1, 927 .div = 3, 928 .hw.init = &(struct clk_init_data){ 929 .name = "cpu_clk_div3", 930 .ops = &clk_fixed_factor_ops, 931 .parent_hws = (const struct clk_hw *[]) { 932 &meson8b_cpu_clk.hw 933 }, 934 .num_parents = 1, 935 }, 936 }; 937 938 static struct clk_fixed_factor meson8b_cpu_clk_div4 = { 939 .mult = 1, 940 .div = 4, 941 .hw.init = &(struct clk_init_data){ 942 .name = "cpu_clk_div4", 943 .ops = &clk_fixed_factor_ops, 944 .parent_hws = (const struct clk_hw *[]) { 945 &meson8b_cpu_clk.hw 946 }, 947 .num_parents = 1, 948 }, 949 }; 950 951 static struct clk_fixed_factor meson8b_cpu_clk_div5 = { 952 .mult = 1, 953 .div = 5, 954 .hw.init = &(struct clk_init_data){ 955 .name = "cpu_clk_div5", 956 .ops = &clk_fixed_factor_ops, 957 .parent_hws = (const struct clk_hw *[]) { 958 &meson8b_cpu_clk.hw 959 }, 960 .num_parents = 1, 961 }, 962 }; 963 964 static struct clk_fixed_factor meson8b_cpu_clk_div6 = { 965 .mult = 1, 966 .div = 6, 967 .hw.init = &(struct clk_init_data){ 968 .name = "cpu_clk_div6", 969 .ops = &clk_fixed_factor_ops, 970 .parent_hws = (const struct clk_hw *[]) { 971 &meson8b_cpu_clk.hw 972 }, 973 .num_parents = 1, 974 }, 975 }; 976 977 static struct clk_fixed_factor meson8b_cpu_clk_div7 = { 978 .mult = 1, 979 .div = 7, 980 .hw.init = &(struct clk_init_data){ 981 .name = "cpu_clk_div7", 982 .ops = &clk_fixed_factor_ops, 983 .parent_hws = (const struct clk_hw *[]) { 984 &meson8b_cpu_clk.hw 985 }, 986 .num_parents = 1, 987 }, 988 }; 989 990 static struct clk_fixed_factor meson8b_cpu_clk_div8 = { 991 .mult = 1, 992 .div = 8, 993 .hw.init = &(struct clk_init_data){ 994 .name = "cpu_clk_div8", 995 .ops = &clk_fixed_factor_ops, 996 .parent_hws = (const struct clk_hw *[]) { 997 &meson8b_cpu_clk.hw 998 }, 999 .num_parents = 1, 1000 }, 1001 }; 1002 1003 static u32 mux_table_apb[] = { 1, 2, 3, 4, 5, 6, 7 }; 1004 static struct clk_regmap meson8b_apb_clk_sel = { 1005 .data = &(struct clk_regmap_mux_data){ 1006 .offset = HHI_SYS_CPU_CLK_CNTL1, 1007 .mask = 0x7, 1008 .shift = 3, 1009 .table = mux_table_apb, 1010 }, 1011 .hw.init = &(struct clk_init_data){ 1012 .name = "apb_clk_sel", 1013 .ops = &clk_regmap_mux_ops, 1014 .parent_hws = (const struct clk_hw *[]) { 1015 &meson8b_cpu_clk_div2.hw, 1016 &meson8b_cpu_clk_div3.hw, 1017 &meson8b_cpu_clk_div4.hw, 1018 &meson8b_cpu_clk_div5.hw, 1019 &meson8b_cpu_clk_div6.hw, 1020 &meson8b_cpu_clk_div7.hw, 1021 &meson8b_cpu_clk_div8.hw, 1022 }, 1023 .num_parents = 7, 1024 }, 1025 }; 1026 1027 static struct clk_regmap meson8b_apb_clk_gate = { 1028 .data = &(struct clk_regmap_gate_data){ 1029 .offset = HHI_SYS_CPU_CLK_CNTL1, 1030 .bit_idx = 16, 1031 .flags = CLK_GATE_SET_TO_DISABLE, 1032 }, 1033 .hw.init = &(struct clk_init_data){ 1034 .name = "apb_clk_dis", 1035 .ops = &clk_regmap_gate_ro_ops, 1036 .parent_hws = (const struct clk_hw *[]) { 1037 &meson8b_apb_clk_sel.hw 1038 }, 1039 .num_parents = 1, 1040 .flags = CLK_SET_RATE_PARENT, 1041 }, 1042 }; 1043 1044 static struct clk_regmap meson8b_periph_clk_sel = { 1045 .data = &(struct clk_regmap_mux_data){ 1046 .offset = HHI_SYS_CPU_CLK_CNTL1, 1047 .mask = 0x7, 1048 .shift = 6, 1049 }, 1050 .hw.init = &(struct clk_init_data){ 1051 .name = "periph_clk_sel", 1052 .ops = &clk_regmap_mux_ops, 1053 .parent_hws = (const struct clk_hw *[]) { 1054 &meson8b_cpu_clk_div2.hw, 1055 &meson8b_cpu_clk_div3.hw, 1056 &meson8b_cpu_clk_div4.hw, 1057 &meson8b_cpu_clk_div5.hw, 1058 &meson8b_cpu_clk_div6.hw, 1059 &meson8b_cpu_clk_div7.hw, 1060 &meson8b_cpu_clk_div8.hw, 1061 }, 1062 .num_parents = 7, 1063 }, 1064 }; 1065 1066 static struct clk_regmap meson8b_periph_clk_gate = { 1067 .data = &(struct clk_regmap_gate_data){ 1068 .offset = HHI_SYS_CPU_CLK_CNTL1, 1069 .bit_idx = 17, 1070 .flags = CLK_GATE_SET_TO_DISABLE, 1071 }, 1072 .hw.init = &(struct clk_init_data){ 1073 .name = "periph_clk_dis", 1074 .ops = &clk_regmap_gate_ro_ops, 1075 .parent_hws = (const struct clk_hw *[]) { 1076 &meson8b_periph_clk_sel.hw 1077 }, 1078 .num_parents = 1, 1079 .flags = CLK_SET_RATE_PARENT, 1080 }, 1081 }; 1082 1083 static u32 mux_table_axi[] = { 1, 2, 3, 4, 5, 6, 7 }; 1084 static struct clk_regmap meson8b_axi_clk_sel = { 1085 .data = &(struct clk_regmap_mux_data){ 1086 .offset = HHI_SYS_CPU_CLK_CNTL1, 1087 .mask = 0x7, 1088 .shift = 9, 1089 .table = mux_table_axi, 1090 }, 1091 .hw.init = &(struct clk_init_data){ 1092 .name = "axi_clk_sel", 1093 .ops = &clk_regmap_mux_ops, 1094 .parent_hws = (const struct clk_hw *[]) { 1095 &meson8b_cpu_clk_div2.hw, 1096 &meson8b_cpu_clk_div3.hw, 1097 &meson8b_cpu_clk_div4.hw, 1098 &meson8b_cpu_clk_div5.hw, 1099 &meson8b_cpu_clk_div6.hw, 1100 &meson8b_cpu_clk_div7.hw, 1101 &meson8b_cpu_clk_div8.hw, 1102 }, 1103 .num_parents = 7, 1104 }, 1105 }; 1106 1107 static struct clk_regmap meson8b_axi_clk_gate = { 1108 .data = &(struct clk_regmap_gate_data){ 1109 .offset = HHI_SYS_CPU_CLK_CNTL1, 1110 .bit_idx = 18, 1111 .flags = CLK_GATE_SET_TO_DISABLE, 1112 }, 1113 .hw.init = &(struct clk_init_data){ 1114 .name = "axi_clk_dis", 1115 .ops = &clk_regmap_gate_ro_ops, 1116 .parent_hws = (const struct clk_hw *[]) { 1117 &meson8b_axi_clk_sel.hw 1118 }, 1119 .num_parents = 1, 1120 .flags = CLK_SET_RATE_PARENT, 1121 }, 1122 }; 1123 1124 static struct clk_regmap meson8b_l2_dram_clk_sel = { 1125 .data = &(struct clk_regmap_mux_data){ 1126 .offset = HHI_SYS_CPU_CLK_CNTL1, 1127 .mask = 0x7, 1128 .shift = 12, 1129 }, 1130 .hw.init = &(struct clk_init_data){ 1131 .name = "l2_dram_clk_sel", 1132 .ops = &clk_regmap_mux_ops, 1133 .parent_hws = (const struct clk_hw *[]) { 1134 &meson8b_cpu_clk_div2.hw, 1135 &meson8b_cpu_clk_div3.hw, 1136 &meson8b_cpu_clk_div4.hw, 1137 &meson8b_cpu_clk_div5.hw, 1138 &meson8b_cpu_clk_div6.hw, 1139 &meson8b_cpu_clk_div7.hw, 1140 &meson8b_cpu_clk_div8.hw, 1141 }, 1142 .num_parents = 7, 1143 }, 1144 }; 1145 1146 static struct clk_regmap meson8b_l2_dram_clk_gate = { 1147 .data = &(struct clk_regmap_gate_data){ 1148 .offset = HHI_SYS_CPU_CLK_CNTL1, 1149 .bit_idx = 19, 1150 .flags = CLK_GATE_SET_TO_DISABLE, 1151 }, 1152 .hw.init = &(struct clk_init_data){ 1153 .name = "l2_dram_clk_dis", 1154 .ops = &clk_regmap_gate_ro_ops, 1155 .parent_hws = (const struct clk_hw *[]) { 1156 &meson8b_l2_dram_clk_sel.hw 1157 }, 1158 .num_parents = 1, 1159 .flags = CLK_SET_RATE_PARENT, 1160 }, 1161 }; 1162 1163 /* also called LVDS_CLK_EN */ 1164 static struct clk_regmap meson8b_vid_pll_lvds_en = { 1165 .data = &(struct clk_regmap_gate_data){ 1166 .offset = HHI_VID_DIVIDER_CNTL, 1167 .bit_idx = 11, 1168 }, 1169 .hw.init = &(struct clk_init_data){ 1170 .name = "vid_pll_lvds_en", 1171 .ops = &clk_regmap_gate_ops, 1172 .parent_hws = (const struct clk_hw *[]) { 1173 &meson8b_hdmi_pll_lvds_out.hw 1174 }, 1175 .num_parents = 1, 1176 .flags = CLK_SET_RATE_PARENT, 1177 }, 1178 }; 1179 1180 static struct clk_regmap meson8b_vid_pll_in_sel = { 1181 .data = &(struct clk_regmap_mux_data){ 1182 .offset = HHI_VID_DIVIDER_CNTL, 1183 .mask = 0x1, 1184 .shift = 15, 1185 }, 1186 .hw.init = &(struct clk_init_data){ 1187 .name = "vid_pll_in_sel", 1188 .ops = &clk_regmap_mux_ops, 1189 /* 1190 * TODO: depending on the SoC there is also a second parent: 1191 * Meson8: unknown 1192 * Meson8b: hdmi_pll_dco 1193 * Meson8m2: vid2_pll 1194 */ 1195 .parent_hws = (const struct clk_hw *[]) { 1196 &meson8b_vid_pll_lvds_en.hw 1197 }, 1198 .num_parents = 1, 1199 .flags = CLK_SET_RATE_PARENT, 1200 }, 1201 }; 1202 1203 static struct clk_regmap meson8b_vid_pll_in_en = { 1204 .data = &(struct clk_regmap_gate_data){ 1205 .offset = HHI_VID_DIVIDER_CNTL, 1206 .bit_idx = 16, 1207 }, 1208 .hw.init = &(struct clk_init_data){ 1209 .name = "vid_pll_in_en", 1210 .ops = &clk_regmap_gate_ops, 1211 .parent_hws = (const struct clk_hw *[]) { 1212 &meson8b_vid_pll_in_sel.hw 1213 }, 1214 .num_parents = 1, 1215 .flags = CLK_SET_RATE_PARENT, 1216 }, 1217 }; 1218 1219 static struct clk_regmap meson8b_vid_pll_pre_div = { 1220 .data = &(struct clk_regmap_div_data){ 1221 .offset = HHI_VID_DIVIDER_CNTL, 1222 .shift = 4, 1223 .width = 3, 1224 }, 1225 .hw.init = &(struct clk_init_data){ 1226 .name = "vid_pll_pre_div", 1227 .ops = &clk_regmap_divider_ops, 1228 .parent_hws = (const struct clk_hw *[]) { 1229 &meson8b_vid_pll_in_en.hw 1230 }, 1231 .num_parents = 1, 1232 .flags = CLK_SET_RATE_PARENT, 1233 }, 1234 }; 1235 1236 static struct clk_regmap meson8b_vid_pll_post_div = { 1237 .data = &(struct clk_regmap_div_data){ 1238 .offset = HHI_VID_DIVIDER_CNTL, 1239 .shift = 12, 1240 .width = 3, 1241 }, 1242 .hw.init = &(struct clk_init_data){ 1243 .name = "vid_pll_post_div", 1244 .ops = &clk_regmap_divider_ops, 1245 .parent_hws = (const struct clk_hw *[]) { 1246 &meson8b_vid_pll_pre_div.hw 1247 }, 1248 .num_parents = 1, 1249 .flags = CLK_SET_RATE_PARENT, 1250 }, 1251 }; 1252 1253 static struct clk_regmap meson8b_vid_pll = { 1254 .data = &(struct clk_regmap_mux_data){ 1255 .offset = HHI_VID_DIVIDER_CNTL, 1256 .mask = 0x3, 1257 .shift = 8, 1258 }, 1259 .hw.init = &(struct clk_init_data){ 1260 .name = "vid_pll", 1261 .ops = &clk_regmap_mux_ops, 1262 /* TODO: parent 0x2 is vid_pll_pre_div_mult7_div2 */ 1263 .parent_hws = (const struct clk_hw *[]) { 1264 &meson8b_vid_pll_pre_div.hw, 1265 &meson8b_vid_pll_post_div.hw, 1266 }, 1267 .num_parents = 2, 1268 .flags = CLK_SET_RATE_PARENT, 1269 }, 1270 }; 1271 1272 static struct clk_regmap meson8b_vid_pll_final_div = { 1273 .data = &(struct clk_regmap_div_data){ 1274 .offset = HHI_VID_CLK_DIV, 1275 .shift = 0, 1276 .width = 8, 1277 }, 1278 .hw.init = &(struct clk_init_data){ 1279 .name = "vid_pll_final_div", 1280 .ops = &clk_regmap_divider_ops, 1281 .parent_hws = (const struct clk_hw *[]) { 1282 &meson8b_vid_pll.hw 1283 }, 1284 .num_parents = 1, 1285 .flags = CLK_SET_RATE_PARENT, 1286 }, 1287 }; 1288 1289 static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = { 1290 &meson8b_vid_pll_final_div.hw, 1291 &meson8b_fclk_div4.hw, 1292 &meson8b_fclk_div3.hw, 1293 &meson8b_fclk_div5.hw, 1294 &meson8b_vid_pll_final_div.hw, 1295 &meson8b_fclk_div7.hw, 1296 &meson8b_mpll1.hw, 1297 }; 1298 1299 static struct clk_regmap meson8b_vclk_in_sel = { 1300 .data = &(struct clk_regmap_mux_data){ 1301 .offset = HHI_VID_CLK_CNTL, 1302 .mask = 0x7, 1303 .shift = 16, 1304 }, 1305 .hw.init = &(struct clk_init_data){ 1306 .name = "vclk_in_sel", 1307 .ops = &clk_regmap_mux_ops, 1308 .parent_hws = meson8b_vclk_mux_parent_hws, 1309 .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws), 1310 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 1311 }, 1312 }; 1313 1314 static struct clk_regmap meson8b_vclk_in_en = { 1315 .data = &(struct clk_regmap_gate_data){ 1316 .offset = HHI_VID_CLK_DIV, 1317 .bit_idx = 16, 1318 }, 1319 .hw.init = &(struct clk_init_data){ 1320 .name = "vclk_in_en", 1321 .ops = &clk_regmap_gate_ops, 1322 .parent_hws = (const struct clk_hw *[]) { 1323 &meson8b_vclk_in_sel.hw 1324 }, 1325 .num_parents = 1, 1326 .flags = CLK_SET_RATE_PARENT, 1327 }, 1328 }; 1329 1330 static struct clk_regmap meson8b_vclk_en = { 1331 .data = &(struct clk_regmap_gate_data){ 1332 .offset = HHI_VID_CLK_CNTL, 1333 .bit_idx = 19, 1334 }, 1335 .hw.init = &(struct clk_init_data){ 1336 .name = "vclk_en", 1337 .ops = &clk_regmap_gate_ops, 1338 .parent_hws = (const struct clk_hw *[]) { 1339 &meson8b_vclk_in_en.hw 1340 }, 1341 .num_parents = 1, 1342 .flags = CLK_SET_RATE_PARENT, 1343 }, 1344 }; 1345 1346 static struct clk_regmap meson8b_vclk_div1_gate = { 1347 .data = &(struct clk_regmap_gate_data){ 1348 .offset = HHI_VID_CLK_CNTL, 1349 .bit_idx = 0, 1350 }, 1351 .hw.init = &(struct clk_init_data){ 1352 .name = "vclk_div1_en", 1353 .ops = &clk_regmap_gate_ops, 1354 .parent_hws = (const struct clk_hw *[]) { 1355 &meson8b_vclk_en.hw 1356 }, 1357 .num_parents = 1, 1358 .flags = CLK_SET_RATE_PARENT, 1359 }, 1360 }; 1361 1362 static struct clk_fixed_factor meson8b_vclk_div2_div = { 1363 .mult = 1, 1364 .div = 2, 1365 .hw.init = &(struct clk_init_data){ 1366 .name = "vclk_div2", 1367 .ops = &clk_fixed_factor_ops, 1368 .parent_hws = (const struct clk_hw *[]) { 1369 &meson8b_vclk_en.hw 1370 }, 1371 .num_parents = 1, 1372 .flags = CLK_SET_RATE_PARENT, 1373 } 1374 }; 1375 1376 static struct clk_regmap meson8b_vclk_div2_div_gate = { 1377 .data = &(struct clk_regmap_gate_data){ 1378 .offset = HHI_VID_CLK_CNTL, 1379 .bit_idx = 1, 1380 }, 1381 .hw.init = &(struct clk_init_data){ 1382 .name = "vclk_div2_en", 1383 .ops = &clk_regmap_gate_ops, 1384 .parent_hws = (const struct clk_hw *[]) { 1385 &meson8b_vclk_div2_div.hw 1386 }, 1387 .num_parents = 1, 1388 .flags = CLK_SET_RATE_PARENT, 1389 }, 1390 }; 1391 1392 static struct clk_fixed_factor meson8b_vclk_div4_div = { 1393 .mult = 1, 1394 .div = 4, 1395 .hw.init = &(struct clk_init_data){ 1396 .name = "vclk_div4", 1397 .ops = &clk_fixed_factor_ops, 1398 .parent_hws = (const struct clk_hw *[]) { 1399 &meson8b_vclk_en.hw 1400 }, 1401 .num_parents = 1, 1402 .flags = CLK_SET_RATE_PARENT, 1403 } 1404 }; 1405 1406 static struct clk_regmap meson8b_vclk_div4_div_gate = { 1407 .data = &(struct clk_regmap_gate_data){ 1408 .offset = HHI_VID_CLK_CNTL, 1409 .bit_idx = 2, 1410 }, 1411 .hw.init = &(struct clk_init_data){ 1412 .name = "vclk_div4_en", 1413 .ops = &clk_regmap_gate_ops, 1414 .parent_hws = (const struct clk_hw *[]) { 1415 &meson8b_vclk_div4_div.hw 1416 }, 1417 .num_parents = 1, 1418 .flags = CLK_SET_RATE_PARENT, 1419 }, 1420 }; 1421 1422 static struct clk_fixed_factor meson8b_vclk_div6_div = { 1423 .mult = 1, 1424 .div = 6, 1425 .hw.init = &(struct clk_init_data){ 1426 .name = "vclk_div6", 1427 .ops = &clk_fixed_factor_ops, 1428 .parent_hws = (const struct clk_hw *[]) { 1429 &meson8b_vclk_en.hw 1430 }, 1431 .num_parents = 1, 1432 .flags = CLK_SET_RATE_PARENT, 1433 } 1434 }; 1435 1436 static struct clk_regmap meson8b_vclk_div6_div_gate = { 1437 .data = &(struct clk_regmap_gate_data){ 1438 .offset = HHI_VID_CLK_CNTL, 1439 .bit_idx = 3, 1440 }, 1441 .hw.init = &(struct clk_init_data){ 1442 .name = "vclk_div6_en", 1443 .ops = &clk_regmap_gate_ops, 1444 .parent_hws = (const struct clk_hw *[]) { 1445 &meson8b_vclk_div6_div.hw 1446 }, 1447 .num_parents = 1, 1448 .flags = CLK_SET_RATE_PARENT, 1449 }, 1450 }; 1451 1452 static struct clk_fixed_factor meson8b_vclk_div12_div = { 1453 .mult = 1, 1454 .div = 12, 1455 .hw.init = &(struct clk_init_data){ 1456 .name = "vclk_div12", 1457 .ops = &clk_fixed_factor_ops, 1458 .parent_hws = (const struct clk_hw *[]) { 1459 &meson8b_vclk_en.hw 1460 }, 1461 .num_parents = 1, 1462 .flags = CLK_SET_RATE_PARENT, 1463 } 1464 }; 1465 1466 static struct clk_regmap meson8b_vclk_div12_div_gate = { 1467 .data = &(struct clk_regmap_gate_data){ 1468 .offset = HHI_VID_CLK_CNTL, 1469 .bit_idx = 4, 1470 }, 1471 .hw.init = &(struct clk_init_data){ 1472 .name = "vclk_div12_en", 1473 .ops = &clk_regmap_gate_ops, 1474 .parent_hws = (const struct clk_hw *[]) { 1475 &meson8b_vclk_div12_div.hw 1476 }, 1477 .num_parents = 1, 1478 .flags = CLK_SET_RATE_PARENT, 1479 }, 1480 }; 1481 1482 static struct clk_regmap meson8b_vclk2_in_sel = { 1483 .data = &(struct clk_regmap_mux_data){ 1484 .offset = HHI_VIID_CLK_CNTL, 1485 .mask = 0x7, 1486 .shift = 16, 1487 }, 1488 .hw.init = &(struct clk_init_data){ 1489 .name = "vclk2_in_sel", 1490 .ops = &clk_regmap_mux_ops, 1491 .parent_hws = meson8b_vclk_mux_parent_hws, 1492 .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws), 1493 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 1494 }, 1495 }; 1496 1497 static struct clk_regmap meson8b_vclk2_clk_in_en = { 1498 .data = &(struct clk_regmap_gate_data){ 1499 .offset = HHI_VIID_CLK_DIV, 1500 .bit_idx = 16, 1501 }, 1502 .hw.init = &(struct clk_init_data){ 1503 .name = "vclk2_in_en", 1504 .ops = &clk_regmap_gate_ops, 1505 .parent_hws = (const struct clk_hw *[]) { 1506 &meson8b_vclk2_in_sel.hw 1507 }, 1508 .num_parents = 1, 1509 .flags = CLK_SET_RATE_PARENT, 1510 }, 1511 }; 1512 1513 static struct clk_regmap meson8b_vclk2_clk_en = { 1514 .data = &(struct clk_regmap_gate_data){ 1515 .offset = HHI_VIID_CLK_DIV, 1516 .bit_idx = 19, 1517 }, 1518 .hw.init = &(struct clk_init_data){ 1519 .name = "vclk2_en", 1520 .ops = &clk_regmap_gate_ops, 1521 .parent_hws = (const struct clk_hw *[]) { 1522 &meson8b_vclk2_clk_in_en.hw 1523 }, 1524 .num_parents = 1, 1525 .flags = CLK_SET_RATE_PARENT, 1526 }, 1527 }; 1528 1529 static struct clk_regmap meson8b_vclk2_div1_gate = { 1530 .data = &(struct clk_regmap_gate_data){ 1531 .offset = HHI_VIID_CLK_DIV, 1532 .bit_idx = 0, 1533 }, 1534 .hw.init = &(struct clk_init_data){ 1535 .name = "vclk2_div1_en", 1536 .ops = &clk_regmap_gate_ops, 1537 .parent_hws = (const struct clk_hw *[]) { 1538 &meson8b_vclk2_clk_en.hw 1539 }, 1540 .num_parents = 1, 1541 .flags = CLK_SET_RATE_PARENT, 1542 }, 1543 }; 1544 1545 static struct clk_fixed_factor meson8b_vclk2_div2_div = { 1546 .mult = 1, 1547 .div = 2, 1548 .hw.init = &(struct clk_init_data){ 1549 .name = "vclk2_div2", 1550 .ops = &clk_fixed_factor_ops, 1551 .parent_hws = (const struct clk_hw *[]) { 1552 &meson8b_vclk2_clk_en.hw 1553 }, 1554 .num_parents = 1, 1555 .flags = CLK_SET_RATE_PARENT, 1556 } 1557 }; 1558 1559 static struct clk_regmap meson8b_vclk2_div2_div_gate = { 1560 .data = &(struct clk_regmap_gate_data){ 1561 .offset = HHI_VIID_CLK_DIV, 1562 .bit_idx = 1, 1563 }, 1564 .hw.init = &(struct clk_init_data){ 1565 .name = "vclk2_div2_en", 1566 .ops = &clk_regmap_gate_ops, 1567 .parent_hws = (const struct clk_hw *[]) { 1568 &meson8b_vclk2_div2_div.hw 1569 }, 1570 .num_parents = 1, 1571 .flags = CLK_SET_RATE_PARENT, 1572 }, 1573 }; 1574 1575 static struct clk_fixed_factor meson8b_vclk2_div4_div = { 1576 .mult = 1, 1577 .div = 4, 1578 .hw.init = &(struct clk_init_data){ 1579 .name = "vclk2_div4", 1580 .ops = &clk_fixed_factor_ops, 1581 .parent_hws = (const struct clk_hw *[]) { 1582 &meson8b_vclk2_clk_en.hw 1583 }, 1584 .num_parents = 1, 1585 .flags = CLK_SET_RATE_PARENT, 1586 } 1587 }; 1588 1589 static struct clk_regmap meson8b_vclk2_div4_div_gate = { 1590 .data = &(struct clk_regmap_gate_data){ 1591 .offset = HHI_VIID_CLK_DIV, 1592 .bit_idx = 2, 1593 }, 1594 .hw.init = &(struct clk_init_data){ 1595 .name = "vclk2_div4_en", 1596 .ops = &clk_regmap_gate_ops, 1597 .parent_hws = (const struct clk_hw *[]) { 1598 &meson8b_vclk2_div4_div.hw 1599 }, 1600 .num_parents = 1, 1601 .flags = CLK_SET_RATE_PARENT, 1602 }, 1603 }; 1604 1605 static struct clk_fixed_factor meson8b_vclk2_div6_div = { 1606 .mult = 1, 1607 .div = 6, 1608 .hw.init = &(struct clk_init_data){ 1609 .name = "vclk2_div6", 1610 .ops = &clk_fixed_factor_ops, 1611 .parent_hws = (const struct clk_hw *[]) { 1612 &meson8b_vclk2_clk_en.hw 1613 }, 1614 .num_parents = 1, 1615 .flags = CLK_SET_RATE_PARENT, 1616 } 1617 }; 1618 1619 static struct clk_regmap meson8b_vclk2_div6_div_gate = { 1620 .data = &(struct clk_regmap_gate_data){ 1621 .offset = HHI_VIID_CLK_DIV, 1622 .bit_idx = 3, 1623 }, 1624 .hw.init = &(struct clk_init_data){ 1625 .name = "vclk2_div6_en", 1626 .ops = &clk_regmap_gate_ops, 1627 .parent_hws = (const struct clk_hw *[]) { 1628 &meson8b_vclk2_div6_div.hw 1629 }, 1630 .num_parents = 1, 1631 .flags = CLK_SET_RATE_PARENT, 1632 }, 1633 }; 1634 1635 static struct clk_fixed_factor meson8b_vclk2_div12_div = { 1636 .mult = 1, 1637 .div = 12, 1638 .hw.init = &(struct clk_init_data){ 1639 .name = "vclk2_div12", 1640 .ops = &clk_fixed_factor_ops, 1641 .parent_hws = (const struct clk_hw *[]) { 1642 &meson8b_vclk2_clk_en.hw 1643 }, 1644 .num_parents = 1, 1645 .flags = CLK_SET_RATE_PARENT, 1646 } 1647 }; 1648 1649 static struct clk_regmap meson8b_vclk2_div12_div_gate = { 1650 .data = &(struct clk_regmap_gate_data){ 1651 .offset = HHI_VIID_CLK_DIV, 1652 .bit_idx = 4, 1653 }, 1654 .hw.init = &(struct clk_init_data){ 1655 .name = "vclk2_div12_en", 1656 .ops = &clk_regmap_gate_ops, 1657 .parent_hws = (const struct clk_hw *[]) { 1658 &meson8b_vclk2_div12_div.hw 1659 }, 1660 .num_parents = 1, 1661 .flags = CLK_SET_RATE_PARENT, 1662 }, 1663 }; 1664 1665 static const struct clk_hw *meson8b_vclk_enc_mux_parent_hws[] = { 1666 &meson8b_vclk_div1_gate.hw, 1667 &meson8b_vclk_div2_div_gate.hw, 1668 &meson8b_vclk_div4_div_gate.hw, 1669 &meson8b_vclk_div6_div_gate.hw, 1670 &meson8b_vclk_div12_div_gate.hw, 1671 }; 1672 1673 static struct clk_regmap meson8b_cts_enct_sel = { 1674 .data = &(struct clk_regmap_mux_data){ 1675 .offset = HHI_VID_CLK_DIV, 1676 .mask = 0xf, 1677 .shift = 20, 1678 }, 1679 .hw.init = &(struct clk_init_data){ 1680 .name = "cts_enct_sel", 1681 .ops = &clk_regmap_mux_ops, 1682 .parent_hws = meson8b_vclk_enc_mux_parent_hws, 1683 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws), 1684 .flags = CLK_SET_RATE_PARENT, 1685 }, 1686 }; 1687 1688 static struct clk_regmap meson8b_cts_enct = { 1689 .data = &(struct clk_regmap_gate_data){ 1690 .offset = HHI_VID_CLK_CNTL2, 1691 .bit_idx = 1, 1692 }, 1693 .hw.init = &(struct clk_init_data){ 1694 .name = "cts_enct", 1695 .ops = &clk_regmap_gate_ops, 1696 .parent_hws = (const struct clk_hw *[]) { 1697 &meson8b_cts_enct_sel.hw 1698 }, 1699 .num_parents = 1, 1700 .flags = CLK_SET_RATE_PARENT, 1701 }, 1702 }; 1703 1704 static struct clk_regmap meson8b_cts_encp_sel = { 1705 .data = &(struct clk_regmap_mux_data){ 1706 .offset = HHI_VID_CLK_DIV, 1707 .mask = 0xf, 1708 .shift = 24, 1709 }, 1710 .hw.init = &(struct clk_init_data){ 1711 .name = "cts_encp_sel", 1712 .ops = &clk_regmap_mux_ops, 1713 .parent_hws = meson8b_vclk_enc_mux_parent_hws, 1714 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws), 1715 .flags = CLK_SET_RATE_PARENT, 1716 }, 1717 }; 1718 1719 static struct clk_regmap meson8b_cts_encp = { 1720 .data = &(struct clk_regmap_gate_data){ 1721 .offset = HHI_VID_CLK_CNTL2, 1722 .bit_idx = 2, 1723 }, 1724 .hw.init = &(struct clk_init_data){ 1725 .name = "cts_encp", 1726 .ops = &clk_regmap_gate_ops, 1727 .parent_hws = (const struct clk_hw *[]) { 1728 &meson8b_cts_encp_sel.hw 1729 }, 1730 .num_parents = 1, 1731 .flags = CLK_SET_RATE_PARENT, 1732 }, 1733 }; 1734 1735 static struct clk_regmap meson8b_cts_enci_sel = { 1736 .data = &(struct clk_regmap_mux_data){ 1737 .offset = HHI_VID_CLK_DIV, 1738 .mask = 0xf, 1739 .shift = 28, 1740 }, 1741 .hw.init = &(struct clk_init_data){ 1742 .name = "cts_enci_sel", 1743 .ops = &clk_regmap_mux_ops, 1744 .parent_hws = meson8b_vclk_enc_mux_parent_hws, 1745 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws), 1746 .flags = CLK_SET_RATE_PARENT, 1747 }, 1748 }; 1749 1750 static struct clk_regmap meson8b_cts_enci = { 1751 .data = &(struct clk_regmap_gate_data){ 1752 .offset = HHI_VID_CLK_CNTL2, 1753 .bit_idx = 0, 1754 }, 1755 .hw.init = &(struct clk_init_data){ 1756 .name = "cts_enci", 1757 .ops = &clk_regmap_gate_ops, 1758 .parent_hws = (const struct clk_hw *[]) { 1759 &meson8b_cts_enci_sel.hw 1760 }, 1761 .num_parents = 1, 1762 .flags = CLK_SET_RATE_PARENT, 1763 }, 1764 }; 1765 1766 static struct clk_regmap meson8b_hdmi_tx_pixel_sel = { 1767 .data = &(struct clk_regmap_mux_data){ 1768 .offset = HHI_HDMI_CLK_CNTL, 1769 .mask = 0xf, 1770 .shift = 16, 1771 }, 1772 .hw.init = &(struct clk_init_data){ 1773 .name = "hdmi_tx_pixel_sel", 1774 .ops = &clk_regmap_mux_ops, 1775 .parent_hws = meson8b_vclk_enc_mux_parent_hws, 1776 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws), 1777 .flags = CLK_SET_RATE_PARENT, 1778 }, 1779 }; 1780 1781 static struct clk_regmap meson8b_hdmi_tx_pixel = { 1782 .data = &(struct clk_regmap_gate_data){ 1783 .offset = HHI_VID_CLK_CNTL2, 1784 .bit_idx = 5, 1785 }, 1786 .hw.init = &(struct clk_init_data){ 1787 .name = "hdmi_tx_pixel", 1788 .ops = &clk_regmap_gate_ops, 1789 .parent_hws = (const struct clk_hw *[]) { 1790 &meson8b_hdmi_tx_pixel_sel.hw 1791 }, 1792 .num_parents = 1, 1793 .flags = CLK_SET_RATE_PARENT, 1794 }, 1795 }; 1796 1797 static const struct clk_hw *meson8b_vclk2_enc_mux_parent_hws[] = { 1798 &meson8b_vclk2_div1_gate.hw, 1799 &meson8b_vclk2_div2_div_gate.hw, 1800 &meson8b_vclk2_div4_div_gate.hw, 1801 &meson8b_vclk2_div6_div_gate.hw, 1802 &meson8b_vclk2_div12_div_gate.hw, 1803 }; 1804 1805 static struct clk_regmap meson8b_cts_encl_sel = { 1806 .data = &(struct clk_regmap_mux_data){ 1807 .offset = HHI_VIID_CLK_DIV, 1808 .mask = 0xf, 1809 .shift = 12, 1810 }, 1811 .hw.init = &(struct clk_init_data){ 1812 .name = "cts_encl_sel", 1813 .ops = &clk_regmap_mux_ops, 1814 .parent_hws = meson8b_vclk2_enc_mux_parent_hws, 1815 .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws), 1816 .flags = CLK_SET_RATE_PARENT, 1817 }, 1818 }; 1819 1820 static struct clk_regmap meson8b_cts_encl = { 1821 .data = &(struct clk_regmap_gate_data){ 1822 .offset = HHI_VID_CLK_CNTL2, 1823 .bit_idx = 3, 1824 }, 1825 .hw.init = &(struct clk_init_data){ 1826 .name = "cts_encl", 1827 .ops = &clk_regmap_gate_ops, 1828 .parent_hws = (const struct clk_hw *[]) { 1829 &meson8b_cts_encl_sel.hw 1830 }, 1831 .num_parents = 1, 1832 .flags = CLK_SET_RATE_PARENT, 1833 }, 1834 }; 1835 1836 static struct clk_regmap meson8b_cts_vdac0_sel = { 1837 .data = &(struct clk_regmap_mux_data){ 1838 .offset = HHI_VIID_CLK_DIV, 1839 .mask = 0xf, 1840 .shift = 28, 1841 }, 1842 .hw.init = &(struct clk_init_data){ 1843 .name = "cts_vdac0_sel", 1844 .ops = &clk_regmap_mux_ops, 1845 .parent_hws = meson8b_vclk2_enc_mux_parent_hws, 1846 .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws), 1847 .flags = CLK_SET_RATE_PARENT, 1848 }, 1849 }; 1850 1851 static struct clk_regmap meson8b_cts_vdac0 = { 1852 .data = &(struct clk_regmap_gate_data){ 1853 .offset = HHI_VID_CLK_CNTL2, 1854 .bit_idx = 4, 1855 }, 1856 .hw.init = &(struct clk_init_data){ 1857 .name = "cts_vdac0", 1858 .ops = &clk_regmap_gate_ops, 1859 .parent_hws = (const struct clk_hw *[]) { 1860 &meson8b_cts_vdac0_sel.hw 1861 }, 1862 .num_parents = 1, 1863 .flags = CLK_SET_RATE_PARENT, 1864 }, 1865 }; 1866 1867 static struct clk_regmap meson8b_hdmi_sys_sel = { 1868 .data = &(struct clk_regmap_mux_data){ 1869 .offset = HHI_HDMI_CLK_CNTL, 1870 .mask = 0x3, 1871 .shift = 9, 1872 .flags = CLK_MUX_ROUND_CLOSEST, 1873 }, 1874 .hw.init = &(struct clk_init_data){ 1875 .name = "hdmi_sys_sel", 1876 .ops = &clk_regmap_mux_ops, 1877 /* FIXME: all other parents are unknown */ 1878 .parent_data = &(const struct clk_parent_data) { 1879 .fw_name = "xtal", 1880 .name = "xtal", 1881 .index = -1, 1882 }, 1883 .num_parents = 1, 1884 .flags = CLK_SET_RATE_NO_REPARENT, 1885 }, 1886 }; 1887 1888 static struct clk_regmap meson8b_hdmi_sys_div = { 1889 .data = &(struct clk_regmap_div_data){ 1890 .offset = HHI_HDMI_CLK_CNTL, 1891 .shift = 0, 1892 .width = 7, 1893 }, 1894 .hw.init = &(struct clk_init_data){ 1895 .name = "hdmi_sys_div", 1896 .ops = &clk_regmap_divider_ops, 1897 .parent_hws = (const struct clk_hw *[]) { 1898 &meson8b_hdmi_sys_sel.hw 1899 }, 1900 .num_parents = 1, 1901 .flags = CLK_SET_RATE_PARENT, 1902 }, 1903 }; 1904 1905 static struct clk_regmap meson8b_hdmi_sys = { 1906 .data = &(struct clk_regmap_gate_data){ 1907 .offset = HHI_HDMI_CLK_CNTL, 1908 .bit_idx = 8, 1909 }, 1910 .hw.init = &(struct clk_init_data) { 1911 .name = "hdmi_sys", 1912 .ops = &clk_regmap_gate_ops, 1913 .parent_hws = (const struct clk_hw *[]) { 1914 &meson8b_hdmi_sys_div.hw 1915 }, 1916 .num_parents = 1, 1917 .flags = CLK_SET_RATE_PARENT, 1918 }, 1919 }; 1920 1921 /* 1922 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) 1923 * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can 1924 * actually manage this glitch-free mux because it does top-to-bottom 1925 * updates the each clock tree and switches to the "inactive" one when 1926 * CLK_SET_RATE_GATE is set. 1927 * Meson8 only has mali_0 and no glitch-free mux. 1928 */ 1929 static const struct clk_parent_data meson8b_mali_0_1_parent_data[] = { 1930 { .fw_name = "xtal", .name = "xtal", .index = -1, }, 1931 { .hw = &meson8b_mpll2.hw, }, 1932 { .hw = &meson8b_mpll1.hw, }, 1933 { .hw = &meson8b_fclk_div7.hw, }, 1934 { .hw = &meson8b_fclk_div4.hw, }, 1935 { .hw = &meson8b_fclk_div3.hw, }, 1936 { .hw = &meson8b_fclk_div5.hw, }, 1937 }; 1938 1939 static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 }; 1940 1941 static struct clk_regmap meson8b_mali_0_sel = { 1942 .data = &(struct clk_regmap_mux_data){ 1943 .offset = HHI_MALI_CLK_CNTL, 1944 .mask = 0x7, 1945 .shift = 9, 1946 .table = meson8b_mali_0_1_mux_table, 1947 }, 1948 .hw.init = &(struct clk_init_data){ 1949 .name = "mali_0_sel", 1950 .ops = &clk_regmap_mux_ops, 1951 .parent_data = meson8b_mali_0_1_parent_data, 1952 .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data), 1953 /* 1954 * Don't propagate rate changes up because the only changeable 1955 * parents are mpll1 and mpll2 but we need those for audio and 1956 * RGMII (Ethernet). We don't want to change the audio or 1957 * Ethernet clocks when setting the GPU frequency. 1958 */ 1959 .flags = 0, 1960 }, 1961 }; 1962 1963 static struct clk_regmap meson8b_mali_0_div = { 1964 .data = &(struct clk_regmap_div_data){ 1965 .offset = HHI_MALI_CLK_CNTL, 1966 .shift = 0, 1967 .width = 7, 1968 }, 1969 .hw.init = &(struct clk_init_data){ 1970 .name = "mali_0_div", 1971 .ops = &clk_regmap_divider_ops, 1972 .parent_hws = (const struct clk_hw *[]) { 1973 &meson8b_mali_0_sel.hw 1974 }, 1975 .num_parents = 1, 1976 .flags = CLK_SET_RATE_PARENT, 1977 }, 1978 }; 1979 1980 static struct clk_regmap meson8b_mali_0 = { 1981 .data = &(struct clk_regmap_gate_data){ 1982 .offset = HHI_MALI_CLK_CNTL, 1983 .bit_idx = 8, 1984 }, 1985 .hw.init = &(struct clk_init_data){ 1986 .name = "mali_0", 1987 .ops = &clk_regmap_gate_ops, 1988 .parent_hws = (const struct clk_hw *[]) { 1989 &meson8b_mali_0_div.hw 1990 }, 1991 .num_parents = 1, 1992 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, 1993 }, 1994 }; 1995 1996 static struct clk_regmap meson8b_mali_1_sel = { 1997 .data = &(struct clk_regmap_mux_data){ 1998 .offset = HHI_MALI_CLK_CNTL, 1999 .mask = 0x7, 2000 .shift = 25, 2001 .table = meson8b_mali_0_1_mux_table, 2002 }, 2003 .hw.init = &(struct clk_init_data){ 2004 .name = "mali_1_sel", 2005 .ops = &clk_regmap_mux_ops, 2006 .parent_data = meson8b_mali_0_1_parent_data, 2007 .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data), 2008 /* 2009 * Don't propagate rate changes up because the only changeable 2010 * parents are mpll1 and mpll2 but we need those for audio and 2011 * RGMII (Ethernet). We don't want to change the audio or 2012 * Ethernet clocks when setting the GPU frequency. 2013 */ 2014 .flags = 0, 2015 }, 2016 }; 2017 2018 static struct clk_regmap meson8b_mali_1_div = { 2019 .data = &(struct clk_regmap_div_data){ 2020 .offset = HHI_MALI_CLK_CNTL, 2021 .shift = 16, 2022 .width = 7, 2023 }, 2024 .hw.init = &(struct clk_init_data){ 2025 .name = "mali_1_div", 2026 .ops = &clk_regmap_divider_ops, 2027 .parent_hws = (const struct clk_hw *[]) { 2028 &meson8b_mali_1_sel.hw 2029 }, 2030 .num_parents = 1, 2031 .flags = CLK_SET_RATE_PARENT, 2032 }, 2033 }; 2034 2035 static struct clk_regmap meson8b_mali_1 = { 2036 .data = &(struct clk_regmap_gate_data){ 2037 .offset = HHI_MALI_CLK_CNTL, 2038 .bit_idx = 24, 2039 }, 2040 .hw.init = &(struct clk_init_data){ 2041 .name = "mali_1", 2042 .ops = &clk_regmap_gate_ops, 2043 .parent_hws = (const struct clk_hw *[]) { 2044 &meson8b_mali_1_div.hw 2045 }, 2046 .num_parents = 1, 2047 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, 2048 }, 2049 }; 2050 2051 static struct clk_regmap meson8b_mali = { 2052 .data = &(struct clk_regmap_mux_data){ 2053 .offset = HHI_MALI_CLK_CNTL, 2054 .mask = 1, 2055 .shift = 31, 2056 }, 2057 .hw.init = &(struct clk_init_data){ 2058 .name = "mali", 2059 .ops = &clk_regmap_mux_ops, 2060 .parent_hws = (const struct clk_hw *[]) { 2061 &meson8b_mali_0.hw, 2062 &meson8b_mali_1.hw, 2063 }, 2064 .num_parents = 2, 2065 .flags = CLK_SET_RATE_PARENT, 2066 }, 2067 }; 2068 2069 static const struct reg_sequence meson8m2_gp_pll_init_regs[] = { 2070 { .reg = HHI_GP_PLL_CNTL2, .def = 0x59c88000 }, 2071 { .reg = HHI_GP_PLL_CNTL3, .def = 0xca463823 }, 2072 { .reg = HHI_GP_PLL_CNTL4, .def = 0x0286a027 }, 2073 { .reg = HHI_GP_PLL_CNTL5, .def = 0x00003000 }, 2074 }; 2075 2076 static const struct pll_params_table meson8m2_gp_pll_params_table[] = { 2077 PLL_PARAMS(182, 3), 2078 { /* sentinel */ }, 2079 }; 2080 2081 static struct clk_regmap meson8m2_gp_pll_dco = { 2082 .data = &(struct meson_clk_pll_data){ 2083 .en = { 2084 .reg_off = HHI_GP_PLL_CNTL, 2085 .shift = 30, 2086 .width = 1, 2087 }, 2088 .m = { 2089 .reg_off = HHI_GP_PLL_CNTL, 2090 .shift = 0, 2091 .width = 9, 2092 }, 2093 .n = { 2094 .reg_off = HHI_GP_PLL_CNTL, 2095 .shift = 9, 2096 .width = 5, 2097 }, 2098 .l = { 2099 .reg_off = HHI_GP_PLL_CNTL, 2100 .shift = 31, 2101 .width = 1, 2102 }, 2103 .rst = { 2104 .reg_off = HHI_GP_PLL_CNTL, 2105 .shift = 29, 2106 .width = 1, 2107 }, 2108 .table = meson8m2_gp_pll_params_table, 2109 .init_regs = meson8m2_gp_pll_init_regs, 2110 .init_count = ARRAY_SIZE(meson8m2_gp_pll_init_regs), 2111 }, 2112 .hw.init = &(struct clk_init_data){ 2113 .name = "gp_pll_dco", 2114 .ops = &meson_clk_pll_ops, 2115 .parent_data = &(const struct clk_parent_data) { 2116 .fw_name = "xtal", 2117 .name = "xtal", 2118 .index = -1, 2119 }, 2120 .num_parents = 1, 2121 }, 2122 }; 2123 2124 static struct clk_regmap meson8m2_gp_pll = { 2125 .data = &(struct clk_regmap_div_data){ 2126 .offset = HHI_GP_PLL_CNTL, 2127 .shift = 16, 2128 .width = 2, 2129 .flags = CLK_DIVIDER_POWER_OF_TWO, 2130 }, 2131 .hw.init = &(struct clk_init_data){ 2132 .name = "gp_pll", 2133 .ops = &clk_regmap_divider_ops, 2134 .parent_hws = (const struct clk_hw *[]) { 2135 &meson8m2_gp_pll_dco.hw 2136 }, 2137 .num_parents = 1, 2138 .flags = CLK_SET_RATE_PARENT, 2139 }, 2140 }; 2141 2142 static const struct clk_hw *meson8b_vpu_0_1_parent_hws[] = { 2143 &meson8b_fclk_div4.hw, 2144 &meson8b_fclk_div3.hw, 2145 &meson8b_fclk_div5.hw, 2146 &meson8b_fclk_div7.hw, 2147 }; 2148 2149 static const struct clk_hw *mmeson8m2_vpu_0_1_parent_hws[] = { 2150 &meson8b_fclk_div4.hw, 2151 &meson8b_fclk_div3.hw, 2152 &meson8b_fclk_div5.hw, 2153 &meson8m2_gp_pll.hw, 2154 }; 2155 2156 static struct clk_regmap meson8b_vpu_0_sel = { 2157 .data = &(struct clk_regmap_mux_data){ 2158 .offset = HHI_VPU_CLK_CNTL, 2159 .mask = 0x3, 2160 .shift = 9, 2161 }, 2162 .hw.init = &(struct clk_init_data){ 2163 .name = "vpu_0_sel", 2164 .ops = &clk_regmap_mux_ops, 2165 .parent_hws = meson8b_vpu_0_1_parent_hws, 2166 .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws), 2167 .flags = CLK_SET_RATE_PARENT, 2168 }, 2169 }; 2170 2171 static struct clk_regmap meson8m2_vpu_0_sel = { 2172 .data = &(struct clk_regmap_mux_data){ 2173 .offset = HHI_VPU_CLK_CNTL, 2174 .mask = 0x3, 2175 .shift = 9, 2176 }, 2177 .hw.init = &(struct clk_init_data){ 2178 .name = "vpu_0_sel", 2179 .ops = &clk_regmap_mux_ops, 2180 .parent_hws = mmeson8m2_vpu_0_1_parent_hws, 2181 .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws), 2182 .flags = CLK_SET_RATE_PARENT, 2183 }, 2184 }; 2185 2186 static struct clk_regmap meson8b_vpu_0_div = { 2187 .data = &(struct clk_regmap_div_data){ 2188 .offset = HHI_VPU_CLK_CNTL, 2189 .shift = 0, 2190 .width = 7, 2191 }, 2192 .hw.init = &(struct clk_init_data){ 2193 .name = "vpu_0_div", 2194 .ops = &clk_regmap_divider_ops, 2195 .parent_data = &(const struct clk_parent_data) { 2196 /* 2197 * Note: 2198 * meson8b and meson8m2 have different vpu_0_sels (with 2199 * different struct clk_hw). We fallback to the global 2200 * naming string mechanism so vpu_0_div picks up the 2201 * appropriate one. 2202 */ 2203 .name = "vpu_0_sel", 2204 .index = -1, 2205 }, 2206 .num_parents = 1, 2207 .flags = CLK_SET_RATE_PARENT, 2208 }, 2209 }; 2210 2211 static struct clk_regmap meson8b_vpu_0 = { 2212 .data = &(struct clk_regmap_gate_data){ 2213 .offset = HHI_VPU_CLK_CNTL, 2214 .bit_idx = 8, 2215 }, 2216 .hw.init = &(struct clk_init_data) { 2217 .name = "vpu_0", 2218 .ops = &clk_regmap_gate_ops, 2219 .parent_hws = (const struct clk_hw *[]) { 2220 &meson8b_vpu_0_div.hw 2221 }, 2222 .num_parents = 1, 2223 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, 2224 }, 2225 }; 2226 2227 static struct clk_regmap meson8b_vpu_1_sel = { 2228 .data = &(struct clk_regmap_mux_data){ 2229 .offset = HHI_VPU_CLK_CNTL, 2230 .mask = 0x3, 2231 .shift = 25, 2232 }, 2233 .hw.init = &(struct clk_init_data){ 2234 .name = "vpu_1_sel", 2235 .ops = &clk_regmap_mux_ops, 2236 .parent_hws = meson8b_vpu_0_1_parent_hws, 2237 .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws), 2238 .flags = CLK_SET_RATE_PARENT, 2239 }, 2240 }; 2241 2242 static struct clk_regmap meson8m2_vpu_1_sel = { 2243 .data = &(struct clk_regmap_mux_data){ 2244 .offset = HHI_VPU_CLK_CNTL, 2245 .mask = 0x3, 2246 .shift = 25, 2247 }, 2248 .hw.init = &(struct clk_init_data){ 2249 .name = "vpu_1_sel", 2250 .ops = &clk_regmap_mux_ops, 2251 .parent_hws = mmeson8m2_vpu_0_1_parent_hws, 2252 .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws), 2253 .flags = CLK_SET_RATE_PARENT, 2254 }, 2255 }; 2256 2257 static struct clk_regmap meson8b_vpu_1_div = { 2258 .data = &(struct clk_regmap_div_data){ 2259 .offset = HHI_VPU_CLK_CNTL, 2260 .shift = 16, 2261 .width = 7, 2262 }, 2263 .hw.init = &(struct clk_init_data){ 2264 .name = "vpu_1_div", 2265 .ops = &clk_regmap_divider_ops, 2266 .parent_data = &(const struct clk_parent_data) { 2267 /* 2268 * Note: 2269 * meson8b and meson8m2 have different vpu_1_sels (with 2270 * different struct clk_hw). We fallback to the global 2271 * naming string mechanism so vpu_1_div picks up the 2272 * appropriate one. 2273 */ 2274 .name = "vpu_1_sel", 2275 .index = -1, 2276 }, 2277 .num_parents = 1, 2278 .flags = CLK_SET_RATE_PARENT, 2279 }, 2280 }; 2281 2282 static struct clk_regmap meson8b_vpu_1 = { 2283 .data = &(struct clk_regmap_gate_data){ 2284 .offset = HHI_VPU_CLK_CNTL, 2285 .bit_idx = 24, 2286 }, 2287 .hw.init = &(struct clk_init_data) { 2288 .name = "vpu_1", 2289 .ops = &clk_regmap_gate_ops, 2290 .parent_hws = (const struct clk_hw *[]) { 2291 &meson8b_vpu_1_div.hw 2292 }, 2293 .num_parents = 1, 2294 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, 2295 }, 2296 }; 2297 2298 /* 2299 * The VPU clock has two identical clock trees (vpu_0 and vpu_1) 2300 * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can 2301 * actually manage this glitch-free mux because it does top-to-bottom 2302 * updates the each clock tree and switches to the "inactive" one when 2303 * CLK_SET_RATE_GATE is set. 2304 * Meson8 only has vpu_0 and no glitch-free mux. 2305 */ 2306 static struct clk_regmap meson8b_vpu = { 2307 .data = &(struct clk_regmap_mux_data){ 2308 .offset = HHI_VPU_CLK_CNTL, 2309 .mask = 1, 2310 .shift = 31, 2311 }, 2312 .hw.init = &(struct clk_init_data){ 2313 .name = "vpu", 2314 .ops = &clk_regmap_mux_ops, 2315 .parent_hws = (const struct clk_hw *[]) { 2316 &meson8b_vpu_0.hw, 2317 &meson8b_vpu_1.hw, 2318 }, 2319 .num_parents = 2, 2320 .flags = CLK_SET_RATE_PARENT, 2321 }, 2322 }; 2323 2324 static const struct clk_hw *meson8b_vdec_parent_hws[] = { 2325 &meson8b_fclk_div4.hw, 2326 &meson8b_fclk_div3.hw, 2327 &meson8b_fclk_div5.hw, 2328 &meson8b_fclk_div7.hw, 2329 &meson8b_mpll2.hw, 2330 &meson8b_mpll1.hw, 2331 }; 2332 2333 static struct clk_regmap meson8b_vdec_1_sel = { 2334 .data = &(struct clk_regmap_mux_data){ 2335 .offset = HHI_VDEC_CLK_CNTL, 2336 .mask = 0x3, 2337 .shift = 9, 2338 .flags = CLK_MUX_ROUND_CLOSEST, 2339 }, 2340 .hw.init = &(struct clk_init_data){ 2341 .name = "vdec_1_sel", 2342 .ops = &clk_regmap_mux_ops, 2343 .parent_hws = meson8b_vdec_parent_hws, 2344 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws), 2345 .flags = CLK_SET_RATE_PARENT, 2346 }, 2347 }; 2348 2349 static struct clk_regmap meson8b_vdec_1_1_div = { 2350 .data = &(struct clk_regmap_div_data){ 2351 .offset = HHI_VDEC_CLK_CNTL, 2352 .shift = 0, 2353 .width = 7, 2354 .flags = CLK_DIVIDER_ROUND_CLOSEST, 2355 }, 2356 .hw.init = &(struct clk_init_data){ 2357 .name = "vdec_1_1_div", 2358 .ops = &clk_regmap_divider_ops, 2359 .parent_hws = (const struct clk_hw *[]) { 2360 &meson8b_vdec_1_sel.hw 2361 }, 2362 .num_parents = 1, 2363 .flags = CLK_SET_RATE_PARENT, 2364 }, 2365 }; 2366 2367 static struct clk_regmap meson8b_vdec_1_1 = { 2368 .data = &(struct clk_regmap_gate_data){ 2369 .offset = HHI_VDEC_CLK_CNTL, 2370 .bit_idx = 8, 2371 }, 2372 .hw.init = &(struct clk_init_data) { 2373 .name = "vdec_1_1", 2374 .ops = &clk_regmap_gate_ops, 2375 .parent_hws = (const struct clk_hw *[]) { 2376 &meson8b_vdec_1_1_div.hw 2377 }, 2378 .num_parents = 1, 2379 .flags = CLK_SET_RATE_PARENT, 2380 }, 2381 }; 2382 2383 static struct clk_regmap meson8b_vdec_1_2_div = { 2384 .data = &(struct clk_regmap_div_data){ 2385 .offset = HHI_VDEC3_CLK_CNTL, 2386 .shift = 0, 2387 .width = 7, 2388 .flags = CLK_DIVIDER_ROUND_CLOSEST, 2389 }, 2390 .hw.init = &(struct clk_init_data){ 2391 .name = "vdec_1_2_div", 2392 .ops = &clk_regmap_divider_ops, 2393 .parent_hws = (const struct clk_hw *[]) { 2394 &meson8b_vdec_1_sel.hw 2395 }, 2396 .num_parents = 1, 2397 .flags = CLK_SET_RATE_PARENT, 2398 }, 2399 }; 2400 2401 static struct clk_regmap meson8b_vdec_1_2 = { 2402 .data = &(struct clk_regmap_gate_data){ 2403 .offset = HHI_VDEC3_CLK_CNTL, 2404 .bit_idx = 8, 2405 }, 2406 .hw.init = &(struct clk_init_data) { 2407 .name = "vdec_1_2", 2408 .ops = &clk_regmap_gate_ops, 2409 .parent_hws = (const struct clk_hw *[]) { 2410 &meson8b_vdec_1_2_div.hw 2411 }, 2412 .num_parents = 1, 2413 .flags = CLK_SET_RATE_PARENT, 2414 }, 2415 }; 2416 2417 static struct clk_regmap meson8b_vdec_1 = { 2418 .data = &(struct clk_regmap_mux_data){ 2419 .offset = HHI_VDEC3_CLK_CNTL, 2420 .mask = 0x1, 2421 .shift = 15, 2422 .flags = CLK_MUX_ROUND_CLOSEST, 2423 }, 2424 .hw.init = &(struct clk_init_data){ 2425 .name = "vdec_1", 2426 .ops = &clk_regmap_mux_ops, 2427 .parent_hws = (const struct clk_hw *[]) { 2428 &meson8b_vdec_1_1.hw, 2429 &meson8b_vdec_1_2.hw, 2430 }, 2431 .num_parents = 2, 2432 .flags = CLK_SET_RATE_PARENT, 2433 }, 2434 }; 2435 2436 static struct clk_regmap meson8b_vdec_hcodec_sel = { 2437 .data = &(struct clk_regmap_mux_data){ 2438 .offset = HHI_VDEC_CLK_CNTL, 2439 .mask = 0x3, 2440 .shift = 25, 2441 .flags = CLK_MUX_ROUND_CLOSEST, 2442 }, 2443 .hw.init = &(struct clk_init_data){ 2444 .name = "vdec_hcodec_sel", 2445 .ops = &clk_regmap_mux_ops, 2446 .parent_hws = meson8b_vdec_parent_hws, 2447 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws), 2448 .flags = CLK_SET_RATE_PARENT, 2449 }, 2450 }; 2451 2452 static struct clk_regmap meson8b_vdec_hcodec_div = { 2453 .data = &(struct clk_regmap_div_data){ 2454 .offset = HHI_VDEC_CLK_CNTL, 2455 .shift = 16, 2456 .width = 7, 2457 .flags = CLK_DIVIDER_ROUND_CLOSEST, 2458 }, 2459 .hw.init = &(struct clk_init_data){ 2460 .name = "vdec_hcodec_div", 2461 .ops = &clk_regmap_divider_ops, 2462 .parent_hws = (const struct clk_hw *[]) { 2463 &meson8b_vdec_hcodec_sel.hw 2464 }, 2465 .num_parents = 1, 2466 .flags = CLK_SET_RATE_PARENT, 2467 }, 2468 }; 2469 2470 static struct clk_regmap meson8b_vdec_hcodec = { 2471 .data = &(struct clk_regmap_gate_data){ 2472 .offset = HHI_VDEC_CLK_CNTL, 2473 .bit_idx = 24, 2474 }, 2475 .hw.init = &(struct clk_init_data) { 2476 .name = "vdec_hcodec", 2477 .ops = &clk_regmap_gate_ops, 2478 .parent_hws = (const struct clk_hw *[]) { 2479 &meson8b_vdec_hcodec_div.hw 2480 }, 2481 .num_parents = 1, 2482 .flags = CLK_SET_RATE_PARENT, 2483 }, 2484 }; 2485 2486 static struct clk_regmap meson8b_vdec_2_sel = { 2487 .data = &(struct clk_regmap_mux_data){ 2488 .offset = HHI_VDEC2_CLK_CNTL, 2489 .mask = 0x3, 2490 .shift = 9, 2491 .flags = CLK_MUX_ROUND_CLOSEST, 2492 }, 2493 .hw.init = &(struct clk_init_data){ 2494 .name = "vdec_2_sel", 2495 .ops = &clk_regmap_mux_ops, 2496 .parent_hws = meson8b_vdec_parent_hws, 2497 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws), 2498 .flags = CLK_SET_RATE_PARENT, 2499 }, 2500 }; 2501 2502 static struct clk_regmap meson8b_vdec_2_div = { 2503 .data = &(struct clk_regmap_div_data){ 2504 .offset = HHI_VDEC2_CLK_CNTL, 2505 .shift = 0, 2506 .width = 7, 2507 .flags = CLK_DIVIDER_ROUND_CLOSEST, 2508 }, 2509 .hw.init = &(struct clk_init_data){ 2510 .name = "vdec_2_div", 2511 .ops = &clk_regmap_divider_ops, 2512 .parent_hws = (const struct clk_hw *[]) { 2513 &meson8b_vdec_2_sel.hw 2514 }, 2515 .num_parents = 1, 2516 .flags = CLK_SET_RATE_PARENT, 2517 }, 2518 }; 2519 2520 static struct clk_regmap meson8b_vdec_2 = { 2521 .data = &(struct clk_regmap_gate_data){ 2522 .offset = HHI_VDEC2_CLK_CNTL, 2523 .bit_idx = 8, 2524 }, 2525 .hw.init = &(struct clk_init_data) { 2526 .name = "vdec_2", 2527 .ops = &clk_regmap_gate_ops, 2528 .parent_hws = (const struct clk_hw *[]) { 2529 &meson8b_vdec_2_div.hw 2530 }, 2531 .num_parents = 1, 2532 .flags = CLK_SET_RATE_PARENT, 2533 }, 2534 }; 2535 2536 static struct clk_regmap meson8b_vdec_hevc_sel = { 2537 .data = &(struct clk_regmap_mux_data){ 2538 .offset = HHI_VDEC2_CLK_CNTL, 2539 .mask = 0x3, 2540 .shift = 25, 2541 .flags = CLK_MUX_ROUND_CLOSEST, 2542 }, 2543 .hw.init = &(struct clk_init_data){ 2544 .name = "vdec_hevc_sel", 2545 .ops = &clk_regmap_mux_ops, 2546 .parent_hws = meson8b_vdec_parent_hws, 2547 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws), 2548 .flags = CLK_SET_RATE_PARENT, 2549 }, 2550 }; 2551 2552 static struct clk_regmap meson8b_vdec_hevc_div = { 2553 .data = &(struct clk_regmap_div_data){ 2554 .offset = HHI_VDEC2_CLK_CNTL, 2555 .shift = 16, 2556 .width = 7, 2557 .flags = CLK_DIVIDER_ROUND_CLOSEST, 2558 }, 2559 .hw.init = &(struct clk_init_data){ 2560 .name = "vdec_hevc_div", 2561 .ops = &clk_regmap_divider_ops, 2562 .parent_hws = (const struct clk_hw *[]) { 2563 &meson8b_vdec_hevc_sel.hw 2564 }, 2565 .num_parents = 1, 2566 .flags = CLK_SET_RATE_PARENT, 2567 }, 2568 }; 2569 2570 static struct clk_regmap meson8b_vdec_hevc_en = { 2571 .data = &(struct clk_regmap_gate_data){ 2572 .offset = HHI_VDEC2_CLK_CNTL, 2573 .bit_idx = 24, 2574 }, 2575 .hw.init = &(struct clk_init_data) { 2576 .name = "vdec_hevc_en", 2577 .ops = &clk_regmap_gate_ops, 2578 .parent_hws = (const struct clk_hw *[]) { 2579 &meson8b_vdec_hevc_div.hw 2580 }, 2581 .num_parents = 1, 2582 .flags = CLK_SET_RATE_PARENT, 2583 }, 2584 }; 2585 2586 static struct clk_regmap meson8b_vdec_hevc = { 2587 .data = &(struct clk_regmap_mux_data){ 2588 .offset = HHI_VDEC2_CLK_CNTL, 2589 .mask = 0x1, 2590 .shift = 31, 2591 .flags = CLK_MUX_ROUND_CLOSEST, 2592 }, 2593 .hw.init = &(struct clk_init_data){ 2594 .name = "vdec_hevc", 2595 .ops = &clk_regmap_mux_ops, 2596 /* TODO: The second parent is currently unknown */ 2597 .parent_hws = (const struct clk_hw *[]) { 2598 &meson8b_vdec_hevc_en.hw 2599 }, 2600 .num_parents = 1, 2601 .flags = CLK_SET_RATE_PARENT, 2602 }, 2603 }; 2604 2605 /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */ 2606 static const struct clk_hw *meson8b_cts_amclk_parent_hws[] = { 2607 &meson8b_mpll0.hw, 2608 &meson8b_mpll1.hw, 2609 &meson8b_mpll2.hw 2610 }; 2611 2612 static u32 meson8b_cts_amclk_mux_table[] = { 1, 2, 3 }; 2613 2614 static struct clk_regmap meson8b_cts_amclk_sel = { 2615 .data = &(struct clk_regmap_mux_data){ 2616 .offset = HHI_AUD_CLK_CNTL, 2617 .mask = 0x3, 2618 .shift = 9, 2619 .table = meson8b_cts_amclk_mux_table, 2620 .flags = CLK_MUX_ROUND_CLOSEST, 2621 }, 2622 .hw.init = &(struct clk_init_data){ 2623 .name = "cts_amclk_sel", 2624 .ops = &clk_regmap_mux_ops, 2625 .parent_hws = meson8b_cts_amclk_parent_hws, 2626 .num_parents = ARRAY_SIZE(meson8b_cts_amclk_parent_hws), 2627 }, 2628 }; 2629 2630 static struct clk_regmap meson8b_cts_amclk_div = { 2631 .data = &(struct clk_regmap_div_data) { 2632 .offset = HHI_AUD_CLK_CNTL, 2633 .shift = 0, 2634 .width = 8, 2635 .flags = CLK_DIVIDER_ROUND_CLOSEST, 2636 }, 2637 .hw.init = &(struct clk_init_data){ 2638 .name = "cts_amclk_div", 2639 .ops = &clk_regmap_divider_ops, 2640 .parent_hws = (const struct clk_hw *[]) { 2641 &meson8b_cts_amclk_sel.hw 2642 }, 2643 .num_parents = 1, 2644 .flags = CLK_SET_RATE_PARENT, 2645 }, 2646 }; 2647 2648 static struct clk_regmap meson8b_cts_amclk = { 2649 .data = &(struct clk_regmap_gate_data){ 2650 .offset = HHI_AUD_CLK_CNTL, 2651 .bit_idx = 8, 2652 }, 2653 .hw.init = &(struct clk_init_data){ 2654 .name = "cts_amclk", 2655 .ops = &clk_regmap_gate_ops, 2656 .parent_hws = (const struct clk_hw *[]) { 2657 &meson8b_cts_amclk_div.hw 2658 }, 2659 .num_parents = 1, 2660 .flags = CLK_SET_RATE_PARENT, 2661 }, 2662 }; 2663 2664 /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */ 2665 static const struct clk_hw *meson8b_cts_mclk_i958_parent_hws[] = { 2666 &meson8b_mpll0.hw, 2667 &meson8b_mpll1.hw, 2668 &meson8b_mpll2.hw 2669 }; 2670 2671 static u32 meson8b_cts_mclk_i958_mux_table[] = { 1, 2, 3 }; 2672 2673 static struct clk_regmap meson8b_cts_mclk_i958_sel = { 2674 .data = &(struct clk_regmap_mux_data){ 2675 .offset = HHI_AUD_CLK_CNTL2, 2676 .mask = 0x3, 2677 .shift = 25, 2678 .table = meson8b_cts_mclk_i958_mux_table, 2679 .flags = CLK_MUX_ROUND_CLOSEST, 2680 }, 2681 .hw.init = &(struct clk_init_data) { 2682 .name = "cts_mclk_i958_sel", 2683 .ops = &clk_regmap_mux_ops, 2684 .parent_hws = meson8b_cts_mclk_i958_parent_hws, 2685 .num_parents = ARRAY_SIZE(meson8b_cts_mclk_i958_parent_hws), 2686 }, 2687 }; 2688 2689 static struct clk_regmap meson8b_cts_mclk_i958_div = { 2690 .data = &(struct clk_regmap_div_data){ 2691 .offset = HHI_AUD_CLK_CNTL2, 2692 .shift = 16, 2693 .width = 8, 2694 .flags = CLK_DIVIDER_ROUND_CLOSEST, 2695 }, 2696 .hw.init = &(struct clk_init_data) { 2697 .name = "cts_mclk_i958_div", 2698 .ops = &clk_regmap_divider_ops, 2699 .parent_hws = (const struct clk_hw *[]) { 2700 &meson8b_cts_mclk_i958_sel.hw 2701 }, 2702 .num_parents = 1, 2703 .flags = CLK_SET_RATE_PARENT, 2704 }, 2705 }; 2706 2707 static struct clk_regmap meson8b_cts_mclk_i958 = { 2708 .data = &(struct clk_regmap_gate_data){ 2709 .offset = HHI_AUD_CLK_CNTL2, 2710 .bit_idx = 24, 2711 }, 2712 .hw.init = &(struct clk_init_data){ 2713 .name = "cts_mclk_i958", 2714 .ops = &clk_regmap_gate_ops, 2715 .parent_hws = (const struct clk_hw *[]) { 2716 &meson8b_cts_mclk_i958_div.hw 2717 }, 2718 .num_parents = 1, 2719 .flags = CLK_SET_RATE_PARENT, 2720 }, 2721 }; 2722 2723 static struct clk_regmap meson8b_cts_i958 = { 2724 .data = &(struct clk_regmap_mux_data){ 2725 .offset = HHI_AUD_CLK_CNTL2, 2726 .mask = 0x1, 2727 .shift = 27, 2728 }, 2729 .hw.init = &(struct clk_init_data){ 2730 .name = "cts_i958", 2731 .ops = &clk_regmap_mux_ops, 2732 .parent_hws = (const struct clk_hw *[]) { 2733 &meson8b_cts_amclk.hw, 2734 &meson8b_cts_mclk_i958.hw 2735 }, 2736 .num_parents = 2, 2737 /* 2738 * The parent is specific to origin of the audio data. Let the 2739 * consumer choose the appropriate parent. 2740 */ 2741 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2742 }, 2743 }; 2744 2745 #define MESON_GATE(_name, _reg, _bit) \ 2746 MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw) 2747 2748 /* Everything Else (EE) domain gates */ 2749 2750 static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0); 2751 static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1); 2752 static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5); 2753 static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6); 2754 static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7); 2755 static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8); 2756 static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9); 2757 static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10); 2758 static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11); 2759 static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12); 2760 static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13); 2761 static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14); 2762 static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15); 2763 static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16); 2764 static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17); 2765 static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18); 2766 static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19); 2767 static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23); 2768 static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30); 2769 2770 static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2); 2771 static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3); 2772 static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4); 2773 static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14); 2774 static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15); 2775 static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16); 2776 static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20); 2777 static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21); 2778 static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22); 2779 static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23); 2780 static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24); 2781 static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25); 2782 static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26); 2783 static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28); 2784 static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29); 2785 static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30); 2786 static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31); 2787 2788 static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1); 2789 static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); 2790 static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3); 2791 static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4); 2792 static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); 2793 static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); 2794 static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11); 2795 static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12); 2796 static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15); 2797 static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22); 2798 static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25); 2799 static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); 2800 static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29); 2801 2802 static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1); 2803 static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2); 2804 static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3); 2805 static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4); 2806 static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8); 2807 static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9); 2808 static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10); 2809 static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14); 2810 static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16); 2811 static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20); 2812 static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21); 2813 static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22); 2814 static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24); 2815 static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25); 2816 static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26); 2817 static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31); 2818 2819 /* AIU gates */ 2820 #define MESON_AIU_GLUE_GATE(_name, _reg, _bit) \ 2821 MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw) 2822 2823 static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw); 2824 static MESON_AIU_GLUE_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7); 2825 static MESON_AIU_GLUE_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8); 2826 static MESON_AIU_GLUE_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9); 2827 static MESON_AIU_GLUE_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10); 2828 static MESON_AIU_GLUE_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11); 2829 static MESON_AIU_GLUE_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12); 2830 static MESON_AIU_GLUE_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13); 2831 2832 /* Always On (AO) domain gates */ 2833 2834 static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0); 2835 static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1); 2836 static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2); 2837 static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3); 2838 2839 static struct clk_hw *meson8_hw_clks[] = { 2840 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw, 2841 [CLKID_PLL_VID] = &meson8b_vid_pll.hw, 2842 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw, 2843 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw, 2844 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw, 2845 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw, 2846 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw, 2847 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw, 2848 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw, 2849 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw, 2850 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw, 2851 [CLKID_CLK81] = &meson8b_clk81.hw, 2852 [CLKID_DDR] = &meson8b_ddr.hw, 2853 [CLKID_DOS] = &meson8b_dos.hw, 2854 [CLKID_ISA] = &meson8b_isa.hw, 2855 [CLKID_PL301] = &meson8b_pl301.hw, 2856 [CLKID_PERIPHS] = &meson8b_periphs.hw, 2857 [CLKID_SPICC] = &meson8b_spicc.hw, 2858 [CLKID_I2C] = &meson8b_i2c.hw, 2859 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw, 2860 [CLKID_SMART_CARD] = &meson8b_smart_card.hw, 2861 [CLKID_RNG0] = &meson8b_rng0.hw, 2862 [CLKID_UART0] = &meson8b_uart0.hw, 2863 [CLKID_SDHC] = &meson8b_sdhc.hw, 2864 [CLKID_STREAM] = &meson8b_stream.hw, 2865 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw, 2866 [CLKID_SDIO] = &meson8b_sdio.hw, 2867 [CLKID_ABUF] = &meson8b_abuf.hw, 2868 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw, 2869 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw, 2870 [CLKID_SPI] = &meson8b_spi.hw, 2871 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw, 2872 [CLKID_ETH] = &meson8b_eth.hw, 2873 [CLKID_DEMUX] = &meson8b_demux.hw, 2874 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw, 2875 [CLKID_IEC958] = &meson8b_iec958.hw, 2876 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw, 2877 [CLKID_AMCLK] = &meson8b_amclk.hw, 2878 [CLKID_AIFIFO2] = &meson8b_aififo2.hw, 2879 [CLKID_MIXER] = &meson8b_mixer.hw, 2880 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw, 2881 [CLKID_ADC] = &meson8b_adc.hw, 2882 [CLKID_BLKMV] = &meson8b_blkmv.hw, 2883 [CLKID_AIU] = &meson8b_aiu.hw, 2884 [CLKID_UART1] = &meson8b_uart1.hw, 2885 [CLKID_G2D] = &meson8b_g2d.hw, 2886 [CLKID_USB0] = &meson8b_usb0.hw, 2887 [CLKID_USB1] = &meson8b_usb1.hw, 2888 [CLKID_RESET] = &meson8b_reset.hw, 2889 [CLKID_NAND] = &meson8b_nand.hw, 2890 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw, 2891 [CLKID_USB] = &meson8b_usb.hw, 2892 [CLKID_VDIN1] = &meson8b_vdin1.hw, 2893 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw, 2894 [CLKID_EFUSE] = &meson8b_efuse.hw, 2895 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw, 2896 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw, 2897 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw, 2898 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw, 2899 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw, 2900 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw, 2901 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw, 2902 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw, 2903 [CLKID_DVIN] = &meson8b_dvin.hw, 2904 [CLKID_UART2] = &meson8b_uart2.hw, 2905 [CLKID_SANA] = &meson8b_sana.hw, 2906 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw, 2907 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw, 2908 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw, 2909 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw, 2910 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw, 2911 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw, 2912 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw, 2913 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw, 2914 [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw, 2915 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw, 2916 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw, 2917 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw, 2918 [CLKID_ENC480P] = &meson8b_enc480p.hw, 2919 [CLKID_RNG1] = &meson8b_rng1.hw, 2920 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw, 2921 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw, 2922 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw, 2923 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw, 2924 [CLKID_EDP] = &meson8b_edp.hw, 2925 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw, 2926 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw, 2927 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw, 2928 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw, 2929 [CLKID_MPLL0] = &meson8b_mpll0.hw, 2930 [CLKID_MPLL1] = &meson8b_mpll1.hw, 2931 [CLKID_MPLL2] = &meson8b_mpll2.hw, 2932 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw, 2933 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw, 2934 [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw, 2935 [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw, 2936 [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw, 2937 [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw, 2938 [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw, 2939 [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw, 2940 [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw, 2941 [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw, 2942 [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw, 2943 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw, 2944 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw, 2945 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw, 2946 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw, 2947 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw, 2948 [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw, 2949 [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw, 2950 [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw, 2951 [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw, 2952 [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw, 2953 [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw, 2954 [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw, 2955 [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw, 2956 [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw, 2957 [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw, 2958 [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw, 2959 [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw, 2960 [CLKID_APB] = &meson8b_apb_clk_gate.hw, 2961 [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw, 2962 [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw, 2963 [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw, 2964 [CLKID_AXI] = &meson8b_axi_clk_gate.hw, 2965 [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw, 2966 [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw, 2967 [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw, 2968 [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw, 2969 [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw, 2970 [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw, 2971 [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw, 2972 [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw, 2973 [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw, 2974 [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw, 2975 [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw, 2976 [CLKID_VCLK_EN] = &meson8b_vclk_en.hw, 2977 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw, 2978 [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw, 2979 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw, 2980 [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw, 2981 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw, 2982 [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw, 2983 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw, 2984 [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw, 2985 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw, 2986 [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw, 2987 [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw, 2988 [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw, 2989 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw, 2990 [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw, 2991 [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw, 2992 [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw, 2993 [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw, 2994 [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw, 2995 [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw, 2996 [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw, 2997 [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw, 2998 [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw, 2999 [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw, 3000 [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw, 3001 [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw, 3002 [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw, 3003 [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw, 3004 [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw, 3005 [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw, 3006 [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw, 3007 [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw, 3008 [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw, 3009 [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw, 3010 [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw, 3011 [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw, 3012 [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw, 3013 [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw, 3014 [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw, 3015 [CLKID_MALI] = &meson8b_mali_0.hw, 3016 [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw, 3017 [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw, 3018 [CLKID_VPU] = &meson8b_vpu_0.hw, 3019 [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw, 3020 [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw, 3021 [CLKID_VDEC_1] = &meson8b_vdec_1_1.hw, 3022 [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw, 3023 [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw, 3024 [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw, 3025 [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw, 3026 [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw, 3027 [CLKID_VDEC_2] = &meson8b_vdec_2.hw, 3028 [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw, 3029 [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw, 3030 [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw, 3031 [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw, 3032 [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw, 3033 [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw, 3034 [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw, 3035 [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw, 3036 [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw, 3037 [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw, 3038 [CLKID_CTS_I958] = &meson8b_cts_i958.hw, 3039 [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, 3040 [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw, 3041 }; 3042 3043 static struct clk_hw *meson8b_hw_clks[] = { 3044 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw, 3045 [CLKID_PLL_VID] = &meson8b_vid_pll.hw, 3046 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw, 3047 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw, 3048 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw, 3049 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw, 3050 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw, 3051 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw, 3052 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw, 3053 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw, 3054 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw, 3055 [CLKID_CLK81] = &meson8b_clk81.hw, 3056 [CLKID_DDR] = &meson8b_ddr.hw, 3057 [CLKID_DOS] = &meson8b_dos.hw, 3058 [CLKID_ISA] = &meson8b_isa.hw, 3059 [CLKID_PL301] = &meson8b_pl301.hw, 3060 [CLKID_PERIPHS] = &meson8b_periphs.hw, 3061 [CLKID_SPICC] = &meson8b_spicc.hw, 3062 [CLKID_I2C] = &meson8b_i2c.hw, 3063 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw, 3064 [CLKID_SMART_CARD] = &meson8b_smart_card.hw, 3065 [CLKID_RNG0] = &meson8b_rng0.hw, 3066 [CLKID_UART0] = &meson8b_uart0.hw, 3067 [CLKID_SDHC] = &meson8b_sdhc.hw, 3068 [CLKID_STREAM] = &meson8b_stream.hw, 3069 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw, 3070 [CLKID_SDIO] = &meson8b_sdio.hw, 3071 [CLKID_ABUF] = &meson8b_abuf.hw, 3072 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw, 3073 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw, 3074 [CLKID_SPI] = &meson8b_spi.hw, 3075 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw, 3076 [CLKID_ETH] = &meson8b_eth.hw, 3077 [CLKID_DEMUX] = &meson8b_demux.hw, 3078 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw, 3079 [CLKID_IEC958] = &meson8b_iec958.hw, 3080 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw, 3081 [CLKID_AMCLK] = &meson8b_amclk.hw, 3082 [CLKID_AIFIFO2] = &meson8b_aififo2.hw, 3083 [CLKID_MIXER] = &meson8b_mixer.hw, 3084 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw, 3085 [CLKID_ADC] = &meson8b_adc.hw, 3086 [CLKID_BLKMV] = &meson8b_blkmv.hw, 3087 [CLKID_AIU] = &meson8b_aiu.hw, 3088 [CLKID_UART1] = &meson8b_uart1.hw, 3089 [CLKID_G2D] = &meson8b_g2d.hw, 3090 [CLKID_USB0] = &meson8b_usb0.hw, 3091 [CLKID_USB1] = &meson8b_usb1.hw, 3092 [CLKID_RESET] = &meson8b_reset.hw, 3093 [CLKID_NAND] = &meson8b_nand.hw, 3094 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw, 3095 [CLKID_USB] = &meson8b_usb.hw, 3096 [CLKID_VDIN1] = &meson8b_vdin1.hw, 3097 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw, 3098 [CLKID_EFUSE] = &meson8b_efuse.hw, 3099 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw, 3100 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw, 3101 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw, 3102 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw, 3103 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw, 3104 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw, 3105 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw, 3106 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw, 3107 [CLKID_DVIN] = &meson8b_dvin.hw, 3108 [CLKID_UART2] = &meson8b_uart2.hw, 3109 [CLKID_SANA] = &meson8b_sana.hw, 3110 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw, 3111 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw, 3112 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw, 3113 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw, 3114 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw, 3115 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw, 3116 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw, 3117 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw, 3118 [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw, 3119 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw, 3120 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw, 3121 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw, 3122 [CLKID_ENC480P] = &meson8b_enc480p.hw, 3123 [CLKID_RNG1] = &meson8b_rng1.hw, 3124 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw, 3125 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw, 3126 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw, 3127 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw, 3128 [CLKID_EDP] = &meson8b_edp.hw, 3129 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw, 3130 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw, 3131 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw, 3132 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw, 3133 [CLKID_MPLL0] = &meson8b_mpll0.hw, 3134 [CLKID_MPLL1] = &meson8b_mpll1.hw, 3135 [CLKID_MPLL2] = &meson8b_mpll2.hw, 3136 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw, 3137 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw, 3138 [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw, 3139 [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw, 3140 [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw, 3141 [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw, 3142 [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw, 3143 [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw, 3144 [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw, 3145 [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw, 3146 [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw, 3147 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw, 3148 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw, 3149 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw, 3150 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw, 3151 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw, 3152 [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw, 3153 [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw, 3154 [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw, 3155 [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw, 3156 [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw, 3157 [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw, 3158 [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw, 3159 [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw, 3160 [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw, 3161 [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw, 3162 [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw, 3163 [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw, 3164 [CLKID_APB] = &meson8b_apb_clk_gate.hw, 3165 [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw, 3166 [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw, 3167 [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw, 3168 [CLKID_AXI] = &meson8b_axi_clk_gate.hw, 3169 [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw, 3170 [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw, 3171 [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw, 3172 [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw, 3173 [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw, 3174 [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw, 3175 [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw, 3176 [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw, 3177 [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw, 3178 [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw, 3179 [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw, 3180 [CLKID_VCLK_EN] = &meson8b_vclk_en.hw, 3181 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw, 3182 [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw, 3183 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw, 3184 [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw, 3185 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw, 3186 [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw, 3187 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw, 3188 [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw, 3189 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw, 3190 [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw, 3191 [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw, 3192 [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw, 3193 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw, 3194 [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw, 3195 [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw, 3196 [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw, 3197 [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw, 3198 [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw, 3199 [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw, 3200 [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw, 3201 [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw, 3202 [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw, 3203 [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw, 3204 [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw, 3205 [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw, 3206 [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw, 3207 [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw, 3208 [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw, 3209 [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw, 3210 [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw, 3211 [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw, 3212 [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw, 3213 [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw, 3214 [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw, 3215 [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw, 3216 [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw, 3217 [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw, 3218 [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw, 3219 [CLKID_MALI_0] = &meson8b_mali_0.hw, 3220 [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw, 3221 [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw, 3222 [CLKID_MALI_1] = &meson8b_mali_1.hw, 3223 [CLKID_MALI] = &meson8b_mali.hw, 3224 [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw, 3225 [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw, 3226 [CLKID_VPU_0] = &meson8b_vpu_0.hw, 3227 [CLKID_VPU_1_SEL] = &meson8b_vpu_1_sel.hw, 3228 [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw, 3229 [CLKID_VPU_1] = &meson8b_vpu_1.hw, 3230 [CLKID_VPU] = &meson8b_vpu.hw, 3231 [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw, 3232 [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw, 3233 [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw, 3234 [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw, 3235 [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw, 3236 [CLKID_VDEC_1] = &meson8b_vdec_1.hw, 3237 [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw, 3238 [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw, 3239 [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw, 3240 [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw, 3241 [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw, 3242 [CLKID_VDEC_2] = &meson8b_vdec_2.hw, 3243 [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw, 3244 [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw, 3245 [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw, 3246 [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw, 3247 [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw, 3248 [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw, 3249 [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw, 3250 [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw, 3251 [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw, 3252 [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw, 3253 [CLKID_CTS_I958] = &meson8b_cts_i958.hw, 3254 [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, 3255 [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw, 3256 }; 3257 3258 static struct clk_hw *meson8m2_hw_clks[] = { 3259 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw, 3260 [CLKID_PLL_VID] = &meson8b_vid_pll.hw, 3261 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw, 3262 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw, 3263 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw, 3264 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw, 3265 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw, 3266 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw, 3267 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw, 3268 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw, 3269 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw, 3270 [CLKID_CLK81] = &meson8b_clk81.hw, 3271 [CLKID_DDR] = &meson8b_ddr.hw, 3272 [CLKID_DOS] = &meson8b_dos.hw, 3273 [CLKID_ISA] = &meson8b_isa.hw, 3274 [CLKID_PL301] = &meson8b_pl301.hw, 3275 [CLKID_PERIPHS] = &meson8b_periphs.hw, 3276 [CLKID_SPICC] = &meson8b_spicc.hw, 3277 [CLKID_I2C] = &meson8b_i2c.hw, 3278 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw, 3279 [CLKID_SMART_CARD] = &meson8b_smart_card.hw, 3280 [CLKID_RNG0] = &meson8b_rng0.hw, 3281 [CLKID_UART0] = &meson8b_uart0.hw, 3282 [CLKID_SDHC] = &meson8b_sdhc.hw, 3283 [CLKID_STREAM] = &meson8b_stream.hw, 3284 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw, 3285 [CLKID_SDIO] = &meson8b_sdio.hw, 3286 [CLKID_ABUF] = &meson8b_abuf.hw, 3287 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw, 3288 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw, 3289 [CLKID_SPI] = &meson8b_spi.hw, 3290 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw, 3291 [CLKID_ETH] = &meson8b_eth.hw, 3292 [CLKID_DEMUX] = &meson8b_demux.hw, 3293 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw, 3294 [CLKID_IEC958] = &meson8b_iec958.hw, 3295 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw, 3296 [CLKID_AMCLK] = &meson8b_amclk.hw, 3297 [CLKID_AIFIFO2] = &meson8b_aififo2.hw, 3298 [CLKID_MIXER] = &meson8b_mixer.hw, 3299 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw, 3300 [CLKID_ADC] = &meson8b_adc.hw, 3301 [CLKID_BLKMV] = &meson8b_blkmv.hw, 3302 [CLKID_AIU] = &meson8b_aiu.hw, 3303 [CLKID_UART1] = &meson8b_uart1.hw, 3304 [CLKID_G2D] = &meson8b_g2d.hw, 3305 [CLKID_USB0] = &meson8b_usb0.hw, 3306 [CLKID_USB1] = &meson8b_usb1.hw, 3307 [CLKID_RESET] = &meson8b_reset.hw, 3308 [CLKID_NAND] = &meson8b_nand.hw, 3309 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw, 3310 [CLKID_USB] = &meson8b_usb.hw, 3311 [CLKID_VDIN1] = &meson8b_vdin1.hw, 3312 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw, 3313 [CLKID_EFUSE] = &meson8b_efuse.hw, 3314 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw, 3315 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw, 3316 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw, 3317 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw, 3318 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw, 3319 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw, 3320 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw, 3321 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw, 3322 [CLKID_DVIN] = &meson8b_dvin.hw, 3323 [CLKID_UART2] = &meson8b_uart2.hw, 3324 [CLKID_SANA] = &meson8b_sana.hw, 3325 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw, 3326 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw, 3327 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw, 3328 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw, 3329 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw, 3330 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw, 3331 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw, 3332 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw, 3333 [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw, 3334 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw, 3335 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw, 3336 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw, 3337 [CLKID_ENC480P] = &meson8b_enc480p.hw, 3338 [CLKID_RNG1] = &meson8b_rng1.hw, 3339 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw, 3340 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw, 3341 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw, 3342 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw, 3343 [CLKID_EDP] = &meson8b_edp.hw, 3344 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw, 3345 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw, 3346 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw, 3347 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw, 3348 [CLKID_MPLL0] = &meson8b_mpll0.hw, 3349 [CLKID_MPLL1] = &meson8b_mpll1.hw, 3350 [CLKID_MPLL2] = &meson8b_mpll2.hw, 3351 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw, 3352 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw, 3353 [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw, 3354 [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw, 3355 [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw, 3356 [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw, 3357 [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw, 3358 [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw, 3359 [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw, 3360 [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw, 3361 [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw, 3362 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw, 3363 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw, 3364 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw, 3365 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw, 3366 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw, 3367 [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw, 3368 [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw, 3369 [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw, 3370 [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw, 3371 [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw, 3372 [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw, 3373 [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw, 3374 [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw, 3375 [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw, 3376 [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw, 3377 [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw, 3378 [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw, 3379 [CLKID_APB] = &meson8b_apb_clk_gate.hw, 3380 [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw, 3381 [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw, 3382 [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw, 3383 [CLKID_AXI] = &meson8b_axi_clk_gate.hw, 3384 [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw, 3385 [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw, 3386 [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw, 3387 [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw, 3388 [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw, 3389 [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw, 3390 [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw, 3391 [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw, 3392 [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw, 3393 [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw, 3394 [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw, 3395 [CLKID_VCLK_EN] = &meson8b_vclk_en.hw, 3396 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw, 3397 [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw, 3398 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw, 3399 [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw, 3400 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw, 3401 [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw, 3402 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw, 3403 [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw, 3404 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw, 3405 [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw, 3406 [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw, 3407 [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw, 3408 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw, 3409 [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw, 3410 [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw, 3411 [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw, 3412 [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw, 3413 [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw, 3414 [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw, 3415 [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw, 3416 [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw, 3417 [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw, 3418 [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw, 3419 [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw, 3420 [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw, 3421 [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw, 3422 [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw, 3423 [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw, 3424 [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw, 3425 [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw, 3426 [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw, 3427 [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw, 3428 [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw, 3429 [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw, 3430 [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw, 3431 [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw, 3432 [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw, 3433 [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw, 3434 [CLKID_MALI_0] = &meson8b_mali_0.hw, 3435 [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw, 3436 [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw, 3437 [CLKID_MALI_1] = &meson8b_mali_1.hw, 3438 [CLKID_MALI] = &meson8b_mali.hw, 3439 [CLKID_GP_PLL_DCO] = &meson8m2_gp_pll_dco.hw, 3440 [CLKID_GP_PLL] = &meson8m2_gp_pll.hw, 3441 [CLKID_VPU_0_SEL] = &meson8m2_vpu_0_sel.hw, 3442 [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw, 3443 [CLKID_VPU_0] = &meson8b_vpu_0.hw, 3444 [CLKID_VPU_1_SEL] = &meson8m2_vpu_1_sel.hw, 3445 [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw, 3446 [CLKID_VPU_1] = &meson8b_vpu_1.hw, 3447 [CLKID_VPU] = &meson8b_vpu.hw, 3448 [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw, 3449 [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw, 3450 [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw, 3451 [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw, 3452 [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw, 3453 [CLKID_VDEC_1] = &meson8b_vdec_1.hw, 3454 [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw, 3455 [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw, 3456 [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw, 3457 [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw, 3458 [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw, 3459 [CLKID_VDEC_2] = &meson8b_vdec_2.hw, 3460 [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw, 3461 [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw, 3462 [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw, 3463 [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw, 3464 [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw, 3465 [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw, 3466 [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw, 3467 [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw, 3468 [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw, 3469 [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw, 3470 [CLKID_CTS_I958] = &meson8b_cts_i958.hw, 3471 [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, 3472 [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw, 3473 }; 3474 3475 static const struct meson8b_clk_reset_line { 3476 u32 reg; 3477 u8 bit_idx; 3478 bool active_low; 3479 } meson8b_clk_reset_bits[] = { 3480 [CLKC_RESET_L2_CACHE_SOFT_RESET] = { 3481 .reg = HHI_SYS_CPU_CLK_CNTL0, 3482 .bit_idx = 30, 3483 .active_low = false, 3484 }, 3485 [CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET] = { 3486 .reg = HHI_SYS_CPU_CLK_CNTL0, 3487 .bit_idx = 29, 3488 .active_low = false, 3489 }, 3490 [CLKC_RESET_SCU_SOFT_RESET] = { 3491 .reg = HHI_SYS_CPU_CLK_CNTL0, 3492 .bit_idx = 28, 3493 .active_low = false, 3494 }, 3495 [CLKC_RESET_CPU3_SOFT_RESET] = { 3496 .reg = HHI_SYS_CPU_CLK_CNTL0, 3497 .bit_idx = 27, 3498 .active_low = false, 3499 }, 3500 [CLKC_RESET_CPU2_SOFT_RESET] = { 3501 .reg = HHI_SYS_CPU_CLK_CNTL0, 3502 .bit_idx = 26, 3503 .active_low = false, 3504 }, 3505 [CLKC_RESET_CPU1_SOFT_RESET] = { 3506 .reg = HHI_SYS_CPU_CLK_CNTL0, 3507 .bit_idx = 25, 3508 .active_low = false, 3509 }, 3510 [CLKC_RESET_CPU0_SOFT_RESET] = { 3511 .reg = HHI_SYS_CPU_CLK_CNTL0, 3512 .bit_idx = 24, 3513 .active_low = false, 3514 }, 3515 [CLKC_RESET_A5_GLOBAL_RESET] = { 3516 .reg = HHI_SYS_CPU_CLK_CNTL0, 3517 .bit_idx = 18, 3518 .active_low = false, 3519 }, 3520 [CLKC_RESET_A5_AXI_SOFT_RESET] = { 3521 .reg = HHI_SYS_CPU_CLK_CNTL0, 3522 .bit_idx = 17, 3523 .active_low = false, 3524 }, 3525 [CLKC_RESET_A5_ABP_SOFT_RESET] = { 3526 .reg = HHI_SYS_CPU_CLK_CNTL0, 3527 .bit_idx = 16, 3528 .active_low = false, 3529 }, 3530 [CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET] = { 3531 .reg = HHI_SYS_CPU_CLK_CNTL1, 3532 .bit_idx = 30, 3533 .active_low = false, 3534 }, 3535 [CLKC_RESET_VID_CLK_CNTL_SOFT_RESET] = { 3536 .reg = HHI_VID_CLK_CNTL, 3537 .bit_idx = 15, 3538 .active_low = false, 3539 }, 3540 [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST] = { 3541 .reg = HHI_VID_DIVIDER_CNTL, 3542 .bit_idx = 7, 3543 .active_low = false, 3544 }, 3545 [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE] = { 3546 .reg = HHI_VID_DIVIDER_CNTL, 3547 .bit_idx = 3, 3548 .active_low = false, 3549 }, 3550 [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST] = { 3551 .reg = HHI_VID_DIVIDER_CNTL, 3552 .bit_idx = 1, 3553 .active_low = true, 3554 }, 3555 [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE] = { 3556 .reg = HHI_VID_DIVIDER_CNTL, 3557 .bit_idx = 0, 3558 .active_low = true, 3559 }, 3560 }; 3561 3562 static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev, 3563 unsigned long id, bool assert) 3564 { 3565 struct meson8b_clk_reset *meson8b_clk_reset = 3566 container_of(rcdev, struct meson8b_clk_reset, reset); 3567 const struct meson8b_clk_reset_line *reset; 3568 unsigned int value = 0; 3569 3570 if (id >= ARRAY_SIZE(meson8b_clk_reset_bits)) 3571 return -EINVAL; 3572 3573 reset = &meson8b_clk_reset_bits[id]; 3574 3575 if (assert != reset->active_low) 3576 value = BIT(reset->bit_idx); 3577 3578 regmap_update_bits(meson8b_clk_reset->regmap, reset->reg, 3579 BIT(reset->bit_idx), value); 3580 3581 return 0; 3582 } 3583 3584 static int meson8b_clk_reset_assert(struct reset_controller_dev *rcdev, 3585 unsigned long id) 3586 { 3587 return meson8b_clk_reset_update(rcdev, id, true); 3588 } 3589 3590 static int meson8b_clk_reset_deassert(struct reset_controller_dev *rcdev, 3591 unsigned long id) 3592 { 3593 return meson8b_clk_reset_update(rcdev, id, false); 3594 } 3595 3596 static const struct reset_control_ops meson8b_clk_reset_ops = { 3597 .assert = meson8b_clk_reset_assert, 3598 .deassert = meson8b_clk_reset_deassert, 3599 }; 3600 3601 struct meson8b_nb_data { 3602 struct notifier_block nb; 3603 struct clk_hw *cpu_clk; 3604 }; 3605 3606 static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb, 3607 unsigned long event, void *data) 3608 { 3609 struct meson8b_nb_data *nb_data = 3610 container_of(nb, struct meson8b_nb_data, nb); 3611 struct clk_hw *parent_clk; 3612 int ret; 3613 3614 switch (event) { 3615 case PRE_RATE_CHANGE: 3616 /* xtal */ 3617 parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 0); 3618 break; 3619 3620 case POST_RATE_CHANGE: 3621 /* cpu_scale_out_sel */ 3622 parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 1); 3623 break; 3624 3625 default: 3626 return NOTIFY_DONE; 3627 } 3628 3629 ret = clk_hw_set_parent(nb_data->cpu_clk, parent_clk); 3630 if (ret) 3631 return notifier_from_errno(ret); 3632 3633 udelay(100); 3634 3635 return NOTIFY_OK; 3636 } 3637 3638 static struct meson8b_nb_data meson8b_cpu_nb_data = { 3639 .nb.notifier_call = meson8b_cpu_clk_notifier_cb, 3640 }; 3641 3642 static struct meson_clk_hw_data meson8_clks = { 3643 .hws = meson8_hw_clks, 3644 .num = ARRAY_SIZE(meson8_hw_clks), 3645 }; 3646 3647 static struct meson_clk_hw_data meson8b_clks = { 3648 .hws = meson8b_hw_clks, 3649 .num = ARRAY_SIZE(meson8b_hw_clks), 3650 }; 3651 3652 static struct meson_clk_hw_data meson8m2_clks = { 3653 .hws = meson8m2_hw_clks, 3654 .num = ARRAY_SIZE(meson8m2_hw_clks), 3655 }; 3656 3657 static void __init meson8b_clkc_init_common(struct device_node *np, 3658 struct meson_clk_hw_data *hw_clks) 3659 { 3660 struct meson8b_clk_reset *rstc; 3661 struct device_node *parent_np; 3662 const char *notifier_clk_name; 3663 struct clk *notifier_clk; 3664 struct regmap *map; 3665 int i, ret; 3666 3667 parent_np = of_get_parent(np); 3668 map = syscon_node_to_regmap(parent_np); 3669 of_node_put(parent_np); 3670 if (IS_ERR(map)) { 3671 pr_err("failed to get HHI regmap - Trying obsolete regs\n"); 3672 return; 3673 } 3674 3675 rstc = kzalloc(sizeof(*rstc), GFP_KERNEL); 3676 if (!rstc) 3677 return; 3678 3679 /* Reset Controller */ 3680 rstc->regmap = map; 3681 rstc->reset.ops = &meson8b_clk_reset_ops; 3682 rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits); 3683 rstc->reset.of_node = np; 3684 ret = reset_controller_register(&rstc->reset); 3685 if (ret) { 3686 pr_err("%s: Failed to register clkc reset controller: %d\n", 3687 __func__, ret); 3688 return; 3689 } 3690 3691 /* 3692 * register all clks and start with the first used ID (which is 3693 * CLKID_PLL_FIXED) 3694 */ 3695 for (i = CLKID_PLL_FIXED; i < hw_clks->num; i++) { 3696 /* array might be sparse */ 3697 if (!hw_clks->hws[i]) 3698 continue; 3699 3700 ret = of_clk_hw_register(np, hw_clks->hws[i]); 3701 if (ret) 3702 return; 3703 } 3704 3705 meson8b_cpu_nb_data.cpu_clk = hw_clks->hws[CLKID_CPUCLK]; 3706 3707 /* 3708 * FIXME we shouldn't program the muxes in notifier handlers. The 3709 * tricky programming sequence will be handled by the forthcoming 3710 * coordinated clock rates mechanism once that feature is released. 3711 */ 3712 notifier_clk_name = clk_hw_get_name(&meson8b_cpu_scale_out_sel.hw); 3713 notifier_clk = __clk_lookup(notifier_clk_name); 3714 ret = clk_notifier_register(notifier_clk, &meson8b_cpu_nb_data.nb); 3715 if (ret) { 3716 pr_err("%s: failed to register the CPU clock notifier\n", 3717 __func__); 3718 return; 3719 } 3720 3721 ret = of_clk_add_hw_provider(np, meson_clk_hw_get, hw_clks); 3722 if (ret) 3723 pr_err("%s: failed to register clock provider\n", __func__); 3724 } 3725 3726 static void __init meson8_clkc_init(struct device_node *np) 3727 { 3728 return meson8b_clkc_init_common(np, &meson8_clks); 3729 } 3730 3731 static void __init meson8b_clkc_init(struct device_node *np) 3732 { 3733 return meson8b_clkc_init_common(np, &meson8b_clks); 3734 } 3735 3736 static void __init meson8m2_clkc_init(struct device_node *np) 3737 { 3738 return meson8b_clkc_init_common(np, &meson8m2_clks); 3739 } 3740 3741 CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc", 3742 meson8_clkc_init); 3743 CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc", 3744 meson8b_clkc_init); 3745 CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc", 3746 meson8m2_clkc_init); 3747