1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2015 Endless Mobile, Inc. 4 * Author: Carlo Caione <carlo@endlessm.com> 5 * 6 * Copyright (c) 2016 BayLibre, Inc. 7 * Michael Turquette <mturquette@baylibre.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/init.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/of_address.h> 15 #include <linux/reset-controller.h> 16 #include <linux/slab.h> 17 #include <linux/regmap.h> 18 19 #include "meson8b.h" 20 #include "clk-regmap.h" 21 #include "clk-pll.h" 22 #include "clk-mpll.h" 23 24 static DEFINE_SPINLOCK(meson_clk_lock); 25 26 struct meson8b_clk_reset { 27 struct reset_controller_dev reset; 28 struct regmap *regmap; 29 }; 30 31 static const struct pll_params_table sys_pll_params_table[] = { 32 PLL_PARAMS(50, 1), 33 PLL_PARAMS(51, 1), 34 PLL_PARAMS(52, 1), 35 PLL_PARAMS(53, 1), 36 PLL_PARAMS(54, 1), 37 PLL_PARAMS(55, 1), 38 PLL_PARAMS(56, 1), 39 PLL_PARAMS(57, 1), 40 PLL_PARAMS(58, 1), 41 PLL_PARAMS(59, 1), 42 PLL_PARAMS(60, 1), 43 PLL_PARAMS(61, 1), 44 PLL_PARAMS(62, 1), 45 PLL_PARAMS(63, 1), 46 PLL_PARAMS(64, 1), 47 PLL_PARAMS(65, 1), 48 PLL_PARAMS(66, 1), 49 PLL_PARAMS(67, 1), 50 PLL_PARAMS(68, 1), 51 PLL_PARAMS(84, 1), 52 { /* sentinel */ }, 53 }; 54 55 static struct clk_fixed_rate meson8b_xtal = { 56 .fixed_rate = 24000000, 57 .hw.init = &(struct clk_init_data){ 58 .name = "xtal", 59 .num_parents = 0, 60 .ops = &clk_fixed_rate_ops, 61 }, 62 }; 63 64 static struct clk_regmap meson8b_fixed_pll_dco = { 65 .data = &(struct meson_clk_pll_data){ 66 .en = { 67 .reg_off = HHI_MPLL_CNTL, 68 .shift = 30, 69 .width = 1, 70 }, 71 .m = { 72 .reg_off = HHI_MPLL_CNTL, 73 .shift = 0, 74 .width = 9, 75 }, 76 .n = { 77 .reg_off = HHI_MPLL_CNTL, 78 .shift = 9, 79 .width = 5, 80 }, 81 .frac = { 82 .reg_off = HHI_MPLL_CNTL2, 83 .shift = 0, 84 .width = 12, 85 }, 86 .l = { 87 .reg_off = HHI_MPLL_CNTL, 88 .shift = 31, 89 .width = 1, 90 }, 91 .rst = { 92 .reg_off = HHI_MPLL_CNTL, 93 .shift = 29, 94 .width = 1, 95 }, 96 }, 97 .hw.init = &(struct clk_init_data){ 98 .name = "fixed_pll_dco", 99 .ops = &meson_clk_pll_ro_ops, 100 .parent_names = (const char *[]){ "xtal" }, 101 .num_parents = 1, 102 }, 103 }; 104 105 static struct clk_regmap meson8b_fixed_pll = { 106 .data = &(struct clk_regmap_div_data){ 107 .offset = HHI_MPLL_CNTL, 108 .shift = 16, 109 .width = 2, 110 .flags = CLK_DIVIDER_POWER_OF_TWO, 111 }, 112 .hw.init = &(struct clk_init_data){ 113 .name = "fixed_pll", 114 .ops = &clk_regmap_divider_ro_ops, 115 .parent_names = (const char *[]){ "fixed_pll_dco" }, 116 .num_parents = 1, 117 /* 118 * This clock won't ever change at runtime so 119 * CLK_SET_RATE_PARENT is not required 120 */ 121 }, 122 }; 123 124 static struct clk_regmap meson8b_hdmi_pll_dco = { 125 .data = &(struct meson_clk_pll_data){ 126 .en = { 127 .reg_off = HHI_VID_PLL_CNTL, 128 .shift = 30, 129 .width = 1, 130 }, 131 .m = { 132 .reg_off = HHI_VID_PLL_CNTL, 133 .shift = 0, 134 .width = 9, 135 }, 136 .n = { 137 .reg_off = HHI_VID_PLL_CNTL, 138 .shift = 10, 139 .width = 5, 140 }, 141 .frac = { 142 .reg_off = HHI_VID_PLL_CNTL2, 143 .shift = 0, 144 .width = 12, 145 }, 146 .l = { 147 .reg_off = HHI_VID_PLL_CNTL, 148 .shift = 31, 149 .width = 1, 150 }, 151 .rst = { 152 .reg_off = HHI_VID_PLL_CNTL, 153 .shift = 29, 154 .width = 1, 155 }, 156 }, 157 .hw.init = &(struct clk_init_data){ 158 /* sometimes also called "HPLL" or "HPLL PLL" */ 159 .name = "hdmi_pll_dco", 160 .ops = &meson_clk_pll_ro_ops, 161 .parent_names = (const char *[]){ "xtal" }, 162 .num_parents = 1, 163 }, 164 }; 165 166 static struct clk_regmap meson8b_hdmi_pll_lvds_out = { 167 .data = &(struct clk_regmap_div_data){ 168 .offset = HHI_VID_PLL_CNTL, 169 .shift = 16, 170 .width = 2, 171 .flags = CLK_DIVIDER_POWER_OF_TWO, 172 }, 173 .hw.init = &(struct clk_init_data){ 174 .name = "hdmi_pll_lvds_out", 175 .ops = &clk_regmap_divider_ro_ops, 176 .parent_names = (const char *[]){ "hdmi_pll_dco" }, 177 .num_parents = 1, 178 .flags = CLK_SET_RATE_PARENT, 179 }, 180 }; 181 182 static struct clk_regmap meson8b_hdmi_pll_hdmi_out = { 183 .data = &(struct clk_regmap_div_data){ 184 .offset = HHI_VID_PLL_CNTL, 185 .shift = 18, 186 .width = 2, 187 .flags = CLK_DIVIDER_POWER_OF_TWO, 188 }, 189 .hw.init = &(struct clk_init_data){ 190 .name = "hdmi_pll_hdmi_out", 191 .ops = &clk_regmap_divider_ro_ops, 192 .parent_names = (const char *[]){ "hdmi_pll_dco" }, 193 .num_parents = 1, 194 .flags = CLK_SET_RATE_PARENT, 195 }, 196 }; 197 198 static struct clk_regmap meson8b_sys_pll_dco = { 199 .data = &(struct meson_clk_pll_data){ 200 .en = { 201 .reg_off = HHI_SYS_PLL_CNTL, 202 .shift = 30, 203 .width = 1, 204 }, 205 .m = { 206 .reg_off = HHI_SYS_PLL_CNTL, 207 .shift = 0, 208 .width = 9, 209 }, 210 .n = { 211 .reg_off = HHI_SYS_PLL_CNTL, 212 .shift = 9, 213 .width = 5, 214 }, 215 .l = { 216 .reg_off = HHI_SYS_PLL_CNTL, 217 .shift = 31, 218 .width = 1, 219 }, 220 .rst = { 221 .reg_off = HHI_SYS_PLL_CNTL, 222 .shift = 29, 223 .width = 1, 224 }, 225 .table = sys_pll_params_table, 226 }, 227 .hw.init = &(struct clk_init_data){ 228 .name = "sys_pll_dco", 229 .ops = &meson_clk_pll_ops, 230 .parent_names = (const char *[]){ "xtal" }, 231 .num_parents = 1, 232 }, 233 }; 234 235 static struct clk_regmap meson8b_sys_pll = { 236 .data = &(struct clk_regmap_div_data){ 237 .offset = HHI_SYS_PLL_CNTL, 238 .shift = 16, 239 .width = 2, 240 .flags = CLK_DIVIDER_POWER_OF_TWO, 241 }, 242 .hw.init = &(struct clk_init_data){ 243 .name = "sys_pll", 244 .ops = &clk_regmap_divider_ops, 245 .parent_names = (const char *[]){ "sys_pll_dco" }, 246 .num_parents = 1, 247 .flags = CLK_SET_RATE_PARENT, 248 }, 249 }; 250 251 static struct clk_fixed_factor meson8b_fclk_div2_div = { 252 .mult = 1, 253 .div = 2, 254 .hw.init = &(struct clk_init_data){ 255 .name = "fclk_div2_div", 256 .ops = &clk_fixed_factor_ops, 257 .parent_names = (const char *[]){ "fixed_pll" }, 258 .num_parents = 1, 259 }, 260 }; 261 262 static struct clk_regmap meson8b_fclk_div2 = { 263 .data = &(struct clk_regmap_gate_data){ 264 .offset = HHI_MPLL_CNTL6, 265 .bit_idx = 27, 266 }, 267 .hw.init = &(struct clk_init_data){ 268 .name = "fclk_div2", 269 .ops = &clk_regmap_gate_ops, 270 .parent_names = (const char *[]){ "fclk_div2_div" }, 271 .num_parents = 1, 272 /* 273 * FIXME: Ethernet with a RGMII PHYs is not working if 274 * fclk_div2 is disabled. it is currently unclear why this 275 * is. keep it enabled until the Ethernet driver knows how 276 * to manage this clock. 277 */ 278 .flags = CLK_IS_CRITICAL, 279 }, 280 }; 281 282 static struct clk_fixed_factor meson8b_fclk_div3_div = { 283 .mult = 1, 284 .div = 3, 285 .hw.init = &(struct clk_init_data){ 286 .name = "fclk_div3_div", 287 .ops = &clk_fixed_factor_ops, 288 .parent_names = (const char *[]){ "fixed_pll" }, 289 .num_parents = 1, 290 }, 291 }; 292 293 static struct clk_regmap meson8b_fclk_div3 = { 294 .data = &(struct clk_regmap_gate_data){ 295 .offset = HHI_MPLL_CNTL6, 296 .bit_idx = 28, 297 }, 298 .hw.init = &(struct clk_init_data){ 299 .name = "fclk_div3", 300 .ops = &clk_regmap_gate_ops, 301 .parent_names = (const char *[]){ "fclk_div3_div" }, 302 .num_parents = 1, 303 }, 304 }; 305 306 static struct clk_fixed_factor meson8b_fclk_div4_div = { 307 .mult = 1, 308 .div = 4, 309 .hw.init = &(struct clk_init_data){ 310 .name = "fclk_div4_div", 311 .ops = &clk_fixed_factor_ops, 312 .parent_names = (const char *[]){ "fixed_pll" }, 313 .num_parents = 1, 314 }, 315 }; 316 317 static struct clk_regmap meson8b_fclk_div4 = { 318 .data = &(struct clk_regmap_gate_data){ 319 .offset = HHI_MPLL_CNTL6, 320 .bit_idx = 29, 321 }, 322 .hw.init = &(struct clk_init_data){ 323 .name = "fclk_div4", 324 .ops = &clk_regmap_gate_ops, 325 .parent_names = (const char *[]){ "fclk_div4_div" }, 326 .num_parents = 1, 327 }, 328 }; 329 330 static struct clk_fixed_factor meson8b_fclk_div5_div = { 331 .mult = 1, 332 .div = 5, 333 .hw.init = &(struct clk_init_data){ 334 .name = "fclk_div5_div", 335 .ops = &clk_fixed_factor_ops, 336 .parent_names = (const char *[]){ "fixed_pll" }, 337 .num_parents = 1, 338 }, 339 }; 340 341 static struct clk_regmap meson8b_fclk_div5 = { 342 .data = &(struct clk_regmap_gate_data){ 343 .offset = HHI_MPLL_CNTL6, 344 .bit_idx = 30, 345 }, 346 .hw.init = &(struct clk_init_data){ 347 .name = "fclk_div5", 348 .ops = &clk_regmap_gate_ops, 349 .parent_names = (const char *[]){ "fclk_div5_div" }, 350 .num_parents = 1, 351 }, 352 }; 353 354 static struct clk_fixed_factor meson8b_fclk_div7_div = { 355 .mult = 1, 356 .div = 7, 357 .hw.init = &(struct clk_init_data){ 358 .name = "fclk_div7_div", 359 .ops = &clk_fixed_factor_ops, 360 .parent_names = (const char *[]){ "fixed_pll" }, 361 .num_parents = 1, 362 }, 363 }; 364 365 static struct clk_regmap meson8b_fclk_div7 = { 366 .data = &(struct clk_regmap_gate_data){ 367 .offset = HHI_MPLL_CNTL6, 368 .bit_idx = 31, 369 }, 370 .hw.init = &(struct clk_init_data){ 371 .name = "fclk_div7", 372 .ops = &clk_regmap_gate_ops, 373 .parent_names = (const char *[]){ "fclk_div7_div" }, 374 .num_parents = 1, 375 }, 376 }; 377 378 static struct clk_regmap meson8b_mpll_prediv = { 379 .data = &(struct clk_regmap_div_data){ 380 .offset = HHI_MPLL_CNTL5, 381 .shift = 12, 382 .width = 1, 383 }, 384 .hw.init = &(struct clk_init_data){ 385 .name = "mpll_prediv", 386 .ops = &clk_regmap_divider_ro_ops, 387 .parent_names = (const char *[]){ "fixed_pll" }, 388 .num_parents = 1, 389 }, 390 }; 391 392 static struct clk_regmap meson8b_mpll0_div = { 393 .data = &(struct meson_clk_mpll_data){ 394 .sdm = { 395 .reg_off = HHI_MPLL_CNTL7, 396 .shift = 0, 397 .width = 14, 398 }, 399 .sdm_en = { 400 .reg_off = HHI_MPLL_CNTL7, 401 .shift = 15, 402 .width = 1, 403 }, 404 .n2 = { 405 .reg_off = HHI_MPLL_CNTL7, 406 .shift = 16, 407 .width = 9, 408 }, 409 .ssen = { 410 .reg_off = HHI_MPLL_CNTL, 411 .shift = 25, 412 .width = 1, 413 }, 414 .lock = &meson_clk_lock, 415 }, 416 .hw.init = &(struct clk_init_data){ 417 .name = "mpll0_div", 418 .ops = &meson_clk_mpll_ops, 419 .parent_names = (const char *[]){ "mpll_prediv" }, 420 .num_parents = 1, 421 }, 422 }; 423 424 static struct clk_regmap meson8b_mpll0 = { 425 .data = &(struct clk_regmap_gate_data){ 426 .offset = HHI_MPLL_CNTL7, 427 .bit_idx = 14, 428 }, 429 .hw.init = &(struct clk_init_data){ 430 .name = "mpll0", 431 .ops = &clk_regmap_gate_ops, 432 .parent_names = (const char *[]){ "mpll0_div" }, 433 .num_parents = 1, 434 .flags = CLK_SET_RATE_PARENT, 435 }, 436 }; 437 438 static struct clk_regmap meson8b_mpll1_div = { 439 .data = &(struct meson_clk_mpll_data){ 440 .sdm = { 441 .reg_off = HHI_MPLL_CNTL8, 442 .shift = 0, 443 .width = 14, 444 }, 445 .sdm_en = { 446 .reg_off = HHI_MPLL_CNTL8, 447 .shift = 15, 448 .width = 1, 449 }, 450 .n2 = { 451 .reg_off = HHI_MPLL_CNTL8, 452 .shift = 16, 453 .width = 9, 454 }, 455 .lock = &meson_clk_lock, 456 }, 457 .hw.init = &(struct clk_init_data){ 458 .name = "mpll1_div", 459 .ops = &meson_clk_mpll_ops, 460 .parent_names = (const char *[]){ "mpll_prediv" }, 461 .num_parents = 1, 462 }, 463 }; 464 465 static struct clk_regmap meson8b_mpll1 = { 466 .data = &(struct clk_regmap_gate_data){ 467 .offset = HHI_MPLL_CNTL8, 468 .bit_idx = 14, 469 }, 470 .hw.init = &(struct clk_init_data){ 471 .name = "mpll1", 472 .ops = &clk_regmap_gate_ops, 473 .parent_names = (const char *[]){ "mpll1_div" }, 474 .num_parents = 1, 475 .flags = CLK_SET_RATE_PARENT, 476 }, 477 }; 478 479 static struct clk_regmap meson8b_mpll2_div = { 480 .data = &(struct meson_clk_mpll_data){ 481 .sdm = { 482 .reg_off = HHI_MPLL_CNTL9, 483 .shift = 0, 484 .width = 14, 485 }, 486 .sdm_en = { 487 .reg_off = HHI_MPLL_CNTL9, 488 .shift = 15, 489 .width = 1, 490 }, 491 .n2 = { 492 .reg_off = HHI_MPLL_CNTL9, 493 .shift = 16, 494 .width = 9, 495 }, 496 .lock = &meson_clk_lock, 497 }, 498 .hw.init = &(struct clk_init_data){ 499 .name = "mpll2_div", 500 .ops = &meson_clk_mpll_ops, 501 .parent_names = (const char *[]){ "mpll_prediv" }, 502 .num_parents = 1, 503 }, 504 }; 505 506 static struct clk_regmap meson8b_mpll2 = { 507 .data = &(struct clk_regmap_gate_data){ 508 .offset = HHI_MPLL_CNTL9, 509 .bit_idx = 14, 510 }, 511 .hw.init = &(struct clk_init_data){ 512 .name = "mpll2", 513 .ops = &clk_regmap_gate_ops, 514 .parent_names = (const char *[]){ "mpll2_div" }, 515 .num_parents = 1, 516 .flags = CLK_SET_RATE_PARENT, 517 }, 518 }; 519 520 static u32 mux_table_clk81[] = { 6, 5, 7 }; 521 static struct clk_regmap meson8b_mpeg_clk_sel = { 522 .data = &(struct clk_regmap_mux_data){ 523 .offset = HHI_MPEG_CLK_CNTL, 524 .mask = 0x7, 525 .shift = 12, 526 .table = mux_table_clk81, 527 }, 528 .hw.init = &(struct clk_init_data){ 529 .name = "mpeg_clk_sel", 530 .ops = &clk_regmap_mux_ro_ops, 531 /* 532 * FIXME bits 14:12 selects from 8 possible parents: 533 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, 534 * fclk_div4, fclk_div3, fclk_div5 535 */ 536 .parent_names = (const char *[]){ "fclk_div3", "fclk_div4", 537 "fclk_div5" }, 538 .num_parents = 3, 539 }, 540 }; 541 542 static struct clk_regmap meson8b_mpeg_clk_div = { 543 .data = &(struct clk_regmap_div_data){ 544 .offset = HHI_MPEG_CLK_CNTL, 545 .shift = 0, 546 .width = 7, 547 }, 548 .hw.init = &(struct clk_init_data){ 549 .name = "mpeg_clk_div", 550 .ops = &clk_regmap_divider_ro_ops, 551 .parent_names = (const char *[]){ "mpeg_clk_sel" }, 552 .num_parents = 1, 553 }, 554 }; 555 556 static struct clk_regmap meson8b_clk81 = { 557 .data = &(struct clk_regmap_gate_data){ 558 .offset = HHI_MPEG_CLK_CNTL, 559 .bit_idx = 7, 560 }, 561 .hw.init = &(struct clk_init_data){ 562 .name = "clk81", 563 .ops = &clk_regmap_gate_ops, 564 .parent_names = (const char *[]){ "mpeg_clk_div" }, 565 .num_parents = 1, 566 .flags = CLK_IS_CRITICAL, 567 }, 568 }; 569 570 static struct clk_regmap meson8b_cpu_in_sel = { 571 .data = &(struct clk_regmap_mux_data){ 572 .offset = HHI_SYS_CPU_CLK_CNTL0, 573 .mask = 0x1, 574 .shift = 0, 575 }, 576 .hw.init = &(struct clk_init_data){ 577 .name = "cpu_in_sel", 578 .ops = &clk_regmap_mux_ops, 579 .parent_names = (const char *[]){ "xtal", "sys_pll" }, 580 .num_parents = 2, 581 .flags = (CLK_SET_RATE_PARENT | 582 CLK_SET_RATE_NO_REPARENT), 583 }, 584 }; 585 586 static struct clk_fixed_factor meson8b_cpu_in_div2 = { 587 .mult = 1, 588 .div = 2, 589 .hw.init = &(struct clk_init_data){ 590 .name = "cpu_in_div2", 591 .ops = &clk_fixed_factor_ops, 592 .parent_names = (const char *[]){ "cpu_in_sel" }, 593 .num_parents = 1, 594 .flags = CLK_SET_RATE_PARENT, 595 }, 596 }; 597 598 static struct clk_fixed_factor meson8b_cpu_in_div3 = { 599 .mult = 1, 600 .div = 3, 601 .hw.init = &(struct clk_init_data){ 602 .name = "cpu_in_div3", 603 .ops = &clk_fixed_factor_ops, 604 .parent_names = (const char *[]){ "cpu_in_sel" }, 605 .num_parents = 1, 606 .flags = CLK_SET_RATE_PARENT, 607 }, 608 }; 609 610 static const struct clk_div_table cpu_scale_table[] = { 611 { .val = 1, .div = 4 }, 612 { .val = 2, .div = 6 }, 613 { .val = 3, .div = 8 }, 614 { .val = 4, .div = 10 }, 615 { .val = 5, .div = 12 }, 616 { .val = 6, .div = 14 }, 617 { .val = 7, .div = 16 }, 618 { .val = 8, .div = 18 }, 619 { /* sentinel */ }, 620 }; 621 622 static struct clk_regmap meson8b_cpu_scale_div = { 623 .data = &(struct clk_regmap_div_data){ 624 .offset = HHI_SYS_CPU_CLK_CNTL1, 625 .shift = 20, 626 .width = 10, 627 .table = cpu_scale_table, 628 .flags = CLK_DIVIDER_ALLOW_ZERO, 629 }, 630 .hw.init = &(struct clk_init_data){ 631 .name = "cpu_scale_div", 632 .ops = &clk_regmap_divider_ops, 633 .parent_names = (const char *[]){ "cpu_in_sel" }, 634 .num_parents = 1, 635 .flags = CLK_SET_RATE_PARENT, 636 }, 637 }; 638 639 static u32 mux_table_cpu_scale_out_sel[] = { 0, 1, 3 }; 640 static struct clk_regmap meson8b_cpu_scale_out_sel = { 641 .data = &(struct clk_regmap_mux_data){ 642 .offset = HHI_SYS_CPU_CLK_CNTL0, 643 .mask = 0x3, 644 .shift = 2, 645 .table = mux_table_cpu_scale_out_sel, 646 }, 647 .hw.init = &(struct clk_init_data){ 648 .name = "cpu_scale_out_sel", 649 .ops = &clk_regmap_mux_ops, 650 /* 651 * NOTE: We are skipping the parent with value 0x2 (which is 652 * "cpu_in_div3") because it results in a duty cycle of 33% 653 * which makes the system unstable and can result in a lockup 654 * of the whole system. 655 */ 656 .parent_names = (const char *[]) { "cpu_in_sel", 657 "cpu_in_div2", 658 "cpu_scale_div" }, 659 .num_parents = 3, 660 .flags = CLK_SET_RATE_PARENT, 661 }, 662 }; 663 664 static struct clk_regmap meson8b_cpu_clk = { 665 .data = &(struct clk_regmap_mux_data){ 666 .offset = HHI_SYS_CPU_CLK_CNTL0, 667 .mask = 0x1, 668 .shift = 7, 669 }, 670 .hw.init = &(struct clk_init_data){ 671 .name = "cpu_clk", 672 .ops = &clk_regmap_mux_ops, 673 .parent_names = (const char *[]){ "xtal", 674 "cpu_scale_out_sel" }, 675 .num_parents = 2, 676 .flags = (CLK_SET_RATE_PARENT | 677 CLK_SET_RATE_NO_REPARENT | 678 CLK_IS_CRITICAL), 679 }, 680 }; 681 682 static struct clk_regmap meson8b_nand_clk_sel = { 683 .data = &(struct clk_regmap_mux_data){ 684 .offset = HHI_NAND_CLK_CNTL, 685 .mask = 0x7, 686 .shift = 9, 687 .flags = CLK_MUX_ROUND_CLOSEST, 688 }, 689 .hw.init = &(struct clk_init_data){ 690 .name = "nand_clk_sel", 691 .ops = &clk_regmap_mux_ops, 692 /* FIXME all other parents are unknown: */ 693 .parent_names = (const char *[]){ "fclk_div4", "fclk_div3", 694 "fclk_div5", "fclk_div7", "xtal" }, 695 .num_parents = 5, 696 .flags = CLK_SET_RATE_PARENT, 697 }, 698 }; 699 700 static struct clk_regmap meson8b_nand_clk_div = { 701 .data = &(struct clk_regmap_div_data){ 702 .offset = HHI_NAND_CLK_CNTL, 703 .shift = 0, 704 .width = 7, 705 .flags = CLK_DIVIDER_ROUND_CLOSEST, 706 }, 707 .hw.init = &(struct clk_init_data){ 708 .name = "nand_clk_div", 709 .ops = &clk_regmap_divider_ops, 710 .parent_names = (const char *[]){ "nand_clk_sel" }, 711 .num_parents = 1, 712 .flags = CLK_SET_RATE_PARENT, 713 }, 714 }; 715 716 static struct clk_regmap meson8b_nand_clk_gate = { 717 .data = &(struct clk_regmap_gate_data){ 718 .offset = HHI_NAND_CLK_CNTL, 719 .bit_idx = 8, 720 }, 721 .hw.init = &(struct clk_init_data){ 722 .name = "nand_clk_gate", 723 .ops = &clk_regmap_gate_ops, 724 .parent_names = (const char *[]){ "nand_clk_div" }, 725 .num_parents = 1, 726 .flags = CLK_SET_RATE_PARENT, 727 }, 728 }; 729 730 static struct clk_fixed_factor meson8b_cpu_clk_div2 = { 731 .mult = 1, 732 .div = 2, 733 .hw.init = &(struct clk_init_data){ 734 .name = "cpu_clk_div2", 735 .ops = &clk_fixed_factor_ops, 736 .parent_names = (const char *[]){ "cpu_clk" }, 737 .num_parents = 1, 738 }, 739 }; 740 741 static struct clk_fixed_factor meson8b_cpu_clk_div3 = { 742 .mult = 1, 743 .div = 3, 744 .hw.init = &(struct clk_init_data){ 745 .name = "cpu_clk_div3", 746 .ops = &clk_fixed_factor_ops, 747 .parent_names = (const char *[]){ "cpu_clk" }, 748 .num_parents = 1, 749 }, 750 }; 751 752 static struct clk_fixed_factor meson8b_cpu_clk_div4 = { 753 .mult = 1, 754 .div = 4, 755 .hw.init = &(struct clk_init_data){ 756 .name = "cpu_clk_div4", 757 .ops = &clk_fixed_factor_ops, 758 .parent_names = (const char *[]){ "cpu_clk" }, 759 .num_parents = 1, 760 }, 761 }; 762 763 static struct clk_fixed_factor meson8b_cpu_clk_div5 = { 764 .mult = 1, 765 .div = 5, 766 .hw.init = &(struct clk_init_data){ 767 .name = "cpu_clk_div5", 768 .ops = &clk_fixed_factor_ops, 769 .parent_names = (const char *[]){ "cpu_clk" }, 770 .num_parents = 1, 771 }, 772 }; 773 774 static struct clk_fixed_factor meson8b_cpu_clk_div6 = { 775 .mult = 1, 776 .div = 6, 777 .hw.init = &(struct clk_init_data){ 778 .name = "cpu_clk_div6", 779 .ops = &clk_fixed_factor_ops, 780 .parent_names = (const char *[]){ "cpu_clk" }, 781 .num_parents = 1, 782 }, 783 }; 784 785 static struct clk_fixed_factor meson8b_cpu_clk_div7 = { 786 .mult = 1, 787 .div = 7, 788 .hw.init = &(struct clk_init_data){ 789 .name = "cpu_clk_div7", 790 .ops = &clk_fixed_factor_ops, 791 .parent_names = (const char *[]){ "cpu_clk" }, 792 .num_parents = 1, 793 }, 794 }; 795 796 static struct clk_fixed_factor meson8b_cpu_clk_div8 = { 797 .mult = 1, 798 .div = 8, 799 .hw.init = &(struct clk_init_data){ 800 .name = "cpu_clk_div8", 801 .ops = &clk_fixed_factor_ops, 802 .parent_names = (const char *[]){ "cpu_clk" }, 803 .num_parents = 1, 804 }, 805 }; 806 807 static u32 mux_table_apb[] = { 1, 2, 3, 4, 5, 6, 7 }; 808 static struct clk_regmap meson8b_apb_clk_sel = { 809 .data = &(struct clk_regmap_mux_data){ 810 .offset = HHI_SYS_CPU_CLK_CNTL1, 811 .mask = 0x7, 812 .shift = 3, 813 .table = mux_table_apb, 814 }, 815 .hw.init = &(struct clk_init_data){ 816 .name = "apb_clk_sel", 817 .ops = &clk_regmap_mux_ops, 818 .parent_names = (const char *[]){ "cpu_clk_div2", 819 "cpu_clk_div3", 820 "cpu_clk_div4", 821 "cpu_clk_div5", 822 "cpu_clk_div6", 823 "cpu_clk_div7", 824 "cpu_clk_div8", }, 825 .num_parents = 7, 826 }, 827 }; 828 829 static struct clk_regmap meson8b_apb_clk_gate = { 830 .data = &(struct clk_regmap_gate_data){ 831 .offset = HHI_SYS_CPU_CLK_CNTL1, 832 .bit_idx = 16, 833 .flags = CLK_GATE_SET_TO_DISABLE, 834 }, 835 .hw.init = &(struct clk_init_data){ 836 .name = "apb_clk_dis", 837 .ops = &clk_regmap_gate_ro_ops, 838 .parent_names = (const char *[]){ "apb_clk_sel" }, 839 .num_parents = 1, 840 .flags = CLK_SET_RATE_PARENT, 841 }, 842 }; 843 844 static struct clk_regmap meson8b_periph_clk_sel = { 845 .data = &(struct clk_regmap_mux_data){ 846 .offset = HHI_SYS_CPU_CLK_CNTL1, 847 .mask = 0x7, 848 .shift = 6, 849 }, 850 .hw.init = &(struct clk_init_data){ 851 .name = "periph_clk_sel", 852 .ops = &clk_regmap_mux_ops, 853 .parent_names = (const char *[]){ "cpu_clk_div2", 854 "cpu_clk_div3", 855 "cpu_clk_div4", 856 "cpu_clk_div5", 857 "cpu_clk_div6", 858 "cpu_clk_div7", 859 "cpu_clk_div8", }, 860 .num_parents = 7, 861 }, 862 }; 863 864 static struct clk_regmap meson8b_periph_clk_gate = { 865 .data = &(struct clk_regmap_gate_data){ 866 .offset = HHI_SYS_CPU_CLK_CNTL1, 867 .bit_idx = 17, 868 .flags = CLK_GATE_SET_TO_DISABLE, 869 }, 870 .hw.init = &(struct clk_init_data){ 871 .name = "periph_clk_dis", 872 .ops = &clk_regmap_gate_ro_ops, 873 .parent_names = (const char *[]){ "periph_clk_sel" }, 874 .num_parents = 1, 875 .flags = CLK_SET_RATE_PARENT, 876 }, 877 }; 878 879 static u32 mux_table_axi[] = { 1, 2, 3, 4, 5, 6, 7 }; 880 static struct clk_regmap meson8b_axi_clk_sel = { 881 .data = &(struct clk_regmap_mux_data){ 882 .offset = HHI_SYS_CPU_CLK_CNTL1, 883 .mask = 0x7, 884 .shift = 9, 885 .table = mux_table_axi, 886 }, 887 .hw.init = &(struct clk_init_data){ 888 .name = "axi_clk_sel", 889 .ops = &clk_regmap_mux_ops, 890 .parent_names = (const char *[]){ "cpu_clk_div2", 891 "cpu_clk_div3", 892 "cpu_clk_div4", 893 "cpu_clk_div5", 894 "cpu_clk_div6", 895 "cpu_clk_div7", 896 "cpu_clk_div8", }, 897 .num_parents = 7, 898 }, 899 }; 900 901 static struct clk_regmap meson8b_axi_clk_gate = { 902 .data = &(struct clk_regmap_gate_data){ 903 .offset = HHI_SYS_CPU_CLK_CNTL1, 904 .bit_idx = 18, 905 .flags = CLK_GATE_SET_TO_DISABLE, 906 }, 907 .hw.init = &(struct clk_init_data){ 908 .name = "axi_clk_dis", 909 .ops = &clk_regmap_gate_ro_ops, 910 .parent_names = (const char *[]){ "axi_clk_sel" }, 911 .num_parents = 1, 912 .flags = CLK_SET_RATE_PARENT, 913 }, 914 }; 915 916 static struct clk_regmap meson8b_l2_dram_clk_sel = { 917 .data = &(struct clk_regmap_mux_data){ 918 .offset = HHI_SYS_CPU_CLK_CNTL1, 919 .mask = 0x7, 920 .shift = 12, 921 }, 922 .hw.init = &(struct clk_init_data){ 923 .name = "l2_dram_clk_sel", 924 .ops = &clk_regmap_mux_ops, 925 .parent_names = (const char *[]){ "cpu_clk_div2", 926 "cpu_clk_div3", 927 "cpu_clk_div4", 928 "cpu_clk_div5", 929 "cpu_clk_div6", 930 "cpu_clk_div7", 931 "cpu_clk_div8", }, 932 .num_parents = 7, 933 }, 934 }; 935 936 static struct clk_regmap meson8b_l2_dram_clk_gate = { 937 .data = &(struct clk_regmap_gate_data){ 938 .offset = HHI_SYS_CPU_CLK_CNTL1, 939 .bit_idx = 19, 940 .flags = CLK_GATE_SET_TO_DISABLE, 941 }, 942 .hw.init = &(struct clk_init_data){ 943 .name = "l2_dram_clk_dis", 944 .ops = &clk_regmap_gate_ro_ops, 945 .parent_names = (const char *[]){ "l2_dram_clk_sel" }, 946 .num_parents = 1, 947 .flags = CLK_SET_RATE_PARENT, 948 }, 949 }; 950 951 static struct clk_regmap meson8b_vid_pll_in_sel = { 952 .data = &(struct clk_regmap_mux_data){ 953 .offset = HHI_VID_DIVIDER_CNTL, 954 .mask = 0x1, 955 .shift = 15, 956 }, 957 .hw.init = &(struct clk_init_data){ 958 .name = "vid_pll_in_sel", 959 .ops = &clk_regmap_mux_ro_ops, 960 /* 961 * TODO: depending on the SoC there is also a second parent: 962 * Meson8: unknown 963 * Meson8b: hdmi_pll_dco 964 * Meson8m2: vid2_pll 965 */ 966 .parent_names = (const char *[]){ "hdmi_pll_dco" }, 967 .num_parents = 1, 968 .flags = CLK_SET_RATE_PARENT, 969 }, 970 }; 971 972 static struct clk_regmap meson8b_vid_pll_in_en = { 973 .data = &(struct clk_regmap_gate_data){ 974 .offset = HHI_VID_DIVIDER_CNTL, 975 .bit_idx = 16, 976 }, 977 .hw.init = &(struct clk_init_data){ 978 .name = "vid_pll_in_en", 979 .ops = &clk_regmap_gate_ro_ops, 980 .parent_names = (const char *[]){ "vid_pll_in_sel" }, 981 .num_parents = 1, 982 .flags = CLK_SET_RATE_PARENT, 983 }, 984 }; 985 986 static struct clk_regmap meson8b_vid_pll_pre_div = { 987 .data = &(struct clk_regmap_div_data){ 988 .offset = HHI_VID_DIVIDER_CNTL, 989 .shift = 4, 990 .width = 3, 991 }, 992 .hw.init = &(struct clk_init_data){ 993 .name = "vid_pll_pre_div", 994 .ops = &clk_regmap_divider_ro_ops, 995 .parent_names = (const char *[]){ "vid_pll_in_en" }, 996 .num_parents = 1, 997 .flags = CLK_SET_RATE_PARENT, 998 }, 999 }; 1000 1001 static struct clk_regmap meson8b_vid_pll_post_div = { 1002 .data = &(struct clk_regmap_div_data){ 1003 .offset = HHI_VID_DIVIDER_CNTL, 1004 .shift = 12, 1005 .width = 3, 1006 }, 1007 .hw.init = &(struct clk_init_data){ 1008 .name = "vid_pll_post_div", 1009 .ops = &clk_regmap_divider_ro_ops, 1010 .parent_names = (const char *[]){ "vid_pll_pre_div" }, 1011 .num_parents = 1, 1012 .flags = CLK_SET_RATE_PARENT, 1013 }, 1014 }; 1015 1016 static struct clk_regmap meson8b_vid_pll = { 1017 .data = &(struct clk_regmap_mux_data){ 1018 .offset = HHI_VID_DIVIDER_CNTL, 1019 .mask = 0x3, 1020 .shift = 8, 1021 }, 1022 .hw.init = &(struct clk_init_data){ 1023 .name = "vid_pll", 1024 .ops = &clk_regmap_mux_ro_ops, 1025 /* TODO: parent 0x2 is vid_pll_pre_div_mult7_div2 */ 1026 .parent_names = (const char *[]){ "vid_pll_pre_div", 1027 "vid_pll_post_div" }, 1028 .num_parents = 2, 1029 .flags = CLK_SET_RATE_PARENT, 1030 }, 1031 }; 1032 1033 static struct clk_regmap meson8b_vid_pll_final_div = { 1034 .data = &(struct clk_regmap_div_data){ 1035 .offset = HHI_VID_CLK_DIV, 1036 .shift = 0, 1037 .width = 8, 1038 }, 1039 .hw.init = &(struct clk_init_data){ 1040 .name = "vid_pll_final_div", 1041 .ops = &clk_regmap_divider_ro_ops, 1042 .parent_names = (const char *[]){ "vid_pll" }, 1043 .num_parents = 1, 1044 .flags = CLK_SET_RATE_PARENT, 1045 }, 1046 }; 1047 1048 static const char * const meson8b_vclk_mux_parents[] = { 1049 "vid_pll_final_div", "fclk_div4", "fclk_div3", "fclk_div5", 1050 "vid_pll_final_div", "fclk_div7", "mpll1" 1051 }; 1052 1053 static struct clk_regmap meson8b_vclk_in_sel = { 1054 .data = &(struct clk_regmap_mux_data){ 1055 .offset = HHI_VID_CLK_CNTL, 1056 .mask = 0x7, 1057 .shift = 16, 1058 }, 1059 .hw.init = &(struct clk_init_data){ 1060 .name = "vclk_in_sel", 1061 .ops = &clk_regmap_mux_ro_ops, 1062 .parent_names = meson8b_vclk_mux_parents, 1063 .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parents), 1064 .flags = CLK_SET_RATE_PARENT, 1065 }, 1066 }; 1067 1068 static struct clk_regmap meson8b_vclk_in_en = { 1069 .data = &(struct clk_regmap_gate_data){ 1070 .offset = HHI_VID_CLK_DIV, 1071 .bit_idx = 16, 1072 }, 1073 .hw.init = &(struct clk_init_data){ 1074 .name = "vclk_in_en", 1075 .ops = &clk_regmap_gate_ro_ops, 1076 .parent_names = (const char *[]){ "vclk_in_sel" }, 1077 .num_parents = 1, 1078 .flags = CLK_SET_RATE_PARENT, 1079 }, 1080 }; 1081 1082 static struct clk_regmap meson8b_vclk_div1_gate = { 1083 .data = &(struct clk_regmap_gate_data){ 1084 .offset = HHI_VID_CLK_DIV, 1085 .bit_idx = 0, 1086 }, 1087 .hw.init = &(struct clk_init_data){ 1088 .name = "vclk_div1_en", 1089 .ops = &clk_regmap_gate_ro_ops, 1090 .parent_names = (const char *[]){ "vclk_in_en" }, 1091 .num_parents = 1, 1092 .flags = CLK_SET_RATE_PARENT, 1093 }, 1094 }; 1095 1096 static struct clk_fixed_factor meson8b_vclk_div2_div = { 1097 .mult = 1, 1098 .div = 2, 1099 .hw.init = &(struct clk_init_data){ 1100 .name = "vclk_div2", 1101 .ops = &clk_fixed_factor_ops, 1102 .parent_names = (const char *[]){ "vclk_in_en" }, 1103 .num_parents = 1, 1104 .flags = CLK_SET_RATE_PARENT, 1105 } 1106 }; 1107 1108 static struct clk_regmap meson8b_vclk_div2_div_gate = { 1109 .data = &(struct clk_regmap_gate_data){ 1110 .offset = HHI_VID_CLK_DIV, 1111 .bit_idx = 1, 1112 }, 1113 .hw.init = &(struct clk_init_data){ 1114 .name = "vclk_div2_en", 1115 .ops = &clk_regmap_gate_ro_ops, 1116 .parent_names = (const char *[]){ "vclk_div2" }, 1117 .num_parents = 1, 1118 .flags = CLK_SET_RATE_PARENT, 1119 }, 1120 }; 1121 1122 static struct clk_fixed_factor meson8b_vclk_div4_div = { 1123 .mult = 1, 1124 .div = 4, 1125 .hw.init = &(struct clk_init_data){ 1126 .name = "vclk_div4", 1127 .ops = &clk_fixed_factor_ops, 1128 .parent_names = (const char *[]){ "vclk_in_en" }, 1129 .num_parents = 1, 1130 .flags = CLK_SET_RATE_PARENT, 1131 } 1132 }; 1133 1134 static struct clk_regmap meson8b_vclk_div4_div_gate = { 1135 .data = &(struct clk_regmap_gate_data){ 1136 .offset = HHI_VID_CLK_DIV, 1137 .bit_idx = 2, 1138 }, 1139 .hw.init = &(struct clk_init_data){ 1140 .name = "vclk_div4_en", 1141 .ops = &clk_regmap_gate_ro_ops, 1142 .parent_names = (const char *[]){ "vclk_div4" }, 1143 .num_parents = 1, 1144 .flags = CLK_SET_RATE_PARENT, 1145 }, 1146 }; 1147 1148 static struct clk_fixed_factor meson8b_vclk_div6_div = { 1149 .mult = 1, 1150 .div = 6, 1151 .hw.init = &(struct clk_init_data){ 1152 .name = "vclk_div6", 1153 .ops = &clk_fixed_factor_ops, 1154 .parent_names = (const char *[]){ "vclk_in_en" }, 1155 .num_parents = 1, 1156 .flags = CLK_SET_RATE_PARENT, 1157 } 1158 }; 1159 1160 static struct clk_regmap meson8b_vclk_div6_div_gate = { 1161 .data = &(struct clk_regmap_gate_data){ 1162 .offset = HHI_VID_CLK_DIV, 1163 .bit_idx = 3, 1164 }, 1165 .hw.init = &(struct clk_init_data){ 1166 .name = "vclk_div6_en", 1167 .ops = &clk_regmap_gate_ro_ops, 1168 .parent_names = (const char *[]){ "vclk_div6" }, 1169 .num_parents = 1, 1170 .flags = CLK_SET_RATE_PARENT, 1171 }, 1172 }; 1173 1174 static struct clk_fixed_factor meson8b_vclk_div12_div = { 1175 .mult = 1, 1176 .div = 12, 1177 .hw.init = &(struct clk_init_data){ 1178 .name = "vclk_div12", 1179 .ops = &clk_fixed_factor_ops, 1180 .parent_names = (const char *[]){ "vclk_in_en" }, 1181 .num_parents = 1, 1182 .flags = CLK_SET_RATE_PARENT, 1183 } 1184 }; 1185 1186 static struct clk_regmap meson8b_vclk_div12_div_gate = { 1187 .data = &(struct clk_regmap_gate_data){ 1188 .offset = HHI_VID_CLK_DIV, 1189 .bit_idx = 4, 1190 }, 1191 .hw.init = &(struct clk_init_data){ 1192 .name = "vclk_div12_en", 1193 .ops = &clk_regmap_gate_ro_ops, 1194 .parent_names = (const char *[]){ "vclk_div12" }, 1195 .num_parents = 1, 1196 .flags = CLK_SET_RATE_PARENT, 1197 }, 1198 }; 1199 1200 static struct clk_regmap meson8b_vclk2_in_sel = { 1201 .data = &(struct clk_regmap_mux_data){ 1202 .offset = HHI_VIID_CLK_CNTL, 1203 .mask = 0x7, 1204 .shift = 16, 1205 }, 1206 .hw.init = &(struct clk_init_data){ 1207 .name = "vclk2_in_sel", 1208 .ops = &clk_regmap_mux_ro_ops, 1209 .parent_names = meson8b_vclk_mux_parents, 1210 .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parents), 1211 .flags = CLK_SET_RATE_PARENT, 1212 }, 1213 }; 1214 1215 static struct clk_regmap meson8b_vclk2_clk_in_en = { 1216 .data = &(struct clk_regmap_gate_data){ 1217 .offset = HHI_VIID_CLK_DIV, 1218 .bit_idx = 16, 1219 }, 1220 .hw.init = &(struct clk_init_data){ 1221 .name = "vclk2_in_en", 1222 .ops = &clk_regmap_gate_ro_ops, 1223 .parent_names = (const char *[]){ "vclk2_in_sel" }, 1224 .num_parents = 1, 1225 .flags = CLK_SET_RATE_PARENT, 1226 }, 1227 }; 1228 1229 static struct clk_regmap meson8b_vclk2_div1_gate = { 1230 .data = &(struct clk_regmap_gate_data){ 1231 .offset = HHI_VIID_CLK_DIV, 1232 .bit_idx = 0, 1233 }, 1234 .hw.init = &(struct clk_init_data){ 1235 .name = "vclk2_div1_en", 1236 .ops = &clk_regmap_gate_ro_ops, 1237 .parent_names = (const char *[]){ "vclk2_in_en" }, 1238 .num_parents = 1, 1239 .flags = CLK_SET_RATE_PARENT, 1240 }, 1241 }; 1242 1243 static struct clk_fixed_factor meson8b_vclk2_div2_div = { 1244 .mult = 1, 1245 .div = 2, 1246 .hw.init = &(struct clk_init_data){ 1247 .name = "vclk2_div2", 1248 .ops = &clk_fixed_factor_ops, 1249 .parent_names = (const char *[]){ "vclk2_in_en" }, 1250 .num_parents = 1, 1251 .flags = CLK_SET_RATE_PARENT, 1252 } 1253 }; 1254 1255 static struct clk_regmap meson8b_vclk2_div2_div_gate = { 1256 .data = &(struct clk_regmap_gate_data){ 1257 .offset = HHI_VIID_CLK_DIV, 1258 .bit_idx = 1, 1259 }, 1260 .hw.init = &(struct clk_init_data){ 1261 .name = "vclk2_div2_en", 1262 .ops = &clk_regmap_gate_ro_ops, 1263 .parent_names = (const char *[]){ "vclk2_div2" }, 1264 .num_parents = 1, 1265 .flags = CLK_SET_RATE_PARENT, 1266 }, 1267 }; 1268 1269 static struct clk_fixed_factor meson8b_vclk2_div4_div = { 1270 .mult = 1, 1271 .div = 4, 1272 .hw.init = &(struct clk_init_data){ 1273 .name = "vclk2_div4", 1274 .ops = &clk_fixed_factor_ops, 1275 .parent_names = (const char *[]){ "vclk2_in_en" }, 1276 .num_parents = 1, 1277 .flags = CLK_SET_RATE_PARENT, 1278 } 1279 }; 1280 1281 static struct clk_regmap meson8b_vclk2_div4_div_gate = { 1282 .data = &(struct clk_regmap_gate_data){ 1283 .offset = HHI_VIID_CLK_DIV, 1284 .bit_idx = 2, 1285 }, 1286 .hw.init = &(struct clk_init_data){ 1287 .name = "vclk2_div4_en", 1288 .ops = &clk_regmap_gate_ro_ops, 1289 .parent_names = (const char *[]){ "vclk2_div4" }, 1290 .num_parents = 1, 1291 .flags = CLK_SET_RATE_PARENT, 1292 }, 1293 }; 1294 1295 static struct clk_fixed_factor meson8b_vclk2_div6_div = { 1296 .mult = 1, 1297 .div = 6, 1298 .hw.init = &(struct clk_init_data){ 1299 .name = "vclk2_div6", 1300 .ops = &clk_fixed_factor_ops, 1301 .parent_names = (const char *[]){ "vclk2_in_en" }, 1302 .num_parents = 1, 1303 .flags = CLK_SET_RATE_PARENT, 1304 } 1305 }; 1306 1307 static struct clk_regmap meson8b_vclk2_div6_div_gate = { 1308 .data = &(struct clk_regmap_gate_data){ 1309 .offset = HHI_VIID_CLK_DIV, 1310 .bit_idx = 3, 1311 }, 1312 .hw.init = &(struct clk_init_data){ 1313 .name = "vclk2_div6_en", 1314 .ops = &clk_regmap_gate_ro_ops, 1315 .parent_names = (const char *[]){ "vclk2_div6" }, 1316 .num_parents = 1, 1317 .flags = CLK_SET_RATE_PARENT, 1318 }, 1319 }; 1320 1321 static struct clk_fixed_factor meson8b_vclk2_div12_div = { 1322 .mult = 1, 1323 .div = 12, 1324 .hw.init = &(struct clk_init_data){ 1325 .name = "vclk2_div12", 1326 .ops = &clk_fixed_factor_ops, 1327 .parent_names = (const char *[]){ "vclk2_in_en" }, 1328 .num_parents = 1, 1329 .flags = CLK_SET_RATE_PARENT, 1330 } 1331 }; 1332 1333 static struct clk_regmap meson8b_vclk2_div12_div_gate = { 1334 .data = &(struct clk_regmap_gate_data){ 1335 .offset = HHI_VIID_CLK_DIV, 1336 .bit_idx = 4, 1337 }, 1338 .hw.init = &(struct clk_init_data){ 1339 .name = "vclk2_div12_en", 1340 .ops = &clk_regmap_gate_ro_ops, 1341 .parent_names = (const char *[]){ "vclk2_div12" }, 1342 .num_parents = 1, 1343 .flags = CLK_SET_RATE_PARENT, 1344 }, 1345 }; 1346 1347 static const char * const meson8b_vclk_enc_mux_parents[] = { 1348 "vclk_div1_en", "vclk_div2_en", "vclk_div4_en", "vclk_div6_en", 1349 "vclk_div12_en", 1350 }; 1351 1352 static struct clk_regmap meson8b_cts_enct_sel = { 1353 .data = &(struct clk_regmap_mux_data){ 1354 .offset = HHI_VID_CLK_DIV, 1355 .mask = 0xf, 1356 .shift = 20, 1357 }, 1358 .hw.init = &(struct clk_init_data){ 1359 .name = "cts_enct_sel", 1360 .ops = &clk_regmap_mux_ro_ops, 1361 .parent_names = meson8b_vclk_enc_mux_parents, 1362 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents), 1363 .flags = CLK_SET_RATE_PARENT, 1364 }, 1365 }; 1366 1367 static struct clk_regmap meson8b_cts_enct = { 1368 .data = &(struct clk_regmap_gate_data){ 1369 .offset = HHI_VID_CLK_CNTL2, 1370 .bit_idx = 1, 1371 }, 1372 .hw.init = &(struct clk_init_data){ 1373 .name = "cts_enct", 1374 .ops = &clk_regmap_gate_ro_ops, 1375 .parent_names = (const char *[]){ "cts_enct_sel" }, 1376 .num_parents = 1, 1377 .flags = CLK_SET_RATE_PARENT, 1378 }, 1379 }; 1380 1381 static struct clk_regmap meson8b_cts_encp_sel = { 1382 .data = &(struct clk_regmap_mux_data){ 1383 .offset = HHI_VID_CLK_DIV, 1384 .mask = 0xf, 1385 .shift = 24, 1386 }, 1387 .hw.init = &(struct clk_init_data){ 1388 .name = "cts_encp_sel", 1389 .ops = &clk_regmap_mux_ro_ops, 1390 .parent_names = meson8b_vclk_enc_mux_parents, 1391 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents), 1392 .flags = CLK_SET_RATE_PARENT, 1393 }, 1394 }; 1395 1396 static struct clk_regmap meson8b_cts_encp = { 1397 .data = &(struct clk_regmap_gate_data){ 1398 .offset = HHI_VID_CLK_CNTL2, 1399 .bit_idx = 2, 1400 }, 1401 .hw.init = &(struct clk_init_data){ 1402 .name = "cts_encp", 1403 .ops = &clk_regmap_gate_ro_ops, 1404 .parent_names = (const char *[]){ "cts_encp_sel" }, 1405 .num_parents = 1, 1406 .flags = CLK_SET_RATE_PARENT, 1407 }, 1408 }; 1409 1410 static struct clk_regmap meson8b_cts_enci_sel = { 1411 .data = &(struct clk_regmap_mux_data){ 1412 .offset = HHI_VID_CLK_DIV, 1413 .mask = 0xf, 1414 .shift = 28, 1415 }, 1416 .hw.init = &(struct clk_init_data){ 1417 .name = "cts_enci_sel", 1418 .ops = &clk_regmap_mux_ro_ops, 1419 .parent_names = meson8b_vclk_enc_mux_parents, 1420 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents), 1421 .flags = CLK_SET_RATE_PARENT, 1422 }, 1423 }; 1424 1425 static struct clk_regmap meson8b_cts_enci = { 1426 .data = &(struct clk_regmap_gate_data){ 1427 .offset = HHI_VID_CLK_CNTL2, 1428 .bit_idx = 0, 1429 }, 1430 .hw.init = &(struct clk_init_data){ 1431 .name = "cts_enci", 1432 .ops = &clk_regmap_gate_ro_ops, 1433 .parent_names = (const char *[]){ "cts_enci_sel" }, 1434 .num_parents = 1, 1435 .flags = CLK_SET_RATE_PARENT, 1436 }, 1437 }; 1438 1439 static struct clk_regmap meson8b_hdmi_tx_pixel_sel = { 1440 .data = &(struct clk_regmap_mux_data){ 1441 .offset = HHI_HDMI_CLK_CNTL, 1442 .mask = 0xf, 1443 .shift = 16, 1444 }, 1445 .hw.init = &(struct clk_init_data){ 1446 .name = "hdmi_tx_pixel_sel", 1447 .ops = &clk_regmap_mux_ro_ops, 1448 .parent_names = meson8b_vclk_enc_mux_parents, 1449 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents), 1450 .flags = CLK_SET_RATE_PARENT, 1451 }, 1452 }; 1453 1454 static struct clk_regmap meson8b_hdmi_tx_pixel = { 1455 .data = &(struct clk_regmap_gate_data){ 1456 .offset = HHI_VID_CLK_CNTL2, 1457 .bit_idx = 5, 1458 }, 1459 .hw.init = &(struct clk_init_data){ 1460 .name = "hdmi_tx_pixel", 1461 .ops = &clk_regmap_gate_ro_ops, 1462 .parent_names = (const char *[]){ "hdmi_tx_pixel_sel" }, 1463 .num_parents = 1, 1464 .flags = CLK_SET_RATE_PARENT, 1465 }, 1466 }; 1467 1468 static const char * const meson8b_vclk2_enc_mux_parents[] = { 1469 "vclk2_div1_en", "vclk2_div2_en", "vclk2_div4_en", "vclk2_div6_en", 1470 "vclk2_div12_en", 1471 }; 1472 1473 static struct clk_regmap meson8b_cts_encl_sel = { 1474 .data = &(struct clk_regmap_mux_data){ 1475 .offset = HHI_VIID_CLK_DIV, 1476 .mask = 0xf, 1477 .shift = 12, 1478 }, 1479 .hw.init = &(struct clk_init_data){ 1480 .name = "cts_encl_sel", 1481 .ops = &clk_regmap_mux_ro_ops, 1482 .parent_names = meson8b_vclk2_enc_mux_parents, 1483 .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parents), 1484 .flags = CLK_SET_RATE_PARENT, 1485 }, 1486 }; 1487 1488 static struct clk_regmap meson8b_cts_encl = { 1489 .data = &(struct clk_regmap_gate_data){ 1490 .offset = HHI_VID_CLK_CNTL2, 1491 .bit_idx = 3, 1492 }, 1493 .hw.init = &(struct clk_init_data){ 1494 .name = "cts_encl", 1495 .ops = &clk_regmap_gate_ro_ops, 1496 .parent_names = (const char *[]){ "cts_encl_sel" }, 1497 .num_parents = 1, 1498 .flags = CLK_SET_RATE_PARENT, 1499 }, 1500 }; 1501 1502 static struct clk_regmap meson8b_cts_vdac0_sel = { 1503 .data = &(struct clk_regmap_mux_data){ 1504 .offset = HHI_VIID_CLK_DIV, 1505 .mask = 0xf, 1506 .shift = 28, 1507 }, 1508 .hw.init = &(struct clk_init_data){ 1509 .name = "cts_vdac0_sel", 1510 .ops = &clk_regmap_mux_ro_ops, 1511 .parent_names = meson8b_vclk2_enc_mux_parents, 1512 .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parents), 1513 .flags = CLK_SET_RATE_PARENT, 1514 }, 1515 }; 1516 1517 static struct clk_regmap meson8b_cts_vdac0 = { 1518 .data = &(struct clk_regmap_gate_data){ 1519 .offset = HHI_VID_CLK_CNTL2, 1520 .bit_idx = 4, 1521 }, 1522 .hw.init = &(struct clk_init_data){ 1523 .name = "cts_vdac0", 1524 .ops = &clk_regmap_gate_ro_ops, 1525 .parent_names = (const char *[]){ "cts_vdac0_sel" }, 1526 .num_parents = 1, 1527 .flags = CLK_SET_RATE_PARENT, 1528 }, 1529 }; 1530 1531 static struct clk_regmap meson8b_hdmi_sys_sel = { 1532 .data = &(struct clk_regmap_mux_data){ 1533 .offset = HHI_HDMI_CLK_CNTL, 1534 .mask = 0x3, 1535 .shift = 9, 1536 .flags = CLK_MUX_ROUND_CLOSEST, 1537 }, 1538 .hw.init = &(struct clk_init_data){ 1539 .name = "hdmi_sys_sel", 1540 .ops = &clk_regmap_mux_ro_ops, 1541 /* FIXME: all other parents are unknown */ 1542 .parent_names = (const char *[]){ "xtal" }, 1543 .num_parents = 1, 1544 .flags = CLK_SET_RATE_NO_REPARENT, 1545 }, 1546 }; 1547 1548 static struct clk_regmap meson8b_hdmi_sys_div = { 1549 .data = &(struct clk_regmap_div_data){ 1550 .offset = HHI_HDMI_CLK_CNTL, 1551 .shift = 0, 1552 .width = 7, 1553 }, 1554 .hw.init = &(struct clk_init_data){ 1555 .name = "hdmi_sys_div", 1556 .ops = &clk_regmap_divider_ro_ops, 1557 .parent_names = (const char *[]){ "hdmi_sys_sel" }, 1558 .num_parents = 1, 1559 .flags = CLK_SET_RATE_PARENT, 1560 }, 1561 }; 1562 1563 static struct clk_regmap meson8b_hdmi_sys = { 1564 .data = &(struct clk_regmap_gate_data){ 1565 .offset = HHI_HDMI_CLK_CNTL, 1566 .bit_idx = 8, 1567 }, 1568 .hw.init = &(struct clk_init_data) { 1569 .name = "hdmi_sys", 1570 .ops = &clk_regmap_gate_ro_ops, 1571 .parent_names = (const char *[]){ "hdmi_sys_div" }, 1572 .num_parents = 1, 1573 .flags = CLK_SET_RATE_PARENT, 1574 }, 1575 }; 1576 1577 /* 1578 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) 1579 * muxed by a glitch-free switch on Meson8b and Meson8m2. Meson8 only 1580 * has mali_0 and no glitch-free mux. 1581 */ 1582 static const char * const meson8b_mali_0_1_parent_names[] = { 1583 "xtal", "mpll2", "mpll1", "fclk_div7", "fclk_div4", "fclk_div3", 1584 "fclk_div5" 1585 }; 1586 1587 static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 }; 1588 1589 static struct clk_regmap meson8b_mali_0_sel = { 1590 .data = &(struct clk_regmap_mux_data){ 1591 .offset = HHI_MALI_CLK_CNTL, 1592 .mask = 0x7, 1593 .shift = 9, 1594 .table = meson8b_mali_0_1_mux_table, 1595 }, 1596 .hw.init = &(struct clk_init_data){ 1597 .name = "mali_0_sel", 1598 .ops = &clk_regmap_mux_ops, 1599 .parent_names = meson8b_mali_0_1_parent_names, 1600 .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_names), 1601 /* 1602 * Don't propagate rate changes up because the only changeable 1603 * parents are mpll1 and mpll2 but we need those for audio and 1604 * RGMII (Ethernet). We don't want to change the audio or 1605 * Ethernet clocks when setting the GPU frequency. 1606 */ 1607 .flags = 0, 1608 }, 1609 }; 1610 1611 static struct clk_regmap meson8b_mali_0_div = { 1612 .data = &(struct clk_regmap_div_data){ 1613 .offset = HHI_MALI_CLK_CNTL, 1614 .shift = 0, 1615 .width = 7, 1616 }, 1617 .hw.init = &(struct clk_init_data){ 1618 .name = "mali_0_div", 1619 .ops = &clk_regmap_divider_ops, 1620 .parent_names = (const char *[]){ "mali_0_sel" }, 1621 .num_parents = 1, 1622 .flags = CLK_SET_RATE_PARENT, 1623 }, 1624 }; 1625 1626 static struct clk_regmap meson8b_mali_0 = { 1627 .data = &(struct clk_regmap_gate_data){ 1628 .offset = HHI_MALI_CLK_CNTL, 1629 .bit_idx = 8, 1630 }, 1631 .hw.init = &(struct clk_init_data){ 1632 .name = "mali_0", 1633 .ops = &clk_regmap_gate_ops, 1634 .parent_names = (const char *[]){ "mali_0_div" }, 1635 .num_parents = 1, 1636 .flags = CLK_SET_RATE_PARENT, 1637 }, 1638 }; 1639 1640 static struct clk_regmap meson8b_mali_1_sel = { 1641 .data = &(struct clk_regmap_mux_data){ 1642 .offset = HHI_MALI_CLK_CNTL, 1643 .mask = 0x7, 1644 .shift = 25, 1645 .table = meson8b_mali_0_1_mux_table, 1646 }, 1647 .hw.init = &(struct clk_init_data){ 1648 .name = "mali_1_sel", 1649 .ops = &clk_regmap_mux_ops, 1650 .parent_names = meson8b_mali_0_1_parent_names, 1651 .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_names), 1652 /* 1653 * Don't propagate rate changes up because the only changeable 1654 * parents are mpll1 and mpll2 but we need those for audio and 1655 * RGMII (Ethernet). We don't want to change the audio or 1656 * Ethernet clocks when setting the GPU frequency. 1657 */ 1658 .flags = 0, 1659 }, 1660 }; 1661 1662 static struct clk_regmap meson8b_mali_1_div = { 1663 .data = &(struct clk_regmap_div_data){ 1664 .offset = HHI_MALI_CLK_CNTL, 1665 .shift = 16, 1666 .width = 7, 1667 }, 1668 .hw.init = &(struct clk_init_data){ 1669 .name = "mali_1_div", 1670 .ops = &clk_regmap_divider_ops, 1671 .parent_names = (const char *[]){ "mali_1_sel" }, 1672 .num_parents = 1, 1673 .flags = CLK_SET_RATE_PARENT, 1674 }, 1675 }; 1676 1677 static struct clk_regmap meson8b_mali_1 = { 1678 .data = &(struct clk_regmap_gate_data){ 1679 .offset = HHI_MALI_CLK_CNTL, 1680 .bit_idx = 24, 1681 }, 1682 .hw.init = &(struct clk_init_data){ 1683 .name = "mali_1", 1684 .ops = &clk_regmap_gate_ops, 1685 .parent_names = (const char *[]){ "mali_1_div" }, 1686 .num_parents = 1, 1687 .flags = CLK_SET_RATE_PARENT, 1688 }, 1689 }; 1690 1691 static struct clk_regmap meson8b_mali = { 1692 .data = &(struct clk_regmap_mux_data){ 1693 .offset = HHI_MALI_CLK_CNTL, 1694 .mask = 1, 1695 .shift = 31, 1696 }, 1697 .hw.init = &(struct clk_init_data){ 1698 .name = "mali", 1699 .ops = &clk_regmap_mux_ops, 1700 .parent_names = (const char *[]){ "mali_0", "mali_1" }, 1701 .num_parents = 2, 1702 .flags = CLK_SET_RATE_PARENT, 1703 }, 1704 }; 1705 1706 /* Everything Else (EE) domain gates */ 1707 1708 static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0); 1709 static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1); 1710 static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5); 1711 static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6); 1712 static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7); 1713 static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8); 1714 static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9); 1715 static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10); 1716 static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11); 1717 static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12); 1718 static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13); 1719 static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14); 1720 static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15); 1721 static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16); 1722 static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17); 1723 static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18); 1724 static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19); 1725 static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23); 1726 static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30); 1727 1728 static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2); 1729 static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3); 1730 static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4); 1731 static MESON_GATE(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6); 1732 static MESON_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7); 1733 static MESON_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8); 1734 static MESON_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9); 1735 static MESON_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10); 1736 static MESON_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11); 1737 static MESON_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12); 1738 static MESON_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13); 1739 static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14); 1740 static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15); 1741 static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16); 1742 static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20); 1743 static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21); 1744 static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22); 1745 static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23); 1746 static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24); 1747 static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25); 1748 static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26); 1749 static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28); 1750 static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29); 1751 static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30); 1752 static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31); 1753 1754 static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1); 1755 static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); 1756 static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3); 1757 static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4); 1758 static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); 1759 static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); 1760 static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11); 1761 static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12); 1762 static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15); 1763 static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22); 1764 static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25); 1765 static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); 1766 static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29); 1767 1768 static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1); 1769 static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2); 1770 static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3); 1771 static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4); 1772 static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8); 1773 static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9); 1774 static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10); 1775 static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14); 1776 static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16); 1777 static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20); 1778 static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21); 1779 static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22); 1780 static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24); 1781 static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25); 1782 static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26); 1783 static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31); 1784 1785 /* Always On (AO) domain gates */ 1786 1787 static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0); 1788 static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1); 1789 static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2); 1790 static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3); 1791 1792 static struct clk_hw_onecell_data meson8_hw_onecell_data = { 1793 .hws = { 1794 [CLKID_XTAL] = &meson8b_xtal.hw, 1795 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw, 1796 [CLKID_PLL_VID] = &meson8b_vid_pll.hw, 1797 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw, 1798 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw, 1799 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw, 1800 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw, 1801 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw, 1802 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw, 1803 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw, 1804 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw, 1805 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw, 1806 [CLKID_CLK81] = &meson8b_clk81.hw, 1807 [CLKID_DDR] = &meson8b_ddr.hw, 1808 [CLKID_DOS] = &meson8b_dos.hw, 1809 [CLKID_ISA] = &meson8b_isa.hw, 1810 [CLKID_PL301] = &meson8b_pl301.hw, 1811 [CLKID_PERIPHS] = &meson8b_periphs.hw, 1812 [CLKID_SPICC] = &meson8b_spicc.hw, 1813 [CLKID_I2C] = &meson8b_i2c.hw, 1814 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw, 1815 [CLKID_SMART_CARD] = &meson8b_smart_card.hw, 1816 [CLKID_RNG0] = &meson8b_rng0.hw, 1817 [CLKID_UART0] = &meson8b_uart0.hw, 1818 [CLKID_SDHC] = &meson8b_sdhc.hw, 1819 [CLKID_STREAM] = &meson8b_stream.hw, 1820 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw, 1821 [CLKID_SDIO] = &meson8b_sdio.hw, 1822 [CLKID_ABUF] = &meson8b_abuf.hw, 1823 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw, 1824 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw, 1825 [CLKID_SPI] = &meson8b_spi.hw, 1826 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw, 1827 [CLKID_ETH] = &meson8b_eth.hw, 1828 [CLKID_DEMUX] = &meson8b_demux.hw, 1829 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw, 1830 [CLKID_IEC958] = &meson8b_iec958.hw, 1831 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw, 1832 [CLKID_AMCLK] = &meson8b_amclk.hw, 1833 [CLKID_AIFIFO2] = &meson8b_aififo2.hw, 1834 [CLKID_MIXER] = &meson8b_mixer.hw, 1835 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw, 1836 [CLKID_ADC] = &meson8b_adc.hw, 1837 [CLKID_BLKMV] = &meson8b_blkmv.hw, 1838 [CLKID_AIU] = &meson8b_aiu.hw, 1839 [CLKID_UART1] = &meson8b_uart1.hw, 1840 [CLKID_G2D] = &meson8b_g2d.hw, 1841 [CLKID_USB0] = &meson8b_usb0.hw, 1842 [CLKID_USB1] = &meson8b_usb1.hw, 1843 [CLKID_RESET] = &meson8b_reset.hw, 1844 [CLKID_NAND] = &meson8b_nand.hw, 1845 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw, 1846 [CLKID_USB] = &meson8b_usb.hw, 1847 [CLKID_VDIN1] = &meson8b_vdin1.hw, 1848 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw, 1849 [CLKID_EFUSE] = &meson8b_efuse.hw, 1850 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw, 1851 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw, 1852 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw, 1853 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw, 1854 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw, 1855 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw, 1856 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw, 1857 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw, 1858 [CLKID_DVIN] = &meson8b_dvin.hw, 1859 [CLKID_UART2] = &meson8b_uart2.hw, 1860 [CLKID_SANA] = &meson8b_sana.hw, 1861 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw, 1862 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw, 1863 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw, 1864 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw, 1865 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw, 1866 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw, 1867 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw, 1868 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw, 1869 [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw, 1870 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw, 1871 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw, 1872 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw, 1873 [CLKID_ENC480P] = &meson8b_enc480p.hw, 1874 [CLKID_RNG1] = &meson8b_rng1.hw, 1875 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw, 1876 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw, 1877 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw, 1878 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw, 1879 [CLKID_EDP] = &meson8b_edp.hw, 1880 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw, 1881 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw, 1882 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw, 1883 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw, 1884 [CLKID_MPLL0] = &meson8b_mpll0.hw, 1885 [CLKID_MPLL1] = &meson8b_mpll1.hw, 1886 [CLKID_MPLL2] = &meson8b_mpll2.hw, 1887 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw, 1888 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw, 1889 [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw, 1890 [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw, 1891 [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw, 1892 [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw, 1893 [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw, 1894 [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw, 1895 [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw, 1896 [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw, 1897 [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw, 1898 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw, 1899 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw, 1900 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw, 1901 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw, 1902 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw, 1903 [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw, 1904 [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw, 1905 [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw, 1906 [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw, 1907 [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw, 1908 [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw, 1909 [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw, 1910 [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw, 1911 [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw, 1912 [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw, 1913 [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw, 1914 [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw, 1915 [CLKID_APB] = &meson8b_apb_clk_gate.hw, 1916 [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw, 1917 [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw, 1918 [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw, 1919 [CLKID_AXI] = &meson8b_axi_clk_gate.hw, 1920 [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw, 1921 [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw, 1922 [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw, 1923 [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw, 1924 [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw, 1925 [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw, 1926 [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw, 1927 [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw, 1928 [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw, 1929 [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw, 1930 [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw, 1931 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw, 1932 [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw, 1933 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw, 1934 [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw, 1935 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw, 1936 [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw, 1937 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw, 1938 [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw, 1939 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw, 1940 [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw, 1941 [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw, 1942 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw, 1943 [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw, 1944 [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw, 1945 [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw, 1946 [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw, 1947 [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw, 1948 [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw, 1949 [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw, 1950 [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw, 1951 [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw, 1952 [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw, 1953 [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw, 1954 [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw, 1955 [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw, 1956 [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw, 1957 [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw, 1958 [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw, 1959 [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw, 1960 [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw, 1961 [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw, 1962 [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw, 1963 [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw, 1964 [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw, 1965 [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw, 1966 [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw, 1967 [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw, 1968 [CLKID_MALI] = &meson8b_mali_0.hw, 1969 [CLK_NR_CLKS] = NULL, 1970 }, 1971 .num = CLK_NR_CLKS, 1972 }; 1973 1974 static struct clk_hw_onecell_data meson8b_hw_onecell_data = { 1975 .hws = { 1976 [CLKID_XTAL] = &meson8b_xtal.hw, 1977 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw, 1978 [CLKID_PLL_VID] = &meson8b_vid_pll.hw, 1979 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw, 1980 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw, 1981 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw, 1982 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw, 1983 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw, 1984 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw, 1985 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw, 1986 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw, 1987 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw, 1988 [CLKID_CLK81] = &meson8b_clk81.hw, 1989 [CLKID_DDR] = &meson8b_ddr.hw, 1990 [CLKID_DOS] = &meson8b_dos.hw, 1991 [CLKID_ISA] = &meson8b_isa.hw, 1992 [CLKID_PL301] = &meson8b_pl301.hw, 1993 [CLKID_PERIPHS] = &meson8b_periphs.hw, 1994 [CLKID_SPICC] = &meson8b_spicc.hw, 1995 [CLKID_I2C] = &meson8b_i2c.hw, 1996 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw, 1997 [CLKID_SMART_CARD] = &meson8b_smart_card.hw, 1998 [CLKID_RNG0] = &meson8b_rng0.hw, 1999 [CLKID_UART0] = &meson8b_uart0.hw, 2000 [CLKID_SDHC] = &meson8b_sdhc.hw, 2001 [CLKID_STREAM] = &meson8b_stream.hw, 2002 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw, 2003 [CLKID_SDIO] = &meson8b_sdio.hw, 2004 [CLKID_ABUF] = &meson8b_abuf.hw, 2005 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw, 2006 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw, 2007 [CLKID_SPI] = &meson8b_spi.hw, 2008 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw, 2009 [CLKID_ETH] = &meson8b_eth.hw, 2010 [CLKID_DEMUX] = &meson8b_demux.hw, 2011 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw, 2012 [CLKID_IEC958] = &meson8b_iec958.hw, 2013 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw, 2014 [CLKID_AMCLK] = &meson8b_amclk.hw, 2015 [CLKID_AIFIFO2] = &meson8b_aififo2.hw, 2016 [CLKID_MIXER] = &meson8b_mixer.hw, 2017 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw, 2018 [CLKID_ADC] = &meson8b_adc.hw, 2019 [CLKID_BLKMV] = &meson8b_blkmv.hw, 2020 [CLKID_AIU] = &meson8b_aiu.hw, 2021 [CLKID_UART1] = &meson8b_uart1.hw, 2022 [CLKID_G2D] = &meson8b_g2d.hw, 2023 [CLKID_USB0] = &meson8b_usb0.hw, 2024 [CLKID_USB1] = &meson8b_usb1.hw, 2025 [CLKID_RESET] = &meson8b_reset.hw, 2026 [CLKID_NAND] = &meson8b_nand.hw, 2027 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw, 2028 [CLKID_USB] = &meson8b_usb.hw, 2029 [CLKID_VDIN1] = &meson8b_vdin1.hw, 2030 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw, 2031 [CLKID_EFUSE] = &meson8b_efuse.hw, 2032 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw, 2033 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw, 2034 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw, 2035 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw, 2036 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw, 2037 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw, 2038 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw, 2039 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw, 2040 [CLKID_DVIN] = &meson8b_dvin.hw, 2041 [CLKID_UART2] = &meson8b_uart2.hw, 2042 [CLKID_SANA] = &meson8b_sana.hw, 2043 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw, 2044 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw, 2045 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw, 2046 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw, 2047 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw, 2048 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw, 2049 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw, 2050 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw, 2051 [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw, 2052 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw, 2053 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw, 2054 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw, 2055 [CLKID_ENC480P] = &meson8b_enc480p.hw, 2056 [CLKID_RNG1] = &meson8b_rng1.hw, 2057 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw, 2058 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw, 2059 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw, 2060 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw, 2061 [CLKID_EDP] = &meson8b_edp.hw, 2062 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw, 2063 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw, 2064 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw, 2065 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw, 2066 [CLKID_MPLL0] = &meson8b_mpll0.hw, 2067 [CLKID_MPLL1] = &meson8b_mpll1.hw, 2068 [CLKID_MPLL2] = &meson8b_mpll2.hw, 2069 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw, 2070 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw, 2071 [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw, 2072 [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw, 2073 [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw, 2074 [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw, 2075 [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw, 2076 [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw, 2077 [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw, 2078 [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw, 2079 [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw, 2080 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw, 2081 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw, 2082 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw, 2083 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw, 2084 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw, 2085 [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw, 2086 [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw, 2087 [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw, 2088 [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw, 2089 [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw, 2090 [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw, 2091 [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw, 2092 [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw, 2093 [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw, 2094 [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw, 2095 [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw, 2096 [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw, 2097 [CLKID_APB] = &meson8b_apb_clk_gate.hw, 2098 [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw, 2099 [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw, 2100 [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw, 2101 [CLKID_AXI] = &meson8b_axi_clk_gate.hw, 2102 [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw, 2103 [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw, 2104 [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw, 2105 [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw, 2106 [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw, 2107 [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw, 2108 [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw, 2109 [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw, 2110 [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw, 2111 [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw, 2112 [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw, 2113 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw, 2114 [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw, 2115 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw, 2116 [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw, 2117 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw, 2118 [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw, 2119 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw, 2120 [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw, 2121 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw, 2122 [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw, 2123 [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw, 2124 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw, 2125 [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw, 2126 [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw, 2127 [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw, 2128 [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw, 2129 [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw, 2130 [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw, 2131 [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw, 2132 [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw, 2133 [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw, 2134 [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw, 2135 [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw, 2136 [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw, 2137 [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw, 2138 [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw, 2139 [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw, 2140 [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw, 2141 [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw, 2142 [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw, 2143 [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw, 2144 [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw, 2145 [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw, 2146 [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw, 2147 [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw, 2148 [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw, 2149 [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw, 2150 [CLKID_MALI_0] = &meson8b_mali_0.hw, 2151 [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw, 2152 [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw, 2153 [CLKID_MALI_1] = &meson8b_mali_1.hw, 2154 [CLKID_MALI] = &meson8b_mali.hw, 2155 [CLK_NR_CLKS] = NULL, 2156 }, 2157 .num = CLK_NR_CLKS, 2158 }; 2159 2160 static struct clk_regmap *const meson8b_clk_regmaps[] = { 2161 &meson8b_clk81, 2162 &meson8b_ddr, 2163 &meson8b_dos, 2164 &meson8b_isa, 2165 &meson8b_pl301, 2166 &meson8b_periphs, 2167 &meson8b_spicc, 2168 &meson8b_i2c, 2169 &meson8b_sar_adc, 2170 &meson8b_smart_card, 2171 &meson8b_rng0, 2172 &meson8b_uart0, 2173 &meson8b_sdhc, 2174 &meson8b_stream, 2175 &meson8b_async_fifo, 2176 &meson8b_sdio, 2177 &meson8b_abuf, 2178 &meson8b_hiu_iface, 2179 &meson8b_assist_misc, 2180 &meson8b_spi, 2181 &meson8b_i2s_spdif, 2182 &meson8b_eth, 2183 &meson8b_demux, 2184 &meson8b_aiu_glue, 2185 &meson8b_iec958, 2186 &meson8b_i2s_out, 2187 &meson8b_amclk, 2188 &meson8b_aififo2, 2189 &meson8b_mixer, 2190 &meson8b_mixer_iface, 2191 &meson8b_adc, 2192 &meson8b_blkmv, 2193 &meson8b_aiu, 2194 &meson8b_uart1, 2195 &meson8b_g2d, 2196 &meson8b_usb0, 2197 &meson8b_usb1, 2198 &meson8b_reset, 2199 &meson8b_nand, 2200 &meson8b_dos_parser, 2201 &meson8b_usb, 2202 &meson8b_vdin1, 2203 &meson8b_ahb_arb0, 2204 &meson8b_efuse, 2205 &meson8b_boot_rom, 2206 &meson8b_ahb_data_bus, 2207 &meson8b_ahb_ctrl_bus, 2208 &meson8b_hdmi_intr_sync, 2209 &meson8b_hdmi_pclk, 2210 &meson8b_usb1_ddr_bridge, 2211 &meson8b_usb0_ddr_bridge, 2212 &meson8b_mmc_pclk, 2213 &meson8b_dvin, 2214 &meson8b_uart2, 2215 &meson8b_sana, 2216 &meson8b_vpu_intr, 2217 &meson8b_sec_ahb_ahb3_bridge, 2218 &meson8b_clk81_a9, 2219 &meson8b_vclk2_venci0, 2220 &meson8b_vclk2_venci1, 2221 &meson8b_vclk2_vencp0, 2222 &meson8b_vclk2_vencp1, 2223 &meson8b_gclk_venci_int, 2224 &meson8b_gclk_vencp_int, 2225 &meson8b_dac_clk, 2226 &meson8b_aoclk_gate, 2227 &meson8b_iec958_gate, 2228 &meson8b_enc480p, 2229 &meson8b_rng1, 2230 &meson8b_gclk_vencl_int, 2231 &meson8b_vclk2_venclmcc, 2232 &meson8b_vclk2_vencl, 2233 &meson8b_vclk2_other, 2234 &meson8b_edp, 2235 &meson8b_ao_media_cpu, 2236 &meson8b_ao_ahb_sram, 2237 &meson8b_ao_ahb_bus, 2238 &meson8b_ao_iface, 2239 &meson8b_mpeg_clk_div, 2240 &meson8b_mpeg_clk_sel, 2241 &meson8b_mpll0, 2242 &meson8b_mpll1, 2243 &meson8b_mpll2, 2244 &meson8b_mpll0_div, 2245 &meson8b_mpll1_div, 2246 &meson8b_mpll2_div, 2247 &meson8b_fixed_pll, 2248 &meson8b_sys_pll, 2249 &meson8b_cpu_in_sel, 2250 &meson8b_cpu_scale_div, 2251 &meson8b_cpu_scale_out_sel, 2252 &meson8b_cpu_clk, 2253 &meson8b_mpll_prediv, 2254 &meson8b_fclk_div2, 2255 &meson8b_fclk_div3, 2256 &meson8b_fclk_div4, 2257 &meson8b_fclk_div5, 2258 &meson8b_fclk_div7, 2259 &meson8b_nand_clk_sel, 2260 &meson8b_nand_clk_div, 2261 &meson8b_nand_clk_gate, 2262 &meson8b_fixed_pll_dco, 2263 &meson8b_hdmi_pll_dco, 2264 &meson8b_sys_pll_dco, 2265 &meson8b_apb_clk_sel, 2266 &meson8b_apb_clk_gate, 2267 &meson8b_periph_clk_sel, 2268 &meson8b_periph_clk_gate, 2269 &meson8b_axi_clk_sel, 2270 &meson8b_axi_clk_gate, 2271 &meson8b_l2_dram_clk_sel, 2272 &meson8b_l2_dram_clk_gate, 2273 &meson8b_hdmi_pll_lvds_out, 2274 &meson8b_hdmi_pll_hdmi_out, 2275 &meson8b_vid_pll_in_sel, 2276 &meson8b_vid_pll_in_en, 2277 &meson8b_vid_pll_pre_div, 2278 &meson8b_vid_pll_post_div, 2279 &meson8b_vid_pll, 2280 &meson8b_vid_pll_final_div, 2281 &meson8b_vclk_in_sel, 2282 &meson8b_vclk_in_en, 2283 &meson8b_vclk_div1_gate, 2284 &meson8b_vclk_div2_div_gate, 2285 &meson8b_vclk_div4_div_gate, 2286 &meson8b_vclk_div6_div_gate, 2287 &meson8b_vclk_div12_div_gate, 2288 &meson8b_vclk2_in_sel, 2289 &meson8b_vclk2_clk_in_en, 2290 &meson8b_vclk2_div1_gate, 2291 &meson8b_vclk2_div2_div_gate, 2292 &meson8b_vclk2_div4_div_gate, 2293 &meson8b_vclk2_div6_div_gate, 2294 &meson8b_vclk2_div12_div_gate, 2295 &meson8b_cts_enct_sel, 2296 &meson8b_cts_enct, 2297 &meson8b_cts_encp_sel, 2298 &meson8b_cts_encp, 2299 &meson8b_cts_enci_sel, 2300 &meson8b_cts_enci, 2301 &meson8b_hdmi_tx_pixel_sel, 2302 &meson8b_hdmi_tx_pixel, 2303 &meson8b_cts_encl_sel, 2304 &meson8b_cts_encl, 2305 &meson8b_cts_vdac0_sel, 2306 &meson8b_cts_vdac0, 2307 &meson8b_hdmi_sys_sel, 2308 &meson8b_hdmi_sys_div, 2309 &meson8b_hdmi_sys, 2310 &meson8b_mali_0_sel, 2311 &meson8b_mali_0_div, 2312 &meson8b_mali_0, 2313 &meson8b_mali_1_sel, 2314 &meson8b_mali_1_div, 2315 &meson8b_mali_1, 2316 &meson8b_mali, 2317 }; 2318 2319 static const struct meson8b_clk_reset_line { 2320 u32 reg; 2321 u8 bit_idx; 2322 } meson8b_clk_reset_bits[] = { 2323 [CLKC_RESET_L2_CACHE_SOFT_RESET] = { 2324 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 30 2325 }, 2326 [CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET] = { 2327 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 29 2328 }, 2329 [CLKC_RESET_SCU_SOFT_RESET] = { 2330 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 28 2331 }, 2332 [CLKC_RESET_CPU3_SOFT_RESET] = { 2333 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 27 2334 }, 2335 [CLKC_RESET_CPU2_SOFT_RESET] = { 2336 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 26 2337 }, 2338 [CLKC_RESET_CPU1_SOFT_RESET] = { 2339 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 25 2340 }, 2341 [CLKC_RESET_CPU0_SOFT_RESET] = { 2342 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 24 2343 }, 2344 [CLKC_RESET_A5_GLOBAL_RESET] = { 2345 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 18 2346 }, 2347 [CLKC_RESET_A5_AXI_SOFT_RESET] = { 2348 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 17 2349 }, 2350 [CLKC_RESET_A5_ABP_SOFT_RESET] = { 2351 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 16 2352 }, 2353 [CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET] = { 2354 .reg = HHI_SYS_CPU_CLK_CNTL1, .bit_idx = 30 2355 }, 2356 [CLKC_RESET_VID_CLK_CNTL_SOFT_RESET] = { 2357 .reg = HHI_VID_CLK_CNTL, .bit_idx = 15 2358 }, 2359 [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST] = { 2360 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 7 2361 }, 2362 [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE] = { 2363 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 3 2364 }, 2365 [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST] = { 2366 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 1 2367 }, 2368 [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE] = { 2369 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 0 2370 }, 2371 }; 2372 2373 static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev, 2374 unsigned long id, bool assert) 2375 { 2376 struct meson8b_clk_reset *meson8b_clk_reset = 2377 container_of(rcdev, struct meson8b_clk_reset, reset); 2378 unsigned long flags; 2379 const struct meson8b_clk_reset_line *reset; 2380 2381 if (id >= ARRAY_SIZE(meson8b_clk_reset_bits)) 2382 return -EINVAL; 2383 2384 reset = &meson8b_clk_reset_bits[id]; 2385 2386 spin_lock_irqsave(&meson_clk_lock, flags); 2387 2388 if (assert) 2389 regmap_update_bits(meson8b_clk_reset->regmap, reset->reg, 2390 BIT(reset->bit_idx), BIT(reset->bit_idx)); 2391 else 2392 regmap_update_bits(meson8b_clk_reset->regmap, reset->reg, 2393 BIT(reset->bit_idx), 0); 2394 2395 spin_unlock_irqrestore(&meson_clk_lock, flags); 2396 2397 return 0; 2398 } 2399 2400 static int meson8b_clk_reset_assert(struct reset_controller_dev *rcdev, 2401 unsigned long id) 2402 { 2403 return meson8b_clk_reset_update(rcdev, id, true); 2404 } 2405 2406 static int meson8b_clk_reset_deassert(struct reset_controller_dev *rcdev, 2407 unsigned long id) 2408 { 2409 return meson8b_clk_reset_update(rcdev, id, false); 2410 } 2411 2412 static const struct reset_control_ops meson8b_clk_reset_ops = { 2413 .assert = meson8b_clk_reset_assert, 2414 .deassert = meson8b_clk_reset_deassert, 2415 }; 2416 2417 struct meson8b_nb_data { 2418 struct notifier_block nb; 2419 struct clk_hw_onecell_data *onecell_data; 2420 }; 2421 2422 static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb, 2423 unsigned long event, void *data) 2424 { 2425 struct meson8b_nb_data *nb_data = 2426 container_of(nb, struct meson8b_nb_data, nb); 2427 struct clk_hw **hws = nb_data->onecell_data->hws; 2428 struct clk_hw *cpu_clk_hw, *parent_clk_hw; 2429 struct clk *cpu_clk, *parent_clk; 2430 int ret; 2431 2432 switch (event) { 2433 case PRE_RATE_CHANGE: 2434 parent_clk_hw = hws[CLKID_XTAL]; 2435 break; 2436 2437 case POST_RATE_CHANGE: 2438 parent_clk_hw = hws[CLKID_CPU_SCALE_OUT_SEL]; 2439 break; 2440 2441 default: 2442 return NOTIFY_DONE; 2443 } 2444 2445 cpu_clk_hw = hws[CLKID_CPUCLK]; 2446 cpu_clk = __clk_lookup(clk_hw_get_name(cpu_clk_hw)); 2447 2448 parent_clk = __clk_lookup(clk_hw_get_name(parent_clk_hw)); 2449 2450 ret = clk_set_parent(cpu_clk, parent_clk); 2451 if (ret) 2452 return notifier_from_errno(ret); 2453 2454 udelay(100); 2455 2456 return NOTIFY_OK; 2457 } 2458 2459 static struct meson8b_nb_data meson8b_cpu_nb_data = { 2460 .nb.notifier_call = meson8b_cpu_clk_notifier_cb, 2461 }; 2462 2463 static const struct regmap_config clkc_regmap_config = { 2464 .reg_bits = 32, 2465 .val_bits = 32, 2466 .reg_stride = 4, 2467 }; 2468 2469 static void __init meson8b_clkc_init_common(struct device_node *np, 2470 struct clk_hw_onecell_data *clk_hw_onecell_data) 2471 { 2472 struct meson8b_clk_reset *rstc; 2473 const char *notifier_clk_name; 2474 struct clk *notifier_clk; 2475 void __iomem *clk_base; 2476 struct regmap *map; 2477 int i, ret; 2478 2479 map = syscon_node_to_regmap(of_get_parent(np)); 2480 if (IS_ERR(map)) { 2481 pr_info("failed to get HHI regmap - Trying obsolete regs\n"); 2482 2483 /* Generic clocks, PLLs and some of the reset-bits */ 2484 clk_base = of_iomap(np, 1); 2485 if (!clk_base) { 2486 pr_err("%s: Unable to map clk base\n", __func__); 2487 return; 2488 } 2489 2490 map = regmap_init_mmio(NULL, clk_base, &clkc_regmap_config); 2491 if (IS_ERR(map)) 2492 return; 2493 } 2494 2495 rstc = kzalloc(sizeof(*rstc), GFP_KERNEL); 2496 if (!rstc) 2497 return; 2498 2499 /* Reset Controller */ 2500 rstc->regmap = map; 2501 rstc->reset.ops = &meson8b_clk_reset_ops; 2502 rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits); 2503 rstc->reset.of_node = np; 2504 ret = reset_controller_register(&rstc->reset); 2505 if (ret) { 2506 pr_err("%s: Failed to register clkc reset controller: %d\n", 2507 __func__, ret); 2508 return; 2509 } 2510 2511 /* Populate regmap for the regmap backed clocks */ 2512 for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++) 2513 meson8b_clk_regmaps[i]->map = map; 2514 2515 /* 2516 * register all clks 2517 * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1 2518 */ 2519 for (i = CLKID_XTAL; i < CLK_NR_CLKS; i++) { 2520 /* array might be sparse */ 2521 if (!clk_hw_onecell_data->hws[i]) 2522 continue; 2523 2524 ret = clk_hw_register(NULL, clk_hw_onecell_data->hws[i]); 2525 if (ret) 2526 return; 2527 } 2528 2529 meson8b_cpu_nb_data.onecell_data = clk_hw_onecell_data; 2530 2531 /* 2532 * FIXME we shouldn't program the muxes in notifier handlers. The 2533 * tricky programming sequence will be handled by the forthcoming 2534 * coordinated clock rates mechanism once that feature is released. 2535 */ 2536 notifier_clk_name = clk_hw_get_name(&meson8b_cpu_scale_out_sel.hw); 2537 notifier_clk = __clk_lookup(notifier_clk_name); 2538 ret = clk_notifier_register(notifier_clk, &meson8b_cpu_nb_data.nb); 2539 if (ret) { 2540 pr_err("%s: failed to register the CPU clock notifier\n", 2541 __func__); 2542 return; 2543 } 2544 2545 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, 2546 clk_hw_onecell_data); 2547 if (ret) 2548 pr_err("%s: failed to register clock provider\n", __func__); 2549 } 2550 2551 static void __init meson8_clkc_init(struct device_node *np) 2552 { 2553 return meson8b_clkc_init_common(np, &meson8_hw_onecell_data); 2554 } 2555 2556 static void __init meson8b_clkc_init(struct device_node *np) 2557 { 2558 return meson8b_clkc_init_common(np, &meson8b_hw_onecell_data); 2559 } 2560 2561 CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc", 2562 meson8_clkc_init); 2563 CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc", 2564 meson8b_clkc_init); 2565 CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc", 2566 meson8b_clkc_init); 2567