1 /* 2 * AmLogic S905 / GXBB Clock Controller Driver 3 * 4 * Copyright (c) 2016 AmLogic, Inc. 5 * Michael Turquette <mturquette@baylibre.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/clk.h> 21 #include <linux/clk-provider.h> 22 #include <linux/of_address.h> 23 #include <linux/of_device.h> 24 #include <linux/platform_device.h> 25 #include <linux/init.h> 26 27 #include "clkc.h" 28 #include "gxbb.h" 29 30 static DEFINE_SPINLOCK(clk_lock); 31 32 static const struct pll_rate_table sys_pll_rate_table[] = { 33 PLL_RATE(24000000, 56, 1, 2), 34 PLL_RATE(48000000, 64, 1, 2), 35 PLL_RATE(72000000, 72, 1, 2), 36 PLL_RATE(96000000, 64, 1, 2), 37 PLL_RATE(120000000, 80, 1, 2), 38 PLL_RATE(144000000, 96, 1, 2), 39 PLL_RATE(168000000, 56, 1, 1), 40 PLL_RATE(192000000, 64, 1, 1), 41 PLL_RATE(216000000, 72, 1, 1), 42 PLL_RATE(240000000, 80, 1, 1), 43 PLL_RATE(264000000, 88, 1, 1), 44 PLL_RATE(288000000, 96, 1, 1), 45 PLL_RATE(312000000, 52, 1, 2), 46 PLL_RATE(336000000, 56, 1, 2), 47 PLL_RATE(360000000, 60, 1, 2), 48 PLL_RATE(384000000, 64, 1, 2), 49 PLL_RATE(408000000, 68, 1, 2), 50 PLL_RATE(432000000, 72, 1, 2), 51 PLL_RATE(456000000, 76, 1, 2), 52 PLL_RATE(480000000, 80, 1, 2), 53 PLL_RATE(504000000, 84, 1, 2), 54 PLL_RATE(528000000, 88, 1, 2), 55 PLL_RATE(552000000, 92, 1, 2), 56 PLL_RATE(576000000, 96, 1, 2), 57 PLL_RATE(600000000, 50, 1, 1), 58 PLL_RATE(624000000, 52, 1, 1), 59 PLL_RATE(648000000, 54, 1, 1), 60 PLL_RATE(672000000, 56, 1, 1), 61 PLL_RATE(696000000, 58, 1, 1), 62 PLL_RATE(720000000, 60, 1, 1), 63 PLL_RATE(744000000, 62, 1, 1), 64 PLL_RATE(768000000, 64, 1, 1), 65 PLL_RATE(792000000, 66, 1, 1), 66 PLL_RATE(816000000, 68, 1, 1), 67 PLL_RATE(840000000, 70, 1, 1), 68 PLL_RATE(864000000, 72, 1, 1), 69 PLL_RATE(888000000, 74, 1, 1), 70 PLL_RATE(912000000, 76, 1, 1), 71 PLL_RATE(936000000, 78, 1, 1), 72 PLL_RATE(960000000, 80, 1, 1), 73 PLL_RATE(984000000, 82, 1, 1), 74 PLL_RATE(1008000000, 84, 1, 1), 75 PLL_RATE(1032000000, 86, 1, 1), 76 PLL_RATE(1056000000, 88, 1, 1), 77 PLL_RATE(1080000000, 90, 1, 1), 78 PLL_RATE(1104000000, 92, 1, 1), 79 PLL_RATE(1128000000, 94, 1, 1), 80 PLL_RATE(1152000000, 96, 1, 1), 81 PLL_RATE(1176000000, 98, 1, 1), 82 PLL_RATE(1200000000, 50, 1, 0), 83 PLL_RATE(1224000000, 51, 1, 0), 84 PLL_RATE(1248000000, 52, 1, 0), 85 PLL_RATE(1272000000, 53, 1, 0), 86 PLL_RATE(1296000000, 54, 1, 0), 87 PLL_RATE(1320000000, 55, 1, 0), 88 PLL_RATE(1344000000, 56, 1, 0), 89 PLL_RATE(1368000000, 57, 1, 0), 90 PLL_RATE(1392000000, 58, 1, 0), 91 PLL_RATE(1416000000, 59, 1, 0), 92 PLL_RATE(1440000000, 60, 1, 0), 93 PLL_RATE(1464000000, 61, 1, 0), 94 PLL_RATE(1488000000, 62, 1, 0), 95 PLL_RATE(1512000000, 63, 1, 0), 96 PLL_RATE(1536000000, 64, 1, 0), 97 PLL_RATE(1560000000, 65, 1, 0), 98 PLL_RATE(1584000000, 66, 1, 0), 99 PLL_RATE(1608000000, 67, 1, 0), 100 PLL_RATE(1632000000, 68, 1, 0), 101 PLL_RATE(1656000000, 68, 1, 0), 102 PLL_RATE(1680000000, 68, 1, 0), 103 PLL_RATE(1704000000, 68, 1, 0), 104 PLL_RATE(1728000000, 69, 1, 0), 105 PLL_RATE(1752000000, 69, 1, 0), 106 PLL_RATE(1776000000, 69, 1, 0), 107 PLL_RATE(1800000000, 69, 1, 0), 108 PLL_RATE(1824000000, 70, 1, 0), 109 PLL_RATE(1848000000, 70, 1, 0), 110 PLL_RATE(1872000000, 70, 1, 0), 111 PLL_RATE(1896000000, 70, 1, 0), 112 PLL_RATE(1920000000, 71, 1, 0), 113 PLL_RATE(1944000000, 71, 1, 0), 114 PLL_RATE(1968000000, 71, 1, 0), 115 PLL_RATE(1992000000, 71, 1, 0), 116 PLL_RATE(2016000000, 72, 1, 0), 117 PLL_RATE(2040000000, 72, 1, 0), 118 PLL_RATE(2064000000, 72, 1, 0), 119 PLL_RATE(2088000000, 72, 1, 0), 120 PLL_RATE(2112000000, 73, 1, 0), 121 { /* sentinel */ }, 122 }; 123 124 static const struct pll_rate_table gxbb_gp0_pll_rate_table[] = { 125 PLL_RATE(96000000, 32, 1, 3), 126 PLL_RATE(99000000, 33, 1, 3), 127 PLL_RATE(102000000, 34, 1, 3), 128 PLL_RATE(105000000, 35, 1, 3), 129 PLL_RATE(108000000, 36, 1, 3), 130 PLL_RATE(111000000, 37, 1, 3), 131 PLL_RATE(114000000, 38, 1, 3), 132 PLL_RATE(117000000, 39, 1, 3), 133 PLL_RATE(120000000, 40, 1, 3), 134 PLL_RATE(123000000, 41, 1, 3), 135 PLL_RATE(126000000, 42, 1, 3), 136 PLL_RATE(129000000, 43, 1, 3), 137 PLL_RATE(132000000, 44, 1, 3), 138 PLL_RATE(135000000, 45, 1, 3), 139 PLL_RATE(138000000, 46, 1, 3), 140 PLL_RATE(141000000, 47, 1, 3), 141 PLL_RATE(144000000, 48, 1, 3), 142 PLL_RATE(147000000, 49, 1, 3), 143 PLL_RATE(150000000, 50, 1, 3), 144 PLL_RATE(153000000, 51, 1, 3), 145 PLL_RATE(156000000, 52, 1, 3), 146 PLL_RATE(159000000, 53, 1, 3), 147 PLL_RATE(162000000, 54, 1, 3), 148 PLL_RATE(165000000, 55, 1, 3), 149 PLL_RATE(168000000, 56, 1, 3), 150 PLL_RATE(171000000, 57, 1, 3), 151 PLL_RATE(174000000, 58, 1, 3), 152 PLL_RATE(177000000, 59, 1, 3), 153 PLL_RATE(180000000, 60, 1, 3), 154 PLL_RATE(183000000, 61, 1, 3), 155 PLL_RATE(186000000, 62, 1, 3), 156 PLL_RATE(192000000, 32, 1, 2), 157 PLL_RATE(198000000, 33, 1, 2), 158 PLL_RATE(204000000, 34, 1, 2), 159 PLL_RATE(210000000, 35, 1, 2), 160 PLL_RATE(216000000, 36, 1, 2), 161 PLL_RATE(222000000, 37, 1, 2), 162 PLL_RATE(228000000, 38, 1, 2), 163 PLL_RATE(234000000, 39, 1, 2), 164 PLL_RATE(240000000, 40, 1, 2), 165 PLL_RATE(246000000, 41, 1, 2), 166 PLL_RATE(252000000, 42, 1, 2), 167 PLL_RATE(258000000, 43, 1, 2), 168 PLL_RATE(264000000, 44, 1, 2), 169 PLL_RATE(270000000, 45, 1, 2), 170 PLL_RATE(276000000, 46, 1, 2), 171 PLL_RATE(282000000, 47, 1, 2), 172 PLL_RATE(288000000, 48, 1, 2), 173 PLL_RATE(294000000, 49, 1, 2), 174 PLL_RATE(300000000, 50, 1, 2), 175 PLL_RATE(306000000, 51, 1, 2), 176 PLL_RATE(312000000, 52, 1, 2), 177 PLL_RATE(318000000, 53, 1, 2), 178 PLL_RATE(324000000, 54, 1, 2), 179 PLL_RATE(330000000, 55, 1, 2), 180 PLL_RATE(336000000, 56, 1, 2), 181 PLL_RATE(342000000, 57, 1, 2), 182 PLL_RATE(348000000, 58, 1, 2), 183 PLL_RATE(354000000, 59, 1, 2), 184 PLL_RATE(360000000, 60, 1, 2), 185 PLL_RATE(366000000, 61, 1, 2), 186 PLL_RATE(372000000, 62, 1, 2), 187 PLL_RATE(384000000, 32, 1, 1), 188 PLL_RATE(396000000, 33, 1, 1), 189 PLL_RATE(408000000, 34, 1, 1), 190 PLL_RATE(420000000, 35, 1, 1), 191 PLL_RATE(432000000, 36, 1, 1), 192 PLL_RATE(444000000, 37, 1, 1), 193 PLL_RATE(456000000, 38, 1, 1), 194 PLL_RATE(468000000, 39, 1, 1), 195 PLL_RATE(480000000, 40, 1, 1), 196 PLL_RATE(492000000, 41, 1, 1), 197 PLL_RATE(504000000, 42, 1, 1), 198 PLL_RATE(516000000, 43, 1, 1), 199 PLL_RATE(528000000, 44, 1, 1), 200 PLL_RATE(540000000, 45, 1, 1), 201 PLL_RATE(552000000, 46, 1, 1), 202 PLL_RATE(564000000, 47, 1, 1), 203 PLL_RATE(576000000, 48, 1, 1), 204 PLL_RATE(588000000, 49, 1, 1), 205 PLL_RATE(600000000, 50, 1, 1), 206 PLL_RATE(612000000, 51, 1, 1), 207 PLL_RATE(624000000, 52, 1, 1), 208 PLL_RATE(636000000, 53, 1, 1), 209 PLL_RATE(648000000, 54, 1, 1), 210 PLL_RATE(660000000, 55, 1, 1), 211 PLL_RATE(672000000, 56, 1, 1), 212 PLL_RATE(684000000, 57, 1, 1), 213 PLL_RATE(696000000, 58, 1, 1), 214 PLL_RATE(708000000, 59, 1, 1), 215 PLL_RATE(720000000, 60, 1, 1), 216 PLL_RATE(732000000, 61, 1, 1), 217 PLL_RATE(744000000, 62, 1, 1), 218 PLL_RATE(768000000, 32, 1, 0), 219 PLL_RATE(792000000, 33, 1, 0), 220 PLL_RATE(816000000, 34, 1, 0), 221 PLL_RATE(840000000, 35, 1, 0), 222 PLL_RATE(864000000, 36, 1, 0), 223 PLL_RATE(888000000, 37, 1, 0), 224 PLL_RATE(912000000, 38, 1, 0), 225 PLL_RATE(936000000, 39, 1, 0), 226 PLL_RATE(960000000, 40, 1, 0), 227 PLL_RATE(984000000, 41, 1, 0), 228 PLL_RATE(1008000000, 42, 1, 0), 229 PLL_RATE(1032000000, 43, 1, 0), 230 PLL_RATE(1056000000, 44, 1, 0), 231 PLL_RATE(1080000000, 45, 1, 0), 232 PLL_RATE(1104000000, 46, 1, 0), 233 PLL_RATE(1128000000, 47, 1, 0), 234 PLL_RATE(1152000000, 48, 1, 0), 235 PLL_RATE(1176000000, 49, 1, 0), 236 PLL_RATE(1200000000, 50, 1, 0), 237 PLL_RATE(1224000000, 51, 1, 0), 238 PLL_RATE(1248000000, 52, 1, 0), 239 PLL_RATE(1272000000, 53, 1, 0), 240 PLL_RATE(1296000000, 54, 1, 0), 241 PLL_RATE(1320000000, 55, 1, 0), 242 PLL_RATE(1344000000, 56, 1, 0), 243 PLL_RATE(1368000000, 57, 1, 0), 244 PLL_RATE(1392000000, 58, 1, 0), 245 PLL_RATE(1416000000, 59, 1, 0), 246 PLL_RATE(1440000000, 60, 1, 0), 247 PLL_RATE(1464000000, 61, 1, 0), 248 PLL_RATE(1488000000, 62, 1, 0), 249 { /* sentinel */ }, 250 }; 251 252 static const struct pll_rate_table gxl_gp0_pll_rate_table[] = { 253 PLL_RATE(504000000, 42, 1, 1), 254 PLL_RATE(516000000, 43, 1, 1), 255 PLL_RATE(528000000, 44, 1, 1), 256 PLL_RATE(540000000, 45, 1, 1), 257 PLL_RATE(552000000, 46, 1, 1), 258 PLL_RATE(564000000, 47, 1, 1), 259 PLL_RATE(576000000, 48, 1, 1), 260 PLL_RATE(588000000, 49, 1, 1), 261 PLL_RATE(600000000, 50, 1, 1), 262 PLL_RATE(612000000, 51, 1, 1), 263 PLL_RATE(624000000, 52, 1, 1), 264 PLL_RATE(636000000, 53, 1, 1), 265 PLL_RATE(648000000, 54, 1, 1), 266 PLL_RATE(660000000, 55, 1, 1), 267 PLL_RATE(672000000, 56, 1, 1), 268 PLL_RATE(684000000, 57, 1, 1), 269 PLL_RATE(696000000, 58, 1, 1), 270 PLL_RATE(708000000, 59, 1, 1), 271 PLL_RATE(720000000, 60, 1, 1), 272 PLL_RATE(732000000, 61, 1, 1), 273 PLL_RATE(744000000, 62, 1, 1), 274 PLL_RATE(756000000, 63, 1, 1), 275 PLL_RATE(768000000, 64, 1, 1), 276 PLL_RATE(780000000, 65, 1, 1), 277 PLL_RATE(792000000, 66, 1, 1), 278 { /* sentinel */ }, 279 }; 280 281 static struct meson_clk_pll gxbb_fixed_pll = { 282 .m = { 283 .reg_off = HHI_MPLL_CNTL, 284 .shift = 0, 285 .width = 9, 286 }, 287 .n = { 288 .reg_off = HHI_MPLL_CNTL, 289 .shift = 9, 290 .width = 5, 291 }, 292 .od = { 293 .reg_off = HHI_MPLL_CNTL, 294 .shift = 16, 295 .width = 2, 296 }, 297 .lock = &clk_lock, 298 .hw.init = &(struct clk_init_data){ 299 .name = "fixed_pll", 300 .ops = &meson_clk_pll_ro_ops, 301 .parent_names = (const char *[]){ "xtal" }, 302 .num_parents = 1, 303 .flags = CLK_GET_RATE_NOCACHE, 304 }, 305 }; 306 307 static struct meson_clk_pll gxbb_hdmi_pll = { 308 .m = { 309 .reg_off = HHI_HDMI_PLL_CNTL, 310 .shift = 0, 311 .width = 9, 312 }, 313 .n = { 314 .reg_off = HHI_HDMI_PLL_CNTL, 315 .shift = 9, 316 .width = 5, 317 }, 318 .frac = { 319 .reg_off = HHI_HDMI_PLL_CNTL2, 320 .shift = 0, 321 .width = 12, 322 }, 323 .od = { 324 .reg_off = HHI_HDMI_PLL_CNTL2, 325 .shift = 16, 326 .width = 2, 327 }, 328 .od2 = { 329 .reg_off = HHI_HDMI_PLL_CNTL2, 330 .shift = 22, 331 .width = 2, 332 }, 333 .lock = &clk_lock, 334 .hw.init = &(struct clk_init_data){ 335 .name = "hdmi_pll", 336 .ops = &meson_clk_pll_ro_ops, 337 .parent_names = (const char *[]){ "xtal" }, 338 .num_parents = 1, 339 .flags = CLK_GET_RATE_NOCACHE, 340 }, 341 }; 342 343 static struct meson_clk_pll gxbb_sys_pll = { 344 .m = { 345 .reg_off = HHI_SYS_PLL_CNTL, 346 .shift = 0, 347 .width = 9, 348 }, 349 .n = { 350 .reg_off = HHI_SYS_PLL_CNTL, 351 .shift = 9, 352 .width = 5, 353 }, 354 .od = { 355 .reg_off = HHI_SYS_PLL_CNTL, 356 .shift = 10, 357 .width = 2, 358 }, 359 .rate_table = sys_pll_rate_table, 360 .rate_count = ARRAY_SIZE(sys_pll_rate_table), 361 .lock = &clk_lock, 362 .hw.init = &(struct clk_init_data){ 363 .name = "sys_pll", 364 .ops = &meson_clk_pll_ro_ops, 365 .parent_names = (const char *[]){ "xtal" }, 366 .num_parents = 1, 367 .flags = CLK_GET_RATE_NOCACHE, 368 }, 369 }; 370 371 struct pll_params_table gxbb_gp0_params_table[] = { 372 PLL_PARAM(HHI_GP0_PLL_CNTL, 0x6a000228), 373 PLL_PARAM(HHI_GP0_PLL_CNTL2, 0x69c80000), 374 PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a5590c4), 375 PLL_PARAM(HHI_GP0_PLL_CNTL4, 0x0000500d), 376 }; 377 378 static struct meson_clk_pll gxbb_gp0_pll = { 379 .m = { 380 .reg_off = HHI_GP0_PLL_CNTL, 381 .shift = 0, 382 .width = 9, 383 }, 384 .n = { 385 .reg_off = HHI_GP0_PLL_CNTL, 386 .shift = 9, 387 .width = 5, 388 }, 389 .od = { 390 .reg_off = HHI_GP0_PLL_CNTL, 391 .shift = 16, 392 .width = 2, 393 }, 394 .params = { 395 .params_table = gxbb_gp0_params_table, 396 .params_count = ARRAY_SIZE(gxbb_gp0_params_table), 397 .no_init_reset = true, 398 .clear_reset_for_lock = true, 399 }, 400 .rate_table = gxbb_gp0_pll_rate_table, 401 .rate_count = ARRAY_SIZE(gxbb_gp0_pll_rate_table), 402 .lock = &clk_lock, 403 .hw.init = &(struct clk_init_data){ 404 .name = "gp0_pll", 405 .ops = &meson_clk_pll_ops, 406 .parent_names = (const char *[]){ "xtal" }, 407 .num_parents = 1, 408 .flags = CLK_GET_RATE_NOCACHE, 409 }, 410 }; 411 412 struct pll_params_table gxl_gp0_params_table[] = { 413 PLL_PARAM(HHI_GP0_PLL_CNTL, 0x40010250), 414 PLL_PARAM(HHI_GP0_PLL_CNTL1, 0xc084a000), 415 PLL_PARAM(HHI_GP0_PLL_CNTL2, 0xb75020be), 416 PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a59a288), 417 PLL_PARAM(HHI_GP0_PLL_CNTL4, 0xc000004d), 418 PLL_PARAM(HHI_GP0_PLL_CNTL5, 0x00078000), 419 }; 420 421 static struct meson_clk_pll gxl_gp0_pll = { 422 .m = { 423 .reg_off = HHI_GP0_PLL_CNTL, 424 .shift = 0, 425 .width = 9, 426 }, 427 .n = { 428 .reg_off = HHI_GP0_PLL_CNTL, 429 .shift = 9, 430 .width = 5, 431 }, 432 .od = { 433 .reg_off = HHI_GP0_PLL_CNTL, 434 .shift = 16, 435 .width = 2, 436 }, 437 .params = { 438 .params_table = gxl_gp0_params_table, 439 .params_count = ARRAY_SIZE(gxl_gp0_params_table), 440 .no_init_reset = true, 441 .reset_lock_loop = true, 442 }, 443 .rate_table = gxl_gp0_pll_rate_table, 444 .rate_count = ARRAY_SIZE(gxl_gp0_pll_rate_table), 445 .lock = &clk_lock, 446 .hw.init = &(struct clk_init_data){ 447 .name = "gp0_pll", 448 .ops = &meson_clk_pll_ops, 449 .parent_names = (const char *[]){ "xtal" }, 450 .num_parents = 1, 451 .flags = CLK_GET_RATE_NOCACHE, 452 }, 453 }; 454 455 static struct clk_fixed_factor gxbb_fclk_div2 = { 456 .mult = 1, 457 .div = 2, 458 .hw.init = &(struct clk_init_data){ 459 .name = "fclk_div2", 460 .ops = &clk_fixed_factor_ops, 461 .parent_names = (const char *[]){ "fixed_pll" }, 462 .num_parents = 1, 463 }, 464 }; 465 466 static struct clk_fixed_factor gxbb_fclk_div3 = { 467 .mult = 1, 468 .div = 3, 469 .hw.init = &(struct clk_init_data){ 470 .name = "fclk_div3", 471 .ops = &clk_fixed_factor_ops, 472 .parent_names = (const char *[]){ "fixed_pll" }, 473 .num_parents = 1, 474 }, 475 }; 476 477 static struct clk_fixed_factor gxbb_fclk_div4 = { 478 .mult = 1, 479 .div = 4, 480 .hw.init = &(struct clk_init_data){ 481 .name = "fclk_div4", 482 .ops = &clk_fixed_factor_ops, 483 .parent_names = (const char *[]){ "fixed_pll" }, 484 .num_parents = 1, 485 }, 486 }; 487 488 static struct clk_fixed_factor gxbb_fclk_div5 = { 489 .mult = 1, 490 .div = 5, 491 .hw.init = &(struct clk_init_data){ 492 .name = "fclk_div5", 493 .ops = &clk_fixed_factor_ops, 494 .parent_names = (const char *[]){ "fixed_pll" }, 495 .num_parents = 1, 496 }, 497 }; 498 499 static struct clk_fixed_factor gxbb_fclk_div7 = { 500 .mult = 1, 501 .div = 7, 502 .hw.init = &(struct clk_init_data){ 503 .name = "fclk_div7", 504 .ops = &clk_fixed_factor_ops, 505 .parent_names = (const char *[]){ "fixed_pll" }, 506 .num_parents = 1, 507 }, 508 }; 509 510 static struct meson_clk_mpll gxbb_mpll0 = { 511 .sdm = { 512 .reg_off = HHI_MPLL_CNTL7, 513 .shift = 0, 514 .width = 14, 515 }, 516 .sdm_en = { 517 .reg_off = HHI_MPLL_CNTL7, 518 .shift = 15, 519 .width = 1, 520 }, 521 .n2 = { 522 .reg_off = HHI_MPLL_CNTL7, 523 .shift = 16, 524 .width = 9, 525 }, 526 .en = { 527 .reg_off = HHI_MPLL_CNTL7, 528 .shift = 14, 529 .width = 1, 530 }, 531 .lock = &clk_lock, 532 .hw.init = &(struct clk_init_data){ 533 .name = "mpll0", 534 .ops = &meson_clk_mpll_ops, 535 .parent_names = (const char *[]){ "fixed_pll" }, 536 .num_parents = 1, 537 }, 538 }; 539 540 static struct meson_clk_mpll gxbb_mpll1 = { 541 .sdm = { 542 .reg_off = HHI_MPLL_CNTL8, 543 .shift = 0, 544 .width = 14, 545 }, 546 .sdm_en = { 547 .reg_off = HHI_MPLL_CNTL8, 548 .shift = 15, 549 .width = 1, 550 }, 551 .n2 = { 552 .reg_off = HHI_MPLL_CNTL8, 553 .shift = 16, 554 .width = 9, 555 }, 556 .en = { 557 .reg_off = HHI_MPLL_CNTL8, 558 .shift = 14, 559 .width = 1, 560 }, 561 .lock = &clk_lock, 562 .hw.init = &(struct clk_init_data){ 563 .name = "mpll1", 564 .ops = &meson_clk_mpll_ops, 565 .parent_names = (const char *[]){ "fixed_pll" }, 566 .num_parents = 1, 567 }, 568 }; 569 570 static struct meson_clk_mpll gxbb_mpll2 = { 571 .sdm = { 572 .reg_off = HHI_MPLL_CNTL9, 573 .shift = 0, 574 .width = 14, 575 }, 576 .sdm_en = { 577 .reg_off = HHI_MPLL_CNTL9, 578 .shift = 15, 579 .width = 1, 580 }, 581 .n2 = { 582 .reg_off = HHI_MPLL_CNTL9, 583 .shift = 16, 584 .width = 9, 585 }, 586 .en = { 587 .reg_off = HHI_MPLL_CNTL9, 588 .shift = 14, 589 .width = 1, 590 }, 591 .lock = &clk_lock, 592 .hw.init = &(struct clk_init_data){ 593 .name = "mpll2", 594 .ops = &meson_clk_mpll_ops, 595 .parent_names = (const char *[]){ "fixed_pll" }, 596 .num_parents = 1, 597 }, 598 }; 599 600 /* 601 * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers 602 * and should be modeled with their respective PLLs via the forthcoming 603 * coordinated clock rates feature 604 */ 605 606 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; 607 static const char * const clk81_parent_names[] = { 608 "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", 609 "fclk_div3", "fclk_div5" 610 }; 611 612 static struct clk_mux gxbb_mpeg_clk_sel = { 613 .reg = (void *)HHI_MPEG_CLK_CNTL, 614 .mask = 0x7, 615 .shift = 12, 616 .flags = CLK_MUX_READ_ONLY, 617 .table = mux_table_clk81, 618 .lock = &clk_lock, 619 .hw.init = &(struct clk_init_data){ 620 .name = "mpeg_clk_sel", 621 .ops = &clk_mux_ro_ops, 622 /* 623 * bits 14:12 selects from 8 possible parents: 624 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, 625 * fclk_div4, fclk_div3, fclk_div5 626 */ 627 .parent_names = clk81_parent_names, 628 .num_parents = ARRAY_SIZE(clk81_parent_names), 629 .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED), 630 }, 631 }; 632 633 static struct clk_divider gxbb_mpeg_clk_div = { 634 .reg = (void *)HHI_MPEG_CLK_CNTL, 635 .shift = 0, 636 .width = 7, 637 .lock = &clk_lock, 638 .hw.init = &(struct clk_init_data){ 639 .name = "mpeg_clk_div", 640 .ops = &clk_divider_ops, 641 .parent_names = (const char *[]){ "mpeg_clk_sel" }, 642 .num_parents = 1, 643 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), 644 }, 645 }; 646 647 /* the mother of dragons^W gates */ 648 static struct clk_gate gxbb_clk81 = { 649 .reg = (void *)HHI_MPEG_CLK_CNTL, 650 .bit_idx = 7, 651 .lock = &clk_lock, 652 .hw.init = &(struct clk_init_data){ 653 .name = "clk81", 654 .ops = &clk_gate_ops, 655 .parent_names = (const char *[]){ "mpeg_clk_div" }, 656 .num_parents = 1, 657 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), 658 }, 659 }; 660 661 static struct clk_mux gxbb_sar_adc_clk_sel = { 662 .reg = (void *)HHI_SAR_CLK_CNTL, 663 .mask = 0x3, 664 .shift = 9, 665 .lock = &clk_lock, 666 .hw.init = &(struct clk_init_data){ 667 .name = "sar_adc_clk_sel", 668 .ops = &clk_mux_ops, 669 /* NOTE: The datasheet doesn't list the parents for bit 10 */ 670 .parent_names = (const char *[]){ "xtal", "clk81", }, 671 .num_parents = 2, 672 }, 673 }; 674 675 static struct clk_divider gxbb_sar_adc_clk_div = { 676 .reg = (void *)HHI_SAR_CLK_CNTL, 677 .shift = 0, 678 .width = 8, 679 .lock = &clk_lock, 680 .hw.init = &(struct clk_init_data){ 681 .name = "sar_adc_clk_div", 682 .ops = &clk_divider_ops, 683 .parent_names = (const char *[]){ "sar_adc_clk_sel" }, 684 .num_parents = 1, 685 }, 686 }; 687 688 static struct clk_gate gxbb_sar_adc_clk = { 689 .reg = (void *)HHI_SAR_CLK_CNTL, 690 .bit_idx = 8, 691 .lock = &clk_lock, 692 .hw.init = &(struct clk_init_data){ 693 .name = "sar_adc_clk", 694 .ops = &clk_gate_ops, 695 .parent_names = (const char *[]){ "sar_adc_clk_div" }, 696 .num_parents = 1, 697 .flags = CLK_SET_RATE_PARENT, 698 }, 699 }; 700 701 /* 702 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) 703 * muxed by a glitch-free switch. 704 */ 705 706 static u32 mux_table_mali_0_1[] = {0, 1, 2, 3, 4, 5, 6, 7}; 707 static const char * const gxbb_mali_0_1_parent_names[] = { 708 "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7", 709 "fclk_div4", "fclk_div3", "fclk_div5" 710 }; 711 712 static struct clk_mux gxbb_mali_0_sel = { 713 .reg = (void *)HHI_MALI_CLK_CNTL, 714 .mask = 0x7, 715 .shift = 9, 716 .table = mux_table_mali_0_1, 717 .lock = &clk_lock, 718 .hw.init = &(struct clk_init_data){ 719 .name = "mali_0_sel", 720 .ops = &clk_mux_ops, 721 /* 722 * bits 10:9 selects from 8 possible parents: 723 * xtal, gp0_pll, mpll2, mpll1, fclk_div7, 724 * fclk_div4, fclk_div3, fclk_div5 725 */ 726 .parent_names = gxbb_mali_0_1_parent_names, 727 .num_parents = 8, 728 .flags = CLK_SET_RATE_NO_REPARENT, 729 }, 730 }; 731 732 static struct clk_divider gxbb_mali_0_div = { 733 .reg = (void *)HHI_MALI_CLK_CNTL, 734 .shift = 0, 735 .width = 7, 736 .lock = &clk_lock, 737 .hw.init = &(struct clk_init_data){ 738 .name = "mali_0_div", 739 .ops = &clk_divider_ops, 740 .parent_names = (const char *[]){ "mali_0_sel" }, 741 .num_parents = 1, 742 .flags = CLK_SET_RATE_NO_REPARENT, 743 }, 744 }; 745 746 static struct clk_gate gxbb_mali_0 = { 747 .reg = (void *)HHI_MALI_CLK_CNTL, 748 .bit_idx = 8, 749 .lock = &clk_lock, 750 .hw.init = &(struct clk_init_data){ 751 .name = "mali_0", 752 .ops = &clk_gate_ops, 753 .parent_names = (const char *[]){ "mali_0_div" }, 754 .num_parents = 1, 755 .flags = CLK_SET_RATE_PARENT, 756 }, 757 }; 758 759 static struct clk_mux gxbb_mali_1_sel = { 760 .reg = (void *)HHI_MALI_CLK_CNTL, 761 .mask = 0x7, 762 .shift = 25, 763 .table = mux_table_mali_0_1, 764 .lock = &clk_lock, 765 .hw.init = &(struct clk_init_data){ 766 .name = "mali_1_sel", 767 .ops = &clk_mux_ops, 768 /* 769 * bits 10:9 selects from 8 possible parents: 770 * xtal, gp0_pll, mpll2, mpll1, fclk_div7, 771 * fclk_div4, fclk_div3, fclk_div5 772 */ 773 .parent_names = gxbb_mali_0_1_parent_names, 774 .num_parents = 8, 775 .flags = CLK_SET_RATE_NO_REPARENT, 776 }, 777 }; 778 779 static struct clk_divider gxbb_mali_1_div = { 780 .reg = (void *)HHI_MALI_CLK_CNTL, 781 .shift = 16, 782 .width = 7, 783 .lock = &clk_lock, 784 .hw.init = &(struct clk_init_data){ 785 .name = "mali_1_div", 786 .ops = &clk_divider_ops, 787 .parent_names = (const char *[]){ "mali_1_sel" }, 788 .num_parents = 1, 789 .flags = CLK_SET_RATE_NO_REPARENT, 790 }, 791 }; 792 793 static struct clk_gate gxbb_mali_1 = { 794 .reg = (void *)HHI_MALI_CLK_CNTL, 795 .bit_idx = 24, 796 .lock = &clk_lock, 797 .hw.init = &(struct clk_init_data){ 798 .name = "mali_1", 799 .ops = &clk_gate_ops, 800 .parent_names = (const char *[]){ "mali_1_div" }, 801 .num_parents = 1, 802 .flags = CLK_SET_RATE_PARENT, 803 }, 804 }; 805 806 static u32 mux_table_mali[] = {0, 1}; 807 static const char * const gxbb_mali_parent_names[] = { 808 "mali_0", "mali_1" 809 }; 810 811 static struct clk_mux gxbb_mali = { 812 .reg = (void *)HHI_MALI_CLK_CNTL, 813 .mask = 1, 814 .shift = 31, 815 .table = mux_table_mali, 816 .lock = &clk_lock, 817 .hw.init = &(struct clk_init_data){ 818 .name = "mali", 819 .ops = &clk_mux_ops, 820 .parent_names = gxbb_mali_parent_names, 821 .num_parents = 2, 822 .flags = CLK_SET_RATE_NO_REPARENT, 823 }, 824 }; 825 826 static struct clk_mux gxbb_cts_amclk_sel = { 827 .reg = (void *) HHI_AUD_CLK_CNTL, 828 .mask = 0x3, 829 .shift = 9, 830 /* Default parent unknown (register reset value: 0) */ 831 .table = (u32[]){ 1, 2, 3 }, 832 .lock = &clk_lock, 833 .hw.init = &(struct clk_init_data){ 834 .name = "cts_amclk_sel", 835 .ops = &clk_mux_ops, 836 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" }, 837 .num_parents = 3, 838 .flags = CLK_SET_RATE_PARENT, 839 }, 840 }; 841 842 static struct meson_clk_audio_divider gxbb_cts_amclk_div = { 843 .div = { 844 .reg_off = HHI_AUD_CLK_CNTL, 845 .shift = 0, 846 .width = 8, 847 }, 848 .lock = &clk_lock, 849 .hw.init = &(struct clk_init_data){ 850 .name = "cts_amclk_div", 851 .ops = &meson_clk_audio_divider_ops, 852 .parent_names = (const char *[]){ "cts_amclk_sel" }, 853 .num_parents = 1, 854 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST, 855 }, 856 }; 857 858 static struct clk_gate gxbb_cts_amclk = { 859 .reg = (void *) HHI_AUD_CLK_CNTL, 860 .bit_idx = 8, 861 .lock = &clk_lock, 862 .hw.init = &(struct clk_init_data){ 863 .name = "cts_amclk", 864 .ops = &clk_gate_ops, 865 .parent_names = (const char *[]){ "cts_amclk_div" }, 866 .num_parents = 1, 867 .flags = CLK_SET_RATE_PARENT, 868 }, 869 }; 870 871 static struct clk_mux gxbb_cts_mclk_i958_sel = { 872 .reg = (void *)HHI_AUD_CLK_CNTL2, 873 .mask = 0x3, 874 .shift = 25, 875 /* Default parent unknown (register reset value: 0) */ 876 .table = (u32[]){ 1, 2, 3 }, 877 .lock = &clk_lock, 878 .hw.init = &(struct clk_init_data){ 879 .name = "cts_mclk_i958_sel", 880 .ops = &clk_mux_ops, 881 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" }, 882 .num_parents = 3, 883 .flags = CLK_SET_RATE_PARENT, 884 }, 885 }; 886 887 static struct clk_divider gxbb_cts_mclk_i958_div = { 888 .reg = (void *)HHI_AUD_CLK_CNTL2, 889 .shift = 16, 890 .width = 8, 891 .lock = &clk_lock, 892 .hw.init = &(struct clk_init_data){ 893 .name = "cts_mclk_i958_div", 894 .ops = &clk_divider_ops, 895 .parent_names = (const char *[]){ "cts_mclk_i958_sel" }, 896 .num_parents = 1, 897 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST, 898 }, 899 }; 900 901 static struct clk_gate gxbb_cts_mclk_i958 = { 902 .reg = (void *)HHI_AUD_CLK_CNTL2, 903 .bit_idx = 24, 904 .lock = &clk_lock, 905 .hw.init = &(struct clk_init_data){ 906 .name = "cts_mclk_i958", 907 .ops = &clk_gate_ops, 908 .parent_names = (const char *[]){ "cts_mclk_i958_div" }, 909 .num_parents = 1, 910 .flags = CLK_SET_RATE_PARENT, 911 }, 912 }; 913 914 static struct clk_mux gxbb_cts_i958 = { 915 .reg = (void *)HHI_AUD_CLK_CNTL2, 916 .mask = 0x1, 917 .shift = 27, 918 .lock = &clk_lock, 919 .hw.init = &(struct clk_init_data){ 920 .name = "cts_i958", 921 .ops = &clk_mux_ops, 922 .parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" }, 923 .num_parents = 2, 924 /* 925 *The parent is specific to origin of the audio data. Let the 926 * consumer choose the appropriate parent 927 */ 928 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 929 }, 930 }; 931 932 static struct clk_divider gxbb_32k_clk_div = { 933 .reg = (void *)HHI_32K_CLK_CNTL, 934 .shift = 0, 935 .width = 14, 936 .lock = &clk_lock, 937 .hw.init = &(struct clk_init_data){ 938 .name = "32k_clk_div", 939 .ops = &clk_divider_ops, 940 .parent_names = (const char *[]){ "32k_clk_sel" }, 941 .num_parents = 1, 942 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST, 943 }, 944 }; 945 946 static struct clk_gate gxbb_32k_clk = { 947 .reg = (void *)HHI_32K_CLK_CNTL, 948 .bit_idx = 15, 949 .lock = &clk_lock, 950 .hw.init = &(struct clk_init_data){ 951 .name = "32k_clk", 952 .ops = &clk_gate_ops, 953 .parent_names = (const char *[]){ "32k_clk_div" }, 954 .num_parents = 1, 955 .flags = CLK_SET_RATE_PARENT, 956 }, 957 }; 958 959 static const char * const gxbb_32k_clk_parent_names[] = { 960 "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5" 961 }; 962 963 static struct clk_mux gxbb_32k_clk_sel = { 964 .reg = (void *)HHI_32K_CLK_CNTL, 965 .mask = 0x3, 966 .shift = 16, 967 .lock = &clk_lock, 968 .hw.init = &(struct clk_init_data){ 969 .name = "32k_clk_sel", 970 .ops = &clk_mux_ops, 971 .parent_names = gxbb_32k_clk_parent_names, 972 .num_parents = 4, 973 .flags = CLK_SET_RATE_PARENT, 974 }, 975 }; 976 977 /* Everything Else (EE) domain gates */ 978 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0); 979 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1); 980 static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5); 981 static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6); 982 static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7); 983 static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8); 984 static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9); 985 static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG0, 10); 986 static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11); 987 static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12); 988 static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13); 989 static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14); 990 static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15); 991 static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16); 992 static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17); 993 static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18); 994 static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19); 995 static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23); 996 static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24); 997 static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25); 998 static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26); 999 static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30); 1000 1001 static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2); 1002 static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3); 1003 static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4); 1004 static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6); 1005 static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7); 1006 static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8); 1007 static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9); 1008 static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10); 1009 static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11); 1010 static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12); 1011 static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13); 1012 static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14); 1013 static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15); 1014 static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16); 1015 static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20); 1016 static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21); 1017 static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22); 1018 static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23); 1019 static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24); 1020 static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25); 1021 static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26); 1022 static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28); 1023 static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29); 1024 static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30); 1025 static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31); 1026 1027 static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1); 1028 static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); 1029 static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3); 1030 static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4); 1031 static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); 1032 static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); 1033 static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11); 1034 static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12); 1035 static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15); 1036 static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG2, 22); 1037 static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25); 1038 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); 1039 static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29); 1040 1041 static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1); 1042 static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2); 1043 static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3); 1044 static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4); 1045 static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8); 1046 static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9); 1047 static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10); 1048 static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14); 1049 static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16); 1050 static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20); 1051 static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21); 1052 static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22); 1053 static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24); 1054 static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25); 1055 static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26); 1056 static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31); 1057 1058 /* Always On (AO) domain gates */ 1059 1060 static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0); 1061 static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1); 1062 static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2); 1063 static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3); 1064 static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4); 1065 1066 /* Array of all clocks provided by this provider */ 1067 1068 static struct clk_hw_onecell_data gxbb_hw_onecell_data = { 1069 .hws = { 1070 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 1071 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, 1072 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 1073 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 1074 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 1075 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 1076 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 1077 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 1078 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 1079 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 1080 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 1081 [CLKID_CLK81] = &gxbb_clk81.hw, 1082 [CLKID_MPLL0] = &gxbb_mpll0.hw, 1083 [CLKID_MPLL1] = &gxbb_mpll1.hw, 1084 [CLKID_MPLL2] = &gxbb_mpll2.hw, 1085 [CLKID_DDR] = &gxbb_ddr.hw, 1086 [CLKID_DOS] = &gxbb_dos.hw, 1087 [CLKID_ISA] = &gxbb_isa.hw, 1088 [CLKID_PL301] = &gxbb_pl301.hw, 1089 [CLKID_PERIPHS] = &gxbb_periphs.hw, 1090 [CLKID_SPICC] = &gxbb_spicc.hw, 1091 [CLKID_I2C] = &gxbb_i2c.hw, 1092 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 1093 [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 1094 [CLKID_RNG0] = &gxbb_rng0.hw, 1095 [CLKID_UART0] = &gxbb_uart0.hw, 1096 [CLKID_SDHC] = &gxbb_sdhc.hw, 1097 [CLKID_STREAM] = &gxbb_stream.hw, 1098 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 1099 [CLKID_SDIO] = &gxbb_sdio.hw, 1100 [CLKID_ABUF] = &gxbb_abuf.hw, 1101 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 1102 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 1103 [CLKID_SPI] = &gxbb_spi.hw, 1104 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 1105 [CLKID_ETH] = &gxbb_eth.hw, 1106 [CLKID_DEMUX] = &gxbb_demux.hw, 1107 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 1108 [CLKID_IEC958] = &gxbb_iec958.hw, 1109 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 1110 [CLKID_AMCLK] = &gxbb_amclk.hw, 1111 [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 1112 [CLKID_MIXER] = &gxbb_mixer.hw, 1113 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 1114 [CLKID_ADC] = &gxbb_adc.hw, 1115 [CLKID_BLKMV] = &gxbb_blkmv.hw, 1116 [CLKID_AIU] = &gxbb_aiu.hw, 1117 [CLKID_UART1] = &gxbb_uart1.hw, 1118 [CLKID_G2D] = &gxbb_g2d.hw, 1119 [CLKID_USB0] = &gxbb_usb0.hw, 1120 [CLKID_USB1] = &gxbb_usb1.hw, 1121 [CLKID_RESET] = &gxbb_reset.hw, 1122 [CLKID_NAND] = &gxbb_nand.hw, 1123 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 1124 [CLKID_USB] = &gxbb_usb.hw, 1125 [CLKID_VDIN1] = &gxbb_vdin1.hw, 1126 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 1127 [CLKID_EFUSE] = &gxbb_efuse.hw, 1128 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 1129 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 1130 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 1131 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 1132 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 1133 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 1134 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 1135 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 1136 [CLKID_DVIN] = &gxbb_dvin.hw, 1137 [CLKID_UART2] = &gxbb_uart2.hw, 1138 [CLKID_SANA] = &gxbb_sana.hw, 1139 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 1140 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 1141 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 1142 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 1143 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 1144 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 1145 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 1146 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 1147 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 1148 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 1149 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 1150 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 1151 [CLKID_ENC480P] = &gxbb_enc480p.hw, 1152 [CLKID_RNG1] = &gxbb_rng1.hw, 1153 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 1154 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 1155 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 1156 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 1157 [CLKID_EDP] = &gxbb_edp.hw, 1158 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 1159 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 1160 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 1161 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 1162 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 1163 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 1164 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 1165 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 1166 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 1167 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 1168 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 1169 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 1170 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 1171 [CLKID_MALI_0] = &gxbb_mali_0.hw, 1172 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 1173 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 1174 [CLKID_MALI_1] = &gxbb_mali_1.hw, 1175 [CLKID_MALI] = &gxbb_mali.hw, 1176 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 1177 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 1178 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 1179 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 1180 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 1181 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 1182 [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 1183 [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 1184 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 1185 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 1186 }, 1187 .num = NR_CLKS, 1188 }; 1189 1190 static struct clk_hw_onecell_data gxl_hw_onecell_data = { 1191 .hws = { 1192 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 1193 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, 1194 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 1195 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 1196 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 1197 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 1198 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 1199 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 1200 [CLKID_GP0_PLL] = &gxl_gp0_pll.hw, 1201 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 1202 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 1203 [CLKID_CLK81] = &gxbb_clk81.hw, 1204 [CLKID_MPLL0] = &gxbb_mpll0.hw, 1205 [CLKID_MPLL1] = &gxbb_mpll1.hw, 1206 [CLKID_MPLL2] = &gxbb_mpll2.hw, 1207 [CLKID_DDR] = &gxbb_ddr.hw, 1208 [CLKID_DOS] = &gxbb_dos.hw, 1209 [CLKID_ISA] = &gxbb_isa.hw, 1210 [CLKID_PL301] = &gxbb_pl301.hw, 1211 [CLKID_PERIPHS] = &gxbb_periphs.hw, 1212 [CLKID_SPICC] = &gxbb_spicc.hw, 1213 [CLKID_I2C] = &gxbb_i2c.hw, 1214 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 1215 [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 1216 [CLKID_RNG0] = &gxbb_rng0.hw, 1217 [CLKID_UART0] = &gxbb_uart0.hw, 1218 [CLKID_SDHC] = &gxbb_sdhc.hw, 1219 [CLKID_STREAM] = &gxbb_stream.hw, 1220 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 1221 [CLKID_SDIO] = &gxbb_sdio.hw, 1222 [CLKID_ABUF] = &gxbb_abuf.hw, 1223 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 1224 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 1225 [CLKID_SPI] = &gxbb_spi.hw, 1226 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 1227 [CLKID_ETH] = &gxbb_eth.hw, 1228 [CLKID_DEMUX] = &gxbb_demux.hw, 1229 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 1230 [CLKID_IEC958] = &gxbb_iec958.hw, 1231 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 1232 [CLKID_AMCLK] = &gxbb_amclk.hw, 1233 [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 1234 [CLKID_MIXER] = &gxbb_mixer.hw, 1235 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 1236 [CLKID_ADC] = &gxbb_adc.hw, 1237 [CLKID_BLKMV] = &gxbb_blkmv.hw, 1238 [CLKID_AIU] = &gxbb_aiu.hw, 1239 [CLKID_UART1] = &gxbb_uart1.hw, 1240 [CLKID_G2D] = &gxbb_g2d.hw, 1241 [CLKID_USB0] = &gxbb_usb0.hw, 1242 [CLKID_USB1] = &gxbb_usb1.hw, 1243 [CLKID_RESET] = &gxbb_reset.hw, 1244 [CLKID_NAND] = &gxbb_nand.hw, 1245 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 1246 [CLKID_USB] = &gxbb_usb.hw, 1247 [CLKID_VDIN1] = &gxbb_vdin1.hw, 1248 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 1249 [CLKID_EFUSE] = &gxbb_efuse.hw, 1250 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 1251 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 1252 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 1253 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 1254 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 1255 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 1256 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 1257 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 1258 [CLKID_DVIN] = &gxbb_dvin.hw, 1259 [CLKID_UART2] = &gxbb_uart2.hw, 1260 [CLKID_SANA] = &gxbb_sana.hw, 1261 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 1262 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 1263 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 1264 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 1265 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 1266 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 1267 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 1268 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 1269 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 1270 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 1271 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 1272 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 1273 [CLKID_ENC480P] = &gxbb_enc480p.hw, 1274 [CLKID_RNG1] = &gxbb_rng1.hw, 1275 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 1276 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 1277 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 1278 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 1279 [CLKID_EDP] = &gxbb_edp.hw, 1280 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 1281 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 1282 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 1283 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 1284 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 1285 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 1286 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 1287 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 1288 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 1289 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 1290 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 1291 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 1292 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 1293 [CLKID_MALI_0] = &gxbb_mali_0.hw, 1294 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 1295 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 1296 [CLKID_MALI_1] = &gxbb_mali_1.hw, 1297 [CLKID_MALI] = &gxbb_mali.hw, 1298 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 1299 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 1300 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 1301 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 1302 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 1303 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 1304 [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 1305 [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 1306 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 1307 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 1308 }, 1309 .num = NR_CLKS, 1310 }; 1311 1312 /* Convenience tables to populate base addresses in .probe */ 1313 1314 static struct meson_clk_pll *const gxbb_clk_plls[] = { 1315 &gxbb_fixed_pll, 1316 &gxbb_hdmi_pll, 1317 &gxbb_sys_pll, 1318 &gxbb_gp0_pll, 1319 }; 1320 1321 static struct meson_clk_pll *const gxl_clk_plls[] = { 1322 &gxbb_fixed_pll, 1323 &gxbb_hdmi_pll, 1324 &gxbb_sys_pll, 1325 &gxl_gp0_pll, 1326 }; 1327 1328 static struct meson_clk_mpll *const gxbb_clk_mplls[] = { 1329 &gxbb_mpll0, 1330 &gxbb_mpll1, 1331 &gxbb_mpll2, 1332 }; 1333 1334 static struct clk_gate *const gxbb_clk_gates[] = { 1335 &gxbb_clk81, 1336 &gxbb_ddr, 1337 &gxbb_dos, 1338 &gxbb_isa, 1339 &gxbb_pl301, 1340 &gxbb_periphs, 1341 &gxbb_spicc, 1342 &gxbb_i2c, 1343 &gxbb_sar_adc, 1344 &gxbb_smart_card, 1345 &gxbb_rng0, 1346 &gxbb_uart0, 1347 &gxbb_sdhc, 1348 &gxbb_stream, 1349 &gxbb_async_fifo, 1350 &gxbb_sdio, 1351 &gxbb_abuf, 1352 &gxbb_hiu_iface, 1353 &gxbb_assist_misc, 1354 &gxbb_spi, 1355 &gxbb_i2s_spdif, 1356 &gxbb_eth, 1357 &gxbb_demux, 1358 &gxbb_aiu_glue, 1359 &gxbb_iec958, 1360 &gxbb_i2s_out, 1361 &gxbb_amclk, 1362 &gxbb_aififo2, 1363 &gxbb_mixer, 1364 &gxbb_mixer_iface, 1365 &gxbb_adc, 1366 &gxbb_blkmv, 1367 &gxbb_aiu, 1368 &gxbb_uart1, 1369 &gxbb_g2d, 1370 &gxbb_usb0, 1371 &gxbb_usb1, 1372 &gxbb_reset, 1373 &gxbb_nand, 1374 &gxbb_dos_parser, 1375 &gxbb_usb, 1376 &gxbb_vdin1, 1377 &gxbb_ahb_arb0, 1378 &gxbb_efuse, 1379 &gxbb_boot_rom, 1380 &gxbb_ahb_data_bus, 1381 &gxbb_ahb_ctrl_bus, 1382 &gxbb_hdmi_intr_sync, 1383 &gxbb_hdmi_pclk, 1384 &gxbb_usb1_ddr_bridge, 1385 &gxbb_usb0_ddr_bridge, 1386 &gxbb_mmc_pclk, 1387 &gxbb_dvin, 1388 &gxbb_uart2, 1389 &gxbb_sana, 1390 &gxbb_vpu_intr, 1391 &gxbb_sec_ahb_ahb3_bridge, 1392 &gxbb_clk81_a53, 1393 &gxbb_vclk2_venci0, 1394 &gxbb_vclk2_venci1, 1395 &gxbb_vclk2_vencp0, 1396 &gxbb_vclk2_vencp1, 1397 &gxbb_gclk_venci_int0, 1398 &gxbb_gclk_vencp_int, 1399 &gxbb_dac_clk, 1400 &gxbb_aoclk_gate, 1401 &gxbb_iec958_gate, 1402 &gxbb_enc480p, 1403 &gxbb_rng1, 1404 &gxbb_gclk_venci_int1, 1405 &gxbb_vclk2_venclmcc, 1406 &gxbb_vclk2_vencl, 1407 &gxbb_vclk_other, 1408 &gxbb_edp, 1409 &gxbb_ao_media_cpu, 1410 &gxbb_ao_ahb_sram, 1411 &gxbb_ao_ahb_bus, 1412 &gxbb_ao_iface, 1413 &gxbb_ao_i2c, 1414 &gxbb_emmc_a, 1415 &gxbb_emmc_b, 1416 &gxbb_emmc_c, 1417 &gxbb_sar_adc_clk, 1418 &gxbb_mali_0, 1419 &gxbb_mali_1, 1420 &gxbb_cts_amclk, 1421 &gxbb_cts_mclk_i958, 1422 &gxbb_32k_clk, 1423 }; 1424 1425 static struct clk_mux *const gxbb_clk_muxes[] = { 1426 &gxbb_mpeg_clk_sel, 1427 &gxbb_sar_adc_clk_sel, 1428 &gxbb_mali_0_sel, 1429 &gxbb_mali_1_sel, 1430 &gxbb_mali, 1431 &gxbb_cts_amclk_sel, 1432 &gxbb_cts_mclk_i958_sel, 1433 &gxbb_cts_i958, 1434 &gxbb_32k_clk_sel, 1435 }; 1436 1437 static struct clk_divider *const gxbb_clk_dividers[] = { 1438 &gxbb_mpeg_clk_div, 1439 &gxbb_sar_adc_clk_div, 1440 &gxbb_mali_0_div, 1441 &gxbb_mali_1_div, 1442 &gxbb_cts_mclk_i958_div, 1443 &gxbb_32k_clk_div, 1444 }; 1445 1446 static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = { 1447 &gxbb_cts_amclk_div, 1448 }; 1449 1450 struct clkc_data { 1451 struct clk_gate *const *clk_gates; 1452 unsigned int clk_gates_count; 1453 struct meson_clk_mpll *const *clk_mplls; 1454 unsigned int clk_mplls_count; 1455 struct meson_clk_pll *const *clk_plls; 1456 unsigned int clk_plls_count; 1457 struct clk_mux *const *clk_muxes; 1458 unsigned int clk_muxes_count; 1459 struct clk_divider *const *clk_dividers; 1460 unsigned int clk_dividers_count; 1461 struct meson_clk_audio_divider *const *clk_audio_dividers; 1462 unsigned int clk_audio_dividers_count; 1463 struct clk_hw_onecell_data *hw_onecell_data; 1464 }; 1465 1466 static const struct clkc_data gxbb_clkc_data = { 1467 .clk_gates = gxbb_clk_gates, 1468 .clk_gates_count = ARRAY_SIZE(gxbb_clk_gates), 1469 .clk_mplls = gxbb_clk_mplls, 1470 .clk_mplls_count = ARRAY_SIZE(gxbb_clk_mplls), 1471 .clk_plls = gxbb_clk_plls, 1472 .clk_plls_count = ARRAY_SIZE(gxbb_clk_plls), 1473 .clk_muxes = gxbb_clk_muxes, 1474 .clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes), 1475 .clk_dividers = gxbb_clk_dividers, 1476 .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers), 1477 .clk_audio_dividers = gxbb_audio_dividers, 1478 .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers), 1479 .hw_onecell_data = &gxbb_hw_onecell_data, 1480 }; 1481 1482 static const struct clkc_data gxl_clkc_data = { 1483 .clk_gates = gxbb_clk_gates, 1484 .clk_gates_count = ARRAY_SIZE(gxbb_clk_gates), 1485 .clk_mplls = gxbb_clk_mplls, 1486 .clk_mplls_count = ARRAY_SIZE(gxbb_clk_mplls), 1487 .clk_plls = gxl_clk_plls, 1488 .clk_plls_count = ARRAY_SIZE(gxl_clk_plls), 1489 .clk_muxes = gxbb_clk_muxes, 1490 .clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes), 1491 .clk_dividers = gxbb_clk_dividers, 1492 .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers), 1493 .clk_audio_dividers = gxbb_audio_dividers, 1494 .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers), 1495 .hw_onecell_data = &gxl_hw_onecell_data, 1496 }; 1497 1498 static const struct of_device_id clkc_match_table[] = { 1499 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data }, 1500 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data }, 1501 {}, 1502 }; 1503 1504 static int gxbb_clkc_probe(struct platform_device *pdev) 1505 { 1506 const struct clkc_data *clkc_data; 1507 void __iomem *clk_base; 1508 int ret, clkid, i; 1509 struct device *dev = &pdev->dev; 1510 1511 clkc_data = of_device_get_match_data(&pdev->dev); 1512 if (!clkc_data) 1513 return -EINVAL; 1514 1515 /* Generic clocks and PLLs */ 1516 clk_base = of_iomap(dev->of_node, 0); 1517 if (!clk_base) { 1518 pr_err("%s: Unable to map clk base\n", __func__); 1519 return -ENXIO; 1520 } 1521 1522 /* Populate base address for PLLs */ 1523 for (i = 0; i < clkc_data->clk_plls_count; i++) 1524 clkc_data->clk_plls[i]->base = clk_base; 1525 1526 /* Populate base address for MPLLs */ 1527 for (i = 0; i < clkc_data->clk_mplls_count; i++) 1528 clkc_data->clk_mplls[i]->base = clk_base; 1529 1530 /* Populate base address for gates */ 1531 for (i = 0; i < clkc_data->clk_gates_count; i++) 1532 clkc_data->clk_gates[i]->reg = clk_base + 1533 (u64)clkc_data->clk_gates[i]->reg; 1534 1535 /* Populate base address for muxes */ 1536 for (i = 0; i < clkc_data->clk_muxes_count; i++) 1537 clkc_data->clk_muxes[i]->reg = clk_base + 1538 (u64)clkc_data->clk_muxes[i]->reg; 1539 1540 /* Populate base address for dividers */ 1541 for (i = 0; i < clkc_data->clk_dividers_count; i++) 1542 clkc_data->clk_dividers[i]->reg = clk_base + 1543 (u64)clkc_data->clk_dividers[i]->reg; 1544 1545 /* Populate base address for the audio dividers */ 1546 for (i = 0; i < clkc_data->clk_audio_dividers_count; i++) 1547 clkc_data->clk_audio_dividers[i]->base = clk_base; 1548 1549 /* 1550 * register all clks 1551 */ 1552 for (clkid = 0; clkid < clkc_data->hw_onecell_data->num; clkid++) { 1553 /* array might be sparse */ 1554 if (!clkc_data->hw_onecell_data->hws[clkid]) 1555 continue; 1556 1557 ret = devm_clk_hw_register(dev, 1558 clkc_data->hw_onecell_data->hws[clkid]); 1559 if (ret) 1560 goto iounmap; 1561 } 1562 1563 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, 1564 clkc_data->hw_onecell_data); 1565 1566 iounmap: 1567 iounmap(clk_base); 1568 return ret; 1569 } 1570 1571 static struct platform_driver gxbb_driver = { 1572 .probe = gxbb_clkc_probe, 1573 .driver = { 1574 .name = "gxbb-clkc", 1575 .of_match_table = clkc_match_table, 1576 }, 1577 }; 1578 1579 builtin_platform_driver(gxbb_driver); 1580