xref: /linux/drivers/clk/meson/gxbb.c (revision b60a5b8dcf49af9f2c60ae82e0383ee8e62a9a52)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2016 AmLogic, Inc.
4  * Michael Turquette <mturquette@baylibre.com>
5  */
6 
7 #include <linux/clk-provider.h>
8 #include <linux/init.h>
9 #include <linux/of_device.h>
10 #include <linux/platform_device.h>
11 
12 #include "gxbb.h"
13 #include "clk-input.h"
14 #include "clk-regmap.h"
15 #include "clk-pll.h"
16 #include "clk-mpll.h"
17 #include "meson-eeclk.h"
18 #include "vid-pll-div.h"
19 
20 #define IN_PREFIX "ee-in-"
21 
22 static DEFINE_SPINLOCK(meson_clk_lock);
23 
24 static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
25 	PLL_PARAMS(32, 1),
26 	PLL_PARAMS(33, 1),
27 	PLL_PARAMS(34, 1),
28 	PLL_PARAMS(35, 1),
29 	PLL_PARAMS(36, 1),
30 	PLL_PARAMS(37, 1),
31 	PLL_PARAMS(38, 1),
32 	PLL_PARAMS(39, 1),
33 	PLL_PARAMS(40, 1),
34 	PLL_PARAMS(41, 1),
35 	PLL_PARAMS(42, 1),
36 	PLL_PARAMS(43, 1),
37 	PLL_PARAMS(44, 1),
38 	PLL_PARAMS(45, 1),
39 	PLL_PARAMS(46, 1),
40 	PLL_PARAMS(47, 1),
41 	PLL_PARAMS(48, 1),
42 	PLL_PARAMS(49, 1),
43 	PLL_PARAMS(50, 1),
44 	PLL_PARAMS(51, 1),
45 	PLL_PARAMS(52, 1),
46 	PLL_PARAMS(53, 1),
47 	PLL_PARAMS(54, 1),
48 	PLL_PARAMS(55, 1),
49 	PLL_PARAMS(56, 1),
50 	PLL_PARAMS(57, 1),
51 	PLL_PARAMS(58, 1),
52 	PLL_PARAMS(59, 1),
53 	PLL_PARAMS(60, 1),
54 	PLL_PARAMS(61, 1),
55 	PLL_PARAMS(62, 1),
56 	{ /* sentinel */ },
57 };
58 
59 static const struct pll_params_table gxl_gp0_pll_params_table[] = {
60 	PLL_PARAMS(42, 1),
61 	PLL_PARAMS(43, 1),
62 	PLL_PARAMS(44, 1),
63 	PLL_PARAMS(45, 1),
64 	PLL_PARAMS(46, 1),
65 	PLL_PARAMS(47, 1),
66 	PLL_PARAMS(48, 1),
67 	PLL_PARAMS(49, 1),
68 	PLL_PARAMS(50, 1),
69 	PLL_PARAMS(51, 1),
70 	PLL_PARAMS(52, 1),
71 	PLL_PARAMS(53, 1),
72 	PLL_PARAMS(54, 1),
73 	PLL_PARAMS(55, 1),
74 	PLL_PARAMS(56, 1),
75 	PLL_PARAMS(57, 1),
76 	PLL_PARAMS(58, 1),
77 	PLL_PARAMS(59, 1),
78 	PLL_PARAMS(60, 1),
79 	PLL_PARAMS(61, 1),
80 	PLL_PARAMS(62, 1),
81 	PLL_PARAMS(63, 1),
82 	PLL_PARAMS(64, 1),
83 	PLL_PARAMS(65, 1),
84 	PLL_PARAMS(66, 1),
85 	{ /* sentinel */ },
86 };
87 
88 static struct clk_regmap gxbb_fixed_pll_dco = {
89 	.data = &(struct meson_clk_pll_data){
90 		.en = {
91 			.reg_off = HHI_MPLL_CNTL,
92 			.shift   = 30,
93 			.width   = 1,
94 		},
95 		.m = {
96 			.reg_off = HHI_MPLL_CNTL,
97 			.shift   = 0,
98 			.width   = 9,
99 		},
100 		.n = {
101 			.reg_off = HHI_MPLL_CNTL,
102 			.shift   = 9,
103 			.width   = 5,
104 		},
105 		.frac = {
106 			.reg_off = HHI_MPLL_CNTL2,
107 			.shift   = 0,
108 			.width   = 12,
109 		},
110 		.l = {
111 			.reg_off = HHI_MPLL_CNTL,
112 			.shift   = 31,
113 			.width   = 1,
114 		},
115 		.rst = {
116 			.reg_off = HHI_MPLL_CNTL,
117 			.shift   = 29,
118 			.width   = 1,
119 		},
120 	},
121 	.hw.init = &(struct clk_init_data){
122 		.name = "fixed_pll_dco",
123 		.ops = &meson_clk_pll_ro_ops,
124 		.parent_names = (const char *[]){ IN_PREFIX "xtal" },
125 		.num_parents = 1,
126 	},
127 };
128 
129 static struct clk_regmap gxbb_fixed_pll = {
130 	.data = &(struct clk_regmap_div_data){
131 		.offset = HHI_MPLL_CNTL,
132 		.shift = 16,
133 		.width = 2,
134 		.flags = CLK_DIVIDER_POWER_OF_TWO,
135 	},
136 	.hw.init = &(struct clk_init_data){
137 		.name = "fixed_pll",
138 		.ops = &clk_regmap_divider_ro_ops,
139 		.parent_names = (const char *[]){ "fixed_pll_dco" },
140 		.num_parents = 1,
141 		/*
142 		 * This clock won't ever change at runtime so
143 		 * CLK_SET_RATE_PARENT is not required
144 		 */
145 	},
146 };
147 
148 static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = {
149 	.mult = 2,
150 	.div = 1,
151 	.hw.init = &(struct clk_init_data){
152 		.name = "hdmi_pll_pre_mult",
153 		.ops = &clk_fixed_factor_ops,
154 		.parent_names = (const char *[]){ IN_PREFIX "xtal" },
155 		.num_parents = 1,
156 	},
157 };
158 
159 static struct clk_regmap gxbb_hdmi_pll_dco = {
160 	.data = &(struct meson_clk_pll_data){
161 		.en = {
162 			.reg_off = HHI_HDMI_PLL_CNTL,
163 			.shift   = 30,
164 			.width   = 1,
165 		},
166 		.m = {
167 			.reg_off = HHI_HDMI_PLL_CNTL,
168 			.shift   = 0,
169 			.width   = 9,
170 		},
171 		.n = {
172 			.reg_off = HHI_HDMI_PLL_CNTL,
173 			.shift   = 9,
174 			.width   = 5,
175 		},
176 		.frac = {
177 			.reg_off = HHI_HDMI_PLL_CNTL2,
178 			.shift   = 0,
179 			.width   = 12,
180 		},
181 		.l = {
182 			.reg_off = HHI_HDMI_PLL_CNTL,
183 			.shift   = 31,
184 			.width   = 1,
185 		},
186 		.rst = {
187 			.reg_off = HHI_HDMI_PLL_CNTL,
188 			.shift   = 28,
189 			.width   = 1,
190 		},
191 	},
192 	.hw.init = &(struct clk_init_data){
193 		.name = "hdmi_pll_dco",
194 		.ops = &meson_clk_pll_ro_ops,
195 		.parent_names = (const char *[]){ "hdmi_pll_pre_mult" },
196 		.num_parents = 1,
197 		/*
198 		 * Display directly handle hdmi pll registers ATM, we need
199 		 * NOCACHE to keep our view of the clock as accurate as possible
200 		 */
201 		.flags = CLK_GET_RATE_NOCACHE,
202 	},
203 };
204 
205 static struct clk_regmap gxl_hdmi_pll_dco = {
206 	.data = &(struct meson_clk_pll_data){
207 		.en = {
208 			.reg_off = HHI_HDMI_PLL_CNTL,
209 			.shift   = 30,
210 			.width   = 1,
211 		},
212 		.m = {
213 			.reg_off = HHI_HDMI_PLL_CNTL,
214 			.shift   = 0,
215 			.width   = 9,
216 		},
217 		.n = {
218 			.reg_off = HHI_HDMI_PLL_CNTL,
219 			.shift   = 9,
220 			.width   = 5,
221 		},
222 		/*
223 		 * On gxl, there is a register shift due to
224 		 * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
225 		 * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB
226 		 * instead which is defined at the same offset.
227 		 */
228 		.frac = {
229 			.reg_off = HHI_HDMI_PLL_CNTL2,
230 			.shift   = 0,
231 			.width   = 10,
232 		},
233 		.l = {
234 			.reg_off = HHI_HDMI_PLL_CNTL,
235 			.shift   = 31,
236 			.width   = 1,
237 		},
238 		.rst = {
239 			.reg_off = HHI_HDMI_PLL_CNTL,
240 			.shift   = 28,
241 			.width   = 1,
242 		},
243 	},
244 	.hw.init = &(struct clk_init_data){
245 		.name = "hdmi_pll_dco",
246 		.ops = &meson_clk_pll_ro_ops,
247 		.parent_names = (const char *[]){ IN_PREFIX "xtal" },
248 		.num_parents = 1,
249 		/*
250 		 * Display directly handle hdmi pll registers ATM, we need
251 		 * NOCACHE to keep our view of the clock as accurate as possible
252 		 */
253 		.flags = CLK_GET_RATE_NOCACHE,
254 	},
255 };
256 
257 static struct clk_regmap gxbb_hdmi_pll_od = {
258 	.data = &(struct clk_regmap_div_data){
259 		.offset = HHI_HDMI_PLL_CNTL2,
260 		.shift = 16,
261 		.width = 2,
262 		.flags = CLK_DIVIDER_POWER_OF_TWO,
263 	},
264 	.hw.init = &(struct clk_init_data){
265 		.name = "hdmi_pll_od",
266 		.ops = &clk_regmap_divider_ro_ops,
267 		.parent_names = (const char *[]){ "hdmi_pll_dco" },
268 		.num_parents = 1,
269 		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
270 	},
271 };
272 
273 static struct clk_regmap gxbb_hdmi_pll_od2 = {
274 	.data = &(struct clk_regmap_div_data){
275 		.offset = HHI_HDMI_PLL_CNTL2,
276 		.shift = 22,
277 		.width = 2,
278 		.flags = CLK_DIVIDER_POWER_OF_TWO,
279 	},
280 	.hw.init = &(struct clk_init_data){
281 		.name = "hdmi_pll_od2",
282 		.ops = &clk_regmap_divider_ro_ops,
283 		.parent_names = (const char *[]){ "hdmi_pll_od" },
284 		.num_parents = 1,
285 		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
286 	},
287 };
288 
289 static struct clk_regmap gxbb_hdmi_pll = {
290 	.data = &(struct clk_regmap_div_data){
291 		.offset = HHI_HDMI_PLL_CNTL2,
292 		.shift = 18,
293 		.width = 2,
294 		.flags = CLK_DIVIDER_POWER_OF_TWO,
295 	},
296 	.hw.init = &(struct clk_init_data){
297 		.name = "hdmi_pll",
298 		.ops = &clk_regmap_divider_ro_ops,
299 		.parent_names = (const char *[]){ "hdmi_pll_od2" },
300 		.num_parents = 1,
301 		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
302 	},
303 };
304 
305 static struct clk_regmap gxl_hdmi_pll_od = {
306 	.data = &(struct clk_regmap_div_data){
307 		.offset = HHI_HDMI_PLL_CNTL + 8,
308 		.shift = 21,
309 		.width = 2,
310 		.flags = CLK_DIVIDER_POWER_OF_TWO,
311 	},
312 	.hw.init = &(struct clk_init_data){
313 		.name = "hdmi_pll_od",
314 		.ops = &clk_regmap_divider_ro_ops,
315 		.parent_names = (const char *[]){ "hdmi_pll_dco" },
316 		.num_parents = 1,
317 		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
318 	},
319 };
320 
321 static struct clk_regmap gxl_hdmi_pll_od2 = {
322 	.data = &(struct clk_regmap_div_data){
323 		.offset = HHI_HDMI_PLL_CNTL + 8,
324 		.shift = 23,
325 		.width = 2,
326 		.flags = CLK_DIVIDER_POWER_OF_TWO,
327 	},
328 	.hw.init = &(struct clk_init_data){
329 		.name = "hdmi_pll_od2",
330 		.ops = &clk_regmap_divider_ro_ops,
331 		.parent_names = (const char *[]){ "hdmi_pll_od" },
332 		.num_parents = 1,
333 		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
334 	},
335 };
336 
337 static struct clk_regmap gxl_hdmi_pll = {
338 	.data = &(struct clk_regmap_div_data){
339 		.offset = HHI_HDMI_PLL_CNTL + 8,
340 		.shift = 19,
341 		.width = 2,
342 		.flags = CLK_DIVIDER_POWER_OF_TWO,
343 	},
344 	.hw.init = &(struct clk_init_data){
345 		.name = "hdmi_pll",
346 		.ops = &clk_regmap_divider_ro_ops,
347 		.parent_names = (const char *[]){ "hdmi_pll_od2" },
348 		.num_parents = 1,
349 		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
350 	},
351 };
352 
353 static struct clk_regmap gxbb_sys_pll_dco = {
354 	.data = &(struct meson_clk_pll_data){
355 		.en = {
356 			.reg_off = HHI_SYS_PLL_CNTL,
357 			.shift   = 30,
358 			.width   = 1,
359 		},
360 		.m = {
361 			.reg_off = HHI_SYS_PLL_CNTL,
362 			.shift   = 0,
363 			.width   = 9,
364 		},
365 		.n = {
366 			.reg_off = HHI_SYS_PLL_CNTL,
367 			.shift   = 9,
368 			.width   = 5,
369 		},
370 		.l = {
371 			.reg_off = HHI_SYS_PLL_CNTL,
372 			.shift   = 31,
373 			.width   = 1,
374 		},
375 		.rst = {
376 			.reg_off = HHI_SYS_PLL_CNTL,
377 			.shift   = 29,
378 			.width   = 1,
379 		},
380 	},
381 	.hw.init = &(struct clk_init_data){
382 		.name = "sys_pll_dco",
383 		.ops = &meson_clk_pll_ro_ops,
384 		.parent_names = (const char *[]){ IN_PREFIX "xtal" },
385 		.num_parents = 1,
386 	},
387 };
388 
389 static struct clk_regmap gxbb_sys_pll = {
390 	.data = &(struct clk_regmap_div_data){
391 		.offset = HHI_SYS_PLL_CNTL,
392 		.shift = 10,
393 		.width = 2,
394 		.flags = CLK_DIVIDER_POWER_OF_TWO,
395 	},
396 	.hw.init = &(struct clk_init_data){
397 		.name = "sys_pll",
398 		.ops = &clk_regmap_divider_ro_ops,
399 		.parent_names = (const char *[]){ "sys_pll_dco" },
400 		.num_parents = 1,
401 		.flags = CLK_SET_RATE_PARENT,
402 	},
403 };
404 
405 static const struct reg_sequence gxbb_gp0_init_regs[] = {
406 	{ .reg = HHI_GP0_PLL_CNTL2,	.def = 0x69c80000 },
407 	{ .reg = HHI_GP0_PLL_CNTL3,	.def = 0x0a5590c4 },
408 	{ .reg = HHI_GP0_PLL_CNTL4,	.def = 0x0000500d },
409 };
410 
411 static struct clk_regmap gxbb_gp0_pll_dco = {
412 	.data = &(struct meson_clk_pll_data){
413 		.en = {
414 			.reg_off = HHI_GP0_PLL_CNTL,
415 			.shift   = 30,
416 			.width   = 1,
417 		},
418 		.m = {
419 			.reg_off = HHI_GP0_PLL_CNTL,
420 			.shift   = 0,
421 			.width   = 9,
422 		},
423 		.n = {
424 			.reg_off = HHI_GP0_PLL_CNTL,
425 			.shift   = 9,
426 			.width   = 5,
427 		},
428 		.l = {
429 			.reg_off = HHI_GP0_PLL_CNTL,
430 			.shift   = 31,
431 			.width   = 1,
432 		},
433 		.rst = {
434 			.reg_off = HHI_GP0_PLL_CNTL,
435 			.shift   = 29,
436 			.width   = 1,
437 		},
438 		.table = gxbb_gp0_pll_params_table,
439 		.init_regs = gxbb_gp0_init_regs,
440 		.init_count = ARRAY_SIZE(gxbb_gp0_init_regs),
441 	},
442 	.hw.init = &(struct clk_init_data){
443 		.name = "gp0_pll_dco",
444 		.ops = &meson_clk_pll_ops,
445 		.parent_names = (const char *[]){ IN_PREFIX "xtal" },
446 		.num_parents = 1,
447 	},
448 };
449 
450 static const struct reg_sequence gxl_gp0_init_regs[] = {
451 	{ .reg = HHI_GP0_PLL_CNTL1,	.def = 0xc084b000 },
452 	{ .reg = HHI_GP0_PLL_CNTL2,	.def = 0xb75020be },
453 	{ .reg = HHI_GP0_PLL_CNTL3,	.def = 0x0a59a288 },
454 	{ .reg = HHI_GP0_PLL_CNTL4,	.def = 0xc000004d },
455 	{ .reg = HHI_GP0_PLL_CNTL5,	.def = 0x00078000 },
456 };
457 
458 static struct clk_regmap gxl_gp0_pll_dco = {
459 	.data = &(struct meson_clk_pll_data){
460 		.en = {
461 			.reg_off = HHI_GP0_PLL_CNTL,
462 			.shift   = 30,
463 			.width   = 1,
464 		},
465 		.m = {
466 			.reg_off = HHI_GP0_PLL_CNTL,
467 			.shift   = 0,
468 			.width   = 9,
469 		},
470 		.n = {
471 			.reg_off = HHI_GP0_PLL_CNTL,
472 			.shift   = 9,
473 			.width   = 5,
474 		},
475 		.frac = {
476 			.reg_off = HHI_GP0_PLL_CNTL1,
477 			.shift   = 0,
478 			.width   = 10,
479 		},
480 		.l = {
481 			.reg_off = HHI_GP0_PLL_CNTL,
482 			.shift   = 31,
483 			.width   = 1,
484 		},
485 		.rst = {
486 			.reg_off = HHI_GP0_PLL_CNTL,
487 			.shift   = 29,
488 			.width   = 1,
489 		},
490 		.table = gxl_gp0_pll_params_table,
491 		.init_regs = gxl_gp0_init_regs,
492 		.init_count = ARRAY_SIZE(gxl_gp0_init_regs),
493 	},
494 	.hw.init = &(struct clk_init_data){
495 		.name = "gp0_pll_dco",
496 		.ops = &meson_clk_pll_ops,
497 		.parent_names = (const char *[]){ IN_PREFIX "xtal" },
498 		.num_parents = 1,
499 	},
500 };
501 
502 static struct clk_regmap gxbb_gp0_pll = {
503 	.data = &(struct clk_regmap_div_data){
504 		.offset = HHI_GP0_PLL_CNTL,
505 		.shift = 16,
506 		.width = 2,
507 		.flags = CLK_DIVIDER_POWER_OF_TWO,
508 	},
509 	.hw.init = &(struct clk_init_data){
510 		.name = "gp0_pll",
511 		.ops = &clk_regmap_divider_ops,
512 		.parent_names = (const char *[]){ "gp0_pll_dco" },
513 		.num_parents = 1,
514 		.flags = CLK_SET_RATE_PARENT,
515 	},
516 };
517 
518 static struct clk_fixed_factor gxbb_fclk_div2_div = {
519 	.mult = 1,
520 	.div = 2,
521 	.hw.init = &(struct clk_init_data){
522 		.name = "fclk_div2_div",
523 		.ops = &clk_fixed_factor_ops,
524 		.parent_names = (const char *[]){ "fixed_pll" },
525 		.num_parents = 1,
526 	},
527 };
528 
529 static struct clk_regmap gxbb_fclk_div2 = {
530 	.data = &(struct clk_regmap_gate_data){
531 		.offset = HHI_MPLL_CNTL6,
532 		.bit_idx = 27,
533 	},
534 	.hw.init = &(struct clk_init_data){
535 		.name = "fclk_div2",
536 		.ops = &clk_regmap_gate_ops,
537 		.parent_names = (const char *[]){ "fclk_div2_div" },
538 		.num_parents = 1,
539 		.flags = CLK_IS_CRITICAL,
540 	},
541 };
542 
543 static struct clk_fixed_factor gxbb_fclk_div3_div = {
544 	.mult = 1,
545 	.div = 3,
546 	.hw.init = &(struct clk_init_data){
547 		.name = "fclk_div3_div",
548 		.ops = &clk_fixed_factor_ops,
549 		.parent_names = (const char *[]){ "fixed_pll" },
550 		.num_parents = 1,
551 	},
552 };
553 
554 static struct clk_regmap gxbb_fclk_div3 = {
555 	.data = &(struct clk_regmap_gate_data){
556 		.offset = HHI_MPLL_CNTL6,
557 		.bit_idx = 28,
558 	},
559 	.hw.init = &(struct clk_init_data){
560 		.name = "fclk_div3",
561 		.ops = &clk_regmap_gate_ops,
562 		.parent_names = (const char *[]){ "fclk_div3_div" },
563 		.num_parents = 1,
564 		/*
565 		 * FIXME:
566 		 * This clock, as fdiv2, is used by the SCPI FW and is required
567 		 * by the platform to operate correctly.
568 		 * Until the following condition are met, we need this clock to
569 		 * be marked as critical:
570 		 * a) The SCPI generic driver claims and enable all the clocks
571 		 *    it needs
572 		 * b) CCF has a clock hand-off mechanism to make the sure the
573 		 *    clock stays on until the proper driver comes along
574 		 */
575 		.flags = CLK_IS_CRITICAL,
576 	},
577 };
578 
579 static struct clk_fixed_factor gxbb_fclk_div4_div = {
580 	.mult = 1,
581 	.div = 4,
582 	.hw.init = &(struct clk_init_data){
583 		.name = "fclk_div4_div",
584 		.ops = &clk_fixed_factor_ops,
585 		.parent_names = (const char *[]){ "fixed_pll" },
586 		.num_parents = 1,
587 	},
588 };
589 
590 static struct clk_regmap gxbb_fclk_div4 = {
591 	.data = &(struct clk_regmap_gate_data){
592 		.offset = HHI_MPLL_CNTL6,
593 		.bit_idx = 29,
594 	},
595 	.hw.init = &(struct clk_init_data){
596 		.name = "fclk_div4",
597 		.ops = &clk_regmap_gate_ops,
598 		.parent_names = (const char *[]){ "fclk_div4_div" },
599 		.num_parents = 1,
600 	},
601 };
602 
603 static struct clk_fixed_factor gxbb_fclk_div5_div = {
604 	.mult = 1,
605 	.div = 5,
606 	.hw.init = &(struct clk_init_data){
607 		.name = "fclk_div5_div",
608 		.ops = &clk_fixed_factor_ops,
609 		.parent_names = (const char *[]){ "fixed_pll" },
610 		.num_parents = 1,
611 	},
612 };
613 
614 static struct clk_regmap gxbb_fclk_div5 = {
615 	.data = &(struct clk_regmap_gate_data){
616 		.offset = HHI_MPLL_CNTL6,
617 		.bit_idx = 30,
618 	},
619 	.hw.init = &(struct clk_init_data){
620 		.name = "fclk_div5",
621 		.ops = &clk_regmap_gate_ops,
622 		.parent_names = (const char *[]){ "fclk_div5_div" },
623 		.num_parents = 1,
624 	},
625 };
626 
627 static struct clk_fixed_factor gxbb_fclk_div7_div = {
628 	.mult = 1,
629 	.div = 7,
630 	.hw.init = &(struct clk_init_data){
631 		.name = "fclk_div7_div",
632 		.ops = &clk_fixed_factor_ops,
633 		.parent_names = (const char *[]){ "fixed_pll" },
634 		.num_parents = 1,
635 	},
636 };
637 
638 static struct clk_regmap gxbb_fclk_div7 = {
639 	.data = &(struct clk_regmap_gate_data){
640 		.offset = HHI_MPLL_CNTL6,
641 		.bit_idx = 31,
642 	},
643 	.hw.init = &(struct clk_init_data){
644 		.name = "fclk_div7",
645 		.ops = &clk_regmap_gate_ops,
646 		.parent_names = (const char *[]){ "fclk_div7_div" },
647 		.num_parents = 1,
648 	},
649 };
650 
651 static struct clk_regmap gxbb_mpll_prediv = {
652 	.data = &(struct clk_regmap_div_data){
653 		.offset = HHI_MPLL_CNTL5,
654 		.shift = 12,
655 		.width = 1,
656 	},
657 	.hw.init = &(struct clk_init_data){
658 		.name = "mpll_prediv",
659 		.ops = &clk_regmap_divider_ro_ops,
660 		.parent_names = (const char *[]){ "fixed_pll" },
661 		.num_parents = 1,
662 	},
663 };
664 
665 static struct clk_regmap gxbb_mpll0_div = {
666 	.data = &(struct meson_clk_mpll_data){
667 		.sdm = {
668 			.reg_off = HHI_MPLL_CNTL7,
669 			.shift   = 0,
670 			.width   = 14,
671 		},
672 		.sdm_en = {
673 			.reg_off = HHI_MPLL_CNTL7,
674 			.shift   = 15,
675 			.width	 = 1,
676 		},
677 		.n2 = {
678 			.reg_off = HHI_MPLL_CNTL7,
679 			.shift   = 16,
680 			.width   = 9,
681 		},
682 		.ssen = {
683 			.reg_off = HHI_MPLL_CNTL,
684 			.shift   = 25,
685 			.width	 = 1,
686 		},
687 		.lock = &meson_clk_lock,
688 	},
689 	.hw.init = &(struct clk_init_data){
690 		.name = "mpll0_div",
691 		.ops = &meson_clk_mpll_ops,
692 		.parent_names = (const char *[]){ "mpll_prediv" },
693 		.num_parents = 1,
694 	},
695 };
696 
697 static struct clk_regmap gxbb_mpll0 = {
698 	.data = &(struct clk_regmap_gate_data){
699 		.offset = HHI_MPLL_CNTL7,
700 		.bit_idx = 14,
701 	},
702 	.hw.init = &(struct clk_init_data){
703 		.name = "mpll0",
704 		.ops = &clk_regmap_gate_ops,
705 		.parent_names = (const char *[]){ "mpll0_div" },
706 		.num_parents = 1,
707 		.flags = CLK_SET_RATE_PARENT,
708 	},
709 };
710 
711 static struct clk_regmap gxbb_mpll1_div = {
712 	.data = &(struct meson_clk_mpll_data){
713 		.sdm = {
714 			.reg_off = HHI_MPLL_CNTL8,
715 			.shift   = 0,
716 			.width   = 14,
717 		},
718 		.sdm_en = {
719 			.reg_off = HHI_MPLL_CNTL8,
720 			.shift   = 15,
721 			.width	 = 1,
722 		},
723 		.n2 = {
724 			.reg_off = HHI_MPLL_CNTL8,
725 			.shift   = 16,
726 			.width   = 9,
727 		},
728 		.lock = &meson_clk_lock,
729 	},
730 	.hw.init = &(struct clk_init_data){
731 		.name = "mpll1_div",
732 		.ops = &meson_clk_mpll_ops,
733 		.parent_names = (const char *[]){ "mpll_prediv" },
734 		.num_parents = 1,
735 	},
736 };
737 
738 static struct clk_regmap gxbb_mpll1 = {
739 	.data = &(struct clk_regmap_gate_data){
740 		.offset = HHI_MPLL_CNTL8,
741 		.bit_idx = 14,
742 	},
743 	.hw.init = &(struct clk_init_data){
744 		.name = "mpll1",
745 		.ops = &clk_regmap_gate_ops,
746 		.parent_names = (const char *[]){ "mpll1_div" },
747 		.num_parents = 1,
748 		.flags = CLK_SET_RATE_PARENT,
749 	},
750 };
751 
752 static struct clk_regmap gxbb_mpll2_div = {
753 	.data = &(struct meson_clk_mpll_data){
754 		.sdm = {
755 			.reg_off = HHI_MPLL_CNTL9,
756 			.shift   = 0,
757 			.width   = 14,
758 		},
759 		.sdm_en = {
760 			.reg_off = HHI_MPLL_CNTL9,
761 			.shift   = 15,
762 			.width	 = 1,
763 		},
764 		.n2 = {
765 			.reg_off = HHI_MPLL_CNTL9,
766 			.shift   = 16,
767 			.width   = 9,
768 		},
769 		.lock = &meson_clk_lock,
770 	},
771 	.hw.init = &(struct clk_init_data){
772 		.name = "mpll2_div",
773 		.ops = &meson_clk_mpll_ops,
774 		.parent_names = (const char *[]){ "mpll_prediv" },
775 		.num_parents = 1,
776 	},
777 };
778 
779 static struct clk_regmap gxbb_mpll2 = {
780 	.data = &(struct clk_regmap_gate_data){
781 		.offset = HHI_MPLL_CNTL9,
782 		.bit_idx = 14,
783 	},
784 	.hw.init = &(struct clk_init_data){
785 		.name = "mpll2",
786 		.ops = &clk_regmap_gate_ops,
787 		.parent_names = (const char *[]){ "mpll2_div" },
788 		.num_parents = 1,
789 		.flags = CLK_SET_RATE_PARENT,
790 	},
791 };
792 
793 static u32 mux_table_clk81[]	= { 0, 2, 3, 4, 5, 6, 7 };
794 static const char * const clk81_parent_names[] = {
795 	IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
796 	"fclk_div3", "fclk_div5"
797 };
798 
799 static struct clk_regmap gxbb_mpeg_clk_sel = {
800 	.data = &(struct clk_regmap_mux_data){
801 		.offset = HHI_MPEG_CLK_CNTL,
802 		.mask = 0x7,
803 		.shift = 12,
804 		.table = mux_table_clk81,
805 	},
806 	.hw.init = &(struct clk_init_data){
807 		.name = "mpeg_clk_sel",
808 		.ops = &clk_regmap_mux_ro_ops,
809 		/*
810 		 * bits 14:12 selects from 8 possible parents:
811 		 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
812 		 * fclk_div4, fclk_div3, fclk_div5
813 		 */
814 		.parent_names = clk81_parent_names,
815 		.num_parents = ARRAY_SIZE(clk81_parent_names),
816 	},
817 };
818 
819 static struct clk_regmap gxbb_mpeg_clk_div = {
820 	.data = &(struct clk_regmap_div_data){
821 		.offset = HHI_MPEG_CLK_CNTL,
822 		.shift = 0,
823 		.width = 7,
824 	},
825 	.hw.init = &(struct clk_init_data){
826 		.name = "mpeg_clk_div",
827 		.ops = &clk_regmap_divider_ro_ops,
828 		.parent_names = (const char *[]){ "mpeg_clk_sel" },
829 		.num_parents = 1,
830 	},
831 };
832 
833 /* the mother of dragons gates */
834 static struct clk_regmap gxbb_clk81 = {
835 	.data = &(struct clk_regmap_gate_data){
836 		.offset = HHI_MPEG_CLK_CNTL,
837 		.bit_idx = 7,
838 	},
839 	.hw.init = &(struct clk_init_data){
840 		.name = "clk81",
841 		.ops = &clk_regmap_gate_ops,
842 		.parent_names = (const char *[]){ "mpeg_clk_div" },
843 		.num_parents = 1,
844 		.flags = CLK_IS_CRITICAL,
845 	},
846 };
847 
848 static struct clk_regmap gxbb_sar_adc_clk_sel = {
849 	.data = &(struct clk_regmap_mux_data){
850 		.offset = HHI_SAR_CLK_CNTL,
851 		.mask = 0x3,
852 		.shift = 9,
853 	},
854 	.hw.init = &(struct clk_init_data){
855 		.name = "sar_adc_clk_sel",
856 		.ops = &clk_regmap_mux_ops,
857 		/* NOTE: The datasheet doesn't list the parents for bit 10 */
858 		.parent_names = (const char *[]){ IN_PREFIX "xtal", "clk81", },
859 		.num_parents = 2,
860 	},
861 };
862 
863 static struct clk_regmap gxbb_sar_adc_clk_div = {
864 	.data = &(struct clk_regmap_div_data){
865 		.offset = HHI_SAR_CLK_CNTL,
866 		.shift = 0,
867 		.width = 8,
868 	},
869 	.hw.init = &(struct clk_init_data){
870 		.name = "sar_adc_clk_div",
871 		.ops = &clk_regmap_divider_ops,
872 		.parent_names = (const char *[]){ "sar_adc_clk_sel" },
873 		.num_parents = 1,
874 	},
875 };
876 
877 static struct clk_regmap gxbb_sar_adc_clk = {
878 	.data = &(struct clk_regmap_gate_data){
879 		.offset = HHI_SAR_CLK_CNTL,
880 		.bit_idx = 8,
881 	},
882 	.hw.init = &(struct clk_init_data){
883 		.name = "sar_adc_clk",
884 		.ops = &clk_regmap_gate_ops,
885 		.parent_names = (const char *[]){ "sar_adc_clk_div" },
886 		.num_parents = 1,
887 		.flags = CLK_SET_RATE_PARENT,
888 	},
889 };
890 
891 /*
892  * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
893  * muxed by a glitch-free switch.
894  */
895 
896 static const char * const gxbb_mali_0_1_parent_names[] = {
897 	IN_PREFIX "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
898 	"fclk_div4", "fclk_div3", "fclk_div5"
899 };
900 
901 static struct clk_regmap gxbb_mali_0_sel = {
902 	.data = &(struct clk_regmap_mux_data){
903 		.offset = HHI_MALI_CLK_CNTL,
904 		.mask = 0x7,
905 		.shift = 9,
906 	},
907 	.hw.init = &(struct clk_init_data){
908 		.name = "mali_0_sel",
909 		.ops = &clk_regmap_mux_ops,
910 		/*
911 		 * bits 10:9 selects from 8 possible parents:
912 		 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
913 		 * fclk_div4, fclk_div3, fclk_div5
914 		 */
915 		.parent_names = gxbb_mali_0_1_parent_names,
916 		.num_parents = 8,
917 		.flags = CLK_SET_RATE_NO_REPARENT,
918 	},
919 };
920 
921 static struct clk_regmap gxbb_mali_0_div = {
922 	.data = &(struct clk_regmap_div_data){
923 		.offset = HHI_MALI_CLK_CNTL,
924 		.shift = 0,
925 		.width = 7,
926 	},
927 	.hw.init = &(struct clk_init_data){
928 		.name = "mali_0_div",
929 		.ops = &clk_regmap_divider_ops,
930 		.parent_names = (const char *[]){ "mali_0_sel" },
931 		.num_parents = 1,
932 		.flags = CLK_SET_RATE_NO_REPARENT,
933 	},
934 };
935 
936 static struct clk_regmap gxbb_mali_0 = {
937 	.data = &(struct clk_regmap_gate_data){
938 		.offset = HHI_MALI_CLK_CNTL,
939 		.bit_idx = 8,
940 	},
941 	.hw.init = &(struct clk_init_data){
942 		.name = "mali_0",
943 		.ops = &clk_regmap_gate_ops,
944 		.parent_names = (const char *[]){ "mali_0_div" },
945 		.num_parents = 1,
946 		.flags = CLK_SET_RATE_PARENT,
947 	},
948 };
949 
950 static struct clk_regmap gxbb_mali_1_sel = {
951 	.data = &(struct clk_regmap_mux_data){
952 		.offset = HHI_MALI_CLK_CNTL,
953 		.mask = 0x7,
954 		.shift = 25,
955 	},
956 	.hw.init = &(struct clk_init_data){
957 		.name = "mali_1_sel",
958 		.ops = &clk_regmap_mux_ops,
959 		/*
960 		 * bits 10:9 selects from 8 possible parents:
961 		 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
962 		 * fclk_div4, fclk_div3, fclk_div5
963 		 */
964 		.parent_names = gxbb_mali_0_1_parent_names,
965 		.num_parents = 8,
966 		.flags = CLK_SET_RATE_NO_REPARENT,
967 	},
968 };
969 
970 static struct clk_regmap gxbb_mali_1_div = {
971 	.data = &(struct clk_regmap_div_data){
972 		.offset = HHI_MALI_CLK_CNTL,
973 		.shift = 16,
974 		.width = 7,
975 	},
976 	.hw.init = &(struct clk_init_data){
977 		.name = "mali_1_div",
978 		.ops = &clk_regmap_divider_ops,
979 		.parent_names = (const char *[]){ "mali_1_sel" },
980 		.num_parents = 1,
981 		.flags = CLK_SET_RATE_NO_REPARENT,
982 	},
983 };
984 
985 static struct clk_regmap gxbb_mali_1 = {
986 	.data = &(struct clk_regmap_gate_data){
987 		.offset = HHI_MALI_CLK_CNTL,
988 		.bit_idx = 24,
989 	},
990 	.hw.init = &(struct clk_init_data){
991 		.name = "mali_1",
992 		.ops = &clk_regmap_gate_ops,
993 		.parent_names = (const char *[]){ "mali_1_div" },
994 		.num_parents = 1,
995 		.flags = CLK_SET_RATE_PARENT,
996 	},
997 };
998 
999 static const char * const gxbb_mali_parent_names[] = {
1000 	"mali_0", "mali_1"
1001 };
1002 
1003 static struct clk_regmap gxbb_mali = {
1004 	.data = &(struct clk_regmap_mux_data){
1005 		.offset = HHI_MALI_CLK_CNTL,
1006 		.mask = 1,
1007 		.shift = 31,
1008 	},
1009 	.hw.init = &(struct clk_init_data){
1010 		.name = "mali",
1011 		.ops = &clk_regmap_mux_ops,
1012 		.parent_names = gxbb_mali_parent_names,
1013 		.num_parents = 2,
1014 		.flags = CLK_SET_RATE_NO_REPARENT,
1015 	},
1016 };
1017 
1018 static struct clk_regmap gxbb_cts_amclk_sel = {
1019 	.data = &(struct clk_regmap_mux_data){
1020 		.offset = HHI_AUD_CLK_CNTL,
1021 		.mask = 0x3,
1022 		.shift = 9,
1023 		.table = (u32[]){ 1, 2, 3 },
1024 		.flags = CLK_MUX_ROUND_CLOSEST,
1025 	},
1026 	.hw.init = &(struct clk_init_data){
1027 		.name = "cts_amclk_sel",
1028 		.ops = &clk_regmap_mux_ops,
1029 		.parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
1030 		.num_parents = 3,
1031 	},
1032 };
1033 
1034 static struct clk_regmap gxbb_cts_amclk_div = {
1035 	.data = &(struct clk_regmap_div_data) {
1036 		.offset = HHI_AUD_CLK_CNTL,
1037 		.shift = 0,
1038 		.width = 8,
1039 		.flags = CLK_DIVIDER_ROUND_CLOSEST,
1040 	},
1041 	.hw.init = &(struct clk_init_data){
1042 		.name = "cts_amclk_div",
1043 		.ops = &clk_regmap_divider_ops,
1044 		.parent_names = (const char *[]){ "cts_amclk_sel" },
1045 		.num_parents = 1,
1046 		.flags = CLK_SET_RATE_PARENT,
1047 	},
1048 };
1049 
1050 static struct clk_regmap gxbb_cts_amclk = {
1051 	.data = &(struct clk_regmap_gate_data){
1052 		.offset = HHI_AUD_CLK_CNTL,
1053 		.bit_idx = 8,
1054 	},
1055 	.hw.init = &(struct clk_init_data){
1056 		.name = "cts_amclk",
1057 		.ops = &clk_regmap_gate_ops,
1058 		.parent_names = (const char *[]){ "cts_amclk_div" },
1059 		.num_parents = 1,
1060 		.flags = CLK_SET_RATE_PARENT,
1061 	},
1062 };
1063 
1064 static struct clk_regmap gxbb_cts_mclk_i958_sel = {
1065 	.data = &(struct clk_regmap_mux_data){
1066 		.offset = HHI_AUD_CLK_CNTL2,
1067 		.mask = 0x3,
1068 		.shift = 25,
1069 		.table = (u32[]){ 1, 2, 3 },
1070 		.flags = CLK_MUX_ROUND_CLOSEST,
1071 	},
1072 	.hw.init = &(struct clk_init_data) {
1073 		.name = "cts_mclk_i958_sel",
1074 		.ops = &clk_regmap_mux_ops,
1075 		.parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
1076 		.num_parents = 3,
1077 	},
1078 };
1079 
1080 static struct clk_regmap gxbb_cts_mclk_i958_div = {
1081 	.data = &(struct clk_regmap_div_data){
1082 		.offset = HHI_AUD_CLK_CNTL2,
1083 		.shift = 16,
1084 		.width = 8,
1085 		.flags = CLK_DIVIDER_ROUND_CLOSEST,
1086 	},
1087 	.hw.init = &(struct clk_init_data) {
1088 		.name = "cts_mclk_i958_div",
1089 		.ops = &clk_regmap_divider_ops,
1090 		.parent_names = (const char *[]){ "cts_mclk_i958_sel" },
1091 		.num_parents = 1,
1092 		.flags = CLK_SET_RATE_PARENT,
1093 	},
1094 };
1095 
1096 static struct clk_regmap gxbb_cts_mclk_i958 = {
1097 	.data = &(struct clk_regmap_gate_data){
1098 		.offset = HHI_AUD_CLK_CNTL2,
1099 		.bit_idx = 24,
1100 	},
1101 	.hw.init = &(struct clk_init_data){
1102 		.name = "cts_mclk_i958",
1103 		.ops = &clk_regmap_gate_ops,
1104 		.parent_names = (const char *[]){ "cts_mclk_i958_div" },
1105 		.num_parents = 1,
1106 		.flags = CLK_SET_RATE_PARENT,
1107 	},
1108 };
1109 
1110 static struct clk_regmap gxbb_cts_i958 = {
1111 	.data = &(struct clk_regmap_mux_data){
1112 		.offset = HHI_AUD_CLK_CNTL2,
1113 		.mask = 0x1,
1114 		.shift = 27,
1115 		},
1116 	.hw.init = &(struct clk_init_data){
1117 		.name = "cts_i958",
1118 		.ops = &clk_regmap_mux_ops,
1119 		.parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" },
1120 		.num_parents = 2,
1121 		/*
1122 		 *The parent is specific to origin of the audio data. Let the
1123 		 * consumer choose the appropriate parent
1124 		 */
1125 		.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1126 	},
1127 };
1128 
1129 static struct clk_regmap gxbb_32k_clk_div = {
1130 	.data = &(struct clk_regmap_div_data){
1131 		.offset = HHI_32K_CLK_CNTL,
1132 		.shift = 0,
1133 		.width = 14,
1134 	},
1135 	.hw.init = &(struct clk_init_data){
1136 		.name = "32k_clk_div",
1137 		.ops = &clk_regmap_divider_ops,
1138 		.parent_names = (const char *[]){ "32k_clk_sel" },
1139 		.num_parents = 1,
1140 		.flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
1141 	},
1142 };
1143 
1144 static struct clk_regmap gxbb_32k_clk = {
1145 	.data = &(struct clk_regmap_gate_data){
1146 		.offset = HHI_32K_CLK_CNTL,
1147 		.bit_idx = 15,
1148 	},
1149 	.hw.init = &(struct clk_init_data){
1150 		.name = "32k_clk",
1151 		.ops = &clk_regmap_gate_ops,
1152 		.parent_names = (const char *[]){ "32k_clk_div" },
1153 		.num_parents = 1,
1154 		.flags = CLK_SET_RATE_PARENT,
1155 	},
1156 };
1157 
1158 static const char * const gxbb_32k_clk_parent_names[] = {
1159 	IN_PREFIX "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5"
1160 };
1161 
1162 static struct clk_regmap gxbb_32k_clk_sel = {
1163 	.data = &(struct clk_regmap_mux_data){
1164 		.offset = HHI_32K_CLK_CNTL,
1165 		.mask = 0x3,
1166 		.shift = 16,
1167 		},
1168 	.hw.init = &(struct clk_init_data){
1169 		.name = "32k_clk_sel",
1170 		.ops = &clk_regmap_mux_ops,
1171 		.parent_names = gxbb_32k_clk_parent_names,
1172 		.num_parents = 4,
1173 		.flags = CLK_SET_RATE_PARENT,
1174 	},
1175 };
1176 
1177 static const char * const gxbb_sd_emmc_clk0_parent_names[] = {
1178 	IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
1179 
1180 	/*
1181 	 * Following these parent clocks, we should also have had mpll2, mpll3
1182 	 * and gp0_pll but these clocks are too precious to be used here. All
1183 	 * the necessary rates for MMC and NAND operation can be acheived using
1184 	 * xtal or fclk_div clocks
1185 	 */
1186 };
1187 
1188 /* SDIO clock */
1189 static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = {
1190 	.data = &(struct clk_regmap_mux_data){
1191 		.offset = HHI_SD_EMMC_CLK_CNTL,
1192 		.mask = 0x7,
1193 		.shift = 9,
1194 	},
1195 	.hw.init = &(struct clk_init_data) {
1196 		.name = "sd_emmc_a_clk0_sel",
1197 		.ops = &clk_regmap_mux_ops,
1198 		.parent_names = gxbb_sd_emmc_clk0_parent_names,
1199 		.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1200 		.flags = CLK_SET_RATE_PARENT,
1201 	},
1202 };
1203 
1204 static struct clk_regmap gxbb_sd_emmc_a_clk0_div = {
1205 	.data = &(struct clk_regmap_div_data){
1206 		.offset = HHI_SD_EMMC_CLK_CNTL,
1207 		.shift = 0,
1208 		.width = 7,
1209 		.flags = CLK_DIVIDER_ROUND_CLOSEST,
1210 	},
1211 	.hw.init = &(struct clk_init_data) {
1212 		.name = "sd_emmc_a_clk0_div",
1213 		.ops = &clk_regmap_divider_ops,
1214 		.parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" },
1215 		.num_parents = 1,
1216 		.flags = CLK_SET_RATE_PARENT,
1217 	},
1218 };
1219 
1220 static struct clk_regmap gxbb_sd_emmc_a_clk0 = {
1221 	.data = &(struct clk_regmap_gate_data){
1222 		.offset = HHI_SD_EMMC_CLK_CNTL,
1223 		.bit_idx = 7,
1224 	},
1225 	.hw.init = &(struct clk_init_data){
1226 		.name = "sd_emmc_a_clk0",
1227 		.ops = &clk_regmap_gate_ops,
1228 		.parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },
1229 		.num_parents = 1,
1230 		.flags = CLK_SET_RATE_PARENT,
1231 	},
1232 };
1233 
1234 /* SDcard clock */
1235 static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = {
1236 	.data = &(struct clk_regmap_mux_data){
1237 		.offset = HHI_SD_EMMC_CLK_CNTL,
1238 		.mask = 0x7,
1239 		.shift = 25,
1240 	},
1241 	.hw.init = &(struct clk_init_data) {
1242 		.name = "sd_emmc_b_clk0_sel",
1243 		.ops = &clk_regmap_mux_ops,
1244 		.parent_names = gxbb_sd_emmc_clk0_parent_names,
1245 		.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1246 		.flags = CLK_SET_RATE_PARENT,
1247 	},
1248 };
1249 
1250 static struct clk_regmap gxbb_sd_emmc_b_clk0_div = {
1251 	.data = &(struct clk_regmap_div_data){
1252 		.offset = HHI_SD_EMMC_CLK_CNTL,
1253 		.shift = 16,
1254 		.width = 7,
1255 		.flags = CLK_DIVIDER_ROUND_CLOSEST,
1256 	},
1257 	.hw.init = &(struct clk_init_data) {
1258 		.name = "sd_emmc_b_clk0_div",
1259 		.ops = &clk_regmap_divider_ops,
1260 		.parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
1261 		.num_parents = 1,
1262 		.flags = CLK_SET_RATE_PARENT,
1263 	},
1264 };
1265 
1266 static struct clk_regmap gxbb_sd_emmc_b_clk0 = {
1267 	.data = &(struct clk_regmap_gate_data){
1268 		.offset = HHI_SD_EMMC_CLK_CNTL,
1269 		.bit_idx = 23,
1270 	},
1271 	.hw.init = &(struct clk_init_data){
1272 		.name = "sd_emmc_b_clk0",
1273 		.ops = &clk_regmap_gate_ops,
1274 		.parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
1275 		.num_parents = 1,
1276 		.flags = CLK_SET_RATE_PARENT,
1277 	},
1278 };
1279 
1280 /* EMMC/NAND clock */
1281 static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = {
1282 	.data = &(struct clk_regmap_mux_data){
1283 		.offset = HHI_NAND_CLK_CNTL,
1284 		.mask = 0x7,
1285 		.shift = 9,
1286 	},
1287 	.hw.init = &(struct clk_init_data) {
1288 		.name = "sd_emmc_c_clk0_sel",
1289 		.ops = &clk_regmap_mux_ops,
1290 		.parent_names = gxbb_sd_emmc_clk0_parent_names,
1291 		.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1292 		.flags = CLK_SET_RATE_PARENT,
1293 	},
1294 };
1295 
1296 static struct clk_regmap gxbb_sd_emmc_c_clk0_div = {
1297 	.data = &(struct clk_regmap_div_data){
1298 		.offset = HHI_NAND_CLK_CNTL,
1299 		.shift = 0,
1300 		.width = 7,
1301 		.flags = CLK_DIVIDER_ROUND_CLOSEST,
1302 	},
1303 	.hw.init = &(struct clk_init_data) {
1304 		.name = "sd_emmc_c_clk0_div",
1305 		.ops = &clk_regmap_divider_ops,
1306 		.parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
1307 		.num_parents = 1,
1308 		.flags = CLK_SET_RATE_PARENT,
1309 	},
1310 };
1311 
1312 static struct clk_regmap gxbb_sd_emmc_c_clk0 = {
1313 	.data = &(struct clk_regmap_gate_data){
1314 		.offset = HHI_NAND_CLK_CNTL,
1315 		.bit_idx = 7,
1316 	},
1317 	.hw.init = &(struct clk_init_data){
1318 		.name = "sd_emmc_c_clk0",
1319 		.ops = &clk_regmap_gate_ops,
1320 		.parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
1321 		.num_parents = 1,
1322 		.flags = CLK_SET_RATE_PARENT,
1323 	},
1324 };
1325 
1326 /* VPU Clock */
1327 
1328 static const char * const gxbb_vpu_parent_names[] = {
1329 	"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1330 };
1331 
1332 static struct clk_regmap gxbb_vpu_0_sel = {
1333 	.data = &(struct clk_regmap_mux_data){
1334 		.offset = HHI_VPU_CLK_CNTL,
1335 		.mask = 0x3,
1336 		.shift = 9,
1337 	},
1338 	.hw.init = &(struct clk_init_data){
1339 		.name = "vpu_0_sel",
1340 		.ops = &clk_regmap_mux_ops,
1341 		/*
1342 		 * bits 9:10 selects from 4 possible parents:
1343 		 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1344 		 */
1345 		.parent_names = gxbb_vpu_parent_names,
1346 		.num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
1347 		.flags = CLK_SET_RATE_NO_REPARENT,
1348 	},
1349 };
1350 
1351 static struct clk_regmap gxbb_vpu_0_div = {
1352 	.data = &(struct clk_regmap_div_data){
1353 		.offset = HHI_VPU_CLK_CNTL,
1354 		.shift = 0,
1355 		.width = 7,
1356 	},
1357 	.hw.init = &(struct clk_init_data){
1358 		.name = "vpu_0_div",
1359 		.ops = &clk_regmap_divider_ops,
1360 		.parent_names = (const char *[]){ "vpu_0_sel" },
1361 		.num_parents = 1,
1362 		.flags = CLK_SET_RATE_PARENT,
1363 	},
1364 };
1365 
1366 static struct clk_regmap gxbb_vpu_0 = {
1367 	.data = &(struct clk_regmap_gate_data){
1368 		.offset = HHI_VPU_CLK_CNTL,
1369 		.bit_idx = 8,
1370 	},
1371 	.hw.init = &(struct clk_init_data) {
1372 		.name = "vpu_0",
1373 		.ops = &clk_regmap_gate_ops,
1374 		.parent_names = (const char *[]){ "vpu_0_div" },
1375 		.num_parents = 1,
1376 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1377 	},
1378 };
1379 
1380 static struct clk_regmap gxbb_vpu_1_sel = {
1381 	.data = &(struct clk_regmap_mux_data){
1382 		.offset = HHI_VPU_CLK_CNTL,
1383 		.mask = 0x3,
1384 		.shift = 25,
1385 	},
1386 	.hw.init = &(struct clk_init_data){
1387 		.name = "vpu_1_sel",
1388 		.ops = &clk_regmap_mux_ops,
1389 		/*
1390 		 * bits 25:26 selects from 4 possible parents:
1391 		 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1392 		 */
1393 		.parent_names = gxbb_vpu_parent_names,
1394 		.num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
1395 		.flags = CLK_SET_RATE_NO_REPARENT,
1396 	},
1397 };
1398 
1399 static struct clk_regmap gxbb_vpu_1_div = {
1400 	.data = &(struct clk_regmap_div_data){
1401 		.offset = HHI_VPU_CLK_CNTL,
1402 		.shift = 16,
1403 		.width = 7,
1404 	},
1405 	.hw.init = &(struct clk_init_data){
1406 		.name = "vpu_1_div",
1407 		.ops = &clk_regmap_divider_ops,
1408 		.parent_names = (const char *[]){ "vpu_1_sel" },
1409 		.num_parents = 1,
1410 		.flags = CLK_SET_RATE_PARENT,
1411 	},
1412 };
1413 
1414 static struct clk_regmap gxbb_vpu_1 = {
1415 	.data = &(struct clk_regmap_gate_data){
1416 		.offset = HHI_VPU_CLK_CNTL,
1417 		.bit_idx = 24,
1418 	},
1419 	.hw.init = &(struct clk_init_data) {
1420 		.name = "vpu_1",
1421 		.ops = &clk_regmap_gate_ops,
1422 		.parent_names = (const char *[]){ "vpu_1_div" },
1423 		.num_parents = 1,
1424 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1425 	},
1426 };
1427 
1428 static struct clk_regmap gxbb_vpu = {
1429 	.data = &(struct clk_regmap_mux_data){
1430 		.offset = HHI_VPU_CLK_CNTL,
1431 		.mask = 1,
1432 		.shift = 31,
1433 	},
1434 	.hw.init = &(struct clk_init_data){
1435 		.name = "vpu",
1436 		.ops = &clk_regmap_mux_ops,
1437 		/*
1438 		 * bit 31 selects from 2 possible parents:
1439 		 * vpu_0 or vpu_1
1440 		 */
1441 		.parent_names = (const char *[]){ "vpu_0", "vpu_1" },
1442 		.num_parents = 2,
1443 		.flags = CLK_SET_RATE_NO_REPARENT,
1444 	},
1445 };
1446 
1447 /* VAPB Clock */
1448 
1449 static const char * const gxbb_vapb_parent_names[] = {
1450 	"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1451 };
1452 
1453 static struct clk_regmap gxbb_vapb_0_sel = {
1454 	.data = &(struct clk_regmap_mux_data){
1455 		.offset = HHI_VAPBCLK_CNTL,
1456 		.mask = 0x3,
1457 		.shift = 9,
1458 	},
1459 	.hw.init = &(struct clk_init_data){
1460 		.name = "vapb_0_sel",
1461 		.ops = &clk_regmap_mux_ops,
1462 		/*
1463 		 * bits 9:10 selects from 4 possible parents:
1464 		 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1465 		 */
1466 		.parent_names = gxbb_vapb_parent_names,
1467 		.num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
1468 		.flags = CLK_SET_RATE_NO_REPARENT,
1469 	},
1470 };
1471 
1472 static struct clk_regmap gxbb_vapb_0_div = {
1473 	.data = &(struct clk_regmap_div_data){
1474 		.offset = HHI_VAPBCLK_CNTL,
1475 		.shift = 0,
1476 		.width = 7,
1477 	},
1478 	.hw.init = &(struct clk_init_data){
1479 		.name = "vapb_0_div",
1480 		.ops = &clk_regmap_divider_ops,
1481 		.parent_names = (const char *[]){ "vapb_0_sel" },
1482 		.num_parents = 1,
1483 		.flags = CLK_SET_RATE_PARENT,
1484 	},
1485 };
1486 
1487 static struct clk_regmap gxbb_vapb_0 = {
1488 	.data = &(struct clk_regmap_gate_data){
1489 		.offset = HHI_VAPBCLK_CNTL,
1490 		.bit_idx = 8,
1491 	},
1492 	.hw.init = &(struct clk_init_data) {
1493 		.name = "vapb_0",
1494 		.ops = &clk_regmap_gate_ops,
1495 		.parent_names = (const char *[]){ "vapb_0_div" },
1496 		.num_parents = 1,
1497 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1498 	},
1499 };
1500 
1501 static struct clk_regmap gxbb_vapb_1_sel = {
1502 	.data = &(struct clk_regmap_mux_data){
1503 		.offset = HHI_VAPBCLK_CNTL,
1504 		.mask = 0x3,
1505 		.shift = 25,
1506 	},
1507 	.hw.init = &(struct clk_init_data){
1508 		.name = "vapb_1_sel",
1509 		.ops = &clk_regmap_mux_ops,
1510 		/*
1511 		 * bits 25:26 selects from 4 possible parents:
1512 		 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1513 		 */
1514 		.parent_names = gxbb_vapb_parent_names,
1515 		.num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
1516 		.flags = CLK_SET_RATE_NO_REPARENT,
1517 	},
1518 };
1519 
1520 static struct clk_regmap gxbb_vapb_1_div = {
1521 	.data = &(struct clk_regmap_div_data){
1522 		.offset = HHI_VAPBCLK_CNTL,
1523 		.shift = 16,
1524 		.width = 7,
1525 	},
1526 	.hw.init = &(struct clk_init_data){
1527 		.name = "vapb_1_div",
1528 		.ops = &clk_regmap_divider_ops,
1529 		.parent_names = (const char *[]){ "vapb_1_sel" },
1530 		.num_parents = 1,
1531 		.flags = CLK_SET_RATE_PARENT,
1532 	},
1533 };
1534 
1535 static struct clk_regmap gxbb_vapb_1 = {
1536 	.data = &(struct clk_regmap_gate_data){
1537 		.offset = HHI_VAPBCLK_CNTL,
1538 		.bit_idx = 24,
1539 	},
1540 	.hw.init = &(struct clk_init_data) {
1541 		.name = "vapb_1",
1542 		.ops = &clk_regmap_gate_ops,
1543 		.parent_names = (const char *[]){ "vapb_1_div" },
1544 		.num_parents = 1,
1545 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1546 	},
1547 };
1548 
1549 static struct clk_regmap gxbb_vapb_sel = {
1550 	.data = &(struct clk_regmap_mux_data){
1551 		.offset = HHI_VAPBCLK_CNTL,
1552 		.mask = 1,
1553 		.shift = 31,
1554 	},
1555 	.hw.init = &(struct clk_init_data){
1556 		.name = "vapb_sel",
1557 		.ops = &clk_regmap_mux_ops,
1558 		/*
1559 		 * bit 31 selects from 2 possible parents:
1560 		 * vapb_0 or vapb_1
1561 		 */
1562 		.parent_names = (const char *[]){ "vapb_0", "vapb_1" },
1563 		.num_parents = 2,
1564 		.flags = CLK_SET_RATE_NO_REPARENT,
1565 	},
1566 };
1567 
1568 static struct clk_regmap gxbb_vapb = {
1569 	.data = &(struct clk_regmap_gate_data){
1570 		.offset = HHI_VAPBCLK_CNTL,
1571 		.bit_idx = 30,
1572 	},
1573 	.hw.init = &(struct clk_init_data) {
1574 		.name = "vapb",
1575 		.ops = &clk_regmap_gate_ops,
1576 		.parent_names = (const char *[]){ "vapb_sel" },
1577 		.num_parents = 1,
1578 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1579 	},
1580 };
1581 
1582 /* Video Clocks */
1583 
1584 static struct clk_regmap gxbb_vid_pll_div = {
1585 	.data = &(struct meson_vid_pll_div_data){
1586 		.val = {
1587 			.reg_off = HHI_VID_PLL_CLK_DIV,
1588 			.shift   = 0,
1589 			.width   = 15,
1590 		},
1591 		.sel = {
1592 			.reg_off = HHI_VID_PLL_CLK_DIV,
1593 			.shift   = 16,
1594 			.width   = 2,
1595 		},
1596 	},
1597 	.hw.init = &(struct clk_init_data) {
1598 		.name = "vid_pll_div",
1599 		.ops = &meson_vid_pll_div_ro_ops,
1600 		.parent_names = (const char *[]){ "hdmi_pll" },
1601 		.num_parents = 1,
1602 		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
1603 	},
1604 };
1605 
1606 static const char * const gxbb_vid_pll_parent_names[] = { "vid_pll_div", "hdmi_pll" };
1607 
1608 static struct clk_regmap gxbb_vid_pll_sel = {
1609 	.data = &(struct clk_regmap_mux_data){
1610 		.offset = HHI_VID_PLL_CLK_DIV,
1611 		.mask = 0x1,
1612 		.shift = 18,
1613 	},
1614 	.hw.init = &(struct clk_init_data){
1615 		.name = "vid_pll_sel",
1616 		.ops = &clk_regmap_mux_ops,
1617 		/*
1618 		 * bit 18 selects from 2 possible parents:
1619 		 * vid_pll_div or hdmi_pll
1620 		 */
1621 		.parent_names = gxbb_vid_pll_parent_names,
1622 		.num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_names),
1623 		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1624 	},
1625 };
1626 
1627 static struct clk_regmap gxbb_vid_pll = {
1628 	.data = &(struct clk_regmap_gate_data){
1629 		.offset = HHI_VID_PLL_CLK_DIV,
1630 		.bit_idx = 19,
1631 	},
1632 	.hw.init = &(struct clk_init_data) {
1633 		.name = "vid_pll",
1634 		.ops = &clk_regmap_gate_ops,
1635 		.parent_names = (const char *[]){ "vid_pll_sel" },
1636 		.num_parents = 1,
1637 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1638 	},
1639 };
1640 
1641 static const char * const gxbb_vclk_parent_names[] = {
1642 	"vid_pll", "fclk_div4", "fclk_div3", "fclk_div5", "vid_pll",
1643 	"fclk_div7", "mpll1",
1644 };
1645 
1646 static struct clk_regmap gxbb_vclk_sel = {
1647 	.data = &(struct clk_regmap_mux_data){
1648 		.offset = HHI_VID_CLK_CNTL,
1649 		.mask = 0x7,
1650 		.shift = 16,
1651 	},
1652 	.hw.init = &(struct clk_init_data){
1653 		.name = "vclk_sel",
1654 		.ops = &clk_regmap_mux_ops,
1655 		/*
1656 		 * bits 16:18 selects from 8 possible parents:
1657 		 * vid_pll, fclk_div4, fclk_div3, fclk_div5,
1658 		 * vid_pll, fclk_div7, mp1
1659 		 */
1660 		.parent_names = gxbb_vclk_parent_names,
1661 		.num_parents = ARRAY_SIZE(gxbb_vclk_parent_names),
1662 		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1663 	},
1664 };
1665 
1666 static struct clk_regmap gxbb_vclk2_sel = {
1667 	.data = &(struct clk_regmap_mux_data){
1668 		.offset = HHI_VIID_CLK_CNTL,
1669 		.mask = 0x7,
1670 		.shift = 16,
1671 	},
1672 	.hw.init = &(struct clk_init_data){
1673 		.name = "vclk2_sel",
1674 		.ops = &clk_regmap_mux_ops,
1675 		/*
1676 		 * bits 16:18 selects from 8 possible parents:
1677 		 * vid_pll, fclk_div4, fclk_div3, fclk_div5,
1678 		 * vid_pll, fclk_div7, mp1
1679 		 */
1680 		.parent_names = gxbb_vclk_parent_names,
1681 		.num_parents = ARRAY_SIZE(gxbb_vclk_parent_names),
1682 		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1683 	},
1684 };
1685 
1686 static struct clk_regmap gxbb_vclk_input = {
1687 	.data = &(struct clk_regmap_gate_data){
1688 		.offset = HHI_VID_CLK_DIV,
1689 		.bit_idx = 16,
1690 	},
1691 	.hw.init = &(struct clk_init_data) {
1692 		.name = "vclk_input",
1693 		.ops = &clk_regmap_gate_ops,
1694 		.parent_names = (const char *[]){ "vclk_sel" },
1695 		.num_parents = 1,
1696 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1697 	},
1698 };
1699 
1700 static struct clk_regmap gxbb_vclk2_input = {
1701 	.data = &(struct clk_regmap_gate_data){
1702 		.offset = HHI_VIID_CLK_DIV,
1703 		.bit_idx = 16,
1704 	},
1705 	.hw.init = &(struct clk_init_data) {
1706 		.name = "vclk2_input",
1707 		.ops = &clk_regmap_gate_ops,
1708 		.parent_names = (const char *[]){ "vclk2_sel" },
1709 		.num_parents = 1,
1710 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1711 	},
1712 };
1713 
1714 static struct clk_regmap gxbb_vclk_div = {
1715 	.data = &(struct clk_regmap_div_data){
1716 		.offset = HHI_VID_CLK_DIV,
1717 		.shift = 0,
1718 		.width = 8,
1719 	},
1720 	.hw.init = &(struct clk_init_data){
1721 		.name = "vclk_div",
1722 		.ops = &clk_regmap_divider_ops,
1723 		.parent_names = (const char *[]){ "vclk_input" },
1724 		.num_parents = 1,
1725 		.flags = CLK_GET_RATE_NOCACHE,
1726 	},
1727 };
1728 
1729 static struct clk_regmap gxbb_vclk2_div = {
1730 	.data = &(struct clk_regmap_div_data){
1731 		.offset = HHI_VIID_CLK_DIV,
1732 		.shift = 0,
1733 		.width = 8,
1734 	},
1735 	.hw.init = &(struct clk_init_data){
1736 		.name = "vclk2_div",
1737 		.ops = &clk_regmap_divider_ops,
1738 		.parent_names = (const char *[]){ "vclk2_input" },
1739 		.num_parents = 1,
1740 		.flags = CLK_GET_RATE_NOCACHE,
1741 	},
1742 };
1743 
1744 static struct clk_regmap gxbb_vclk = {
1745 	.data = &(struct clk_regmap_gate_data){
1746 		.offset = HHI_VID_CLK_CNTL,
1747 		.bit_idx = 19,
1748 	},
1749 	.hw.init = &(struct clk_init_data) {
1750 		.name = "vclk",
1751 		.ops = &clk_regmap_gate_ops,
1752 		.parent_names = (const char *[]){ "vclk_div" },
1753 		.num_parents = 1,
1754 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1755 	},
1756 };
1757 
1758 static struct clk_regmap gxbb_vclk2 = {
1759 	.data = &(struct clk_regmap_gate_data){
1760 		.offset = HHI_VIID_CLK_CNTL,
1761 		.bit_idx = 19,
1762 	},
1763 	.hw.init = &(struct clk_init_data) {
1764 		.name = "vclk2",
1765 		.ops = &clk_regmap_gate_ops,
1766 		.parent_names = (const char *[]){ "vclk2_div" },
1767 		.num_parents = 1,
1768 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1769 	},
1770 };
1771 
1772 static struct clk_regmap gxbb_vclk_div1 = {
1773 	.data = &(struct clk_regmap_gate_data){
1774 		.offset = HHI_VID_CLK_CNTL,
1775 		.bit_idx = 0,
1776 	},
1777 	.hw.init = &(struct clk_init_data) {
1778 		.name = "vclk_div1",
1779 		.ops = &clk_regmap_gate_ops,
1780 		.parent_names = (const char *[]){ "vclk" },
1781 		.num_parents = 1,
1782 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1783 	},
1784 };
1785 
1786 static struct clk_regmap gxbb_vclk_div2_en = {
1787 	.data = &(struct clk_regmap_gate_data){
1788 		.offset = HHI_VID_CLK_CNTL,
1789 		.bit_idx = 1,
1790 	},
1791 	.hw.init = &(struct clk_init_data) {
1792 		.name = "vclk_div2_en",
1793 		.ops = &clk_regmap_gate_ops,
1794 		.parent_names = (const char *[]){ "vclk" },
1795 		.num_parents = 1,
1796 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1797 	},
1798 };
1799 
1800 static struct clk_regmap gxbb_vclk_div4_en = {
1801 	.data = &(struct clk_regmap_gate_data){
1802 		.offset = HHI_VID_CLK_CNTL,
1803 		.bit_idx = 2,
1804 	},
1805 	.hw.init = &(struct clk_init_data) {
1806 		.name = "vclk_div4_en",
1807 		.ops = &clk_regmap_gate_ops,
1808 		.parent_names = (const char *[]){ "vclk" },
1809 		.num_parents = 1,
1810 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1811 	},
1812 };
1813 
1814 static struct clk_regmap gxbb_vclk_div6_en = {
1815 	.data = &(struct clk_regmap_gate_data){
1816 		.offset = HHI_VID_CLK_CNTL,
1817 		.bit_idx = 3,
1818 	},
1819 	.hw.init = &(struct clk_init_data) {
1820 		.name = "vclk_div6_en",
1821 		.ops = &clk_regmap_gate_ops,
1822 		.parent_names = (const char *[]){ "vclk" },
1823 		.num_parents = 1,
1824 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1825 	},
1826 };
1827 
1828 static struct clk_regmap gxbb_vclk_div12_en = {
1829 	.data = &(struct clk_regmap_gate_data){
1830 		.offset = HHI_VID_CLK_CNTL,
1831 		.bit_idx = 4,
1832 	},
1833 	.hw.init = &(struct clk_init_data) {
1834 		.name = "vclk_div12_en",
1835 		.ops = &clk_regmap_gate_ops,
1836 		.parent_names = (const char *[]){ "vclk" },
1837 		.num_parents = 1,
1838 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1839 	},
1840 };
1841 
1842 static struct clk_regmap gxbb_vclk2_div1 = {
1843 	.data = &(struct clk_regmap_gate_data){
1844 		.offset = HHI_VIID_CLK_CNTL,
1845 		.bit_idx = 0,
1846 	},
1847 	.hw.init = &(struct clk_init_data) {
1848 		.name = "vclk2_div1",
1849 		.ops = &clk_regmap_gate_ops,
1850 		.parent_names = (const char *[]){ "vclk2" },
1851 		.num_parents = 1,
1852 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1853 	},
1854 };
1855 
1856 static struct clk_regmap gxbb_vclk2_div2_en = {
1857 	.data = &(struct clk_regmap_gate_data){
1858 		.offset = HHI_VIID_CLK_CNTL,
1859 		.bit_idx = 1,
1860 	},
1861 	.hw.init = &(struct clk_init_data) {
1862 		.name = "vclk2_div2_en",
1863 		.ops = &clk_regmap_gate_ops,
1864 		.parent_names = (const char *[]){ "vclk2" },
1865 		.num_parents = 1,
1866 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1867 	},
1868 };
1869 
1870 static struct clk_regmap gxbb_vclk2_div4_en = {
1871 	.data = &(struct clk_regmap_gate_data){
1872 		.offset = HHI_VIID_CLK_CNTL,
1873 		.bit_idx = 2,
1874 	},
1875 	.hw.init = &(struct clk_init_data) {
1876 		.name = "vclk2_div4_en",
1877 		.ops = &clk_regmap_gate_ops,
1878 		.parent_names = (const char *[]){ "vclk2" },
1879 		.num_parents = 1,
1880 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1881 	},
1882 };
1883 
1884 static struct clk_regmap gxbb_vclk2_div6_en = {
1885 	.data = &(struct clk_regmap_gate_data){
1886 		.offset = HHI_VIID_CLK_CNTL,
1887 		.bit_idx = 3,
1888 	},
1889 	.hw.init = &(struct clk_init_data) {
1890 		.name = "vclk2_div6_en",
1891 		.ops = &clk_regmap_gate_ops,
1892 		.parent_names = (const char *[]){ "vclk2" },
1893 		.num_parents = 1,
1894 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1895 	},
1896 };
1897 
1898 static struct clk_regmap gxbb_vclk2_div12_en = {
1899 	.data = &(struct clk_regmap_gate_data){
1900 		.offset = HHI_VIID_CLK_CNTL,
1901 		.bit_idx = 4,
1902 	},
1903 	.hw.init = &(struct clk_init_data) {
1904 		.name = "vclk2_div12_en",
1905 		.ops = &clk_regmap_gate_ops,
1906 		.parent_names = (const char *[]){ "vclk2" },
1907 		.num_parents = 1,
1908 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1909 	},
1910 };
1911 
1912 static struct clk_fixed_factor gxbb_vclk_div2 = {
1913 	.mult = 1,
1914 	.div = 2,
1915 	.hw.init = &(struct clk_init_data){
1916 		.name = "vclk_div2",
1917 		.ops = &clk_fixed_factor_ops,
1918 		.parent_names = (const char *[]){ "vclk_div2_en" },
1919 		.num_parents = 1,
1920 	},
1921 };
1922 
1923 static struct clk_fixed_factor gxbb_vclk_div4 = {
1924 	.mult = 1,
1925 	.div = 4,
1926 	.hw.init = &(struct clk_init_data){
1927 		.name = "vclk_div4",
1928 		.ops = &clk_fixed_factor_ops,
1929 		.parent_names = (const char *[]){ "vclk_div4_en" },
1930 		.num_parents = 1,
1931 	},
1932 };
1933 
1934 static struct clk_fixed_factor gxbb_vclk_div6 = {
1935 	.mult = 1,
1936 	.div = 6,
1937 	.hw.init = &(struct clk_init_data){
1938 		.name = "vclk_div6",
1939 		.ops = &clk_fixed_factor_ops,
1940 		.parent_names = (const char *[]){ "vclk_div6_en" },
1941 		.num_parents = 1,
1942 	},
1943 };
1944 
1945 static struct clk_fixed_factor gxbb_vclk_div12 = {
1946 	.mult = 1,
1947 	.div = 12,
1948 	.hw.init = &(struct clk_init_data){
1949 		.name = "vclk_div12",
1950 		.ops = &clk_fixed_factor_ops,
1951 		.parent_names = (const char *[]){ "vclk_div12_en" },
1952 		.num_parents = 1,
1953 	},
1954 };
1955 
1956 static struct clk_fixed_factor gxbb_vclk2_div2 = {
1957 	.mult = 1,
1958 	.div = 2,
1959 	.hw.init = &(struct clk_init_data){
1960 		.name = "vclk2_div2",
1961 		.ops = &clk_fixed_factor_ops,
1962 		.parent_names = (const char *[]){ "vclk2_div2_en" },
1963 		.num_parents = 1,
1964 	},
1965 };
1966 
1967 static struct clk_fixed_factor gxbb_vclk2_div4 = {
1968 	.mult = 1,
1969 	.div = 4,
1970 	.hw.init = &(struct clk_init_data){
1971 		.name = "vclk2_div4",
1972 		.ops = &clk_fixed_factor_ops,
1973 		.parent_names = (const char *[]){ "vclk2_div4_en" },
1974 		.num_parents = 1,
1975 	},
1976 };
1977 
1978 static struct clk_fixed_factor gxbb_vclk2_div6 = {
1979 	.mult = 1,
1980 	.div = 6,
1981 	.hw.init = &(struct clk_init_data){
1982 		.name = "vclk2_div6",
1983 		.ops = &clk_fixed_factor_ops,
1984 		.parent_names = (const char *[]){ "vclk2_div6_en" },
1985 		.num_parents = 1,
1986 	},
1987 };
1988 
1989 static struct clk_fixed_factor gxbb_vclk2_div12 = {
1990 	.mult = 1,
1991 	.div = 12,
1992 	.hw.init = &(struct clk_init_data){
1993 		.name = "vclk2_div12",
1994 		.ops = &clk_fixed_factor_ops,
1995 		.parent_names = (const char *[]){ "vclk2_div12_en" },
1996 		.num_parents = 1,
1997 	},
1998 };
1999 
2000 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2001 static const char * const gxbb_cts_parent_names[] = {
2002 	"vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
2003 	"vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
2004 	"vclk2_div6", "vclk2_div12"
2005 };
2006 
2007 static struct clk_regmap gxbb_cts_enci_sel = {
2008 	.data = &(struct clk_regmap_mux_data){
2009 		.offset = HHI_VID_CLK_DIV,
2010 		.mask = 0xf,
2011 		.shift = 28,
2012 		.table = mux_table_cts_sel,
2013 	},
2014 	.hw.init = &(struct clk_init_data){
2015 		.name = "cts_enci_sel",
2016 		.ops = &clk_regmap_mux_ops,
2017 		.parent_names = gxbb_cts_parent_names,
2018 		.num_parents = ARRAY_SIZE(gxbb_cts_parent_names),
2019 		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2020 	},
2021 };
2022 
2023 static struct clk_regmap gxbb_cts_encp_sel = {
2024 	.data = &(struct clk_regmap_mux_data){
2025 		.offset = HHI_VID_CLK_DIV,
2026 		.mask = 0xf,
2027 		.shift = 20,
2028 		.table = mux_table_cts_sel,
2029 	},
2030 	.hw.init = &(struct clk_init_data){
2031 		.name = "cts_encp_sel",
2032 		.ops = &clk_regmap_mux_ops,
2033 		.parent_names = gxbb_cts_parent_names,
2034 		.num_parents = ARRAY_SIZE(gxbb_cts_parent_names),
2035 		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2036 	},
2037 };
2038 
2039 static struct clk_regmap gxbb_cts_vdac_sel = {
2040 	.data = &(struct clk_regmap_mux_data){
2041 		.offset = HHI_VIID_CLK_DIV,
2042 		.mask = 0xf,
2043 		.shift = 28,
2044 		.table = mux_table_cts_sel,
2045 	},
2046 	.hw.init = &(struct clk_init_data){
2047 		.name = "cts_vdac_sel",
2048 		.ops = &clk_regmap_mux_ops,
2049 		.parent_names = gxbb_cts_parent_names,
2050 		.num_parents = ARRAY_SIZE(gxbb_cts_parent_names),
2051 		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2052 	},
2053 };
2054 
2055 /* TOFIX: add support for cts_tcon */
2056 static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2057 static const char * const gxbb_cts_hdmi_tx_parent_names[] = {
2058 	"vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
2059 	"vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
2060 	"vclk2_div6", "vclk2_div12"
2061 };
2062 
2063 static struct clk_regmap gxbb_hdmi_tx_sel = {
2064 	.data = &(struct clk_regmap_mux_data){
2065 		.offset = HHI_HDMI_CLK_CNTL,
2066 		.mask = 0xf,
2067 		.shift = 16,
2068 		.table = mux_table_hdmi_tx_sel,
2069 	},
2070 	.hw.init = &(struct clk_init_data){
2071 		.name = "hdmi_tx_sel",
2072 		.ops = &clk_regmap_mux_ops,
2073 		/*
2074 		 * bits 31:28 selects from 12 possible parents:
2075 		 * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12
2076 		 * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
2077 		 * cts_tcon
2078 		 */
2079 		.parent_names = gxbb_cts_hdmi_tx_parent_names,
2080 		.num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_names),
2081 		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2082 	},
2083 };
2084 
2085 static struct clk_regmap gxbb_cts_enci = {
2086 	.data = &(struct clk_regmap_gate_data){
2087 		.offset = HHI_VID_CLK_CNTL2,
2088 		.bit_idx = 0,
2089 	},
2090 	.hw.init = &(struct clk_init_data) {
2091 		.name = "cts_enci",
2092 		.ops = &clk_regmap_gate_ops,
2093 		.parent_names = (const char *[]){ "cts_enci_sel" },
2094 		.num_parents = 1,
2095 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2096 	},
2097 };
2098 
2099 static struct clk_regmap gxbb_cts_encp = {
2100 	.data = &(struct clk_regmap_gate_data){
2101 		.offset = HHI_VID_CLK_CNTL2,
2102 		.bit_idx = 2,
2103 	},
2104 	.hw.init = &(struct clk_init_data) {
2105 		.name = "cts_encp",
2106 		.ops = &clk_regmap_gate_ops,
2107 		.parent_names = (const char *[]){ "cts_encp_sel" },
2108 		.num_parents = 1,
2109 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2110 	},
2111 };
2112 
2113 static struct clk_regmap gxbb_cts_vdac = {
2114 	.data = &(struct clk_regmap_gate_data){
2115 		.offset = HHI_VID_CLK_CNTL2,
2116 		.bit_idx = 4,
2117 	},
2118 	.hw.init = &(struct clk_init_data) {
2119 		.name = "cts_vdac",
2120 		.ops = &clk_regmap_gate_ops,
2121 		.parent_names = (const char *[]){ "cts_vdac_sel" },
2122 		.num_parents = 1,
2123 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2124 	},
2125 };
2126 
2127 static struct clk_regmap gxbb_hdmi_tx = {
2128 	.data = &(struct clk_regmap_gate_data){
2129 		.offset = HHI_VID_CLK_CNTL2,
2130 		.bit_idx = 5,
2131 	},
2132 	.hw.init = &(struct clk_init_data) {
2133 		.name = "hdmi_tx",
2134 		.ops = &clk_regmap_gate_ops,
2135 		.parent_names = (const char *[]){ "hdmi_tx_sel" },
2136 		.num_parents = 1,
2137 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2138 	},
2139 };
2140 
2141 /* HDMI Clocks */
2142 
2143 static const char * const gxbb_hdmi_parent_names[] = {
2144 	IN_PREFIX "xtal", "fclk_div4", "fclk_div3", "fclk_div5"
2145 };
2146 
2147 static struct clk_regmap gxbb_hdmi_sel = {
2148 	.data = &(struct clk_regmap_mux_data){
2149 		.offset = HHI_HDMI_CLK_CNTL,
2150 		.mask = 0x3,
2151 		.shift = 9,
2152 		.flags = CLK_MUX_ROUND_CLOSEST,
2153 	},
2154 	.hw.init = &(struct clk_init_data){
2155 		.name = "hdmi_sel",
2156 		.ops = &clk_regmap_mux_ops,
2157 		.parent_names = gxbb_hdmi_parent_names,
2158 		.num_parents = ARRAY_SIZE(gxbb_hdmi_parent_names),
2159 		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2160 	},
2161 };
2162 
2163 static struct clk_regmap gxbb_hdmi_div = {
2164 	.data = &(struct clk_regmap_div_data){
2165 		.offset = HHI_HDMI_CLK_CNTL,
2166 		.shift = 0,
2167 		.width = 7,
2168 	},
2169 	.hw.init = &(struct clk_init_data){
2170 		.name = "hdmi_div",
2171 		.ops = &clk_regmap_divider_ops,
2172 		.parent_names = (const char *[]){ "hdmi_sel" },
2173 		.num_parents = 1,
2174 		.flags = CLK_GET_RATE_NOCACHE,
2175 	},
2176 };
2177 
2178 static struct clk_regmap gxbb_hdmi = {
2179 	.data = &(struct clk_regmap_gate_data){
2180 		.offset = HHI_HDMI_CLK_CNTL,
2181 		.bit_idx = 8,
2182 	},
2183 	.hw.init = &(struct clk_init_data) {
2184 		.name = "hdmi",
2185 		.ops = &clk_regmap_gate_ops,
2186 		.parent_names = (const char *[]){ "hdmi_div" },
2187 		.num_parents = 1,
2188 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2189 	},
2190 };
2191 
2192 /* VDEC clocks */
2193 
2194 static const char * const gxbb_vdec_parent_names[] = {
2195 	"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
2196 };
2197 
2198 static struct clk_regmap gxbb_vdec_1_sel = {
2199 	.data = &(struct clk_regmap_mux_data){
2200 		.offset = HHI_VDEC_CLK_CNTL,
2201 		.mask = 0x3,
2202 		.shift = 9,
2203 		.flags = CLK_MUX_ROUND_CLOSEST,
2204 	},
2205 	.hw.init = &(struct clk_init_data){
2206 		.name = "vdec_1_sel",
2207 		.ops = &clk_regmap_mux_ops,
2208 		.parent_names = gxbb_vdec_parent_names,
2209 		.num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
2210 		.flags = CLK_SET_RATE_PARENT,
2211 	},
2212 };
2213 
2214 static struct clk_regmap gxbb_vdec_1_div = {
2215 	.data = &(struct clk_regmap_div_data){
2216 		.offset = HHI_VDEC_CLK_CNTL,
2217 		.shift = 0,
2218 		.width = 7,
2219 	},
2220 	.hw.init = &(struct clk_init_data){
2221 		.name = "vdec_1_div",
2222 		.ops = &clk_regmap_divider_ops,
2223 		.parent_names = (const char *[]){ "vdec_1_sel" },
2224 		.num_parents = 1,
2225 		.flags = CLK_SET_RATE_PARENT,
2226 	},
2227 };
2228 
2229 static struct clk_regmap gxbb_vdec_1 = {
2230 	.data = &(struct clk_regmap_gate_data){
2231 		.offset = HHI_VDEC_CLK_CNTL,
2232 		.bit_idx = 8,
2233 	},
2234 	.hw.init = &(struct clk_init_data) {
2235 		.name = "vdec_1",
2236 		.ops = &clk_regmap_gate_ops,
2237 		.parent_names = (const char *[]){ "vdec_1_div" },
2238 		.num_parents = 1,
2239 		.flags = CLK_SET_RATE_PARENT,
2240 	},
2241 };
2242 
2243 static struct clk_regmap gxbb_vdec_hevc_sel = {
2244 	.data = &(struct clk_regmap_mux_data){
2245 		.offset = HHI_VDEC2_CLK_CNTL,
2246 		.mask = 0x3,
2247 		.shift = 25,
2248 		.flags = CLK_MUX_ROUND_CLOSEST,
2249 	},
2250 	.hw.init = &(struct clk_init_data){
2251 		.name = "vdec_hevc_sel",
2252 		.ops = &clk_regmap_mux_ops,
2253 		.parent_names = gxbb_vdec_parent_names,
2254 		.num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
2255 		.flags = CLK_SET_RATE_PARENT,
2256 	},
2257 };
2258 
2259 static struct clk_regmap gxbb_vdec_hevc_div = {
2260 	.data = &(struct clk_regmap_div_data){
2261 		.offset = HHI_VDEC2_CLK_CNTL,
2262 		.shift = 16,
2263 		.width = 7,
2264 	},
2265 	.hw.init = &(struct clk_init_data){
2266 		.name = "vdec_hevc_div",
2267 		.ops = &clk_regmap_divider_ops,
2268 		.parent_names = (const char *[]){ "vdec_hevc_sel" },
2269 		.num_parents = 1,
2270 		.flags = CLK_SET_RATE_PARENT,
2271 	},
2272 };
2273 
2274 static struct clk_regmap gxbb_vdec_hevc = {
2275 	.data = &(struct clk_regmap_gate_data){
2276 		.offset = HHI_VDEC2_CLK_CNTL,
2277 		.bit_idx = 24,
2278 	},
2279 	.hw.init = &(struct clk_init_data) {
2280 		.name = "vdec_hevc",
2281 		.ops = &clk_regmap_gate_ops,
2282 		.parent_names = (const char *[]){ "vdec_hevc_div" },
2283 		.num_parents = 1,
2284 		.flags = CLK_SET_RATE_PARENT,
2285 	},
2286 };
2287 
2288 static u32 mux_table_gen_clk[]	= { 0, 4, 5, 6, 7, 8,
2289 				    9, 10, 11, 13, 14, };
2290 static const char * const gen_clk_parent_names[] = {
2291 	IN_PREFIX "xtal", "vdec_1", "vdec_hevc", "mpll0", "mpll1", "mpll2",
2292 	"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll",
2293 };
2294 
2295 static struct clk_regmap gxbb_gen_clk_sel = {
2296 	.data = &(struct clk_regmap_mux_data){
2297 		.offset = HHI_GEN_CLK_CNTL,
2298 		.mask = 0xf,
2299 		.shift = 12,
2300 		.table = mux_table_gen_clk,
2301 	},
2302 	.hw.init = &(struct clk_init_data){
2303 		.name = "gen_clk_sel",
2304 		.ops = &clk_regmap_mux_ops,
2305 		/*
2306 		 * bits 15:12 selects from 14 possible parents:
2307 		 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
2308 		 * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,
2309 		 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
2310 		 */
2311 		.parent_names = gen_clk_parent_names,
2312 		.num_parents = ARRAY_SIZE(gen_clk_parent_names),
2313 	},
2314 };
2315 
2316 static struct clk_regmap gxbb_gen_clk_div = {
2317 	.data = &(struct clk_regmap_div_data){
2318 		.offset = HHI_GEN_CLK_CNTL,
2319 		.shift = 0,
2320 		.width = 11,
2321 	},
2322 	.hw.init = &(struct clk_init_data){
2323 		.name = "gen_clk_div",
2324 		.ops = &clk_regmap_divider_ops,
2325 		.parent_names = (const char *[]){ "gen_clk_sel" },
2326 		.num_parents = 1,
2327 		.flags = CLK_SET_RATE_PARENT,
2328 	},
2329 };
2330 
2331 static struct clk_regmap gxbb_gen_clk = {
2332 	.data = &(struct clk_regmap_gate_data){
2333 		.offset = HHI_GEN_CLK_CNTL,
2334 		.bit_idx = 7,
2335 	},
2336 	.hw.init = &(struct clk_init_data){
2337 		.name = "gen_clk",
2338 		.ops = &clk_regmap_gate_ops,
2339 		.parent_names = (const char *[]){ "gen_clk_div" },
2340 		.num_parents = 1,
2341 		.flags = CLK_SET_RATE_PARENT,
2342 	},
2343 };
2344 
2345 /* Everything Else (EE) domain gates */
2346 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
2347 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
2348 static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
2349 static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
2350 static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
2351 static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
2352 static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
2353 static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10);
2354 static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
2355 static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
2356 static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
2357 static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
2358 static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
2359 static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
2360 static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
2361 static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
2362 static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
2363 static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
2364 static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
2365 static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
2366 static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
2367 static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
2368 
2369 static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
2370 static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
2371 static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
2372 static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6);
2373 static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7);
2374 static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8);
2375 static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9);
2376 static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10);
2377 static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11);
2378 static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12);
2379 static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13);
2380 static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
2381 static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
2382 static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
2383 static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
2384 static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
2385 static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
2386 static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
2387 static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
2388 static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
2389 static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
2390 static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
2391 static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
2392 static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
2393 static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
2394 
2395 static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
2396 static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
2397 static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
2398 static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
2399 static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
2400 static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
2401 static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
2402 static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
2403 static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
2404 static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);
2405 static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
2406 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
2407 static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
2408 
2409 static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
2410 static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
2411 static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
2412 static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
2413 static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
2414 static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
2415 static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
2416 static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
2417 static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
2418 static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
2419 static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
2420 static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
2421 static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
2422 static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
2423 static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
2424 static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
2425 
2426 /* Always On (AO) domain gates */
2427 
2428 static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
2429 static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
2430 static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
2431 static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
2432 static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
2433 
2434 /* Array of all clocks provided by this provider */
2435 
2436 static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
2437 	.hws = {
2438 		[CLKID_SYS_PLL]		    = &gxbb_sys_pll.hw,
2439 		[CLKID_HDMI_PLL]	    = &gxbb_hdmi_pll.hw,
2440 		[CLKID_FIXED_PLL]	    = &gxbb_fixed_pll.hw,
2441 		[CLKID_FCLK_DIV2]	    = &gxbb_fclk_div2.hw,
2442 		[CLKID_FCLK_DIV3]	    = &gxbb_fclk_div3.hw,
2443 		[CLKID_FCLK_DIV4]	    = &gxbb_fclk_div4.hw,
2444 		[CLKID_FCLK_DIV5]	    = &gxbb_fclk_div5.hw,
2445 		[CLKID_FCLK_DIV7]	    = &gxbb_fclk_div7.hw,
2446 		[CLKID_GP0_PLL]		    = &gxbb_gp0_pll.hw,
2447 		[CLKID_MPEG_SEL]	    = &gxbb_mpeg_clk_sel.hw,
2448 		[CLKID_MPEG_DIV]	    = &gxbb_mpeg_clk_div.hw,
2449 		[CLKID_CLK81]		    = &gxbb_clk81.hw,
2450 		[CLKID_MPLL0]		    = &gxbb_mpll0.hw,
2451 		[CLKID_MPLL1]		    = &gxbb_mpll1.hw,
2452 		[CLKID_MPLL2]		    = &gxbb_mpll2.hw,
2453 		[CLKID_DDR]		    = &gxbb_ddr.hw,
2454 		[CLKID_DOS]		    = &gxbb_dos.hw,
2455 		[CLKID_ISA]		    = &gxbb_isa.hw,
2456 		[CLKID_PL301]		    = &gxbb_pl301.hw,
2457 		[CLKID_PERIPHS]		    = &gxbb_periphs.hw,
2458 		[CLKID_SPICC]		    = &gxbb_spicc.hw,
2459 		[CLKID_I2C]		    = &gxbb_i2c.hw,
2460 		[CLKID_SAR_ADC]		    = &gxbb_sar_adc.hw,
2461 		[CLKID_SMART_CARD]	    = &gxbb_smart_card.hw,
2462 		[CLKID_RNG0]		    = &gxbb_rng0.hw,
2463 		[CLKID_UART0]		    = &gxbb_uart0.hw,
2464 		[CLKID_SDHC]		    = &gxbb_sdhc.hw,
2465 		[CLKID_STREAM]		    = &gxbb_stream.hw,
2466 		[CLKID_ASYNC_FIFO]	    = &gxbb_async_fifo.hw,
2467 		[CLKID_SDIO]		    = &gxbb_sdio.hw,
2468 		[CLKID_ABUF]		    = &gxbb_abuf.hw,
2469 		[CLKID_HIU_IFACE]	    = &gxbb_hiu_iface.hw,
2470 		[CLKID_ASSIST_MISC]	    = &gxbb_assist_misc.hw,
2471 		[CLKID_SPI]		    = &gxbb_spi.hw,
2472 		[CLKID_I2S_SPDIF]	    = &gxbb_i2s_spdif.hw,
2473 		[CLKID_ETH]		    = &gxbb_eth.hw,
2474 		[CLKID_DEMUX]		    = &gxbb_demux.hw,
2475 		[CLKID_AIU_GLUE]	    = &gxbb_aiu_glue.hw,
2476 		[CLKID_IEC958]		    = &gxbb_iec958.hw,
2477 		[CLKID_I2S_OUT]		    = &gxbb_i2s_out.hw,
2478 		[CLKID_AMCLK]		    = &gxbb_amclk.hw,
2479 		[CLKID_AIFIFO2]		    = &gxbb_aififo2.hw,
2480 		[CLKID_MIXER]		    = &gxbb_mixer.hw,
2481 		[CLKID_MIXER_IFACE]	    = &gxbb_mixer_iface.hw,
2482 		[CLKID_ADC]		    = &gxbb_adc.hw,
2483 		[CLKID_BLKMV]		    = &gxbb_blkmv.hw,
2484 		[CLKID_AIU]		    = &gxbb_aiu.hw,
2485 		[CLKID_UART1]		    = &gxbb_uart1.hw,
2486 		[CLKID_G2D]		    = &gxbb_g2d.hw,
2487 		[CLKID_USB0]		    = &gxbb_usb0.hw,
2488 		[CLKID_USB1]		    = &gxbb_usb1.hw,
2489 		[CLKID_RESET]		    = &gxbb_reset.hw,
2490 		[CLKID_NAND]		    = &gxbb_nand.hw,
2491 		[CLKID_DOS_PARSER]	    = &gxbb_dos_parser.hw,
2492 		[CLKID_USB]		    = &gxbb_usb.hw,
2493 		[CLKID_VDIN1]		    = &gxbb_vdin1.hw,
2494 		[CLKID_AHB_ARB0]	    = &gxbb_ahb_arb0.hw,
2495 		[CLKID_EFUSE]		    = &gxbb_efuse.hw,
2496 		[CLKID_BOOT_ROM]	    = &gxbb_boot_rom.hw,
2497 		[CLKID_AHB_DATA_BUS]	    = &gxbb_ahb_data_bus.hw,
2498 		[CLKID_AHB_CTRL_BUS]	    = &gxbb_ahb_ctrl_bus.hw,
2499 		[CLKID_HDMI_INTR_SYNC]	    = &gxbb_hdmi_intr_sync.hw,
2500 		[CLKID_HDMI_PCLK]	    = &gxbb_hdmi_pclk.hw,
2501 		[CLKID_USB1_DDR_BRIDGE]	    = &gxbb_usb1_ddr_bridge.hw,
2502 		[CLKID_USB0_DDR_BRIDGE]	    = &gxbb_usb0_ddr_bridge.hw,
2503 		[CLKID_MMC_PCLK]	    = &gxbb_mmc_pclk.hw,
2504 		[CLKID_DVIN]		    = &gxbb_dvin.hw,
2505 		[CLKID_UART2]		    = &gxbb_uart2.hw,
2506 		[CLKID_SANA]		    = &gxbb_sana.hw,
2507 		[CLKID_VPU_INTR]	    = &gxbb_vpu_intr.hw,
2508 		[CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
2509 		[CLKID_CLK81_A53]	    = &gxbb_clk81_a53.hw,
2510 		[CLKID_VCLK2_VENCI0]	    = &gxbb_vclk2_venci0.hw,
2511 		[CLKID_VCLK2_VENCI1]	    = &gxbb_vclk2_venci1.hw,
2512 		[CLKID_VCLK2_VENCP0]	    = &gxbb_vclk2_vencp0.hw,
2513 		[CLKID_VCLK2_VENCP1]	    = &gxbb_vclk2_vencp1.hw,
2514 		[CLKID_GCLK_VENCI_INT0]	    = &gxbb_gclk_venci_int0.hw,
2515 		[CLKID_GCLK_VENCI_INT]	    = &gxbb_gclk_vencp_int.hw,
2516 		[CLKID_DAC_CLK]		    = &gxbb_dac_clk.hw,
2517 		[CLKID_AOCLK_GATE]	    = &gxbb_aoclk_gate.hw,
2518 		[CLKID_IEC958_GATE]	    = &gxbb_iec958_gate.hw,
2519 		[CLKID_ENC480P]		    = &gxbb_enc480p.hw,
2520 		[CLKID_RNG1]		    = &gxbb_rng1.hw,
2521 		[CLKID_GCLK_VENCI_INT1]	    = &gxbb_gclk_venci_int1.hw,
2522 		[CLKID_VCLK2_VENCLMCC]	    = &gxbb_vclk2_venclmcc.hw,
2523 		[CLKID_VCLK2_VENCL]	    = &gxbb_vclk2_vencl.hw,
2524 		[CLKID_VCLK_OTHER]	    = &gxbb_vclk_other.hw,
2525 		[CLKID_EDP]		    = &gxbb_edp.hw,
2526 		[CLKID_AO_MEDIA_CPU]	    = &gxbb_ao_media_cpu.hw,
2527 		[CLKID_AO_AHB_SRAM]	    = &gxbb_ao_ahb_sram.hw,
2528 		[CLKID_AO_AHB_BUS]	    = &gxbb_ao_ahb_bus.hw,
2529 		[CLKID_AO_IFACE]	    = &gxbb_ao_iface.hw,
2530 		[CLKID_AO_I2C]		    = &gxbb_ao_i2c.hw,
2531 		[CLKID_SD_EMMC_A]	    = &gxbb_emmc_a.hw,
2532 		[CLKID_SD_EMMC_B]	    = &gxbb_emmc_b.hw,
2533 		[CLKID_SD_EMMC_C]	    = &gxbb_emmc_c.hw,
2534 		[CLKID_SAR_ADC_CLK]	    = &gxbb_sar_adc_clk.hw,
2535 		[CLKID_SAR_ADC_SEL]	    = &gxbb_sar_adc_clk_sel.hw,
2536 		[CLKID_SAR_ADC_DIV]	    = &gxbb_sar_adc_clk_div.hw,
2537 		[CLKID_MALI_0_SEL]	    = &gxbb_mali_0_sel.hw,
2538 		[CLKID_MALI_0_DIV]	    = &gxbb_mali_0_div.hw,
2539 		[CLKID_MALI_0]		    = &gxbb_mali_0.hw,
2540 		[CLKID_MALI_1_SEL]	    = &gxbb_mali_1_sel.hw,
2541 		[CLKID_MALI_1_DIV]	    = &gxbb_mali_1_div.hw,
2542 		[CLKID_MALI_1]		    = &gxbb_mali_1.hw,
2543 		[CLKID_MALI]		    = &gxbb_mali.hw,
2544 		[CLKID_CTS_AMCLK]	    = &gxbb_cts_amclk.hw,
2545 		[CLKID_CTS_AMCLK_SEL]	    = &gxbb_cts_amclk_sel.hw,
2546 		[CLKID_CTS_AMCLK_DIV]	    = &gxbb_cts_amclk_div.hw,
2547 		[CLKID_CTS_MCLK_I958]	    = &gxbb_cts_mclk_i958.hw,
2548 		[CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
2549 		[CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
2550 		[CLKID_CTS_I958]	    = &gxbb_cts_i958.hw,
2551 		[CLKID_32K_CLK]		    = &gxbb_32k_clk.hw,
2552 		[CLKID_32K_CLK_SEL]	    = &gxbb_32k_clk_sel.hw,
2553 		[CLKID_32K_CLK_DIV]	    = &gxbb_32k_clk_div.hw,
2554 		[CLKID_SD_EMMC_A_CLK0_SEL]  = &gxbb_sd_emmc_a_clk0_sel.hw,
2555 		[CLKID_SD_EMMC_A_CLK0_DIV]  = &gxbb_sd_emmc_a_clk0_div.hw,
2556 		[CLKID_SD_EMMC_A_CLK0]	    = &gxbb_sd_emmc_a_clk0.hw,
2557 		[CLKID_SD_EMMC_B_CLK0_SEL]  = &gxbb_sd_emmc_b_clk0_sel.hw,
2558 		[CLKID_SD_EMMC_B_CLK0_DIV]  = &gxbb_sd_emmc_b_clk0_div.hw,
2559 		[CLKID_SD_EMMC_B_CLK0]	    = &gxbb_sd_emmc_b_clk0.hw,
2560 		[CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
2561 		[CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
2562 		[CLKID_SD_EMMC_C_CLK0]	    = &gxbb_sd_emmc_c_clk0.hw,
2563 		[CLKID_VPU_0_SEL]	    = &gxbb_vpu_0_sel.hw,
2564 		[CLKID_VPU_0_DIV]	    = &gxbb_vpu_0_div.hw,
2565 		[CLKID_VPU_0]		    = &gxbb_vpu_0.hw,
2566 		[CLKID_VPU_1_SEL]	    = &gxbb_vpu_1_sel.hw,
2567 		[CLKID_VPU_1_DIV]	    = &gxbb_vpu_1_div.hw,
2568 		[CLKID_VPU_1]		    = &gxbb_vpu_1.hw,
2569 		[CLKID_VPU]		    = &gxbb_vpu.hw,
2570 		[CLKID_VAPB_0_SEL]	    = &gxbb_vapb_0_sel.hw,
2571 		[CLKID_VAPB_0_DIV]	    = &gxbb_vapb_0_div.hw,
2572 		[CLKID_VAPB_0]		    = &gxbb_vapb_0.hw,
2573 		[CLKID_VAPB_1_SEL]	    = &gxbb_vapb_1_sel.hw,
2574 		[CLKID_VAPB_1_DIV]	    = &gxbb_vapb_1_div.hw,
2575 		[CLKID_VAPB_1]		    = &gxbb_vapb_1.hw,
2576 		[CLKID_VAPB_SEL]	    = &gxbb_vapb_sel.hw,
2577 		[CLKID_VAPB]		    = &gxbb_vapb.hw,
2578 		[CLKID_HDMI_PLL_PRE_MULT]   = &gxbb_hdmi_pll_pre_mult.hw,
2579 		[CLKID_MPLL0_DIV]	    = &gxbb_mpll0_div.hw,
2580 		[CLKID_MPLL1_DIV]	    = &gxbb_mpll1_div.hw,
2581 		[CLKID_MPLL2_DIV]	    = &gxbb_mpll2_div.hw,
2582 		[CLKID_MPLL_PREDIV]	    = &gxbb_mpll_prediv.hw,
2583 		[CLKID_FCLK_DIV2_DIV]	    = &gxbb_fclk_div2_div.hw,
2584 		[CLKID_FCLK_DIV3_DIV]	    = &gxbb_fclk_div3_div.hw,
2585 		[CLKID_FCLK_DIV4_DIV]	    = &gxbb_fclk_div4_div.hw,
2586 		[CLKID_FCLK_DIV5_DIV]	    = &gxbb_fclk_div5_div.hw,
2587 		[CLKID_FCLK_DIV7_DIV]	    = &gxbb_fclk_div7_div.hw,
2588 		[CLKID_VDEC_1_SEL]	    = &gxbb_vdec_1_sel.hw,
2589 		[CLKID_VDEC_1_DIV]	    = &gxbb_vdec_1_div.hw,
2590 		[CLKID_VDEC_1]		    = &gxbb_vdec_1.hw,
2591 		[CLKID_VDEC_HEVC_SEL]	    = &gxbb_vdec_hevc_sel.hw,
2592 		[CLKID_VDEC_HEVC_DIV]	    = &gxbb_vdec_hevc_div.hw,
2593 		[CLKID_VDEC_HEVC]	    = &gxbb_vdec_hevc.hw,
2594 		[CLKID_GEN_CLK_SEL]	    = &gxbb_gen_clk_sel.hw,
2595 		[CLKID_GEN_CLK_DIV]	    = &gxbb_gen_clk_div.hw,
2596 		[CLKID_GEN_CLK]		    = &gxbb_gen_clk.hw,
2597 		[CLKID_FIXED_PLL_DCO]	    = &gxbb_fixed_pll_dco.hw,
2598 		[CLKID_HDMI_PLL_DCO]	    = &gxbb_hdmi_pll_dco.hw,
2599 		[CLKID_HDMI_PLL_OD]	    = &gxbb_hdmi_pll_od.hw,
2600 		[CLKID_HDMI_PLL_OD2]	    = &gxbb_hdmi_pll_od2.hw,
2601 		[CLKID_SYS_PLL_DCO]	    = &gxbb_sys_pll_dco.hw,
2602 		[CLKID_GP0_PLL_DCO]	    = &gxbb_gp0_pll_dco.hw,
2603 		[CLKID_VID_PLL_DIV]	    = &gxbb_vid_pll_div.hw,
2604 		[CLKID_VID_PLL_SEL]	    = &gxbb_vid_pll_sel.hw,
2605 		[CLKID_VID_PLL]		    = &gxbb_vid_pll.hw,
2606 		[CLKID_VCLK_SEL]	    = &gxbb_vclk_sel.hw,
2607 		[CLKID_VCLK2_SEL]	    = &gxbb_vclk2_sel.hw,
2608 		[CLKID_VCLK_INPUT]	    = &gxbb_vclk_input.hw,
2609 		[CLKID_VCLK2_INPUT]	    = &gxbb_vclk2_input.hw,
2610 		[CLKID_VCLK_DIV]	    = &gxbb_vclk_div.hw,
2611 		[CLKID_VCLK2_DIV]	    = &gxbb_vclk2_div.hw,
2612 		[CLKID_VCLK]		    = &gxbb_vclk.hw,
2613 		[CLKID_VCLK2]		    = &gxbb_vclk2.hw,
2614 		[CLKID_VCLK_DIV1]	    = &gxbb_vclk_div1.hw,
2615 		[CLKID_VCLK_DIV2_EN]	    = &gxbb_vclk_div2_en.hw,
2616 		[CLKID_VCLK_DIV2]	    = &gxbb_vclk_div2.hw,
2617 		[CLKID_VCLK_DIV4_EN]	    = &gxbb_vclk_div4_en.hw,
2618 		[CLKID_VCLK_DIV4]	    = &gxbb_vclk_div4.hw,
2619 		[CLKID_VCLK_DIV6_EN]	    = &gxbb_vclk_div6_en.hw,
2620 		[CLKID_VCLK_DIV6]	    = &gxbb_vclk_div6.hw,
2621 		[CLKID_VCLK_DIV12_EN]	    = &gxbb_vclk_div12_en.hw,
2622 		[CLKID_VCLK_DIV12]	    = &gxbb_vclk_div12.hw,
2623 		[CLKID_VCLK2_DIV1]	    = &gxbb_vclk2_div1.hw,
2624 		[CLKID_VCLK2_DIV2_EN]	    = &gxbb_vclk2_div2_en.hw,
2625 		[CLKID_VCLK2_DIV2]	    = &gxbb_vclk2_div2.hw,
2626 		[CLKID_VCLK2_DIV4_EN]	    = &gxbb_vclk2_div4_en.hw,
2627 		[CLKID_VCLK2_DIV4]	    = &gxbb_vclk2_div4.hw,
2628 		[CLKID_VCLK2_DIV6_EN]	    = &gxbb_vclk2_div6_en.hw,
2629 		[CLKID_VCLK2_DIV6]	    = &gxbb_vclk2_div6.hw,
2630 		[CLKID_VCLK2_DIV12_EN]	    = &gxbb_vclk2_div12_en.hw,
2631 		[CLKID_VCLK2_DIV12]	    = &gxbb_vclk2_div12.hw,
2632 		[CLKID_CTS_ENCI_SEL]	    = &gxbb_cts_enci_sel.hw,
2633 		[CLKID_CTS_ENCP_SEL]	    = &gxbb_cts_encp_sel.hw,
2634 		[CLKID_CTS_VDAC_SEL]	    = &gxbb_cts_vdac_sel.hw,
2635 		[CLKID_HDMI_TX_SEL]	    = &gxbb_hdmi_tx_sel.hw,
2636 		[CLKID_CTS_ENCI]	    = &gxbb_cts_enci.hw,
2637 		[CLKID_CTS_ENCP]	    = &gxbb_cts_encp.hw,
2638 		[CLKID_CTS_VDAC]	    = &gxbb_cts_vdac.hw,
2639 		[CLKID_HDMI_TX]		    = &gxbb_hdmi_tx.hw,
2640 		[CLKID_HDMI_SEL]	    = &gxbb_hdmi_sel.hw,
2641 		[CLKID_HDMI_DIV]	    = &gxbb_hdmi_div.hw,
2642 		[CLKID_HDMI]		    = &gxbb_hdmi.hw,
2643 		[NR_CLKS]		    = NULL,
2644 	},
2645 	.num = NR_CLKS,
2646 };
2647 
2648 static struct clk_hw_onecell_data gxl_hw_onecell_data = {
2649 	.hws = {
2650 		[CLKID_SYS_PLL]		    = &gxbb_sys_pll.hw,
2651 		[CLKID_HDMI_PLL]	    = &gxl_hdmi_pll.hw,
2652 		[CLKID_FIXED_PLL]	    = &gxbb_fixed_pll.hw,
2653 		[CLKID_FCLK_DIV2]	    = &gxbb_fclk_div2.hw,
2654 		[CLKID_FCLK_DIV3]	    = &gxbb_fclk_div3.hw,
2655 		[CLKID_FCLK_DIV4]	    = &gxbb_fclk_div4.hw,
2656 		[CLKID_FCLK_DIV5]	    = &gxbb_fclk_div5.hw,
2657 		[CLKID_FCLK_DIV7]	    = &gxbb_fclk_div7.hw,
2658 		[CLKID_GP0_PLL]		    = &gxbb_gp0_pll.hw,
2659 		[CLKID_MPEG_SEL]	    = &gxbb_mpeg_clk_sel.hw,
2660 		[CLKID_MPEG_DIV]	    = &gxbb_mpeg_clk_div.hw,
2661 		[CLKID_CLK81]		    = &gxbb_clk81.hw,
2662 		[CLKID_MPLL0]		    = &gxbb_mpll0.hw,
2663 		[CLKID_MPLL1]		    = &gxbb_mpll1.hw,
2664 		[CLKID_MPLL2]		    = &gxbb_mpll2.hw,
2665 		[CLKID_DDR]		    = &gxbb_ddr.hw,
2666 		[CLKID_DOS]		    = &gxbb_dos.hw,
2667 		[CLKID_ISA]		    = &gxbb_isa.hw,
2668 		[CLKID_PL301]		    = &gxbb_pl301.hw,
2669 		[CLKID_PERIPHS]		    = &gxbb_periphs.hw,
2670 		[CLKID_SPICC]		    = &gxbb_spicc.hw,
2671 		[CLKID_I2C]		    = &gxbb_i2c.hw,
2672 		[CLKID_SAR_ADC]		    = &gxbb_sar_adc.hw,
2673 		[CLKID_SMART_CARD]	    = &gxbb_smart_card.hw,
2674 		[CLKID_RNG0]		    = &gxbb_rng0.hw,
2675 		[CLKID_UART0]		    = &gxbb_uart0.hw,
2676 		[CLKID_SDHC]		    = &gxbb_sdhc.hw,
2677 		[CLKID_STREAM]		    = &gxbb_stream.hw,
2678 		[CLKID_ASYNC_FIFO]	    = &gxbb_async_fifo.hw,
2679 		[CLKID_SDIO]		    = &gxbb_sdio.hw,
2680 		[CLKID_ABUF]		    = &gxbb_abuf.hw,
2681 		[CLKID_HIU_IFACE]	    = &gxbb_hiu_iface.hw,
2682 		[CLKID_ASSIST_MISC]	    = &gxbb_assist_misc.hw,
2683 		[CLKID_SPI]		    = &gxbb_spi.hw,
2684 		[CLKID_I2S_SPDIF]	    = &gxbb_i2s_spdif.hw,
2685 		[CLKID_ETH]		    = &gxbb_eth.hw,
2686 		[CLKID_DEMUX]		    = &gxbb_demux.hw,
2687 		[CLKID_AIU_GLUE]	    = &gxbb_aiu_glue.hw,
2688 		[CLKID_IEC958]		    = &gxbb_iec958.hw,
2689 		[CLKID_I2S_OUT]		    = &gxbb_i2s_out.hw,
2690 		[CLKID_AMCLK]		    = &gxbb_amclk.hw,
2691 		[CLKID_AIFIFO2]		    = &gxbb_aififo2.hw,
2692 		[CLKID_MIXER]		    = &gxbb_mixer.hw,
2693 		[CLKID_MIXER_IFACE]	    = &gxbb_mixer_iface.hw,
2694 		[CLKID_ADC]		    = &gxbb_adc.hw,
2695 		[CLKID_BLKMV]		    = &gxbb_blkmv.hw,
2696 		[CLKID_AIU]		    = &gxbb_aiu.hw,
2697 		[CLKID_UART1]		    = &gxbb_uart1.hw,
2698 		[CLKID_G2D]		    = &gxbb_g2d.hw,
2699 		[CLKID_USB0]		    = &gxbb_usb0.hw,
2700 		[CLKID_USB1]		    = &gxbb_usb1.hw,
2701 		[CLKID_RESET]		    = &gxbb_reset.hw,
2702 		[CLKID_NAND]		    = &gxbb_nand.hw,
2703 		[CLKID_DOS_PARSER]	    = &gxbb_dos_parser.hw,
2704 		[CLKID_USB]		    = &gxbb_usb.hw,
2705 		[CLKID_VDIN1]		    = &gxbb_vdin1.hw,
2706 		[CLKID_AHB_ARB0]	    = &gxbb_ahb_arb0.hw,
2707 		[CLKID_EFUSE]		    = &gxbb_efuse.hw,
2708 		[CLKID_BOOT_ROM]	    = &gxbb_boot_rom.hw,
2709 		[CLKID_AHB_DATA_BUS]	    = &gxbb_ahb_data_bus.hw,
2710 		[CLKID_AHB_CTRL_BUS]	    = &gxbb_ahb_ctrl_bus.hw,
2711 		[CLKID_HDMI_INTR_SYNC]	    = &gxbb_hdmi_intr_sync.hw,
2712 		[CLKID_HDMI_PCLK]	    = &gxbb_hdmi_pclk.hw,
2713 		[CLKID_USB1_DDR_BRIDGE]	    = &gxbb_usb1_ddr_bridge.hw,
2714 		[CLKID_USB0_DDR_BRIDGE]	    = &gxbb_usb0_ddr_bridge.hw,
2715 		[CLKID_MMC_PCLK]	    = &gxbb_mmc_pclk.hw,
2716 		[CLKID_DVIN]		    = &gxbb_dvin.hw,
2717 		[CLKID_UART2]		    = &gxbb_uart2.hw,
2718 		[CLKID_SANA]		    = &gxbb_sana.hw,
2719 		[CLKID_VPU_INTR]	    = &gxbb_vpu_intr.hw,
2720 		[CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
2721 		[CLKID_CLK81_A53]	    = &gxbb_clk81_a53.hw,
2722 		[CLKID_VCLK2_VENCI0]	    = &gxbb_vclk2_venci0.hw,
2723 		[CLKID_VCLK2_VENCI1]	    = &gxbb_vclk2_venci1.hw,
2724 		[CLKID_VCLK2_VENCP0]	    = &gxbb_vclk2_vencp0.hw,
2725 		[CLKID_VCLK2_VENCP1]	    = &gxbb_vclk2_vencp1.hw,
2726 		[CLKID_GCLK_VENCI_INT0]	    = &gxbb_gclk_venci_int0.hw,
2727 		[CLKID_GCLK_VENCI_INT]	    = &gxbb_gclk_vencp_int.hw,
2728 		[CLKID_DAC_CLK]		    = &gxbb_dac_clk.hw,
2729 		[CLKID_AOCLK_GATE]	    = &gxbb_aoclk_gate.hw,
2730 		[CLKID_IEC958_GATE]	    = &gxbb_iec958_gate.hw,
2731 		[CLKID_ENC480P]		    = &gxbb_enc480p.hw,
2732 		[CLKID_RNG1]		    = &gxbb_rng1.hw,
2733 		[CLKID_GCLK_VENCI_INT1]	    = &gxbb_gclk_venci_int1.hw,
2734 		[CLKID_VCLK2_VENCLMCC]	    = &gxbb_vclk2_venclmcc.hw,
2735 		[CLKID_VCLK2_VENCL]	    = &gxbb_vclk2_vencl.hw,
2736 		[CLKID_VCLK_OTHER]	    = &gxbb_vclk_other.hw,
2737 		[CLKID_EDP]		    = &gxbb_edp.hw,
2738 		[CLKID_AO_MEDIA_CPU]	    = &gxbb_ao_media_cpu.hw,
2739 		[CLKID_AO_AHB_SRAM]	    = &gxbb_ao_ahb_sram.hw,
2740 		[CLKID_AO_AHB_BUS]	    = &gxbb_ao_ahb_bus.hw,
2741 		[CLKID_AO_IFACE]	    = &gxbb_ao_iface.hw,
2742 		[CLKID_AO_I2C]		    = &gxbb_ao_i2c.hw,
2743 		[CLKID_SD_EMMC_A]	    = &gxbb_emmc_a.hw,
2744 		[CLKID_SD_EMMC_B]	    = &gxbb_emmc_b.hw,
2745 		[CLKID_SD_EMMC_C]	    = &gxbb_emmc_c.hw,
2746 		[CLKID_SAR_ADC_CLK]	    = &gxbb_sar_adc_clk.hw,
2747 		[CLKID_SAR_ADC_SEL]	    = &gxbb_sar_adc_clk_sel.hw,
2748 		[CLKID_SAR_ADC_DIV]	    = &gxbb_sar_adc_clk_div.hw,
2749 		[CLKID_MALI_0_SEL]	    = &gxbb_mali_0_sel.hw,
2750 		[CLKID_MALI_0_DIV]	    = &gxbb_mali_0_div.hw,
2751 		[CLKID_MALI_0]		    = &gxbb_mali_0.hw,
2752 		[CLKID_MALI_1_SEL]	    = &gxbb_mali_1_sel.hw,
2753 		[CLKID_MALI_1_DIV]	    = &gxbb_mali_1_div.hw,
2754 		[CLKID_MALI_1]		    = &gxbb_mali_1.hw,
2755 		[CLKID_MALI]		    = &gxbb_mali.hw,
2756 		[CLKID_CTS_AMCLK]	    = &gxbb_cts_amclk.hw,
2757 		[CLKID_CTS_AMCLK_SEL]	    = &gxbb_cts_amclk_sel.hw,
2758 		[CLKID_CTS_AMCLK_DIV]	    = &gxbb_cts_amclk_div.hw,
2759 		[CLKID_CTS_MCLK_I958]	    = &gxbb_cts_mclk_i958.hw,
2760 		[CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
2761 		[CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
2762 		[CLKID_CTS_I958]	    = &gxbb_cts_i958.hw,
2763 		[CLKID_32K_CLK]		    = &gxbb_32k_clk.hw,
2764 		[CLKID_32K_CLK_SEL]	    = &gxbb_32k_clk_sel.hw,
2765 		[CLKID_32K_CLK_DIV]	    = &gxbb_32k_clk_div.hw,
2766 		[CLKID_SD_EMMC_A_CLK0_SEL]  = &gxbb_sd_emmc_a_clk0_sel.hw,
2767 		[CLKID_SD_EMMC_A_CLK0_DIV]  = &gxbb_sd_emmc_a_clk0_div.hw,
2768 		[CLKID_SD_EMMC_A_CLK0]	    = &gxbb_sd_emmc_a_clk0.hw,
2769 		[CLKID_SD_EMMC_B_CLK0_SEL]  = &gxbb_sd_emmc_b_clk0_sel.hw,
2770 		[CLKID_SD_EMMC_B_CLK0_DIV]  = &gxbb_sd_emmc_b_clk0_div.hw,
2771 		[CLKID_SD_EMMC_B_CLK0]	    = &gxbb_sd_emmc_b_clk0.hw,
2772 		[CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
2773 		[CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
2774 		[CLKID_SD_EMMC_C_CLK0]	    = &gxbb_sd_emmc_c_clk0.hw,
2775 		[CLKID_VPU_0_SEL]	    = &gxbb_vpu_0_sel.hw,
2776 		[CLKID_VPU_0_DIV]	    = &gxbb_vpu_0_div.hw,
2777 		[CLKID_VPU_0]		    = &gxbb_vpu_0.hw,
2778 		[CLKID_VPU_1_SEL]	    = &gxbb_vpu_1_sel.hw,
2779 		[CLKID_VPU_1_DIV]	    = &gxbb_vpu_1_div.hw,
2780 		[CLKID_VPU_1]		    = &gxbb_vpu_1.hw,
2781 		[CLKID_VPU]		    = &gxbb_vpu.hw,
2782 		[CLKID_VAPB_0_SEL]	    = &gxbb_vapb_0_sel.hw,
2783 		[CLKID_VAPB_0_DIV]	    = &gxbb_vapb_0_div.hw,
2784 		[CLKID_VAPB_0]		    = &gxbb_vapb_0.hw,
2785 		[CLKID_VAPB_1_SEL]	    = &gxbb_vapb_1_sel.hw,
2786 		[CLKID_VAPB_1_DIV]	    = &gxbb_vapb_1_div.hw,
2787 		[CLKID_VAPB_1]		    = &gxbb_vapb_1.hw,
2788 		[CLKID_VAPB_SEL]	    = &gxbb_vapb_sel.hw,
2789 		[CLKID_VAPB]		    = &gxbb_vapb.hw,
2790 		[CLKID_MPLL0_DIV]	    = &gxbb_mpll0_div.hw,
2791 		[CLKID_MPLL1_DIV]	    = &gxbb_mpll1_div.hw,
2792 		[CLKID_MPLL2_DIV]	    = &gxbb_mpll2_div.hw,
2793 		[CLKID_MPLL_PREDIV]	    = &gxbb_mpll_prediv.hw,
2794 		[CLKID_FCLK_DIV2_DIV]	    = &gxbb_fclk_div2_div.hw,
2795 		[CLKID_FCLK_DIV3_DIV]	    = &gxbb_fclk_div3_div.hw,
2796 		[CLKID_FCLK_DIV4_DIV]	    = &gxbb_fclk_div4_div.hw,
2797 		[CLKID_FCLK_DIV5_DIV]	    = &gxbb_fclk_div5_div.hw,
2798 		[CLKID_FCLK_DIV7_DIV]	    = &gxbb_fclk_div7_div.hw,
2799 		[CLKID_VDEC_1_SEL]	    = &gxbb_vdec_1_sel.hw,
2800 		[CLKID_VDEC_1_DIV]	    = &gxbb_vdec_1_div.hw,
2801 		[CLKID_VDEC_1]		    = &gxbb_vdec_1.hw,
2802 		[CLKID_VDEC_HEVC_SEL]	    = &gxbb_vdec_hevc_sel.hw,
2803 		[CLKID_VDEC_HEVC_DIV]	    = &gxbb_vdec_hevc_div.hw,
2804 		[CLKID_VDEC_HEVC]	    = &gxbb_vdec_hevc.hw,
2805 		[CLKID_GEN_CLK_SEL]	    = &gxbb_gen_clk_sel.hw,
2806 		[CLKID_GEN_CLK_DIV]	    = &gxbb_gen_clk_div.hw,
2807 		[CLKID_GEN_CLK]		    = &gxbb_gen_clk.hw,
2808 		[CLKID_FIXED_PLL_DCO]	    = &gxbb_fixed_pll_dco.hw,
2809 		[CLKID_HDMI_PLL_DCO]	    = &gxl_hdmi_pll_dco.hw,
2810 		[CLKID_HDMI_PLL_OD]	    = &gxl_hdmi_pll_od.hw,
2811 		[CLKID_HDMI_PLL_OD2]	    = &gxl_hdmi_pll_od2.hw,
2812 		[CLKID_SYS_PLL_DCO]	    = &gxbb_sys_pll_dco.hw,
2813 		[CLKID_GP0_PLL_DCO]	    = &gxl_gp0_pll_dco.hw,
2814 		[CLKID_VID_PLL_DIV]	    = &gxbb_vid_pll_div.hw,
2815 		[CLKID_VID_PLL_SEL]	    = &gxbb_vid_pll_sel.hw,
2816 		[CLKID_VID_PLL]		    = &gxbb_vid_pll.hw,
2817 		[CLKID_VCLK_SEL]	    = &gxbb_vclk_sel.hw,
2818 		[CLKID_VCLK2_SEL]	    = &gxbb_vclk2_sel.hw,
2819 		[CLKID_VCLK_INPUT]	    = &gxbb_vclk_input.hw,
2820 		[CLKID_VCLK2_INPUT]	    = &gxbb_vclk2_input.hw,
2821 		[CLKID_VCLK_DIV]	    = &gxbb_vclk_div.hw,
2822 		[CLKID_VCLK2_DIV]	    = &gxbb_vclk2_div.hw,
2823 		[CLKID_VCLK]		    = &gxbb_vclk.hw,
2824 		[CLKID_VCLK2]		    = &gxbb_vclk2.hw,
2825 		[CLKID_VCLK_DIV1]	    = &gxbb_vclk_div1.hw,
2826 		[CLKID_VCLK_DIV2_EN]	    = &gxbb_vclk_div2_en.hw,
2827 		[CLKID_VCLK_DIV2]	    = &gxbb_vclk_div2.hw,
2828 		[CLKID_VCLK_DIV4_EN]	    = &gxbb_vclk_div4_en.hw,
2829 		[CLKID_VCLK_DIV4]	    = &gxbb_vclk_div4.hw,
2830 		[CLKID_VCLK_DIV6_EN]	    = &gxbb_vclk_div6_en.hw,
2831 		[CLKID_VCLK_DIV6]	    = &gxbb_vclk_div6.hw,
2832 		[CLKID_VCLK_DIV12_EN]	    = &gxbb_vclk_div12_en.hw,
2833 		[CLKID_VCLK_DIV12]	    = &gxbb_vclk_div12.hw,
2834 		[CLKID_VCLK2_DIV1]	    = &gxbb_vclk2_div1.hw,
2835 		[CLKID_VCLK2_DIV2_EN]	    = &gxbb_vclk2_div2_en.hw,
2836 		[CLKID_VCLK2_DIV2]	    = &gxbb_vclk2_div2.hw,
2837 		[CLKID_VCLK2_DIV4_EN]	    = &gxbb_vclk2_div4_en.hw,
2838 		[CLKID_VCLK2_DIV4]	    = &gxbb_vclk2_div4.hw,
2839 		[CLKID_VCLK2_DIV6_EN]	    = &gxbb_vclk2_div6_en.hw,
2840 		[CLKID_VCLK2_DIV6]	    = &gxbb_vclk2_div6.hw,
2841 		[CLKID_VCLK2_DIV12_EN]	    = &gxbb_vclk2_div12_en.hw,
2842 		[CLKID_VCLK2_DIV12]	    = &gxbb_vclk2_div12.hw,
2843 		[CLKID_CTS_ENCI_SEL]	    = &gxbb_cts_enci_sel.hw,
2844 		[CLKID_CTS_ENCP_SEL]	    = &gxbb_cts_encp_sel.hw,
2845 		[CLKID_CTS_VDAC_SEL]	    = &gxbb_cts_vdac_sel.hw,
2846 		[CLKID_HDMI_TX_SEL]	    = &gxbb_hdmi_tx_sel.hw,
2847 		[CLKID_CTS_ENCI]	    = &gxbb_cts_enci.hw,
2848 		[CLKID_CTS_ENCP]	    = &gxbb_cts_encp.hw,
2849 		[CLKID_CTS_VDAC]	    = &gxbb_cts_vdac.hw,
2850 		[CLKID_HDMI_TX]		    = &gxbb_hdmi_tx.hw,
2851 		[CLKID_HDMI_SEL]	    = &gxbb_hdmi_sel.hw,
2852 		[CLKID_HDMI_DIV]	    = &gxbb_hdmi_div.hw,
2853 		[CLKID_HDMI]		    = &gxbb_hdmi.hw,
2854 		[NR_CLKS]		    = NULL,
2855 	},
2856 	.num = NR_CLKS,
2857 };
2858 
2859 static struct clk_regmap *const gxbb_clk_regmaps[] = {
2860 	&gxbb_clk81,
2861 	&gxbb_ddr,
2862 	&gxbb_dos,
2863 	&gxbb_isa,
2864 	&gxbb_pl301,
2865 	&gxbb_periphs,
2866 	&gxbb_spicc,
2867 	&gxbb_i2c,
2868 	&gxbb_sar_adc,
2869 	&gxbb_smart_card,
2870 	&gxbb_rng0,
2871 	&gxbb_uart0,
2872 	&gxbb_sdhc,
2873 	&gxbb_stream,
2874 	&gxbb_async_fifo,
2875 	&gxbb_sdio,
2876 	&gxbb_abuf,
2877 	&gxbb_hiu_iface,
2878 	&gxbb_assist_misc,
2879 	&gxbb_spi,
2880 	&gxbb_i2s_spdif,
2881 	&gxbb_eth,
2882 	&gxbb_demux,
2883 	&gxbb_aiu_glue,
2884 	&gxbb_iec958,
2885 	&gxbb_i2s_out,
2886 	&gxbb_amclk,
2887 	&gxbb_aififo2,
2888 	&gxbb_mixer,
2889 	&gxbb_mixer_iface,
2890 	&gxbb_adc,
2891 	&gxbb_blkmv,
2892 	&gxbb_aiu,
2893 	&gxbb_uart1,
2894 	&gxbb_g2d,
2895 	&gxbb_usb0,
2896 	&gxbb_usb1,
2897 	&gxbb_reset,
2898 	&gxbb_nand,
2899 	&gxbb_dos_parser,
2900 	&gxbb_usb,
2901 	&gxbb_vdin1,
2902 	&gxbb_ahb_arb0,
2903 	&gxbb_efuse,
2904 	&gxbb_boot_rom,
2905 	&gxbb_ahb_data_bus,
2906 	&gxbb_ahb_ctrl_bus,
2907 	&gxbb_hdmi_intr_sync,
2908 	&gxbb_hdmi_pclk,
2909 	&gxbb_usb1_ddr_bridge,
2910 	&gxbb_usb0_ddr_bridge,
2911 	&gxbb_mmc_pclk,
2912 	&gxbb_dvin,
2913 	&gxbb_uart2,
2914 	&gxbb_sana,
2915 	&gxbb_vpu_intr,
2916 	&gxbb_sec_ahb_ahb3_bridge,
2917 	&gxbb_clk81_a53,
2918 	&gxbb_vclk2_venci0,
2919 	&gxbb_vclk2_venci1,
2920 	&gxbb_vclk2_vencp0,
2921 	&gxbb_vclk2_vencp1,
2922 	&gxbb_gclk_venci_int0,
2923 	&gxbb_gclk_vencp_int,
2924 	&gxbb_dac_clk,
2925 	&gxbb_aoclk_gate,
2926 	&gxbb_iec958_gate,
2927 	&gxbb_enc480p,
2928 	&gxbb_rng1,
2929 	&gxbb_gclk_venci_int1,
2930 	&gxbb_vclk2_venclmcc,
2931 	&gxbb_vclk2_vencl,
2932 	&gxbb_vclk_other,
2933 	&gxbb_edp,
2934 	&gxbb_ao_media_cpu,
2935 	&gxbb_ao_ahb_sram,
2936 	&gxbb_ao_ahb_bus,
2937 	&gxbb_ao_iface,
2938 	&gxbb_ao_i2c,
2939 	&gxbb_emmc_a,
2940 	&gxbb_emmc_b,
2941 	&gxbb_emmc_c,
2942 	&gxbb_sar_adc_clk,
2943 	&gxbb_mali_0,
2944 	&gxbb_mali_1,
2945 	&gxbb_cts_amclk,
2946 	&gxbb_cts_mclk_i958,
2947 	&gxbb_32k_clk,
2948 	&gxbb_sd_emmc_a_clk0,
2949 	&gxbb_sd_emmc_b_clk0,
2950 	&gxbb_sd_emmc_c_clk0,
2951 	&gxbb_vpu_0,
2952 	&gxbb_vpu_1,
2953 	&gxbb_vapb_0,
2954 	&gxbb_vapb_1,
2955 	&gxbb_vapb,
2956 	&gxbb_mpeg_clk_div,
2957 	&gxbb_sar_adc_clk_div,
2958 	&gxbb_mali_0_div,
2959 	&gxbb_mali_1_div,
2960 	&gxbb_cts_mclk_i958_div,
2961 	&gxbb_32k_clk_div,
2962 	&gxbb_sd_emmc_a_clk0_div,
2963 	&gxbb_sd_emmc_b_clk0_div,
2964 	&gxbb_sd_emmc_c_clk0_div,
2965 	&gxbb_vpu_0_div,
2966 	&gxbb_vpu_1_div,
2967 	&gxbb_vapb_0_div,
2968 	&gxbb_vapb_1_div,
2969 	&gxbb_mpeg_clk_sel,
2970 	&gxbb_sar_adc_clk_sel,
2971 	&gxbb_mali_0_sel,
2972 	&gxbb_mali_1_sel,
2973 	&gxbb_mali,
2974 	&gxbb_cts_amclk_sel,
2975 	&gxbb_cts_mclk_i958_sel,
2976 	&gxbb_cts_i958,
2977 	&gxbb_32k_clk_sel,
2978 	&gxbb_sd_emmc_a_clk0_sel,
2979 	&gxbb_sd_emmc_b_clk0_sel,
2980 	&gxbb_sd_emmc_c_clk0_sel,
2981 	&gxbb_vpu_0_sel,
2982 	&gxbb_vpu_1_sel,
2983 	&gxbb_vpu,
2984 	&gxbb_vapb_0_sel,
2985 	&gxbb_vapb_1_sel,
2986 	&gxbb_vapb_sel,
2987 	&gxbb_mpll0,
2988 	&gxbb_mpll1,
2989 	&gxbb_mpll2,
2990 	&gxbb_mpll0_div,
2991 	&gxbb_mpll1_div,
2992 	&gxbb_mpll2_div,
2993 	&gxbb_cts_amclk_div,
2994 	&gxbb_fixed_pll,
2995 	&gxbb_sys_pll,
2996 	&gxbb_mpll_prediv,
2997 	&gxbb_fclk_div2,
2998 	&gxbb_fclk_div3,
2999 	&gxbb_fclk_div4,
3000 	&gxbb_fclk_div5,
3001 	&gxbb_fclk_div7,
3002 	&gxbb_vdec_1_sel,
3003 	&gxbb_vdec_1_div,
3004 	&gxbb_vdec_1,
3005 	&gxbb_vdec_hevc_sel,
3006 	&gxbb_vdec_hevc_div,
3007 	&gxbb_vdec_hevc,
3008 	&gxbb_gen_clk_sel,
3009 	&gxbb_gen_clk_div,
3010 	&gxbb_gen_clk,
3011 	&gxbb_fixed_pll_dco,
3012 	&gxbb_sys_pll_dco,
3013 	&gxbb_gp0_pll,
3014 	&gxbb_vid_pll,
3015 	&gxbb_vid_pll_sel,
3016 	&gxbb_vid_pll_div,
3017 	&gxbb_vclk,
3018 	&gxbb_vclk_sel,
3019 	&gxbb_vclk_div,
3020 	&gxbb_vclk_input,
3021 	&gxbb_vclk_div1,
3022 	&gxbb_vclk_div2_en,
3023 	&gxbb_vclk_div4_en,
3024 	&gxbb_vclk_div6_en,
3025 	&gxbb_vclk_div12_en,
3026 	&gxbb_vclk2,
3027 	&gxbb_vclk2_sel,
3028 	&gxbb_vclk2_div,
3029 	&gxbb_vclk2_input,
3030 	&gxbb_vclk2_div1,
3031 	&gxbb_vclk2_div2_en,
3032 	&gxbb_vclk2_div4_en,
3033 	&gxbb_vclk2_div6_en,
3034 	&gxbb_vclk2_div12_en,
3035 	&gxbb_cts_enci,
3036 	&gxbb_cts_enci_sel,
3037 	&gxbb_cts_encp,
3038 	&gxbb_cts_encp_sel,
3039 	&gxbb_cts_vdac,
3040 	&gxbb_cts_vdac_sel,
3041 	&gxbb_hdmi_tx,
3042 	&gxbb_hdmi_tx_sel,
3043 	&gxbb_hdmi_sel,
3044 	&gxbb_hdmi_div,
3045 	&gxbb_hdmi,
3046 	&gxbb_gp0_pll_dco,
3047 	&gxbb_hdmi_pll,
3048 	&gxbb_hdmi_pll_od,
3049 	&gxbb_hdmi_pll_od2,
3050 	&gxbb_hdmi_pll_dco,
3051 };
3052 
3053 static struct clk_regmap *const gxl_clk_regmaps[] = {
3054 	&gxbb_clk81,
3055 	&gxbb_ddr,
3056 	&gxbb_dos,
3057 	&gxbb_isa,
3058 	&gxbb_pl301,
3059 	&gxbb_periphs,
3060 	&gxbb_spicc,
3061 	&gxbb_i2c,
3062 	&gxbb_sar_adc,
3063 	&gxbb_smart_card,
3064 	&gxbb_rng0,
3065 	&gxbb_uart0,
3066 	&gxbb_sdhc,
3067 	&gxbb_stream,
3068 	&gxbb_async_fifo,
3069 	&gxbb_sdio,
3070 	&gxbb_abuf,
3071 	&gxbb_hiu_iface,
3072 	&gxbb_assist_misc,
3073 	&gxbb_spi,
3074 	&gxbb_i2s_spdif,
3075 	&gxbb_eth,
3076 	&gxbb_demux,
3077 	&gxbb_aiu_glue,
3078 	&gxbb_iec958,
3079 	&gxbb_i2s_out,
3080 	&gxbb_amclk,
3081 	&gxbb_aififo2,
3082 	&gxbb_mixer,
3083 	&gxbb_mixer_iface,
3084 	&gxbb_adc,
3085 	&gxbb_blkmv,
3086 	&gxbb_aiu,
3087 	&gxbb_uart1,
3088 	&gxbb_g2d,
3089 	&gxbb_usb0,
3090 	&gxbb_usb1,
3091 	&gxbb_reset,
3092 	&gxbb_nand,
3093 	&gxbb_dos_parser,
3094 	&gxbb_usb,
3095 	&gxbb_vdin1,
3096 	&gxbb_ahb_arb0,
3097 	&gxbb_efuse,
3098 	&gxbb_boot_rom,
3099 	&gxbb_ahb_data_bus,
3100 	&gxbb_ahb_ctrl_bus,
3101 	&gxbb_hdmi_intr_sync,
3102 	&gxbb_hdmi_pclk,
3103 	&gxbb_usb1_ddr_bridge,
3104 	&gxbb_usb0_ddr_bridge,
3105 	&gxbb_mmc_pclk,
3106 	&gxbb_dvin,
3107 	&gxbb_uart2,
3108 	&gxbb_sana,
3109 	&gxbb_vpu_intr,
3110 	&gxbb_sec_ahb_ahb3_bridge,
3111 	&gxbb_clk81_a53,
3112 	&gxbb_vclk2_venci0,
3113 	&gxbb_vclk2_venci1,
3114 	&gxbb_vclk2_vencp0,
3115 	&gxbb_vclk2_vencp1,
3116 	&gxbb_gclk_venci_int0,
3117 	&gxbb_gclk_vencp_int,
3118 	&gxbb_dac_clk,
3119 	&gxbb_aoclk_gate,
3120 	&gxbb_iec958_gate,
3121 	&gxbb_enc480p,
3122 	&gxbb_rng1,
3123 	&gxbb_gclk_venci_int1,
3124 	&gxbb_vclk2_venclmcc,
3125 	&gxbb_vclk2_vencl,
3126 	&gxbb_vclk_other,
3127 	&gxbb_edp,
3128 	&gxbb_ao_media_cpu,
3129 	&gxbb_ao_ahb_sram,
3130 	&gxbb_ao_ahb_bus,
3131 	&gxbb_ao_iface,
3132 	&gxbb_ao_i2c,
3133 	&gxbb_emmc_a,
3134 	&gxbb_emmc_b,
3135 	&gxbb_emmc_c,
3136 	&gxbb_sar_adc_clk,
3137 	&gxbb_mali_0,
3138 	&gxbb_mali_1,
3139 	&gxbb_cts_amclk,
3140 	&gxbb_cts_mclk_i958,
3141 	&gxbb_32k_clk,
3142 	&gxbb_sd_emmc_a_clk0,
3143 	&gxbb_sd_emmc_b_clk0,
3144 	&gxbb_sd_emmc_c_clk0,
3145 	&gxbb_vpu_0,
3146 	&gxbb_vpu_1,
3147 	&gxbb_vapb_0,
3148 	&gxbb_vapb_1,
3149 	&gxbb_vapb,
3150 	&gxbb_mpeg_clk_div,
3151 	&gxbb_sar_adc_clk_div,
3152 	&gxbb_mali_0_div,
3153 	&gxbb_mali_1_div,
3154 	&gxbb_cts_mclk_i958_div,
3155 	&gxbb_32k_clk_div,
3156 	&gxbb_sd_emmc_a_clk0_div,
3157 	&gxbb_sd_emmc_b_clk0_div,
3158 	&gxbb_sd_emmc_c_clk0_div,
3159 	&gxbb_vpu_0_div,
3160 	&gxbb_vpu_1_div,
3161 	&gxbb_vapb_0_div,
3162 	&gxbb_vapb_1_div,
3163 	&gxbb_mpeg_clk_sel,
3164 	&gxbb_sar_adc_clk_sel,
3165 	&gxbb_mali_0_sel,
3166 	&gxbb_mali_1_sel,
3167 	&gxbb_mali,
3168 	&gxbb_cts_amclk_sel,
3169 	&gxbb_cts_mclk_i958_sel,
3170 	&gxbb_cts_i958,
3171 	&gxbb_32k_clk_sel,
3172 	&gxbb_sd_emmc_a_clk0_sel,
3173 	&gxbb_sd_emmc_b_clk0_sel,
3174 	&gxbb_sd_emmc_c_clk0_sel,
3175 	&gxbb_vpu_0_sel,
3176 	&gxbb_vpu_1_sel,
3177 	&gxbb_vpu,
3178 	&gxbb_vapb_0_sel,
3179 	&gxbb_vapb_1_sel,
3180 	&gxbb_vapb_sel,
3181 	&gxbb_mpll0,
3182 	&gxbb_mpll1,
3183 	&gxbb_mpll2,
3184 	&gxbb_mpll0_div,
3185 	&gxbb_mpll1_div,
3186 	&gxbb_mpll2_div,
3187 	&gxbb_cts_amclk_div,
3188 	&gxbb_fixed_pll,
3189 	&gxbb_sys_pll,
3190 	&gxbb_mpll_prediv,
3191 	&gxbb_fclk_div2,
3192 	&gxbb_fclk_div3,
3193 	&gxbb_fclk_div4,
3194 	&gxbb_fclk_div5,
3195 	&gxbb_fclk_div7,
3196 	&gxbb_vdec_1_sel,
3197 	&gxbb_vdec_1_div,
3198 	&gxbb_vdec_1,
3199 	&gxbb_vdec_hevc_sel,
3200 	&gxbb_vdec_hevc_div,
3201 	&gxbb_vdec_hevc,
3202 	&gxbb_gen_clk_sel,
3203 	&gxbb_gen_clk_div,
3204 	&gxbb_gen_clk,
3205 	&gxbb_fixed_pll_dco,
3206 	&gxbb_sys_pll_dco,
3207 	&gxbb_gp0_pll,
3208 	&gxbb_vid_pll,
3209 	&gxbb_vid_pll_sel,
3210 	&gxbb_vid_pll_div,
3211 	&gxbb_vclk,
3212 	&gxbb_vclk_sel,
3213 	&gxbb_vclk_div,
3214 	&gxbb_vclk_input,
3215 	&gxbb_vclk_div1,
3216 	&gxbb_vclk_div2_en,
3217 	&gxbb_vclk_div4_en,
3218 	&gxbb_vclk_div6_en,
3219 	&gxbb_vclk_div12_en,
3220 	&gxbb_vclk2,
3221 	&gxbb_vclk2_sel,
3222 	&gxbb_vclk2_div,
3223 	&gxbb_vclk2_input,
3224 	&gxbb_vclk2_div1,
3225 	&gxbb_vclk2_div2_en,
3226 	&gxbb_vclk2_div4_en,
3227 	&gxbb_vclk2_div6_en,
3228 	&gxbb_vclk2_div12_en,
3229 	&gxbb_cts_enci,
3230 	&gxbb_cts_enci_sel,
3231 	&gxbb_cts_encp,
3232 	&gxbb_cts_encp_sel,
3233 	&gxbb_cts_vdac,
3234 	&gxbb_cts_vdac_sel,
3235 	&gxbb_hdmi_tx,
3236 	&gxbb_hdmi_tx_sel,
3237 	&gxbb_hdmi_sel,
3238 	&gxbb_hdmi_div,
3239 	&gxbb_hdmi,
3240 	&gxl_gp0_pll_dco,
3241 	&gxl_hdmi_pll,
3242 	&gxl_hdmi_pll_od,
3243 	&gxl_hdmi_pll_od2,
3244 	&gxl_hdmi_pll_dco,
3245 };
3246 
3247 static const struct meson_eeclkc_data gxbb_clkc_data = {
3248 	.regmap_clks = gxbb_clk_regmaps,
3249 	.regmap_clk_num = ARRAY_SIZE(gxbb_clk_regmaps),
3250 	.hw_onecell_data = &gxbb_hw_onecell_data,
3251 };
3252 
3253 static const struct meson_eeclkc_data gxl_clkc_data = {
3254 	.regmap_clks = gxl_clk_regmaps,
3255 	.regmap_clk_num = ARRAY_SIZE(gxl_clk_regmaps),
3256 	.hw_onecell_data = &gxl_hw_onecell_data,
3257 };
3258 
3259 static const struct of_device_id clkc_match_table[] = {
3260 	{ .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
3261 	{ .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
3262 	{},
3263 };
3264 
3265 static struct platform_driver gxbb_driver = {
3266 	.probe		= meson_eeclkc_probe,
3267 	.driver		= {
3268 		.name	= "gxbb-clkc",
3269 		.of_match_table = clkc_match_table,
3270 	},
3271 };
3272 
3273 builtin_platform_driver(gxbb_driver);
3274