1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2016 AmLogic, Inc. 4 * Michael Turquette <mturquette@baylibre.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/init.h> 9 #include <linux/platform_device.h> 10 #include <linux/module.h> 11 12 #include "clk-regmap.h" 13 #include "clk-pll.h" 14 #include "clk-mpll.h" 15 #include "meson-clkc-utils.h" 16 #include "vid-pll-div.h" 17 18 #include <dt-bindings/clock/gxbb-clkc.h> 19 20 #define SCR 0x2c 21 #define TIMEOUT_VALUE 0x3c 22 23 #define HHI_GP0_PLL_CNTL 0x40 24 #define HHI_GP0_PLL_CNTL2 0x44 25 #define HHI_GP0_PLL_CNTL3 0x48 26 #define HHI_GP0_PLL_CNTL4 0x4c 27 #define HHI_GP0_PLL_CNTL5 0x50 28 #define HHI_GP0_PLL_CNTL1 0x58 29 30 #define HHI_XTAL_DIVN_CNTL 0xbc 31 #define HHI_TIMER90K 0xec 32 33 #define HHI_MEM_PD_REG0 0x100 34 #define HHI_MEM_PD_REG1 0x104 35 #define HHI_VPU_MEM_PD_REG1 0x108 36 #define HHI_VIID_CLK_DIV 0x128 37 #define HHI_VIID_CLK_CNTL 0x12c 38 39 #define HHI_GCLK_MPEG0 0x140 40 #define HHI_GCLK_MPEG1 0x144 41 #define HHI_GCLK_MPEG2 0x148 42 #define HHI_GCLK_OTHER 0x150 43 #define HHI_GCLK_AO 0x154 44 #define HHI_SYS_OSCIN_CNTL 0x158 45 #define HHI_SYS_CPU_CLK_CNTL1 0x15c 46 #define HHI_SYS_CPU_RESET_CNTL 0x160 47 #define HHI_VID_CLK_DIV 0x164 48 49 #define HHI_MPEG_CLK_CNTL 0x174 50 #define HHI_AUD_CLK_CNTL 0x178 51 #define HHI_VID_CLK_CNTL 0x17c 52 #define HHI_AUD_CLK_CNTL2 0x190 53 #define HHI_VID_CLK_CNTL2 0x194 54 #define HHI_SYS_CPU_CLK_CNTL0 0x19c 55 #define HHI_VID_PLL_CLK_DIV 0x1a0 56 #define HHI_AUD_CLK_CNTL3 0x1a4 57 #define HHI_MALI_CLK_CNTL 0x1b0 58 #define HHI_VPU_CLK_CNTL 0x1bc 59 60 #define HHI_HDMI_CLK_CNTL 0x1cc 61 #define HHI_VDEC_CLK_CNTL 0x1e0 62 #define HHI_VDEC2_CLK_CNTL 0x1e4 63 #define HHI_VDEC3_CLK_CNTL 0x1e8 64 #define HHI_VDEC4_CLK_CNTL 0x1ec 65 #define HHI_HDCP22_CLK_CNTL 0x1f0 66 #define HHI_VAPBCLK_CNTL 0x1f4 67 68 #define HHI_VPU_CLKB_CNTL 0x20c 69 #define HHI_USB_CLK_CNTL 0x220 70 #define HHI_32K_CLK_CNTL 0x224 71 #define HHI_GEN_CLK_CNTL 0x228 72 73 #define HHI_PCM_CLK_CNTL 0x258 74 #define HHI_NAND_CLK_CNTL 0x25c 75 #define HHI_SD_EMMC_CLK_CNTL 0x264 76 77 #define HHI_MPLL_CNTL 0x280 78 #define HHI_MPLL_CNTL2 0x284 79 #define HHI_MPLL_CNTL3 0x288 80 #define HHI_MPLL_CNTL4 0x28c 81 #define HHI_MPLL_CNTL5 0x290 82 #define HHI_MPLL_CNTL6 0x294 83 #define HHI_MPLL_CNTL7 0x298 84 #define HHI_MPLL_CNTL8 0x29c 85 #define HHI_MPLL_CNTL9 0x2a0 86 #define HHI_MPLL_CNTL10 0x2a4 87 88 #define HHI_MPLL3_CNTL0 0x2e0 89 #define HHI_MPLL3_CNTL1 0x2e4 90 #define HHI_VDAC_CNTL0 0x2f4 91 #define HHI_VDAC_CNTL1 0x2f8 92 93 #define HHI_SYS_PLL_CNTL 0x300 94 #define HHI_SYS_PLL_CNTL2 0x304 95 #define HHI_SYS_PLL_CNTL3 0x308 96 #define HHI_SYS_PLL_CNTL4 0x30c 97 #define HHI_SYS_PLL_CNTL5 0x310 98 #define HHI_DPLL_TOP_I 0x318 99 #define HHI_DPLL_TOP2_I 0x31c 100 #define HHI_HDMI_PLL_CNTL 0x320 101 #define HHI_HDMI_PLL_CNTL2 0x324 102 #define HHI_HDMI_PLL_CNTL3 0x328 103 #define HHI_HDMI_PLL_CNTL4 0x32c 104 #define HHI_HDMI_PLL_CNTL5 0x330 105 #define HHI_HDMI_PLL_CNTL6 0x334 106 #define HHI_HDMI_PLL_CNTL_I 0x338 107 #define HHI_HDMI_PLL_CNTL7 0x33c 108 109 #define HHI_HDMI_PHY_CNTL0 0x3a0 110 #define HHI_HDMI_PHY_CNTL1 0x3a4 111 #define HHI_HDMI_PHY_CNTL2 0x3a8 112 #define HHI_HDMI_PHY_CNTL3 0x3ac 113 114 #define HHI_VID_LOCK_CLK_CNTL 0x3c8 115 #define HHI_BT656_CLK_CNTL 0x3d4 116 #define HHI_SAR_CLK_CNTL 0x3d8 117 118 static struct clk_regmap gxbb_fixed_pll_dco = { 119 .data = &(struct meson_clk_pll_data){ 120 .en = { 121 .reg_off = HHI_MPLL_CNTL, 122 .shift = 30, 123 .width = 1, 124 }, 125 .m = { 126 .reg_off = HHI_MPLL_CNTL, 127 .shift = 0, 128 .width = 9, 129 }, 130 .n = { 131 .reg_off = HHI_MPLL_CNTL, 132 .shift = 9, 133 .width = 5, 134 }, 135 .frac = { 136 .reg_off = HHI_MPLL_CNTL2, 137 .shift = 0, 138 .width = 12, 139 }, 140 .l = { 141 .reg_off = HHI_MPLL_CNTL, 142 .shift = 31, 143 .width = 1, 144 }, 145 .rst = { 146 .reg_off = HHI_MPLL_CNTL, 147 .shift = 29, 148 .width = 1, 149 }, 150 }, 151 .hw.init = &(struct clk_init_data){ 152 .name = "fixed_pll_dco", 153 .ops = &meson_clk_pll_ro_ops, 154 .parent_data = &(const struct clk_parent_data) { 155 .fw_name = "xtal", 156 }, 157 .num_parents = 1, 158 }, 159 }; 160 161 static struct clk_regmap gxbb_fixed_pll = { 162 .data = &(struct clk_regmap_div_data){ 163 .offset = HHI_MPLL_CNTL, 164 .shift = 16, 165 .width = 2, 166 .flags = CLK_DIVIDER_POWER_OF_TWO, 167 }, 168 .hw.init = &(struct clk_init_data){ 169 .name = "fixed_pll", 170 .ops = &clk_regmap_divider_ro_ops, 171 .parent_hws = (const struct clk_hw *[]) { 172 &gxbb_fixed_pll_dco.hw 173 }, 174 .num_parents = 1, 175 /* 176 * This clock won't ever change at runtime so 177 * CLK_SET_RATE_PARENT is not required 178 */ 179 }, 180 }; 181 182 static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = { 183 .mult = 2, 184 .div = 1, 185 .hw.init = &(struct clk_init_data){ 186 .name = "hdmi_pll_pre_mult", 187 .ops = &clk_fixed_factor_ops, 188 .parent_data = &(const struct clk_parent_data) { 189 .fw_name = "xtal", 190 }, 191 .num_parents = 1, 192 }, 193 }; 194 195 static struct clk_regmap gxbb_hdmi_pll_dco = { 196 .data = &(struct meson_clk_pll_data){ 197 .en = { 198 .reg_off = HHI_HDMI_PLL_CNTL, 199 .shift = 30, 200 .width = 1, 201 }, 202 .m = { 203 .reg_off = HHI_HDMI_PLL_CNTL, 204 .shift = 0, 205 .width = 9, 206 }, 207 .n = { 208 .reg_off = HHI_HDMI_PLL_CNTL, 209 .shift = 9, 210 .width = 5, 211 }, 212 .frac = { 213 .reg_off = HHI_HDMI_PLL_CNTL2, 214 .shift = 0, 215 .width = 12, 216 }, 217 .l = { 218 .reg_off = HHI_HDMI_PLL_CNTL, 219 .shift = 31, 220 .width = 1, 221 }, 222 .rst = { 223 .reg_off = HHI_HDMI_PLL_CNTL, 224 .shift = 28, 225 .width = 1, 226 }, 227 }, 228 .hw.init = &(struct clk_init_data){ 229 .name = "hdmi_pll_dco", 230 .ops = &meson_clk_pll_ro_ops, 231 .parent_hws = (const struct clk_hw *[]) { 232 &gxbb_hdmi_pll_pre_mult.hw 233 }, 234 .num_parents = 1, 235 /* 236 * Display directly handle hdmi pll registers ATM, we need 237 * NOCACHE to keep our view of the clock as accurate as possible 238 */ 239 .flags = CLK_GET_RATE_NOCACHE, 240 }, 241 }; 242 243 static struct clk_regmap gxl_hdmi_pll_dco = { 244 .data = &(struct meson_clk_pll_data){ 245 .en = { 246 .reg_off = HHI_HDMI_PLL_CNTL, 247 .shift = 30, 248 .width = 1, 249 }, 250 .m = { 251 .reg_off = HHI_HDMI_PLL_CNTL, 252 .shift = 0, 253 .width = 9, 254 }, 255 .n = { 256 .reg_off = HHI_HDMI_PLL_CNTL, 257 .shift = 9, 258 .width = 5, 259 }, 260 /* 261 * On gxl, there is a register shift due to 262 * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb, 263 * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB 264 * instead which is defined at the same offset. 265 */ 266 .frac = { 267 .reg_off = HHI_HDMI_PLL_CNTL2, 268 .shift = 0, 269 .width = 10, 270 }, 271 .l = { 272 .reg_off = HHI_HDMI_PLL_CNTL, 273 .shift = 31, 274 .width = 1, 275 }, 276 .rst = { 277 .reg_off = HHI_HDMI_PLL_CNTL, 278 .shift = 28, 279 .width = 1, 280 }, 281 }, 282 .hw.init = &(struct clk_init_data){ 283 .name = "hdmi_pll_dco", 284 .ops = &meson_clk_pll_ro_ops, 285 .parent_data = &(const struct clk_parent_data) { 286 .fw_name = "xtal", 287 }, 288 .num_parents = 1, 289 /* 290 * Display directly handle hdmi pll registers ATM, we need 291 * NOCACHE to keep our view of the clock as accurate as possible 292 */ 293 .flags = CLK_GET_RATE_NOCACHE, 294 }, 295 }; 296 297 static struct clk_regmap gxbb_hdmi_pll_od = { 298 .data = &(struct clk_regmap_div_data){ 299 .offset = HHI_HDMI_PLL_CNTL2, 300 .shift = 16, 301 .width = 2, 302 .flags = CLK_DIVIDER_POWER_OF_TWO, 303 }, 304 .hw.init = &(struct clk_init_data){ 305 .name = "hdmi_pll_od", 306 .ops = &clk_regmap_divider_ro_ops, 307 .parent_hws = (const struct clk_hw *[]) { 308 &gxbb_hdmi_pll_dco.hw 309 }, 310 .num_parents = 1, 311 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 312 }, 313 }; 314 315 static struct clk_regmap gxbb_hdmi_pll_od2 = { 316 .data = &(struct clk_regmap_div_data){ 317 .offset = HHI_HDMI_PLL_CNTL2, 318 .shift = 22, 319 .width = 2, 320 .flags = CLK_DIVIDER_POWER_OF_TWO, 321 }, 322 .hw.init = &(struct clk_init_data){ 323 .name = "hdmi_pll_od2", 324 .ops = &clk_regmap_divider_ro_ops, 325 .parent_hws = (const struct clk_hw *[]) { 326 &gxbb_hdmi_pll_od.hw 327 }, 328 .num_parents = 1, 329 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 330 }, 331 }; 332 333 static struct clk_regmap gxbb_hdmi_pll = { 334 .data = &(struct clk_regmap_div_data){ 335 .offset = HHI_HDMI_PLL_CNTL2, 336 .shift = 18, 337 .width = 2, 338 .flags = CLK_DIVIDER_POWER_OF_TWO, 339 }, 340 .hw.init = &(struct clk_init_data){ 341 .name = "hdmi_pll", 342 .ops = &clk_regmap_divider_ro_ops, 343 .parent_hws = (const struct clk_hw *[]) { 344 &gxbb_hdmi_pll_od2.hw 345 }, 346 .num_parents = 1, 347 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 348 }, 349 }; 350 351 /* 352 * GXL hdmi OD dividers are POWER_OF_TWO dividers but limited to /4. 353 * A divider value of 3 should map to /8 but instead map /4 so ignore it. 354 */ 355 static const struct clk_div_table gxl_hdmi_pll_od_div_table[] = { 356 { .val = 0, .div = 1 }, 357 { .val = 1, .div = 2 }, 358 { .val = 2, .div = 4 }, 359 { /* sentinel */ } 360 }; 361 362 static struct clk_regmap gxl_hdmi_pll_od = { 363 .data = &(struct clk_regmap_div_data){ 364 .offset = HHI_HDMI_PLL_CNTL3, 365 .shift = 21, 366 .width = 2, 367 .table = gxl_hdmi_pll_od_div_table, 368 }, 369 .hw.init = &(struct clk_init_data){ 370 .name = "hdmi_pll_od", 371 .ops = &clk_regmap_divider_ro_ops, 372 .parent_hws = (const struct clk_hw *[]) { 373 &gxl_hdmi_pll_dco.hw 374 }, 375 .num_parents = 1, 376 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 377 }, 378 }; 379 380 static struct clk_regmap gxl_hdmi_pll_od2 = { 381 .data = &(struct clk_regmap_div_data){ 382 .offset = HHI_HDMI_PLL_CNTL3, 383 .shift = 23, 384 .width = 2, 385 .table = gxl_hdmi_pll_od_div_table, 386 }, 387 .hw.init = &(struct clk_init_data){ 388 .name = "hdmi_pll_od2", 389 .ops = &clk_regmap_divider_ro_ops, 390 .parent_hws = (const struct clk_hw *[]) { 391 &gxl_hdmi_pll_od.hw 392 }, 393 .num_parents = 1, 394 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 395 }, 396 }; 397 398 static struct clk_regmap gxl_hdmi_pll = { 399 .data = &(struct clk_regmap_div_data){ 400 .offset = HHI_HDMI_PLL_CNTL3, 401 .shift = 19, 402 .width = 2, 403 .table = gxl_hdmi_pll_od_div_table, 404 }, 405 .hw.init = &(struct clk_init_data){ 406 .name = "hdmi_pll", 407 .ops = &clk_regmap_divider_ro_ops, 408 .parent_hws = (const struct clk_hw *[]) { 409 &gxl_hdmi_pll_od2.hw 410 }, 411 .num_parents = 1, 412 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 413 }, 414 }; 415 416 static struct clk_regmap gxbb_sys_pll_dco = { 417 .data = &(struct meson_clk_pll_data){ 418 .en = { 419 .reg_off = HHI_SYS_PLL_CNTL, 420 .shift = 30, 421 .width = 1, 422 }, 423 .m = { 424 .reg_off = HHI_SYS_PLL_CNTL, 425 .shift = 0, 426 .width = 9, 427 }, 428 .n = { 429 .reg_off = HHI_SYS_PLL_CNTL, 430 .shift = 9, 431 .width = 5, 432 }, 433 .l = { 434 .reg_off = HHI_SYS_PLL_CNTL, 435 .shift = 31, 436 .width = 1, 437 }, 438 .rst = { 439 .reg_off = HHI_SYS_PLL_CNTL, 440 .shift = 29, 441 .width = 1, 442 }, 443 }, 444 .hw.init = &(struct clk_init_data){ 445 .name = "sys_pll_dco", 446 .ops = &meson_clk_pll_ro_ops, 447 .parent_data = &(const struct clk_parent_data) { 448 .fw_name = "xtal", 449 }, 450 .num_parents = 1, 451 }, 452 }; 453 454 static struct clk_regmap gxbb_sys_pll = { 455 .data = &(struct clk_regmap_div_data){ 456 .offset = HHI_SYS_PLL_CNTL, 457 .shift = 10, 458 .width = 2, 459 .flags = CLK_DIVIDER_POWER_OF_TWO, 460 }, 461 .hw.init = &(struct clk_init_data){ 462 .name = "sys_pll", 463 .ops = &clk_regmap_divider_ro_ops, 464 .parent_hws = (const struct clk_hw *[]) { 465 &gxbb_sys_pll_dco.hw 466 }, 467 .num_parents = 1, 468 .flags = CLK_SET_RATE_PARENT, 469 }, 470 }; 471 472 static const struct pll_params_table gxbb_gp0_pll_params_table[] = { 473 PLL_PARAMS(32, 1), 474 PLL_PARAMS(33, 1), 475 PLL_PARAMS(34, 1), 476 PLL_PARAMS(35, 1), 477 PLL_PARAMS(36, 1), 478 PLL_PARAMS(37, 1), 479 PLL_PARAMS(38, 1), 480 PLL_PARAMS(39, 1), 481 PLL_PARAMS(40, 1), 482 PLL_PARAMS(41, 1), 483 PLL_PARAMS(42, 1), 484 PLL_PARAMS(43, 1), 485 PLL_PARAMS(44, 1), 486 PLL_PARAMS(45, 1), 487 PLL_PARAMS(46, 1), 488 PLL_PARAMS(47, 1), 489 PLL_PARAMS(48, 1), 490 PLL_PARAMS(49, 1), 491 PLL_PARAMS(50, 1), 492 PLL_PARAMS(51, 1), 493 PLL_PARAMS(52, 1), 494 PLL_PARAMS(53, 1), 495 PLL_PARAMS(54, 1), 496 PLL_PARAMS(55, 1), 497 PLL_PARAMS(56, 1), 498 PLL_PARAMS(57, 1), 499 PLL_PARAMS(58, 1), 500 PLL_PARAMS(59, 1), 501 PLL_PARAMS(60, 1), 502 PLL_PARAMS(61, 1), 503 PLL_PARAMS(62, 1), 504 { /* sentinel */ }, 505 }; 506 507 static const struct reg_sequence gxbb_gp0_pll_init_regs[] = { 508 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 }, 509 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 }, 510 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d }, 511 }; 512 513 static struct clk_regmap gxbb_gp0_pll_dco = { 514 .data = &(struct meson_clk_pll_data){ 515 .en = { 516 .reg_off = HHI_GP0_PLL_CNTL, 517 .shift = 30, 518 .width = 1, 519 }, 520 .m = { 521 .reg_off = HHI_GP0_PLL_CNTL, 522 .shift = 0, 523 .width = 9, 524 }, 525 .n = { 526 .reg_off = HHI_GP0_PLL_CNTL, 527 .shift = 9, 528 .width = 5, 529 }, 530 .l = { 531 .reg_off = HHI_GP0_PLL_CNTL, 532 .shift = 31, 533 .width = 1, 534 }, 535 .rst = { 536 .reg_off = HHI_GP0_PLL_CNTL, 537 .shift = 29, 538 .width = 1, 539 }, 540 .table = gxbb_gp0_pll_params_table, 541 .init_regs = gxbb_gp0_pll_init_regs, 542 .init_count = ARRAY_SIZE(gxbb_gp0_pll_init_regs), 543 }, 544 .hw.init = &(struct clk_init_data){ 545 .name = "gp0_pll_dco", 546 .ops = &meson_clk_pll_ops, 547 .parent_data = &(const struct clk_parent_data) { 548 .fw_name = "xtal", 549 }, 550 .num_parents = 1, 551 }, 552 }; 553 554 static const struct pll_params_table gxl_gp0_pll_params_table[] = { 555 PLL_PARAMS(42, 1), 556 PLL_PARAMS(43, 1), 557 PLL_PARAMS(44, 1), 558 PLL_PARAMS(45, 1), 559 PLL_PARAMS(46, 1), 560 PLL_PARAMS(47, 1), 561 PLL_PARAMS(48, 1), 562 PLL_PARAMS(49, 1), 563 PLL_PARAMS(50, 1), 564 PLL_PARAMS(51, 1), 565 PLL_PARAMS(52, 1), 566 PLL_PARAMS(53, 1), 567 PLL_PARAMS(54, 1), 568 PLL_PARAMS(55, 1), 569 PLL_PARAMS(56, 1), 570 PLL_PARAMS(57, 1), 571 PLL_PARAMS(58, 1), 572 PLL_PARAMS(59, 1), 573 PLL_PARAMS(60, 1), 574 PLL_PARAMS(61, 1), 575 PLL_PARAMS(62, 1), 576 PLL_PARAMS(63, 1), 577 PLL_PARAMS(64, 1), 578 PLL_PARAMS(65, 1), 579 PLL_PARAMS(66, 1), 580 { /* sentinel */ }, 581 }; 582 583 static const struct reg_sequence gxl_gp0_pll_init_regs[] = { 584 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 }, 585 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, 586 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, 587 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, 588 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, 589 }; 590 591 static struct clk_regmap gxl_gp0_pll_dco = { 592 .data = &(struct meson_clk_pll_data){ 593 .en = { 594 .reg_off = HHI_GP0_PLL_CNTL, 595 .shift = 30, 596 .width = 1, 597 }, 598 .m = { 599 .reg_off = HHI_GP0_PLL_CNTL, 600 .shift = 0, 601 .width = 9, 602 }, 603 .n = { 604 .reg_off = HHI_GP0_PLL_CNTL, 605 .shift = 9, 606 .width = 5, 607 }, 608 .frac = { 609 .reg_off = HHI_GP0_PLL_CNTL1, 610 .shift = 0, 611 .width = 10, 612 }, 613 .l = { 614 .reg_off = HHI_GP0_PLL_CNTL, 615 .shift = 31, 616 .width = 1, 617 }, 618 .rst = { 619 .reg_off = HHI_GP0_PLL_CNTL, 620 .shift = 29, 621 .width = 1, 622 }, 623 .table = gxl_gp0_pll_params_table, 624 .init_regs = gxl_gp0_pll_init_regs, 625 .init_count = ARRAY_SIZE(gxl_gp0_pll_init_regs), 626 }, 627 .hw.init = &(struct clk_init_data){ 628 .name = "gp0_pll_dco", 629 .ops = &meson_clk_pll_ops, 630 .parent_data = &(const struct clk_parent_data) { 631 .fw_name = "xtal", 632 }, 633 .num_parents = 1, 634 }, 635 }; 636 637 static struct clk_regmap gxbb_gp0_pll = { 638 .data = &(struct clk_regmap_div_data){ 639 .offset = HHI_GP0_PLL_CNTL, 640 .shift = 16, 641 .width = 2, 642 .flags = CLK_DIVIDER_POWER_OF_TWO, 643 }, 644 .hw.init = &(struct clk_init_data){ 645 .name = "gp0_pll", 646 .ops = &clk_regmap_divider_ops, 647 .parent_data = &(const struct clk_parent_data) { 648 /* 649 * Note: 650 * GXL and GXBB have different gp0_pll_dco (with 651 * different struct clk_hw). We fallback to the global 652 * naming string mechanism so gp0_pll picks up the 653 * appropriate one. 654 */ 655 .name = "gp0_pll_dco", 656 .index = -1, 657 }, 658 .num_parents = 1, 659 .flags = CLK_SET_RATE_PARENT, 660 }, 661 }; 662 663 static struct clk_fixed_factor gxbb_fclk_div2_div = { 664 .mult = 1, 665 .div = 2, 666 .hw.init = &(struct clk_init_data){ 667 .name = "fclk_div2_div", 668 .ops = &clk_fixed_factor_ops, 669 .parent_hws = (const struct clk_hw *[]) { 670 &gxbb_fixed_pll.hw 671 }, 672 .num_parents = 1, 673 }, 674 }; 675 676 static struct clk_regmap gxbb_fclk_div2 = { 677 .data = &(struct clk_regmap_gate_data){ 678 .offset = HHI_MPLL_CNTL6, 679 .bit_idx = 27, 680 }, 681 .hw.init = &(struct clk_init_data){ 682 .name = "fclk_div2", 683 .ops = &clk_regmap_gate_ops, 684 .parent_hws = (const struct clk_hw *[]) { 685 &gxbb_fclk_div2_div.hw 686 }, 687 .num_parents = 1, 688 .flags = CLK_IS_CRITICAL, 689 }, 690 }; 691 692 static struct clk_fixed_factor gxbb_fclk_div3_div = { 693 .mult = 1, 694 .div = 3, 695 .hw.init = &(struct clk_init_data){ 696 .name = "fclk_div3_div", 697 .ops = &clk_fixed_factor_ops, 698 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 699 .num_parents = 1, 700 }, 701 }; 702 703 static struct clk_regmap gxbb_fclk_div3 = { 704 .data = &(struct clk_regmap_gate_data){ 705 .offset = HHI_MPLL_CNTL6, 706 .bit_idx = 28, 707 }, 708 .hw.init = &(struct clk_init_data){ 709 .name = "fclk_div3", 710 .ops = &clk_regmap_gate_ops, 711 .parent_hws = (const struct clk_hw *[]) { 712 &gxbb_fclk_div3_div.hw 713 }, 714 .num_parents = 1, 715 /* 716 * FIXME: 717 * This clock, as fdiv2, is used by the SCPI FW and is required 718 * by the platform to operate correctly. 719 * Until the following condition are met, we need this clock to 720 * be marked as critical: 721 * a) The SCPI generic driver claims and enable all the clocks 722 * it needs 723 * b) CCF has a clock hand-off mechanism to make the sure the 724 * clock stays on until the proper driver comes along 725 */ 726 .flags = CLK_IS_CRITICAL, 727 }, 728 }; 729 730 static struct clk_fixed_factor gxbb_fclk_div4_div = { 731 .mult = 1, 732 .div = 4, 733 .hw.init = &(struct clk_init_data){ 734 .name = "fclk_div4_div", 735 .ops = &clk_fixed_factor_ops, 736 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 737 .num_parents = 1, 738 }, 739 }; 740 741 static struct clk_regmap gxbb_fclk_div4 = { 742 .data = &(struct clk_regmap_gate_data){ 743 .offset = HHI_MPLL_CNTL6, 744 .bit_idx = 29, 745 }, 746 .hw.init = &(struct clk_init_data){ 747 .name = "fclk_div4", 748 .ops = &clk_regmap_gate_ops, 749 .parent_hws = (const struct clk_hw *[]) { 750 &gxbb_fclk_div4_div.hw 751 }, 752 .num_parents = 1, 753 }, 754 }; 755 756 static struct clk_fixed_factor gxbb_fclk_div5_div = { 757 .mult = 1, 758 .div = 5, 759 .hw.init = &(struct clk_init_data){ 760 .name = "fclk_div5_div", 761 .ops = &clk_fixed_factor_ops, 762 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 763 .num_parents = 1, 764 }, 765 }; 766 767 static struct clk_regmap gxbb_fclk_div5 = { 768 .data = &(struct clk_regmap_gate_data){ 769 .offset = HHI_MPLL_CNTL6, 770 .bit_idx = 30, 771 }, 772 .hw.init = &(struct clk_init_data){ 773 .name = "fclk_div5", 774 .ops = &clk_regmap_gate_ops, 775 .parent_hws = (const struct clk_hw *[]) { 776 &gxbb_fclk_div5_div.hw 777 }, 778 .num_parents = 1, 779 }, 780 }; 781 782 static struct clk_fixed_factor gxbb_fclk_div7_div = { 783 .mult = 1, 784 .div = 7, 785 .hw.init = &(struct clk_init_data){ 786 .name = "fclk_div7_div", 787 .ops = &clk_fixed_factor_ops, 788 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 789 .num_parents = 1, 790 }, 791 }; 792 793 static struct clk_regmap gxbb_fclk_div7 = { 794 .data = &(struct clk_regmap_gate_data){ 795 .offset = HHI_MPLL_CNTL6, 796 .bit_idx = 31, 797 }, 798 .hw.init = &(struct clk_init_data){ 799 .name = "fclk_div7", 800 .ops = &clk_regmap_gate_ops, 801 .parent_hws = (const struct clk_hw *[]) { 802 &gxbb_fclk_div7_div.hw 803 }, 804 .num_parents = 1, 805 }, 806 }; 807 808 static struct clk_regmap gxbb_mpll_prediv = { 809 .data = &(struct clk_regmap_div_data){ 810 .offset = HHI_MPLL_CNTL5, 811 .shift = 12, 812 .width = 1, 813 }, 814 .hw.init = &(struct clk_init_data){ 815 .name = "mpll_prediv", 816 .ops = &clk_regmap_divider_ro_ops, 817 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 818 .num_parents = 1, 819 }, 820 }; 821 822 static struct clk_regmap gxbb_mpll0_div = { 823 .data = &(struct meson_clk_mpll_data){ 824 .sdm = { 825 .reg_off = HHI_MPLL_CNTL7, 826 .shift = 0, 827 .width = 14, 828 }, 829 .sdm_en = { 830 .reg_off = HHI_MPLL_CNTL, 831 .shift = 25, 832 .width = 1, 833 }, 834 .n2 = { 835 .reg_off = HHI_MPLL_CNTL7, 836 .shift = 16, 837 .width = 9, 838 }, 839 }, 840 .hw.init = &(struct clk_init_data){ 841 .name = "mpll0_div", 842 .ops = &meson_clk_mpll_ops, 843 .parent_hws = (const struct clk_hw *[]) { 844 &gxbb_mpll_prediv.hw 845 }, 846 .num_parents = 1, 847 }, 848 }; 849 850 static struct clk_regmap gxl_mpll0_div = { 851 .data = &(struct meson_clk_mpll_data){ 852 .sdm = { 853 .reg_off = HHI_MPLL_CNTL7, 854 .shift = 0, 855 .width = 14, 856 }, 857 .sdm_en = { 858 .reg_off = HHI_MPLL_CNTL7, 859 .shift = 15, 860 .width = 1, 861 }, 862 .n2 = { 863 .reg_off = HHI_MPLL_CNTL7, 864 .shift = 16, 865 .width = 9, 866 }, 867 }, 868 .hw.init = &(struct clk_init_data){ 869 .name = "mpll0_div", 870 .ops = &meson_clk_mpll_ops, 871 .parent_hws = (const struct clk_hw *[]) { 872 &gxbb_mpll_prediv.hw 873 }, 874 .num_parents = 1, 875 }, 876 }; 877 878 static struct clk_regmap gxbb_mpll0 = { 879 .data = &(struct clk_regmap_gate_data){ 880 .offset = HHI_MPLL_CNTL7, 881 .bit_idx = 14, 882 }, 883 .hw.init = &(struct clk_init_data){ 884 .name = "mpll0", 885 .ops = &clk_regmap_gate_ops, 886 .parent_data = &(const struct clk_parent_data) { 887 /* 888 * Note: 889 * GXL and GXBB have different SDM_EN registers. We 890 * fallback to the global naming string mechanism so 891 * mpll0_div picks up the appropriate one. 892 */ 893 .name = "mpll0_div", 894 .index = -1, 895 }, 896 .num_parents = 1, 897 .flags = CLK_SET_RATE_PARENT, 898 }, 899 }; 900 901 static struct clk_regmap gxbb_mpll1_div = { 902 .data = &(struct meson_clk_mpll_data){ 903 .sdm = { 904 .reg_off = HHI_MPLL_CNTL8, 905 .shift = 0, 906 .width = 14, 907 }, 908 .sdm_en = { 909 .reg_off = HHI_MPLL_CNTL8, 910 .shift = 15, 911 .width = 1, 912 }, 913 .n2 = { 914 .reg_off = HHI_MPLL_CNTL8, 915 .shift = 16, 916 .width = 9, 917 }, 918 }, 919 .hw.init = &(struct clk_init_data){ 920 .name = "mpll1_div", 921 .ops = &meson_clk_mpll_ops, 922 .parent_hws = (const struct clk_hw *[]) { 923 &gxbb_mpll_prediv.hw 924 }, 925 .num_parents = 1, 926 }, 927 }; 928 929 static struct clk_regmap gxbb_mpll1 = { 930 .data = &(struct clk_regmap_gate_data){ 931 .offset = HHI_MPLL_CNTL8, 932 .bit_idx = 14, 933 }, 934 .hw.init = &(struct clk_init_data){ 935 .name = "mpll1", 936 .ops = &clk_regmap_gate_ops, 937 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll1_div.hw }, 938 .num_parents = 1, 939 .flags = CLK_SET_RATE_PARENT, 940 }, 941 }; 942 943 static struct clk_regmap gxbb_mpll2_div = { 944 .data = &(struct meson_clk_mpll_data){ 945 .sdm = { 946 .reg_off = HHI_MPLL_CNTL9, 947 .shift = 0, 948 .width = 14, 949 }, 950 .sdm_en = { 951 .reg_off = HHI_MPLL_CNTL9, 952 .shift = 15, 953 .width = 1, 954 }, 955 .n2 = { 956 .reg_off = HHI_MPLL_CNTL9, 957 .shift = 16, 958 .width = 9, 959 }, 960 }, 961 .hw.init = &(struct clk_init_data){ 962 .name = "mpll2_div", 963 .ops = &meson_clk_mpll_ops, 964 .parent_hws = (const struct clk_hw *[]) { 965 &gxbb_mpll_prediv.hw 966 }, 967 .num_parents = 1, 968 }, 969 }; 970 971 static struct clk_regmap gxbb_mpll2 = { 972 .data = &(struct clk_regmap_gate_data){ 973 .offset = HHI_MPLL_CNTL9, 974 .bit_idx = 14, 975 }, 976 .hw.init = &(struct clk_init_data){ 977 .name = "mpll2", 978 .ops = &clk_regmap_gate_ops, 979 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll2_div.hw }, 980 .num_parents = 1, 981 .flags = CLK_SET_RATE_PARENT, 982 }, 983 }; 984 985 /* clk81 is often referred as "mpeg_clk" */ 986 static u32 clk81_parents_val_table[] = { 0, 2, 3, 4, 5, 6, 7 }; 987 static const struct clk_parent_data clk81_parents[] = { 988 { .fw_name = "xtal", }, 989 { .hw = &gxbb_fclk_div7.hw }, 990 { .hw = &gxbb_mpll1.hw }, 991 { .hw = &gxbb_mpll2.hw }, 992 { .hw = &gxbb_fclk_div4.hw }, 993 { .hw = &gxbb_fclk_div3.hw }, 994 { .hw = &gxbb_fclk_div5.hw }, 995 }; 996 997 static struct clk_regmap gxbb_clk81_sel = { 998 .data = &(struct clk_regmap_mux_data){ 999 .offset = HHI_MPEG_CLK_CNTL, 1000 .mask = 0x7, 1001 .shift = 12, 1002 .table = clk81_parents_val_table, 1003 }, 1004 .hw.init = &(struct clk_init_data){ 1005 .name = "clk81_sel", 1006 .ops = &clk_regmap_mux_ro_ops, 1007 /* 1008 * bits 14:12 selects from 8 possible parents: 1009 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, 1010 * fclk_div4, fclk_div3, fclk_div5 1011 */ 1012 .parent_data = clk81_parents, 1013 .num_parents = ARRAY_SIZE(clk81_parents), 1014 }, 1015 }; 1016 1017 static struct clk_regmap gxbb_clk81_div = { 1018 .data = &(struct clk_regmap_div_data){ 1019 .offset = HHI_MPEG_CLK_CNTL, 1020 .shift = 0, 1021 .width = 7, 1022 }, 1023 .hw.init = &(struct clk_init_data){ 1024 .name = "clk81_div", 1025 .ops = &clk_regmap_divider_ro_ops, 1026 .parent_hws = (const struct clk_hw *[]) { 1027 &gxbb_clk81_sel.hw 1028 }, 1029 .num_parents = 1, 1030 }, 1031 }; 1032 1033 /* the mother of dragons gates */ 1034 static struct clk_regmap gxbb_clk81 = { 1035 .data = &(struct clk_regmap_gate_data){ 1036 .offset = HHI_MPEG_CLK_CNTL, 1037 .bit_idx = 7, 1038 }, 1039 .hw.init = &(struct clk_init_data){ 1040 .name = "clk81", 1041 .ops = &clk_regmap_gate_ops, 1042 .parent_hws = (const struct clk_hw *[]) { 1043 &gxbb_clk81_div.hw 1044 }, 1045 .num_parents = 1, 1046 .flags = CLK_IS_CRITICAL, 1047 }, 1048 }; 1049 1050 static struct clk_regmap gxbb_sar_adc_clk_sel = { 1051 .data = &(struct clk_regmap_mux_data){ 1052 .offset = HHI_SAR_CLK_CNTL, 1053 .mask = 0x3, 1054 .shift = 9, 1055 }, 1056 .hw.init = &(struct clk_init_data){ 1057 .name = "sar_adc_clk_sel", 1058 .ops = &clk_regmap_mux_ops, 1059 /* NOTE: The datasheet doesn't list the parents for bit 10 */ 1060 .parent_data = (const struct clk_parent_data []) { 1061 { .fw_name = "xtal", }, 1062 { .hw = &gxbb_clk81.hw }, 1063 }, 1064 .num_parents = 2, 1065 }, 1066 }; 1067 1068 static struct clk_regmap gxbb_sar_adc_clk_div = { 1069 .data = &(struct clk_regmap_div_data){ 1070 .offset = HHI_SAR_CLK_CNTL, 1071 .shift = 0, 1072 .width = 8, 1073 }, 1074 .hw.init = &(struct clk_init_data){ 1075 .name = "sar_adc_clk_div", 1076 .ops = &clk_regmap_divider_ops, 1077 .parent_hws = (const struct clk_hw *[]) { 1078 &gxbb_sar_adc_clk_sel.hw 1079 }, 1080 .num_parents = 1, 1081 .flags = CLK_SET_RATE_PARENT, 1082 }, 1083 }; 1084 1085 static struct clk_regmap gxbb_sar_adc_clk = { 1086 .data = &(struct clk_regmap_gate_data){ 1087 .offset = HHI_SAR_CLK_CNTL, 1088 .bit_idx = 8, 1089 }, 1090 .hw.init = &(struct clk_init_data){ 1091 .name = "sar_adc_clk", 1092 .ops = &clk_regmap_gate_ops, 1093 .parent_hws = (const struct clk_hw *[]) { 1094 &gxbb_sar_adc_clk_div.hw 1095 }, 1096 .num_parents = 1, 1097 .flags = CLK_SET_RATE_PARENT, 1098 }, 1099 }; 1100 1101 /* 1102 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) 1103 * muxed by a glitch-free switch. The CCF can manage this glitch-free 1104 * mux because it does top-to-bottom updates the each clock tree and 1105 * switches to the "inactive" one when CLK_SET_RATE_GATE is set. 1106 */ 1107 1108 static const struct clk_parent_data gxbb_mali_parents[] = { 1109 { .fw_name = "xtal", }, 1110 { .hw = &gxbb_gp0_pll.hw }, 1111 { .hw = &gxbb_mpll2.hw }, 1112 { .hw = &gxbb_mpll1.hw }, 1113 { .hw = &gxbb_fclk_div7.hw }, 1114 { .hw = &gxbb_fclk_div4.hw }, 1115 { .hw = &gxbb_fclk_div3.hw }, 1116 { .hw = &gxbb_fclk_div5.hw }, 1117 }; 1118 1119 static struct clk_regmap gxbb_mali_0_sel = { 1120 .data = &(struct clk_regmap_mux_data){ 1121 .offset = HHI_MALI_CLK_CNTL, 1122 .mask = 0x7, 1123 .shift = 9, 1124 }, 1125 .hw.init = &(struct clk_init_data){ 1126 .name = "mali_0_sel", 1127 .ops = &clk_regmap_mux_ops, 1128 .parent_data = gxbb_mali_parents, 1129 .num_parents = ARRAY_SIZE(gxbb_mali_parents), 1130 /* 1131 * Don't request the parent to change the rate because 1132 * all GPU frequencies can be derived from the fclk_* 1133 * clocks and one special GP0_PLL setting. This is 1134 * important because we need the MPLL clocks for audio. 1135 */ 1136 .flags = 0, 1137 }, 1138 }; 1139 1140 static struct clk_regmap gxbb_mali_0_div = { 1141 .data = &(struct clk_regmap_div_data){ 1142 .offset = HHI_MALI_CLK_CNTL, 1143 .shift = 0, 1144 .width = 7, 1145 }, 1146 .hw.init = &(struct clk_init_data){ 1147 .name = "mali_0_div", 1148 .ops = &clk_regmap_divider_ops, 1149 .parent_hws = (const struct clk_hw *[]) { 1150 &gxbb_mali_0_sel.hw 1151 }, 1152 .num_parents = 1, 1153 .flags = CLK_SET_RATE_PARENT, 1154 }, 1155 }; 1156 1157 static struct clk_regmap gxbb_mali_0 = { 1158 .data = &(struct clk_regmap_gate_data){ 1159 .offset = HHI_MALI_CLK_CNTL, 1160 .bit_idx = 8, 1161 }, 1162 .hw.init = &(struct clk_init_data){ 1163 .name = "mali_0", 1164 .ops = &clk_regmap_gate_ops, 1165 .parent_hws = (const struct clk_hw *[]) { 1166 &gxbb_mali_0_div.hw 1167 }, 1168 .num_parents = 1, 1169 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, 1170 }, 1171 }; 1172 1173 static struct clk_regmap gxbb_mali_1_sel = { 1174 .data = &(struct clk_regmap_mux_data){ 1175 .offset = HHI_MALI_CLK_CNTL, 1176 .mask = 0x7, 1177 .shift = 25, 1178 }, 1179 .hw.init = &(struct clk_init_data){ 1180 .name = "mali_1_sel", 1181 .ops = &clk_regmap_mux_ops, 1182 .parent_data = gxbb_mali_parents, 1183 .num_parents = ARRAY_SIZE(gxbb_mali_parents), 1184 /* 1185 * Don't request the parent to change the rate because 1186 * all GPU frequencies can be derived from the fclk_* 1187 * clocks and one special GP0_PLL setting. This is 1188 * important because we need the MPLL clocks for audio. 1189 */ 1190 .flags = 0, 1191 }, 1192 }; 1193 1194 static struct clk_regmap gxbb_mali_1_div = { 1195 .data = &(struct clk_regmap_div_data){ 1196 .offset = HHI_MALI_CLK_CNTL, 1197 .shift = 16, 1198 .width = 7, 1199 }, 1200 .hw.init = &(struct clk_init_data){ 1201 .name = "mali_1_div", 1202 .ops = &clk_regmap_divider_ops, 1203 .parent_hws = (const struct clk_hw *[]) { 1204 &gxbb_mali_1_sel.hw 1205 }, 1206 .num_parents = 1, 1207 .flags = CLK_SET_RATE_PARENT, 1208 }, 1209 }; 1210 1211 static struct clk_regmap gxbb_mali_1 = { 1212 .data = &(struct clk_regmap_gate_data){ 1213 .offset = HHI_MALI_CLK_CNTL, 1214 .bit_idx = 24, 1215 }, 1216 .hw.init = &(struct clk_init_data){ 1217 .name = "mali_1", 1218 .ops = &clk_regmap_gate_ops, 1219 .parent_hws = (const struct clk_hw *[]) { 1220 &gxbb_mali_1_div.hw 1221 }, 1222 .num_parents = 1, 1223 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, 1224 }, 1225 }; 1226 1227 static struct clk_regmap gxbb_mali = { 1228 .data = &(struct clk_regmap_mux_data){ 1229 .offset = HHI_MALI_CLK_CNTL, 1230 .mask = 1, 1231 .shift = 31, 1232 }, 1233 .hw.init = &(struct clk_init_data){ 1234 .name = "mali", 1235 .ops = &clk_regmap_mux_ops, 1236 .parent_hws = (const struct clk_hw *[]) { 1237 &gxbb_mali_0.hw, 1238 &gxbb_mali_1.hw, 1239 }, 1240 .num_parents = 2, 1241 .flags = CLK_SET_RATE_PARENT, 1242 }, 1243 }; 1244 1245 static u32 gxbb_cts_mclk_parents_val_table[] = { 1, 2, 3 }; 1246 static const struct clk_hw *gxbb_cts_mclk_parents[] = { 1247 &gxbb_mpll0.hw, 1248 &gxbb_mpll1.hw, 1249 &gxbb_mpll2.hw, 1250 }; 1251 1252 static struct clk_regmap gxbb_cts_amclk_sel = { 1253 .data = &(struct clk_regmap_mux_data){ 1254 .offset = HHI_AUD_CLK_CNTL, 1255 .mask = 0x3, 1256 .shift = 9, 1257 .table = gxbb_cts_mclk_parents_val_table, 1258 .flags = CLK_MUX_ROUND_CLOSEST, 1259 }, 1260 .hw.init = &(struct clk_init_data){ 1261 .name = "cts_amclk_sel", 1262 .ops = &clk_regmap_mux_ops, 1263 .parent_hws = gxbb_cts_mclk_parents, 1264 .num_parents = ARRAY_SIZE(gxbb_cts_mclk_parents), 1265 }, 1266 }; 1267 1268 static struct clk_regmap gxbb_cts_amclk_div = { 1269 .data = &(struct clk_regmap_div_data) { 1270 .offset = HHI_AUD_CLK_CNTL, 1271 .shift = 0, 1272 .width = 8, 1273 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1274 }, 1275 .hw.init = &(struct clk_init_data){ 1276 .name = "cts_amclk_div", 1277 .ops = &clk_regmap_divider_ops, 1278 .parent_hws = (const struct clk_hw *[]) { 1279 &gxbb_cts_amclk_sel.hw 1280 }, 1281 .num_parents = 1, 1282 .flags = CLK_SET_RATE_PARENT, 1283 }, 1284 }; 1285 1286 static struct clk_regmap gxbb_cts_amclk = { 1287 .data = &(struct clk_regmap_gate_data){ 1288 .offset = HHI_AUD_CLK_CNTL, 1289 .bit_idx = 8, 1290 }, 1291 .hw.init = &(struct clk_init_data){ 1292 .name = "cts_amclk", 1293 .ops = &clk_regmap_gate_ops, 1294 .parent_hws = (const struct clk_hw *[]) { 1295 &gxbb_cts_amclk_div.hw 1296 }, 1297 .num_parents = 1, 1298 .flags = CLK_SET_RATE_PARENT, 1299 }, 1300 }; 1301 1302 static struct clk_regmap gxbb_cts_mclk_i958_sel = { 1303 .data = &(struct clk_regmap_mux_data){ 1304 .offset = HHI_AUD_CLK_CNTL2, 1305 .mask = 0x3, 1306 .shift = 25, 1307 .table = gxbb_cts_mclk_parents_val_table, 1308 .flags = CLK_MUX_ROUND_CLOSEST, 1309 }, 1310 .hw.init = &(struct clk_init_data) { 1311 .name = "cts_mclk_i958_sel", 1312 .ops = &clk_regmap_mux_ops, 1313 .parent_hws = gxbb_cts_mclk_parents, 1314 .num_parents = ARRAY_SIZE(gxbb_cts_mclk_parents), 1315 }, 1316 }; 1317 1318 static struct clk_regmap gxbb_cts_mclk_i958_div = { 1319 .data = &(struct clk_regmap_div_data){ 1320 .offset = HHI_AUD_CLK_CNTL2, 1321 .shift = 16, 1322 .width = 8, 1323 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1324 }, 1325 .hw.init = &(struct clk_init_data) { 1326 .name = "cts_mclk_i958_div", 1327 .ops = &clk_regmap_divider_ops, 1328 .parent_hws = (const struct clk_hw *[]) { 1329 &gxbb_cts_mclk_i958_sel.hw 1330 }, 1331 .num_parents = 1, 1332 .flags = CLK_SET_RATE_PARENT, 1333 }, 1334 }; 1335 1336 static struct clk_regmap gxbb_cts_mclk_i958 = { 1337 .data = &(struct clk_regmap_gate_data){ 1338 .offset = HHI_AUD_CLK_CNTL2, 1339 .bit_idx = 24, 1340 }, 1341 .hw.init = &(struct clk_init_data){ 1342 .name = "cts_mclk_i958", 1343 .ops = &clk_regmap_gate_ops, 1344 .parent_hws = (const struct clk_hw *[]) { 1345 &gxbb_cts_mclk_i958_div.hw 1346 }, 1347 .num_parents = 1, 1348 .flags = CLK_SET_RATE_PARENT, 1349 }, 1350 }; 1351 1352 static struct clk_regmap gxbb_cts_i958 = { 1353 .data = &(struct clk_regmap_mux_data){ 1354 .offset = HHI_AUD_CLK_CNTL2, 1355 .mask = 0x1, 1356 .shift = 27, 1357 }, 1358 .hw.init = &(struct clk_init_data){ 1359 .name = "cts_i958", 1360 .ops = &clk_regmap_mux_ops, 1361 .parent_hws = (const struct clk_hw *[]) { 1362 &gxbb_cts_amclk.hw, 1363 &gxbb_cts_mclk_i958.hw 1364 }, 1365 .num_parents = 2, 1366 /* 1367 *The parent is specific to origin of the audio data. Let the 1368 * consumer choose the appropriate parent 1369 */ 1370 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 1371 }, 1372 }; 1373 1374 /* 1375 * This table skips a clock named 'cts_slow_oscin' in the documentation 1376 * This clock does not exist yet in this controller or the AO one 1377 */ 1378 static u32 gxbb_32k_clk_parents_val_table[] = { 0, 2, 3 }; 1379 static const struct clk_parent_data gxbb_32k_clk_parents[] = { 1380 { .fw_name = "xtal", }, 1381 { .hw = &gxbb_fclk_div3.hw }, 1382 { .hw = &gxbb_fclk_div5.hw }, 1383 }; 1384 1385 static struct clk_regmap gxbb_32k_clk_sel = { 1386 .data = &(struct clk_regmap_mux_data){ 1387 .offset = HHI_32K_CLK_CNTL, 1388 .mask = 0x3, 1389 .shift = 16, 1390 .table = gxbb_32k_clk_parents_val_table, 1391 }, 1392 .hw.init = &(struct clk_init_data){ 1393 .name = "32k_clk_sel", 1394 .ops = &clk_regmap_mux_ops, 1395 .parent_data = gxbb_32k_clk_parents, 1396 .num_parents = ARRAY_SIZE(gxbb_32k_clk_parents), 1397 .flags = CLK_SET_RATE_PARENT, 1398 }, 1399 }; 1400 1401 static struct clk_regmap gxbb_32k_clk_div = { 1402 .data = &(struct clk_regmap_div_data){ 1403 .offset = HHI_32K_CLK_CNTL, 1404 .shift = 0, 1405 .width = 14, 1406 }, 1407 .hw.init = &(struct clk_init_data){ 1408 .name = "32k_clk_div", 1409 .ops = &clk_regmap_divider_ops, 1410 .parent_hws = (const struct clk_hw *[]) { 1411 &gxbb_32k_clk_sel.hw 1412 }, 1413 .num_parents = 1, 1414 .flags = CLK_SET_RATE_PARENT, 1415 }, 1416 }; 1417 1418 static struct clk_regmap gxbb_32k_clk = { 1419 .data = &(struct clk_regmap_gate_data){ 1420 .offset = HHI_32K_CLK_CNTL, 1421 .bit_idx = 15, 1422 }, 1423 .hw.init = &(struct clk_init_data){ 1424 .name = "32k_clk", 1425 .ops = &clk_regmap_gate_ops, 1426 .parent_hws = (const struct clk_hw *[]) { 1427 &gxbb_32k_clk_div.hw 1428 }, 1429 .num_parents = 1, 1430 .flags = CLK_SET_RATE_PARENT, 1431 }, 1432 }; 1433 1434 static const struct clk_parent_data gxbb_sd_emmc_clk0_parents[] = { 1435 { .fw_name = "xtal", }, 1436 { .hw = &gxbb_fclk_div2.hw }, 1437 { .hw = &gxbb_fclk_div3.hw }, 1438 { .hw = &gxbb_fclk_div5.hw }, 1439 { .hw = &gxbb_fclk_div7.hw }, 1440 /* 1441 * Following these parent clocks, we should also have had mpll2, mpll3 1442 * and gp0_pll but these clocks are too precious to be used here. All 1443 * the necessary rates for MMC and NAND operation can be achieved using 1444 * xtal or fclk_div clocks 1445 */ 1446 }; 1447 1448 /* SDIO clock */ 1449 static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = { 1450 .data = &(struct clk_regmap_mux_data){ 1451 .offset = HHI_SD_EMMC_CLK_CNTL, 1452 .mask = 0x7, 1453 .shift = 9, 1454 }, 1455 .hw.init = &(struct clk_init_data) { 1456 .name = "sd_emmc_a_clk0_sel", 1457 .ops = &clk_regmap_mux_ops, 1458 .parent_data = gxbb_sd_emmc_clk0_parents, 1459 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parents), 1460 .flags = CLK_SET_RATE_PARENT, 1461 }, 1462 }; 1463 1464 static struct clk_regmap gxbb_sd_emmc_a_clk0_div = { 1465 .data = &(struct clk_regmap_div_data){ 1466 .offset = HHI_SD_EMMC_CLK_CNTL, 1467 .shift = 0, 1468 .width = 7, 1469 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1470 }, 1471 .hw.init = &(struct clk_init_data) { 1472 .name = "sd_emmc_a_clk0_div", 1473 .ops = &clk_regmap_divider_ops, 1474 .parent_hws = (const struct clk_hw *[]) { 1475 &gxbb_sd_emmc_a_clk0_sel.hw 1476 }, 1477 .num_parents = 1, 1478 .flags = CLK_SET_RATE_PARENT, 1479 }, 1480 }; 1481 1482 static struct clk_regmap gxbb_sd_emmc_a_clk0 = { 1483 .data = &(struct clk_regmap_gate_data){ 1484 .offset = HHI_SD_EMMC_CLK_CNTL, 1485 .bit_idx = 7, 1486 }, 1487 .hw.init = &(struct clk_init_data){ 1488 .name = "sd_emmc_a_clk0", 1489 .ops = &clk_regmap_gate_ops, 1490 .parent_hws = (const struct clk_hw *[]) { 1491 &gxbb_sd_emmc_a_clk0_div.hw 1492 }, 1493 .num_parents = 1, 1494 .flags = CLK_SET_RATE_PARENT, 1495 }, 1496 }; 1497 1498 /* SDcard clock */ 1499 static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = { 1500 .data = &(struct clk_regmap_mux_data){ 1501 .offset = HHI_SD_EMMC_CLK_CNTL, 1502 .mask = 0x7, 1503 .shift = 25, 1504 }, 1505 .hw.init = &(struct clk_init_data) { 1506 .name = "sd_emmc_b_clk0_sel", 1507 .ops = &clk_regmap_mux_ops, 1508 .parent_data = gxbb_sd_emmc_clk0_parents, 1509 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parents), 1510 .flags = CLK_SET_RATE_PARENT, 1511 }, 1512 }; 1513 1514 static struct clk_regmap gxbb_sd_emmc_b_clk0_div = { 1515 .data = &(struct clk_regmap_div_data){ 1516 .offset = HHI_SD_EMMC_CLK_CNTL, 1517 .shift = 16, 1518 .width = 7, 1519 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1520 }, 1521 .hw.init = &(struct clk_init_data) { 1522 .name = "sd_emmc_b_clk0_div", 1523 .ops = &clk_regmap_divider_ops, 1524 .parent_hws = (const struct clk_hw *[]) { 1525 &gxbb_sd_emmc_b_clk0_sel.hw 1526 }, 1527 .num_parents = 1, 1528 .flags = CLK_SET_RATE_PARENT, 1529 }, 1530 }; 1531 1532 static struct clk_regmap gxbb_sd_emmc_b_clk0 = { 1533 .data = &(struct clk_regmap_gate_data){ 1534 .offset = HHI_SD_EMMC_CLK_CNTL, 1535 .bit_idx = 23, 1536 }, 1537 .hw.init = &(struct clk_init_data){ 1538 .name = "sd_emmc_b_clk0", 1539 .ops = &clk_regmap_gate_ops, 1540 .parent_hws = (const struct clk_hw *[]) { 1541 &gxbb_sd_emmc_b_clk0_div.hw 1542 }, 1543 .num_parents = 1, 1544 .flags = CLK_SET_RATE_PARENT, 1545 }, 1546 }; 1547 1548 /* EMMC/NAND clock */ 1549 static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = { 1550 .data = &(struct clk_regmap_mux_data){ 1551 .offset = HHI_NAND_CLK_CNTL, 1552 .mask = 0x7, 1553 .shift = 9, 1554 }, 1555 .hw.init = &(struct clk_init_data) { 1556 .name = "sd_emmc_c_clk0_sel", 1557 .ops = &clk_regmap_mux_ops, 1558 .parent_data = gxbb_sd_emmc_clk0_parents, 1559 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parents), 1560 .flags = CLK_SET_RATE_PARENT, 1561 }, 1562 }; 1563 1564 static struct clk_regmap gxbb_sd_emmc_c_clk0_div = { 1565 .data = &(struct clk_regmap_div_data){ 1566 .offset = HHI_NAND_CLK_CNTL, 1567 .shift = 0, 1568 .width = 7, 1569 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1570 }, 1571 .hw.init = &(struct clk_init_data) { 1572 .name = "sd_emmc_c_clk0_div", 1573 .ops = &clk_regmap_divider_ops, 1574 .parent_hws = (const struct clk_hw *[]) { 1575 &gxbb_sd_emmc_c_clk0_sel.hw 1576 }, 1577 .num_parents = 1, 1578 .flags = CLK_SET_RATE_PARENT, 1579 }, 1580 }; 1581 1582 static struct clk_regmap gxbb_sd_emmc_c_clk0 = { 1583 .data = &(struct clk_regmap_gate_data){ 1584 .offset = HHI_NAND_CLK_CNTL, 1585 .bit_idx = 7, 1586 }, 1587 .hw.init = &(struct clk_init_data){ 1588 .name = "sd_emmc_c_clk0", 1589 .ops = &clk_regmap_gate_ops, 1590 .parent_hws = (const struct clk_hw *[]) { 1591 &gxbb_sd_emmc_c_clk0_div.hw 1592 }, 1593 .num_parents = 1, 1594 .flags = CLK_SET_RATE_PARENT, 1595 }, 1596 }; 1597 1598 /* VPU Clock */ 1599 1600 static const struct clk_hw *gxbb_vpu_parents[] = { 1601 &gxbb_fclk_div4.hw, 1602 &gxbb_fclk_div3.hw, 1603 &gxbb_fclk_div5.hw, 1604 &gxbb_fclk_div7.hw, 1605 }; 1606 1607 static struct clk_regmap gxbb_vpu_0_sel = { 1608 .data = &(struct clk_regmap_mux_data){ 1609 .offset = HHI_VPU_CLK_CNTL, 1610 .mask = 0x3, 1611 .shift = 9, 1612 }, 1613 .hw.init = &(struct clk_init_data){ 1614 .name = "vpu_0_sel", 1615 .ops = &clk_regmap_mux_ops, 1616 /* 1617 * bits 9:10 selects from 4 possible parents: 1618 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1619 */ 1620 .parent_hws = gxbb_vpu_parents, 1621 .num_parents = ARRAY_SIZE(gxbb_vpu_parents), 1622 .flags = CLK_SET_RATE_NO_REPARENT, 1623 }, 1624 }; 1625 1626 static struct clk_regmap gxbb_vpu_0_div = { 1627 .data = &(struct clk_regmap_div_data){ 1628 .offset = HHI_VPU_CLK_CNTL, 1629 .shift = 0, 1630 .width = 7, 1631 }, 1632 .hw.init = &(struct clk_init_data){ 1633 .name = "vpu_0_div", 1634 .ops = &clk_regmap_divider_ops, 1635 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_sel.hw }, 1636 .num_parents = 1, 1637 .flags = CLK_SET_RATE_PARENT, 1638 }, 1639 }; 1640 1641 static struct clk_regmap gxbb_vpu_0 = { 1642 .data = &(struct clk_regmap_gate_data){ 1643 .offset = HHI_VPU_CLK_CNTL, 1644 .bit_idx = 8, 1645 }, 1646 .hw.init = &(struct clk_init_data) { 1647 .name = "vpu_0", 1648 .ops = &clk_regmap_gate_ops, 1649 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_div.hw }, 1650 .num_parents = 1, 1651 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1652 }, 1653 }; 1654 1655 static struct clk_regmap gxbb_vpu_1_sel = { 1656 .data = &(struct clk_regmap_mux_data){ 1657 .offset = HHI_VPU_CLK_CNTL, 1658 .mask = 0x3, 1659 .shift = 25, 1660 }, 1661 .hw.init = &(struct clk_init_data){ 1662 .name = "vpu_1_sel", 1663 .ops = &clk_regmap_mux_ops, 1664 /* 1665 * bits 25:26 selects from 4 possible parents: 1666 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1667 */ 1668 .parent_hws = gxbb_vpu_parents, 1669 .num_parents = ARRAY_SIZE(gxbb_vpu_parents), 1670 .flags = CLK_SET_RATE_NO_REPARENT, 1671 }, 1672 }; 1673 1674 static struct clk_regmap gxbb_vpu_1_div = { 1675 .data = &(struct clk_regmap_div_data){ 1676 .offset = HHI_VPU_CLK_CNTL, 1677 .shift = 16, 1678 .width = 7, 1679 }, 1680 .hw.init = &(struct clk_init_data){ 1681 .name = "vpu_1_div", 1682 .ops = &clk_regmap_divider_ops, 1683 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_sel.hw }, 1684 .num_parents = 1, 1685 .flags = CLK_SET_RATE_PARENT, 1686 }, 1687 }; 1688 1689 static struct clk_regmap gxbb_vpu_1 = { 1690 .data = &(struct clk_regmap_gate_data){ 1691 .offset = HHI_VPU_CLK_CNTL, 1692 .bit_idx = 24, 1693 }, 1694 .hw.init = &(struct clk_init_data) { 1695 .name = "vpu_1", 1696 .ops = &clk_regmap_gate_ops, 1697 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_div.hw }, 1698 .num_parents = 1, 1699 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1700 }, 1701 }; 1702 1703 static struct clk_regmap gxbb_vpu = { 1704 .data = &(struct clk_regmap_mux_data){ 1705 .offset = HHI_VPU_CLK_CNTL, 1706 .mask = 1, 1707 .shift = 31, 1708 }, 1709 .hw.init = &(struct clk_init_data){ 1710 .name = "vpu", 1711 .ops = &clk_regmap_mux_ops, 1712 /* 1713 * bit 31 selects from 2 possible parents: 1714 * vpu_0 or vpu_1 1715 */ 1716 .parent_hws = (const struct clk_hw *[]) { 1717 &gxbb_vpu_0.hw, 1718 &gxbb_vpu_1.hw 1719 }, 1720 .num_parents = 2, 1721 .flags = CLK_SET_RATE_NO_REPARENT, 1722 }, 1723 }; 1724 1725 /* VAPB Clock */ 1726 1727 static const struct clk_hw *gxbb_vapb_parents[] = { 1728 &gxbb_fclk_div4.hw, 1729 &gxbb_fclk_div3.hw, 1730 &gxbb_fclk_div5.hw, 1731 &gxbb_fclk_div7.hw, 1732 }; 1733 1734 static struct clk_regmap gxbb_vapb_0_sel = { 1735 .data = &(struct clk_regmap_mux_data){ 1736 .offset = HHI_VAPBCLK_CNTL, 1737 .mask = 0x3, 1738 .shift = 9, 1739 }, 1740 .hw.init = &(struct clk_init_data){ 1741 .name = "vapb_0_sel", 1742 .ops = &clk_regmap_mux_ops, 1743 /* 1744 * bits 9:10 selects from 4 possible parents: 1745 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1746 */ 1747 .parent_hws = gxbb_vapb_parents, 1748 .num_parents = ARRAY_SIZE(gxbb_vapb_parents), 1749 .flags = CLK_SET_RATE_NO_REPARENT, 1750 }, 1751 }; 1752 1753 static struct clk_regmap gxbb_vapb_0_div = { 1754 .data = &(struct clk_regmap_div_data){ 1755 .offset = HHI_VAPBCLK_CNTL, 1756 .shift = 0, 1757 .width = 7, 1758 }, 1759 .hw.init = &(struct clk_init_data){ 1760 .name = "vapb_0_div", 1761 .ops = &clk_regmap_divider_ops, 1762 .parent_hws = (const struct clk_hw *[]) { 1763 &gxbb_vapb_0_sel.hw 1764 }, 1765 .num_parents = 1, 1766 .flags = CLK_SET_RATE_PARENT, 1767 }, 1768 }; 1769 1770 static struct clk_regmap gxbb_vapb_0 = { 1771 .data = &(struct clk_regmap_gate_data){ 1772 .offset = HHI_VAPBCLK_CNTL, 1773 .bit_idx = 8, 1774 }, 1775 .hw.init = &(struct clk_init_data) { 1776 .name = "vapb_0", 1777 .ops = &clk_regmap_gate_ops, 1778 .parent_hws = (const struct clk_hw *[]) { 1779 &gxbb_vapb_0_div.hw 1780 }, 1781 .num_parents = 1, 1782 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1783 }, 1784 }; 1785 1786 static struct clk_regmap gxbb_vapb_1_sel = { 1787 .data = &(struct clk_regmap_mux_data){ 1788 .offset = HHI_VAPBCLK_CNTL, 1789 .mask = 0x3, 1790 .shift = 25, 1791 }, 1792 .hw.init = &(struct clk_init_data){ 1793 .name = "vapb_1_sel", 1794 .ops = &clk_regmap_mux_ops, 1795 /* 1796 * bits 25:26 selects from 4 possible parents: 1797 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1798 */ 1799 .parent_hws = gxbb_vapb_parents, 1800 .num_parents = ARRAY_SIZE(gxbb_vapb_parents), 1801 .flags = CLK_SET_RATE_NO_REPARENT, 1802 }, 1803 }; 1804 1805 static struct clk_regmap gxbb_vapb_1_div = { 1806 .data = &(struct clk_regmap_div_data){ 1807 .offset = HHI_VAPBCLK_CNTL, 1808 .shift = 16, 1809 .width = 7, 1810 }, 1811 .hw.init = &(struct clk_init_data){ 1812 .name = "vapb_1_div", 1813 .ops = &clk_regmap_divider_ops, 1814 .parent_hws = (const struct clk_hw *[]) { 1815 &gxbb_vapb_1_sel.hw 1816 }, 1817 .num_parents = 1, 1818 .flags = CLK_SET_RATE_PARENT, 1819 }, 1820 }; 1821 1822 static struct clk_regmap gxbb_vapb_1 = { 1823 .data = &(struct clk_regmap_gate_data){ 1824 .offset = HHI_VAPBCLK_CNTL, 1825 .bit_idx = 24, 1826 }, 1827 .hw.init = &(struct clk_init_data) { 1828 .name = "vapb_1", 1829 .ops = &clk_regmap_gate_ops, 1830 .parent_hws = (const struct clk_hw *[]) { 1831 &gxbb_vapb_1_div.hw 1832 }, 1833 .num_parents = 1, 1834 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1835 }, 1836 }; 1837 1838 static struct clk_regmap gxbb_vapb_sel = { 1839 .data = &(struct clk_regmap_mux_data){ 1840 .offset = HHI_VAPBCLK_CNTL, 1841 .mask = 1, 1842 .shift = 31, 1843 }, 1844 .hw.init = &(struct clk_init_data){ 1845 .name = "vapb_sel", 1846 .ops = &clk_regmap_mux_ops, 1847 /* 1848 * bit 31 selects from 2 possible parents: 1849 * vapb_0 or vapb_1 1850 */ 1851 .parent_hws = (const struct clk_hw *[]) { 1852 &gxbb_vapb_0.hw, 1853 &gxbb_vapb_1.hw 1854 }, 1855 .num_parents = 2, 1856 .flags = CLK_SET_RATE_NO_REPARENT, 1857 }, 1858 }; 1859 1860 static struct clk_regmap gxbb_vapb = { 1861 .data = &(struct clk_regmap_gate_data){ 1862 .offset = HHI_VAPBCLK_CNTL, 1863 .bit_idx = 30, 1864 }, 1865 .hw.init = &(struct clk_init_data) { 1866 .name = "vapb", 1867 .ops = &clk_regmap_gate_ops, 1868 .parent_hws = (const struct clk_hw *[]) { &gxbb_vapb_sel.hw }, 1869 .num_parents = 1, 1870 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1871 }, 1872 }; 1873 1874 /* Video Clocks */ 1875 1876 static struct clk_regmap gxbb_vid_pll_div = { 1877 .data = &(struct meson_vid_pll_div_data){ 1878 .val = { 1879 .reg_off = HHI_VID_PLL_CLK_DIV, 1880 .shift = 0, 1881 .width = 15, 1882 }, 1883 .sel = { 1884 .reg_off = HHI_VID_PLL_CLK_DIV, 1885 .shift = 16, 1886 .width = 2, 1887 }, 1888 }, 1889 .hw.init = &(struct clk_init_data) { 1890 .name = "vid_pll_div", 1891 .ops = &meson_vid_pll_div_ro_ops, 1892 .parent_data = &(const struct clk_parent_data) { 1893 /* 1894 * Note: 1895 * GXL and GXBB have different hdmi_plls (with 1896 * different struct clk_hw). We fallback to the global 1897 * naming string mechanism so vid_pll_div picks up the 1898 * appropriate one. 1899 */ 1900 .name = "hdmi_pll", 1901 .index = -1, 1902 }, 1903 .num_parents = 1, 1904 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 1905 }, 1906 }; 1907 1908 static const struct clk_parent_data gxbb_vid_pll_parents[] = { 1909 { .hw = &gxbb_vid_pll_div.hw }, 1910 /* 1911 * Note: 1912 * GXL and GXBB have different hdmi_plls (with 1913 * different struct clk_hw). We fallback to the global 1914 * naming string mechanism so vid_pll_div picks up the 1915 * appropriate one. 1916 */ 1917 { .name = "hdmi_pll", .index = -1 }, 1918 }; 1919 1920 static struct clk_regmap gxbb_vid_pll_sel = { 1921 .data = &(struct clk_regmap_mux_data){ 1922 .offset = HHI_VID_PLL_CLK_DIV, 1923 .mask = 0x1, 1924 .shift = 18, 1925 }, 1926 .hw.init = &(struct clk_init_data){ 1927 .name = "vid_pll_sel", 1928 .ops = &clk_regmap_mux_ops, 1929 /* 1930 * bit 18 selects from 2 possible parents: 1931 * vid_pll_div or hdmi_pll 1932 */ 1933 .parent_data = gxbb_vid_pll_parents, 1934 .num_parents = ARRAY_SIZE(gxbb_vid_pll_parents), 1935 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1936 }, 1937 }; 1938 1939 static struct clk_regmap gxbb_vid_pll = { 1940 .data = &(struct clk_regmap_gate_data){ 1941 .offset = HHI_VID_PLL_CLK_DIV, 1942 .bit_idx = 19, 1943 }, 1944 .hw.init = &(struct clk_init_data) { 1945 .name = "vid_pll", 1946 .ops = &clk_regmap_gate_ops, 1947 .parent_hws = (const struct clk_hw *[]) { 1948 &gxbb_vid_pll_sel.hw 1949 }, 1950 .num_parents = 1, 1951 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1952 }, 1953 }; 1954 1955 static const struct clk_hw *gxbb_vclk_parents[] = { 1956 &gxbb_vid_pll.hw, 1957 &gxbb_fclk_div4.hw, 1958 &gxbb_fclk_div3.hw, 1959 &gxbb_fclk_div5.hw, 1960 &gxbb_vid_pll.hw, 1961 &gxbb_fclk_div7.hw, 1962 &gxbb_mpll1.hw, 1963 }; 1964 1965 static struct clk_regmap gxbb_vclk_sel = { 1966 .data = &(struct clk_regmap_mux_data){ 1967 .offset = HHI_VID_CLK_CNTL, 1968 .mask = 0x7, 1969 .shift = 16, 1970 }, 1971 .hw.init = &(struct clk_init_data){ 1972 .name = "vclk_sel", 1973 .ops = &clk_regmap_mux_ops, 1974 /* 1975 * bits 16:18 selects from 8 possible parents: 1976 * vid_pll, fclk_div4, fclk_div3, fclk_div5, 1977 * vid_pll, fclk_div7, mp1 1978 */ 1979 .parent_hws = gxbb_vclk_parents, 1980 .num_parents = ARRAY_SIZE(gxbb_vclk_parents), 1981 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1982 }, 1983 }; 1984 1985 static struct clk_regmap gxbb_vclk2_sel = { 1986 .data = &(struct clk_regmap_mux_data){ 1987 .offset = HHI_VIID_CLK_CNTL, 1988 .mask = 0x7, 1989 .shift = 16, 1990 }, 1991 .hw.init = &(struct clk_init_data){ 1992 .name = "vclk2_sel", 1993 .ops = &clk_regmap_mux_ops, 1994 /* 1995 * bits 16:18 selects from 8 possible parents: 1996 * vid_pll, fclk_div4, fclk_div3, fclk_div5, 1997 * vid_pll, fclk_div7, mp1 1998 */ 1999 .parent_hws = gxbb_vclk_parents, 2000 .num_parents = ARRAY_SIZE(gxbb_vclk_parents), 2001 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2002 }, 2003 }; 2004 2005 static struct clk_regmap gxbb_vclk_input = { 2006 .data = &(struct clk_regmap_gate_data){ 2007 .offset = HHI_VID_CLK_DIV, 2008 .bit_idx = 16, 2009 }, 2010 .hw.init = &(struct clk_init_data) { 2011 .name = "vclk_input", 2012 .ops = &clk_regmap_gate_ops, 2013 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_sel.hw }, 2014 .num_parents = 1, 2015 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2016 }, 2017 }; 2018 2019 static struct clk_regmap gxbb_vclk2_input = { 2020 .data = &(struct clk_regmap_gate_data){ 2021 .offset = HHI_VIID_CLK_DIV, 2022 .bit_idx = 16, 2023 }, 2024 .hw.init = &(struct clk_init_data) { 2025 .name = "vclk2_input", 2026 .ops = &clk_regmap_gate_ops, 2027 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_sel.hw }, 2028 .num_parents = 1, 2029 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2030 }, 2031 }; 2032 2033 static struct clk_regmap gxbb_vclk_div = { 2034 .data = &(struct clk_regmap_div_data){ 2035 .offset = HHI_VID_CLK_DIV, 2036 .shift = 0, 2037 .width = 8, 2038 }, 2039 .hw.init = &(struct clk_init_data){ 2040 .name = "vclk_div", 2041 .ops = &clk_regmap_divider_ops, 2042 .parent_hws = (const struct clk_hw *[]) { 2043 &gxbb_vclk_input.hw 2044 }, 2045 .num_parents = 1, 2046 .flags = CLK_GET_RATE_NOCACHE, 2047 }, 2048 }; 2049 2050 static struct clk_regmap gxbb_vclk2_div = { 2051 .data = &(struct clk_regmap_div_data){ 2052 .offset = HHI_VIID_CLK_DIV, 2053 .shift = 0, 2054 .width = 8, 2055 }, 2056 .hw.init = &(struct clk_init_data){ 2057 .name = "vclk2_div", 2058 .ops = &clk_regmap_divider_ops, 2059 .parent_hws = (const struct clk_hw *[]) { 2060 &gxbb_vclk2_input.hw 2061 }, 2062 .num_parents = 1, 2063 .flags = CLK_GET_RATE_NOCACHE, 2064 }, 2065 }; 2066 2067 static struct clk_regmap gxbb_vclk = { 2068 .data = &(struct clk_regmap_gate_data){ 2069 .offset = HHI_VID_CLK_CNTL, 2070 .bit_idx = 19, 2071 }, 2072 .hw.init = &(struct clk_init_data) { 2073 .name = "vclk", 2074 .ops = &clk_regmap_gate_ops, 2075 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_div.hw }, 2076 .num_parents = 1, 2077 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2078 }, 2079 }; 2080 2081 static struct clk_regmap gxbb_vclk2 = { 2082 .data = &(struct clk_regmap_gate_data){ 2083 .offset = HHI_VIID_CLK_CNTL, 2084 .bit_idx = 19, 2085 }, 2086 .hw.init = &(struct clk_init_data) { 2087 .name = "vclk2", 2088 .ops = &clk_regmap_gate_ops, 2089 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_div.hw }, 2090 .num_parents = 1, 2091 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2092 }, 2093 }; 2094 2095 static struct clk_regmap gxbb_vclk_div1 = { 2096 .data = &(struct clk_regmap_gate_data){ 2097 .offset = HHI_VID_CLK_CNTL, 2098 .bit_idx = 0, 2099 }, 2100 .hw.init = &(struct clk_init_data) { 2101 .name = "vclk_div1", 2102 .ops = &clk_regmap_gate_ops, 2103 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2104 .num_parents = 1, 2105 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2106 }, 2107 }; 2108 2109 static struct clk_regmap gxbb_vclk_div2_en = { 2110 .data = &(struct clk_regmap_gate_data){ 2111 .offset = HHI_VID_CLK_CNTL, 2112 .bit_idx = 1, 2113 }, 2114 .hw.init = &(struct clk_init_data) { 2115 .name = "vclk_div2_en", 2116 .ops = &clk_regmap_gate_ops, 2117 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2118 .num_parents = 1, 2119 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2120 }, 2121 }; 2122 2123 static struct clk_regmap gxbb_vclk_div4_en = { 2124 .data = &(struct clk_regmap_gate_data){ 2125 .offset = HHI_VID_CLK_CNTL, 2126 .bit_idx = 2, 2127 }, 2128 .hw.init = &(struct clk_init_data) { 2129 .name = "vclk_div4_en", 2130 .ops = &clk_regmap_gate_ops, 2131 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2132 .num_parents = 1, 2133 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2134 }, 2135 }; 2136 2137 static struct clk_regmap gxbb_vclk_div6_en = { 2138 .data = &(struct clk_regmap_gate_data){ 2139 .offset = HHI_VID_CLK_CNTL, 2140 .bit_idx = 3, 2141 }, 2142 .hw.init = &(struct clk_init_data) { 2143 .name = "vclk_div6_en", 2144 .ops = &clk_regmap_gate_ops, 2145 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2146 .num_parents = 1, 2147 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2148 }, 2149 }; 2150 2151 static struct clk_regmap gxbb_vclk_div12_en = { 2152 .data = &(struct clk_regmap_gate_data){ 2153 .offset = HHI_VID_CLK_CNTL, 2154 .bit_idx = 4, 2155 }, 2156 .hw.init = &(struct clk_init_data) { 2157 .name = "vclk_div12_en", 2158 .ops = &clk_regmap_gate_ops, 2159 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2160 .num_parents = 1, 2161 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2162 }, 2163 }; 2164 2165 static struct clk_regmap gxbb_vclk2_div1 = { 2166 .data = &(struct clk_regmap_gate_data){ 2167 .offset = HHI_VIID_CLK_CNTL, 2168 .bit_idx = 0, 2169 }, 2170 .hw.init = &(struct clk_init_data) { 2171 .name = "vclk2_div1", 2172 .ops = &clk_regmap_gate_ops, 2173 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2174 .num_parents = 1, 2175 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2176 }, 2177 }; 2178 2179 static struct clk_regmap gxbb_vclk2_div2_en = { 2180 .data = &(struct clk_regmap_gate_data){ 2181 .offset = HHI_VIID_CLK_CNTL, 2182 .bit_idx = 1, 2183 }, 2184 .hw.init = &(struct clk_init_data) { 2185 .name = "vclk2_div2_en", 2186 .ops = &clk_regmap_gate_ops, 2187 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2188 .num_parents = 1, 2189 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2190 }, 2191 }; 2192 2193 static struct clk_regmap gxbb_vclk2_div4_en = { 2194 .data = &(struct clk_regmap_gate_data){ 2195 .offset = HHI_VIID_CLK_CNTL, 2196 .bit_idx = 2, 2197 }, 2198 .hw.init = &(struct clk_init_data) { 2199 .name = "vclk2_div4_en", 2200 .ops = &clk_regmap_gate_ops, 2201 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2202 .num_parents = 1, 2203 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2204 }, 2205 }; 2206 2207 static struct clk_regmap gxbb_vclk2_div6_en = { 2208 .data = &(struct clk_regmap_gate_data){ 2209 .offset = HHI_VIID_CLK_CNTL, 2210 .bit_idx = 3, 2211 }, 2212 .hw.init = &(struct clk_init_data) { 2213 .name = "vclk2_div6_en", 2214 .ops = &clk_regmap_gate_ops, 2215 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2216 .num_parents = 1, 2217 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2218 }, 2219 }; 2220 2221 static struct clk_regmap gxbb_vclk2_div12_en = { 2222 .data = &(struct clk_regmap_gate_data){ 2223 .offset = HHI_VIID_CLK_CNTL, 2224 .bit_idx = 4, 2225 }, 2226 .hw.init = &(struct clk_init_data) { 2227 .name = "vclk2_div12_en", 2228 .ops = &clk_regmap_gate_ops, 2229 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2230 .num_parents = 1, 2231 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2232 }, 2233 }; 2234 2235 static struct clk_fixed_factor gxbb_vclk_div2 = { 2236 .mult = 1, 2237 .div = 2, 2238 .hw.init = &(struct clk_init_data){ 2239 .name = "vclk_div2", 2240 .ops = &clk_fixed_factor_ops, 2241 .parent_hws = (const struct clk_hw *[]) { 2242 &gxbb_vclk_div2_en.hw 2243 }, 2244 .num_parents = 1, 2245 }, 2246 }; 2247 2248 static struct clk_fixed_factor gxbb_vclk_div4 = { 2249 .mult = 1, 2250 .div = 4, 2251 .hw.init = &(struct clk_init_data){ 2252 .name = "vclk_div4", 2253 .ops = &clk_fixed_factor_ops, 2254 .parent_hws = (const struct clk_hw *[]) { 2255 &gxbb_vclk_div4_en.hw 2256 }, 2257 .num_parents = 1, 2258 }, 2259 }; 2260 2261 static struct clk_fixed_factor gxbb_vclk_div6 = { 2262 .mult = 1, 2263 .div = 6, 2264 .hw.init = &(struct clk_init_data){ 2265 .name = "vclk_div6", 2266 .ops = &clk_fixed_factor_ops, 2267 .parent_hws = (const struct clk_hw *[]) { 2268 &gxbb_vclk_div6_en.hw 2269 }, 2270 .num_parents = 1, 2271 }, 2272 }; 2273 2274 static struct clk_fixed_factor gxbb_vclk_div12 = { 2275 .mult = 1, 2276 .div = 12, 2277 .hw.init = &(struct clk_init_data){ 2278 .name = "vclk_div12", 2279 .ops = &clk_fixed_factor_ops, 2280 .parent_hws = (const struct clk_hw *[]) { 2281 &gxbb_vclk_div12_en.hw 2282 }, 2283 .num_parents = 1, 2284 }, 2285 }; 2286 2287 static struct clk_fixed_factor gxbb_vclk2_div2 = { 2288 .mult = 1, 2289 .div = 2, 2290 .hw.init = &(struct clk_init_data){ 2291 .name = "vclk2_div2", 2292 .ops = &clk_fixed_factor_ops, 2293 .parent_hws = (const struct clk_hw *[]) { 2294 &gxbb_vclk2_div2_en.hw 2295 }, 2296 .num_parents = 1, 2297 }, 2298 }; 2299 2300 static struct clk_fixed_factor gxbb_vclk2_div4 = { 2301 .mult = 1, 2302 .div = 4, 2303 .hw.init = &(struct clk_init_data){ 2304 .name = "vclk2_div4", 2305 .ops = &clk_fixed_factor_ops, 2306 .parent_hws = (const struct clk_hw *[]) { 2307 &gxbb_vclk2_div4_en.hw 2308 }, 2309 .num_parents = 1, 2310 }, 2311 }; 2312 2313 static struct clk_fixed_factor gxbb_vclk2_div6 = { 2314 .mult = 1, 2315 .div = 6, 2316 .hw.init = &(struct clk_init_data){ 2317 .name = "vclk2_div6", 2318 .ops = &clk_fixed_factor_ops, 2319 .parent_hws = (const struct clk_hw *[]) { 2320 &gxbb_vclk2_div6_en.hw 2321 }, 2322 .num_parents = 1, 2323 }, 2324 }; 2325 2326 static struct clk_fixed_factor gxbb_vclk2_div12 = { 2327 .mult = 1, 2328 .div = 12, 2329 .hw.init = &(struct clk_init_data){ 2330 .name = "vclk2_div12", 2331 .ops = &clk_fixed_factor_ops, 2332 .parent_hws = (const struct clk_hw *[]) { 2333 &gxbb_vclk2_div12_en.hw 2334 }, 2335 .num_parents = 1, 2336 }, 2337 }; 2338 2339 static u32 gxbb_cts_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 2340 static const struct clk_hw *gxbb_cts_parents[] = { 2341 &gxbb_vclk_div1.hw, 2342 &gxbb_vclk_div2.hw, 2343 &gxbb_vclk_div4.hw, 2344 &gxbb_vclk_div6.hw, 2345 &gxbb_vclk_div12.hw, 2346 &gxbb_vclk2_div1.hw, 2347 &gxbb_vclk2_div2.hw, 2348 &gxbb_vclk2_div4.hw, 2349 &gxbb_vclk2_div6.hw, 2350 &gxbb_vclk2_div12.hw, 2351 }; 2352 2353 static struct clk_regmap gxbb_cts_enci_sel = { 2354 .data = &(struct clk_regmap_mux_data){ 2355 .offset = HHI_VID_CLK_DIV, 2356 .mask = 0xf, 2357 .shift = 28, 2358 .table = gxbb_cts_parents_val_table, 2359 }, 2360 .hw.init = &(struct clk_init_data){ 2361 .name = "cts_enci_sel", 2362 .ops = &clk_regmap_mux_ops, 2363 .parent_hws = gxbb_cts_parents, 2364 .num_parents = ARRAY_SIZE(gxbb_cts_parents), 2365 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2366 }, 2367 }; 2368 2369 static struct clk_regmap gxbb_cts_encp_sel = { 2370 .data = &(struct clk_regmap_mux_data){ 2371 .offset = HHI_VID_CLK_DIV, 2372 .mask = 0xf, 2373 .shift = 20, 2374 .table = gxbb_cts_parents_val_table, 2375 }, 2376 .hw.init = &(struct clk_init_data){ 2377 .name = "cts_encp_sel", 2378 .ops = &clk_regmap_mux_ops, 2379 .parent_hws = gxbb_cts_parents, 2380 .num_parents = ARRAY_SIZE(gxbb_cts_parents), 2381 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2382 }, 2383 }; 2384 2385 static struct clk_regmap gxbb_cts_vdac_sel = { 2386 .data = &(struct clk_regmap_mux_data){ 2387 .offset = HHI_VIID_CLK_DIV, 2388 .mask = 0xf, 2389 .shift = 28, 2390 .table = gxbb_cts_parents_val_table, 2391 }, 2392 .hw.init = &(struct clk_init_data){ 2393 .name = "cts_vdac_sel", 2394 .ops = &clk_regmap_mux_ops, 2395 .parent_hws = gxbb_cts_parents, 2396 .num_parents = ARRAY_SIZE(gxbb_cts_parents), 2397 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2398 }, 2399 }; 2400 2401 static struct clk_regmap gxbb_cts_enci = { 2402 .data = &(struct clk_regmap_gate_data){ 2403 .offset = HHI_VID_CLK_CNTL2, 2404 .bit_idx = 0, 2405 }, 2406 .hw.init = &(struct clk_init_data) { 2407 .name = "cts_enci", 2408 .ops = &clk_regmap_gate_ops, 2409 .parent_hws = (const struct clk_hw *[]) { 2410 &gxbb_cts_enci_sel.hw 2411 }, 2412 .num_parents = 1, 2413 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2414 }, 2415 }; 2416 2417 static struct clk_regmap gxbb_cts_encp = { 2418 .data = &(struct clk_regmap_gate_data){ 2419 .offset = HHI_VID_CLK_CNTL2, 2420 .bit_idx = 2, 2421 }, 2422 .hw.init = &(struct clk_init_data) { 2423 .name = "cts_encp", 2424 .ops = &clk_regmap_gate_ops, 2425 .parent_hws = (const struct clk_hw *[]) { 2426 &gxbb_cts_encp_sel.hw 2427 }, 2428 .num_parents = 1, 2429 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2430 }, 2431 }; 2432 2433 static struct clk_regmap gxbb_cts_vdac = { 2434 .data = &(struct clk_regmap_gate_data){ 2435 .offset = HHI_VID_CLK_CNTL2, 2436 .bit_idx = 4, 2437 }, 2438 .hw.init = &(struct clk_init_data) { 2439 .name = "cts_vdac", 2440 .ops = &clk_regmap_gate_ops, 2441 .parent_hws = (const struct clk_hw *[]) { 2442 &gxbb_cts_vdac_sel.hw 2443 }, 2444 .num_parents = 1, 2445 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2446 }, 2447 }; 2448 2449 /* TOFIX: add support for cts_tcon */ 2450 static u32 gxbb_hdmi_tx_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 2451 static const struct clk_hw *gxbb_hdmi_tx_parents[] = { 2452 &gxbb_vclk_div1.hw, 2453 &gxbb_vclk_div2.hw, 2454 &gxbb_vclk_div4.hw, 2455 &gxbb_vclk_div6.hw, 2456 &gxbb_vclk_div12.hw, 2457 &gxbb_vclk2_div1.hw, 2458 &gxbb_vclk2_div2.hw, 2459 &gxbb_vclk2_div4.hw, 2460 &gxbb_vclk2_div6.hw, 2461 &gxbb_vclk2_div12.hw, 2462 }; 2463 2464 static struct clk_regmap gxbb_hdmi_tx_sel = { 2465 .data = &(struct clk_regmap_mux_data){ 2466 .offset = HHI_HDMI_CLK_CNTL, 2467 .mask = 0xf, 2468 .shift = 16, 2469 .table = gxbb_hdmi_tx_parents_val_table, 2470 }, 2471 .hw.init = &(struct clk_init_data){ 2472 .name = "hdmi_tx_sel", 2473 .ops = &clk_regmap_mux_ops, 2474 /* 2475 * bits 31:28 selects from 12 possible parents: 2476 * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12 2477 * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12, 2478 * cts_tcon 2479 */ 2480 .parent_hws = gxbb_hdmi_tx_parents, 2481 .num_parents = ARRAY_SIZE(gxbb_hdmi_tx_parents), 2482 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2483 }, 2484 }; 2485 2486 static struct clk_regmap gxbb_hdmi_tx = { 2487 .data = &(struct clk_regmap_gate_data){ 2488 .offset = HHI_VID_CLK_CNTL2, 2489 .bit_idx = 5, 2490 }, 2491 .hw.init = &(struct clk_init_data) { 2492 .name = "hdmi_tx", 2493 .ops = &clk_regmap_gate_ops, 2494 .parent_hws = (const struct clk_hw *[]) { 2495 &gxbb_hdmi_tx_sel.hw 2496 }, 2497 .num_parents = 1, 2498 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2499 }, 2500 }; 2501 2502 /* HDMI Clocks */ 2503 2504 static const struct clk_parent_data gxbb_hdmi_parents[] = { 2505 { .fw_name = "xtal", }, 2506 { .hw = &gxbb_fclk_div4.hw }, 2507 { .hw = &gxbb_fclk_div3.hw }, 2508 { .hw = &gxbb_fclk_div5.hw }, 2509 }; 2510 2511 static struct clk_regmap gxbb_hdmi_sel = { 2512 .data = &(struct clk_regmap_mux_data){ 2513 .offset = HHI_HDMI_CLK_CNTL, 2514 .mask = 0x3, 2515 .shift = 9, 2516 .flags = CLK_MUX_ROUND_CLOSEST, 2517 }, 2518 .hw.init = &(struct clk_init_data){ 2519 .name = "hdmi_sel", 2520 .ops = &clk_regmap_mux_ops, 2521 .parent_data = gxbb_hdmi_parents, 2522 .num_parents = ARRAY_SIZE(gxbb_hdmi_parents), 2523 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2524 }, 2525 }; 2526 2527 static struct clk_regmap gxbb_hdmi_div = { 2528 .data = &(struct clk_regmap_div_data){ 2529 .offset = HHI_HDMI_CLK_CNTL, 2530 .shift = 0, 2531 .width = 7, 2532 }, 2533 .hw.init = &(struct clk_init_data){ 2534 .name = "hdmi_div", 2535 .ops = &clk_regmap_divider_ops, 2536 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_sel.hw }, 2537 .num_parents = 1, 2538 .flags = CLK_GET_RATE_NOCACHE, 2539 }, 2540 }; 2541 2542 static struct clk_regmap gxbb_hdmi = { 2543 .data = &(struct clk_regmap_gate_data){ 2544 .offset = HHI_HDMI_CLK_CNTL, 2545 .bit_idx = 8, 2546 }, 2547 .hw.init = &(struct clk_init_data) { 2548 .name = "hdmi", 2549 .ops = &clk_regmap_gate_ops, 2550 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_div.hw }, 2551 .num_parents = 1, 2552 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2553 }, 2554 }; 2555 2556 /* VDEC clocks */ 2557 2558 static const struct clk_hw *gxbb_vdec_parents[] = { 2559 &gxbb_fclk_div4.hw, 2560 &gxbb_fclk_div3.hw, 2561 &gxbb_fclk_div5.hw, 2562 &gxbb_fclk_div7.hw, 2563 }; 2564 2565 static struct clk_regmap gxbb_vdec_1_sel = { 2566 .data = &(struct clk_regmap_mux_data){ 2567 .offset = HHI_VDEC_CLK_CNTL, 2568 .mask = 0x3, 2569 .shift = 9, 2570 .flags = CLK_MUX_ROUND_CLOSEST, 2571 }, 2572 .hw.init = &(struct clk_init_data){ 2573 .name = "vdec_1_sel", 2574 .ops = &clk_regmap_mux_ops, 2575 .parent_hws = gxbb_vdec_parents, 2576 .num_parents = ARRAY_SIZE(gxbb_vdec_parents), 2577 .flags = CLK_SET_RATE_PARENT, 2578 }, 2579 }; 2580 2581 static struct clk_regmap gxbb_vdec_1_div = { 2582 .data = &(struct clk_regmap_div_data){ 2583 .offset = HHI_VDEC_CLK_CNTL, 2584 .shift = 0, 2585 .width = 7, 2586 .flags = CLK_DIVIDER_ROUND_CLOSEST, 2587 }, 2588 .hw.init = &(struct clk_init_data){ 2589 .name = "vdec_1_div", 2590 .ops = &clk_regmap_divider_ops, 2591 .parent_hws = (const struct clk_hw *[]) { 2592 &gxbb_vdec_1_sel.hw 2593 }, 2594 .num_parents = 1, 2595 .flags = CLK_SET_RATE_PARENT, 2596 }, 2597 }; 2598 2599 static struct clk_regmap gxbb_vdec_1 = { 2600 .data = &(struct clk_regmap_gate_data){ 2601 .offset = HHI_VDEC_CLK_CNTL, 2602 .bit_idx = 8, 2603 }, 2604 .hw.init = &(struct clk_init_data) { 2605 .name = "vdec_1", 2606 .ops = &clk_regmap_gate_ops, 2607 .parent_hws = (const struct clk_hw *[]) { 2608 &gxbb_vdec_1_div.hw 2609 }, 2610 .num_parents = 1, 2611 .flags = CLK_SET_RATE_PARENT, 2612 }, 2613 }; 2614 2615 static struct clk_regmap gxbb_vdec_hevc_sel = { 2616 .data = &(struct clk_regmap_mux_data){ 2617 .offset = HHI_VDEC2_CLK_CNTL, 2618 .mask = 0x3, 2619 .shift = 25, 2620 .flags = CLK_MUX_ROUND_CLOSEST, 2621 }, 2622 .hw.init = &(struct clk_init_data){ 2623 .name = "vdec_hevc_sel", 2624 .ops = &clk_regmap_mux_ops, 2625 .parent_hws = gxbb_vdec_parents, 2626 .num_parents = ARRAY_SIZE(gxbb_vdec_parents), 2627 .flags = CLK_SET_RATE_PARENT, 2628 }, 2629 }; 2630 2631 static struct clk_regmap gxbb_vdec_hevc_div = { 2632 .data = &(struct clk_regmap_div_data){ 2633 .offset = HHI_VDEC2_CLK_CNTL, 2634 .shift = 16, 2635 .width = 7, 2636 .flags = CLK_DIVIDER_ROUND_CLOSEST, 2637 }, 2638 .hw.init = &(struct clk_init_data){ 2639 .name = "vdec_hevc_div", 2640 .ops = &clk_regmap_divider_ops, 2641 .parent_hws = (const struct clk_hw *[]) { 2642 &gxbb_vdec_hevc_sel.hw 2643 }, 2644 .num_parents = 1, 2645 .flags = CLK_SET_RATE_PARENT, 2646 }, 2647 }; 2648 2649 static struct clk_regmap gxbb_vdec_hevc = { 2650 .data = &(struct clk_regmap_gate_data){ 2651 .offset = HHI_VDEC2_CLK_CNTL, 2652 .bit_idx = 24, 2653 }, 2654 .hw.init = &(struct clk_init_data) { 2655 .name = "vdec_hevc", 2656 .ops = &clk_regmap_gate_ops, 2657 .parent_hws = (const struct clk_hw *[]) { 2658 &gxbb_vdec_hevc_div.hw 2659 }, 2660 .num_parents = 1, 2661 .flags = CLK_SET_RATE_PARENT, 2662 }, 2663 }; 2664 2665 static u32 gxbb_gen_clk_parents_val_table[] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, }; 2666 static const struct clk_parent_data gxbb_gen_clk_parents[] = { 2667 { .fw_name = "xtal", }, 2668 { .hw = &gxbb_vdec_1.hw }, 2669 { .hw = &gxbb_vdec_hevc.hw }, 2670 { .hw = &gxbb_mpll0.hw }, 2671 { .hw = &gxbb_mpll1.hw }, 2672 { .hw = &gxbb_mpll2.hw }, 2673 { .hw = &gxbb_fclk_div4.hw }, 2674 { .hw = &gxbb_fclk_div3.hw }, 2675 { .hw = &gxbb_fclk_div5.hw }, 2676 { .hw = &gxbb_fclk_div7.hw }, 2677 { .hw = &gxbb_gp0_pll.hw }, 2678 }; 2679 2680 static struct clk_regmap gxbb_gen_clk_sel = { 2681 .data = &(struct clk_regmap_mux_data){ 2682 .offset = HHI_GEN_CLK_CNTL, 2683 .mask = 0xf, 2684 .shift = 12, 2685 .table = gxbb_gen_clk_parents_val_table, 2686 }, 2687 .hw.init = &(struct clk_init_data){ 2688 .name = "gen_clk_sel", 2689 .ops = &clk_regmap_mux_ops, 2690 /* 2691 * bits 15:12 selects from 14 possible parents: 2692 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt], 2693 * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4, 2694 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll 2695 */ 2696 .parent_data = gxbb_gen_clk_parents, 2697 .num_parents = ARRAY_SIZE(gxbb_gen_clk_parents), 2698 }, 2699 }; 2700 2701 static struct clk_regmap gxbb_gen_clk_div = { 2702 .data = &(struct clk_regmap_div_data){ 2703 .offset = HHI_GEN_CLK_CNTL, 2704 .shift = 0, 2705 .width = 11, 2706 }, 2707 .hw.init = &(struct clk_init_data){ 2708 .name = "gen_clk_div", 2709 .ops = &clk_regmap_divider_ops, 2710 .parent_hws = (const struct clk_hw *[]) { 2711 &gxbb_gen_clk_sel.hw 2712 }, 2713 .num_parents = 1, 2714 .flags = CLK_SET_RATE_PARENT, 2715 }, 2716 }; 2717 2718 static struct clk_regmap gxbb_gen_clk = { 2719 .data = &(struct clk_regmap_gate_data){ 2720 .offset = HHI_GEN_CLK_CNTL, 2721 .bit_idx = 7, 2722 }, 2723 .hw.init = &(struct clk_init_data){ 2724 .name = "gen_clk", 2725 .ops = &clk_regmap_gate_ops, 2726 .parent_hws = (const struct clk_hw *[]) { 2727 &gxbb_gen_clk_div.hw 2728 }, 2729 .num_parents = 1, 2730 .flags = CLK_SET_RATE_PARENT, 2731 }, 2732 }; 2733 2734 static const struct clk_parent_data gxbb_pclk_parents = { .hw = &gxbb_clk81.hw }; 2735 2736 #define GXBB_PCLK(_name, _reg, _bit, _flags) \ 2737 MESON_PCLK(_name, _reg, _bit, &gxbb_pclk_parents, _flags) 2738 2739 /* 2740 * Everything Else (EE) domain gates 2741 * 2742 * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons 2743 * Users are encouraged to test without it and submit changes to: 2744 * - remove the flag if not necessary 2745 * - replace the flag with something more adequate, such as CLK_IS_CRITICAL, 2746 * if appropriate. 2747 * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirable 2748 * for a particular clock. 2749 */ 2750 static GXBB_PCLK(gxbb_ddr, HHI_GCLK_MPEG0, 0, CLK_IGNORE_UNUSED); 2751 static GXBB_PCLK(gxbb_dos, HHI_GCLK_MPEG0, 1, CLK_IGNORE_UNUSED); 2752 static GXBB_PCLK(gxbb_isa, HHI_GCLK_MPEG0, 5, CLK_IGNORE_UNUSED); 2753 static GXBB_PCLK(gxbb_pl301, HHI_GCLK_MPEG0, 6, CLK_IGNORE_UNUSED); 2754 static GXBB_PCLK(gxbb_periphs, HHI_GCLK_MPEG0, 7, CLK_IGNORE_UNUSED); 2755 static GXBB_PCLK(gxbb_spicc, HHI_GCLK_MPEG0, 8, CLK_IGNORE_UNUSED); 2756 static GXBB_PCLK(gxbb_i2c, HHI_GCLK_MPEG0, 9, CLK_IGNORE_UNUSED); 2757 static GXBB_PCLK(gxbb_sana, HHI_GCLK_MPEG0, 10, CLK_IGNORE_UNUSED); 2758 static GXBB_PCLK(gxbb_smart_card, HHI_GCLK_MPEG0, 11, CLK_IGNORE_UNUSED); 2759 static GXBB_PCLK(gxbb_rng0, HHI_GCLK_MPEG0, 12, CLK_IGNORE_UNUSED); 2760 static GXBB_PCLK(gxbb_uart0, HHI_GCLK_MPEG0, 13, CLK_IGNORE_UNUSED); 2761 static GXBB_PCLK(gxbb_sdhc, HHI_GCLK_MPEG0, 14, CLK_IGNORE_UNUSED); 2762 static GXBB_PCLK(gxbb_stream, HHI_GCLK_MPEG0, 15, CLK_IGNORE_UNUSED); 2763 static GXBB_PCLK(gxbb_async_fifo, HHI_GCLK_MPEG0, 16, CLK_IGNORE_UNUSED); 2764 static GXBB_PCLK(gxbb_sdio, HHI_GCLK_MPEG0, 17, CLK_IGNORE_UNUSED); 2765 static GXBB_PCLK(gxbb_abuf, HHI_GCLK_MPEG0, 18, CLK_IGNORE_UNUSED); 2766 static GXBB_PCLK(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19, CLK_IGNORE_UNUSED); 2767 static GXBB_PCLK(gxbb_assist_misc, HHI_GCLK_MPEG0, 23, CLK_IGNORE_UNUSED); 2768 static GXBB_PCLK(gxbb_emmc_a, HHI_GCLK_MPEG0, 24, CLK_IGNORE_UNUSED); 2769 static GXBB_PCLK(gxbb_emmc_b, HHI_GCLK_MPEG0, 25, CLK_IGNORE_UNUSED); 2770 static GXBB_PCLK(gxbb_emmc_c, HHI_GCLK_MPEG0, 26, CLK_IGNORE_UNUSED); 2771 static GXBB_PCLK(gxl_acodec, HHI_GCLK_MPEG0, 28, CLK_IGNORE_UNUSED); 2772 static GXBB_PCLK(gxbb_spi, HHI_GCLK_MPEG0, 30, CLK_IGNORE_UNUSED); 2773 2774 static GXBB_PCLK(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2, CLK_IGNORE_UNUSED); 2775 static GXBB_PCLK(gxbb_eth, HHI_GCLK_MPEG1, 3, CLK_IGNORE_UNUSED); 2776 static GXBB_PCLK(gxbb_demux, HHI_GCLK_MPEG1, 4, CLK_IGNORE_UNUSED); 2777 static GXBB_PCLK(gxbb_blkmv, HHI_GCLK_MPEG1, 14, CLK_IGNORE_UNUSED); 2778 static GXBB_PCLK(gxbb_aiu, HHI_GCLK_MPEG1, 15, CLK_IGNORE_UNUSED); 2779 static GXBB_PCLK(gxbb_uart1, HHI_GCLK_MPEG1, 16, CLK_IGNORE_UNUSED); 2780 static GXBB_PCLK(gxbb_g2d, HHI_GCLK_MPEG1, 20, CLK_IGNORE_UNUSED); 2781 static GXBB_PCLK(gxbb_usb0, HHI_GCLK_MPEG1, 21, CLK_IGNORE_UNUSED); 2782 static GXBB_PCLK(gxbb_usb1, HHI_GCLK_MPEG1, 22, CLK_IGNORE_UNUSED); 2783 static GXBB_PCLK(gxbb_reset, HHI_GCLK_MPEG1, 23, CLK_IGNORE_UNUSED); 2784 static GXBB_PCLK(gxbb_nand, HHI_GCLK_MPEG1, 24, CLK_IGNORE_UNUSED); 2785 static GXBB_PCLK(gxbb_dos_parser, HHI_GCLK_MPEG1, 25, CLK_IGNORE_UNUSED); 2786 static GXBB_PCLK(gxbb_usb, HHI_GCLK_MPEG1, 26, CLK_IGNORE_UNUSED); 2787 static GXBB_PCLK(gxbb_vdin1, HHI_GCLK_MPEG1, 28, CLK_IGNORE_UNUSED); 2788 static GXBB_PCLK(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29, CLK_IGNORE_UNUSED); 2789 static GXBB_PCLK(gxbb_efuse, HHI_GCLK_MPEG1, 30, CLK_IGNORE_UNUSED); 2790 static GXBB_PCLK(gxbb_boot_rom, HHI_GCLK_MPEG1, 31, CLK_IGNORE_UNUSED); 2791 2792 static GXBB_PCLK(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1, CLK_IGNORE_UNUSED); 2793 static GXBB_PCLK(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2, CLK_IGNORE_UNUSED); 2794 static GXBB_PCLK(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3, CLK_IGNORE_UNUSED); 2795 static GXBB_PCLK(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4, CLK_IGNORE_UNUSED); 2796 static GXBB_PCLK(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8, CLK_IGNORE_UNUSED); 2797 static GXBB_PCLK(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9, CLK_IGNORE_UNUSED); 2798 static GXBB_PCLK(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11, CLK_IGNORE_UNUSED); 2799 static GXBB_PCLK(gxbb_dvin, HHI_GCLK_MPEG2, 12, CLK_IGNORE_UNUSED); 2800 static GXBB_PCLK(gxbb_uart2, HHI_GCLK_MPEG2, 15, CLK_IGNORE_UNUSED); 2801 static GXBB_PCLK(gxbb_sar_adc, HHI_GCLK_MPEG2, 22, CLK_IGNORE_UNUSED); 2802 static GXBB_PCLK(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25, CLK_IGNORE_UNUSED); 2803 static GXBB_PCLK(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26, CLK_IGNORE_UNUSED); 2804 static GXBB_PCLK(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29, CLK_IGNORE_UNUSED); 2805 2806 static GXBB_PCLK(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1, CLK_IGNORE_UNUSED); 2807 static GXBB_PCLK(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2, CLK_IGNORE_UNUSED); 2808 static GXBB_PCLK(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3, CLK_IGNORE_UNUSED); 2809 static GXBB_PCLK(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4, CLK_IGNORE_UNUSED); 2810 static GXBB_PCLK(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8, CLK_IGNORE_UNUSED); 2811 static GXBB_PCLK(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9, CLK_IGNORE_UNUSED); 2812 static GXBB_PCLK(gxbb_dac_clk, HHI_GCLK_OTHER, 10, CLK_IGNORE_UNUSED); 2813 static GXBB_PCLK(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14, CLK_IGNORE_UNUSED); 2814 static GXBB_PCLK(gxbb_iec958_gate, HHI_GCLK_OTHER, 16, CLK_IGNORE_UNUSED); 2815 static GXBB_PCLK(gxbb_enc480p, HHI_GCLK_OTHER, 20, CLK_IGNORE_UNUSED); 2816 static GXBB_PCLK(gxbb_rng1, HHI_GCLK_OTHER, 21, CLK_IGNORE_UNUSED); 2817 static GXBB_PCLK(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22, CLK_IGNORE_UNUSED); 2818 static GXBB_PCLK(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24, CLK_IGNORE_UNUSED); 2819 static GXBB_PCLK(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25, CLK_IGNORE_UNUSED); 2820 static GXBB_PCLK(gxbb_vclk_other, HHI_GCLK_OTHER, 26, CLK_IGNORE_UNUSED); 2821 static GXBB_PCLK(gxbb_edp, HHI_GCLK_OTHER, 31, CLK_IGNORE_UNUSED); 2822 2823 /* Always On (AO) domain gates */ 2824 2825 static GXBB_PCLK(gxbb_ao_media_cpu, HHI_GCLK_AO, 0, CLK_IGNORE_UNUSED); 2826 static GXBB_PCLK(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1, CLK_IGNORE_UNUSED); 2827 static GXBB_PCLK(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2, CLK_IGNORE_UNUSED); 2828 static GXBB_PCLK(gxbb_ao_iface, HHI_GCLK_AO, 3, CLK_IGNORE_UNUSED); 2829 static GXBB_PCLK(gxbb_ao_i2c, HHI_GCLK_AO, 4, CLK_IGNORE_UNUSED); 2830 2831 /* AIU gates */ 2832 static const struct clk_parent_data gxbb_aiu_glue_parents = { .hw = &gxbb_aiu.hw }; 2833 static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu_glue_parents, CLK_IGNORE_UNUSED); 2834 2835 static const struct clk_parent_data gxbb_aiu_pclk_parents = { .hw = &gxbb_aiu_glue.hw }; 2836 #define GXBB_AIU_PCLK(_name, _bit, _flags) \ 2837 MESON_PCLK(_name, HHI_GCLK_MPEG1, _bit, &gxbb_aiu_pclk_parents, _flags) 2838 2839 static GXBB_AIU_PCLK(gxbb_iec958, 7, CLK_IGNORE_UNUSED); 2840 static GXBB_AIU_PCLK(gxbb_i2s_out, 8, CLK_IGNORE_UNUSED); 2841 static GXBB_AIU_PCLK(gxbb_amclk, 9, CLK_IGNORE_UNUSED); 2842 static GXBB_AIU_PCLK(gxbb_aififo2, 10, CLK_IGNORE_UNUSED); 2843 static GXBB_AIU_PCLK(gxbb_mixer, 11, CLK_IGNORE_UNUSED); 2844 static GXBB_AIU_PCLK(gxbb_mixer_iface, 12, CLK_IGNORE_UNUSED); 2845 static GXBB_AIU_PCLK(gxbb_adc, 13, CLK_IGNORE_UNUSED); 2846 2847 /* Array of all clocks provided by this provider */ 2848 2849 static struct clk_hw *gxbb_hw_clks[] = { 2850 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 2851 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, 2852 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 2853 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 2854 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 2855 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 2856 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 2857 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 2858 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 2859 [CLKID_MPEG_SEL] = &gxbb_clk81_sel.hw, 2860 [CLKID_MPEG_DIV] = &gxbb_clk81_div.hw, 2861 [CLKID_CLK81] = &gxbb_clk81.hw, 2862 [CLKID_MPLL0] = &gxbb_mpll0.hw, 2863 [CLKID_MPLL1] = &gxbb_mpll1.hw, 2864 [CLKID_MPLL2] = &gxbb_mpll2.hw, 2865 [CLKID_DDR] = &gxbb_ddr.hw, 2866 [CLKID_DOS] = &gxbb_dos.hw, 2867 [CLKID_ISA] = &gxbb_isa.hw, 2868 [CLKID_PL301] = &gxbb_pl301.hw, 2869 [CLKID_PERIPHS] = &gxbb_periphs.hw, 2870 [CLKID_SPICC] = &gxbb_spicc.hw, 2871 [CLKID_I2C] = &gxbb_i2c.hw, 2872 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 2873 [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 2874 [CLKID_RNG0] = &gxbb_rng0.hw, 2875 [CLKID_UART0] = &gxbb_uart0.hw, 2876 [CLKID_SDHC] = &gxbb_sdhc.hw, 2877 [CLKID_STREAM] = &gxbb_stream.hw, 2878 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 2879 [CLKID_SDIO] = &gxbb_sdio.hw, 2880 [CLKID_ABUF] = &gxbb_abuf.hw, 2881 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 2882 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 2883 [CLKID_SPI] = &gxbb_spi.hw, 2884 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 2885 [CLKID_ETH] = &gxbb_eth.hw, 2886 [CLKID_DEMUX] = &gxbb_demux.hw, 2887 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 2888 [CLKID_IEC958] = &gxbb_iec958.hw, 2889 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 2890 [CLKID_AMCLK] = &gxbb_amclk.hw, 2891 [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 2892 [CLKID_MIXER] = &gxbb_mixer.hw, 2893 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 2894 [CLKID_ADC] = &gxbb_adc.hw, 2895 [CLKID_BLKMV] = &gxbb_blkmv.hw, 2896 [CLKID_AIU] = &gxbb_aiu.hw, 2897 [CLKID_UART1] = &gxbb_uart1.hw, 2898 [CLKID_G2D] = &gxbb_g2d.hw, 2899 [CLKID_USB0] = &gxbb_usb0.hw, 2900 [CLKID_USB1] = &gxbb_usb1.hw, 2901 [CLKID_RESET] = &gxbb_reset.hw, 2902 [CLKID_NAND] = &gxbb_nand.hw, 2903 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 2904 [CLKID_USB] = &gxbb_usb.hw, 2905 [CLKID_VDIN1] = &gxbb_vdin1.hw, 2906 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 2907 [CLKID_EFUSE] = &gxbb_efuse.hw, 2908 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 2909 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 2910 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 2911 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 2912 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 2913 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 2914 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 2915 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 2916 [CLKID_DVIN] = &gxbb_dvin.hw, 2917 [CLKID_UART2] = &gxbb_uart2.hw, 2918 [CLKID_SANA] = &gxbb_sana.hw, 2919 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 2920 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 2921 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 2922 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 2923 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 2924 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 2925 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 2926 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 2927 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 2928 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 2929 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 2930 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 2931 [CLKID_ENC480P] = &gxbb_enc480p.hw, 2932 [CLKID_RNG1] = &gxbb_rng1.hw, 2933 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 2934 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 2935 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 2936 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 2937 [CLKID_EDP] = &gxbb_edp.hw, 2938 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 2939 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 2940 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 2941 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 2942 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 2943 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 2944 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 2945 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 2946 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 2947 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 2948 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 2949 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 2950 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 2951 [CLKID_MALI_0] = &gxbb_mali_0.hw, 2952 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 2953 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 2954 [CLKID_MALI_1] = &gxbb_mali_1.hw, 2955 [CLKID_MALI] = &gxbb_mali.hw, 2956 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 2957 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 2958 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 2959 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 2960 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 2961 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 2962 [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 2963 [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 2964 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 2965 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 2966 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 2967 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 2968 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 2969 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 2970 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 2971 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 2972 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 2973 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 2974 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 2975 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 2976 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 2977 [CLKID_VPU_0] = &gxbb_vpu_0.hw, 2978 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 2979 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 2980 [CLKID_VPU_1] = &gxbb_vpu_1.hw, 2981 [CLKID_VPU] = &gxbb_vpu.hw, 2982 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 2983 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 2984 [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 2985 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 2986 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 2987 [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 2988 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 2989 [CLKID_VAPB] = &gxbb_vapb.hw, 2990 [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw, 2991 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw, 2992 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 2993 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 2994 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 2995 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 2996 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 2997 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 2998 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 2999 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 3000 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 3001 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 3002 [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 3003 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 3004 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 3005 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 3006 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 3007 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 3008 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 3009 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw, 3010 [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw, 3011 [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw, 3012 [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw, 3013 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw, 3014 [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw, 3015 [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw, 3016 [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw, 3017 [CLKID_VID_PLL] = &gxbb_vid_pll.hw, 3018 [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw, 3019 [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw, 3020 [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw, 3021 [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw, 3022 [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw, 3023 [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw, 3024 [CLKID_VCLK] = &gxbb_vclk.hw, 3025 [CLKID_VCLK2] = &gxbb_vclk2.hw, 3026 [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw, 3027 [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw, 3028 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw, 3029 [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw, 3030 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw, 3031 [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw, 3032 [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw, 3033 [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw, 3034 [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw, 3035 [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw, 3036 [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw, 3037 [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw, 3038 [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw, 3039 [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw, 3040 [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw, 3041 [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw, 3042 [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw, 3043 [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw, 3044 [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw, 3045 [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw, 3046 [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw, 3047 [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw, 3048 [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw, 3049 [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw, 3050 [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw, 3051 [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw, 3052 [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw, 3053 [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw, 3054 [CLKID_HDMI] = &gxbb_hdmi.hw, 3055 }; 3056 3057 static struct clk_hw *gxl_hw_clks[] = { 3058 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 3059 [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw, 3060 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 3061 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 3062 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 3063 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 3064 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 3065 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 3066 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 3067 [CLKID_MPEG_SEL] = &gxbb_clk81_sel.hw, 3068 [CLKID_MPEG_DIV] = &gxbb_clk81_div.hw, 3069 [CLKID_CLK81] = &gxbb_clk81.hw, 3070 [CLKID_MPLL0] = &gxbb_mpll0.hw, 3071 [CLKID_MPLL1] = &gxbb_mpll1.hw, 3072 [CLKID_MPLL2] = &gxbb_mpll2.hw, 3073 [CLKID_DDR] = &gxbb_ddr.hw, 3074 [CLKID_DOS] = &gxbb_dos.hw, 3075 [CLKID_ISA] = &gxbb_isa.hw, 3076 [CLKID_PL301] = &gxbb_pl301.hw, 3077 [CLKID_PERIPHS] = &gxbb_periphs.hw, 3078 [CLKID_SPICC] = &gxbb_spicc.hw, 3079 [CLKID_I2C] = &gxbb_i2c.hw, 3080 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 3081 [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 3082 [CLKID_RNG0] = &gxbb_rng0.hw, 3083 [CLKID_UART0] = &gxbb_uart0.hw, 3084 [CLKID_SDHC] = &gxbb_sdhc.hw, 3085 [CLKID_STREAM] = &gxbb_stream.hw, 3086 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 3087 [CLKID_SDIO] = &gxbb_sdio.hw, 3088 [CLKID_ABUF] = &gxbb_abuf.hw, 3089 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 3090 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 3091 [CLKID_SPI] = &gxbb_spi.hw, 3092 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 3093 [CLKID_ETH] = &gxbb_eth.hw, 3094 [CLKID_DEMUX] = &gxbb_demux.hw, 3095 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 3096 [CLKID_IEC958] = &gxbb_iec958.hw, 3097 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 3098 [CLKID_AMCLK] = &gxbb_amclk.hw, 3099 [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 3100 [CLKID_MIXER] = &gxbb_mixer.hw, 3101 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 3102 [CLKID_ADC] = &gxbb_adc.hw, 3103 [CLKID_BLKMV] = &gxbb_blkmv.hw, 3104 [CLKID_AIU] = &gxbb_aiu.hw, 3105 [CLKID_UART1] = &gxbb_uart1.hw, 3106 [CLKID_G2D] = &gxbb_g2d.hw, 3107 [CLKID_USB0] = &gxbb_usb0.hw, 3108 [CLKID_USB1] = &gxbb_usb1.hw, 3109 [CLKID_RESET] = &gxbb_reset.hw, 3110 [CLKID_NAND] = &gxbb_nand.hw, 3111 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 3112 [CLKID_USB] = &gxbb_usb.hw, 3113 [CLKID_VDIN1] = &gxbb_vdin1.hw, 3114 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 3115 [CLKID_EFUSE] = &gxbb_efuse.hw, 3116 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 3117 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 3118 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 3119 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 3120 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 3121 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 3122 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 3123 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 3124 [CLKID_DVIN] = &gxbb_dvin.hw, 3125 [CLKID_UART2] = &gxbb_uart2.hw, 3126 [CLKID_SANA] = &gxbb_sana.hw, 3127 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 3128 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 3129 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 3130 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 3131 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 3132 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 3133 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 3134 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 3135 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 3136 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 3137 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 3138 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 3139 [CLKID_ENC480P] = &gxbb_enc480p.hw, 3140 [CLKID_RNG1] = &gxbb_rng1.hw, 3141 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 3142 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 3143 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 3144 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 3145 [CLKID_EDP] = &gxbb_edp.hw, 3146 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 3147 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 3148 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 3149 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 3150 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 3151 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 3152 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 3153 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 3154 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 3155 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 3156 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 3157 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 3158 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 3159 [CLKID_MALI_0] = &gxbb_mali_0.hw, 3160 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 3161 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 3162 [CLKID_MALI_1] = &gxbb_mali_1.hw, 3163 [CLKID_MALI] = &gxbb_mali.hw, 3164 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 3165 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 3166 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 3167 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 3168 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 3169 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 3170 [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 3171 [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 3172 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 3173 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 3174 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 3175 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 3176 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 3177 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 3178 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 3179 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 3180 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 3181 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 3182 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 3183 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 3184 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 3185 [CLKID_VPU_0] = &gxbb_vpu_0.hw, 3186 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 3187 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 3188 [CLKID_VPU_1] = &gxbb_vpu_1.hw, 3189 [CLKID_VPU] = &gxbb_vpu.hw, 3190 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 3191 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 3192 [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 3193 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 3194 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 3195 [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 3196 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 3197 [CLKID_VAPB] = &gxbb_vapb.hw, 3198 [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw, 3199 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 3200 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 3201 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 3202 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 3203 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 3204 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 3205 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 3206 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 3207 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 3208 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 3209 [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 3210 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 3211 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 3212 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 3213 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 3214 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 3215 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 3216 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw, 3217 [CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw, 3218 [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw, 3219 [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw, 3220 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw, 3221 [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw, 3222 [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw, 3223 [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw, 3224 [CLKID_VID_PLL] = &gxbb_vid_pll.hw, 3225 [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw, 3226 [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw, 3227 [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw, 3228 [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw, 3229 [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw, 3230 [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw, 3231 [CLKID_VCLK] = &gxbb_vclk.hw, 3232 [CLKID_VCLK2] = &gxbb_vclk2.hw, 3233 [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw, 3234 [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw, 3235 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw, 3236 [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw, 3237 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw, 3238 [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw, 3239 [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw, 3240 [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw, 3241 [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw, 3242 [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw, 3243 [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw, 3244 [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw, 3245 [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw, 3246 [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw, 3247 [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw, 3248 [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw, 3249 [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw, 3250 [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw, 3251 [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw, 3252 [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw, 3253 [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw, 3254 [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw, 3255 [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw, 3256 [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw, 3257 [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw, 3258 [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw, 3259 [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw, 3260 [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw, 3261 [CLKID_HDMI] = &gxbb_hdmi.hw, 3262 [CLKID_ACODEC] = &gxl_acodec.hw, 3263 }; 3264 3265 static const struct meson_clkc_data gxbb_clkc_data = { 3266 .hw_clks = { 3267 .hws = gxbb_hw_clks, 3268 .num = ARRAY_SIZE(gxbb_hw_clks), 3269 }, 3270 }; 3271 3272 static const struct meson_clkc_data gxl_clkc_data = { 3273 .hw_clks = { 3274 .hws = gxl_hw_clks, 3275 .num = ARRAY_SIZE(gxl_hw_clks), 3276 }, 3277 }; 3278 3279 static const struct of_device_id gxbb_clkc_match_table[] = { 3280 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data }, 3281 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data }, 3282 {}, 3283 }; 3284 MODULE_DEVICE_TABLE(of, gxbb_clkc_match_table); 3285 3286 static struct platform_driver gxbb_clkc_driver = { 3287 .probe = meson_clkc_syscon_probe, 3288 .driver = { 3289 .name = "gxbb-clkc", 3290 .of_match_table = gxbb_clkc_match_table, 3291 }, 3292 }; 3293 module_platform_driver(gxbb_clkc_driver); 3294 3295 MODULE_DESCRIPTION("Amlogic GXBB Main Clock Controller driver"); 3296 MODULE_LICENSE("GPL"); 3297 MODULE_IMPORT_NS("CLK_MESON"); 3298