1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AmLogic Meson-AXG Clock Controller Driver 4 * 5 * Copyright (c) 2016 Baylibre SAS. 6 * Author: Michael Turquette <mturquette@baylibre.com> 7 * 8 * Copyright (c) 2017 Amlogic, inc. 9 * Author: Qiufang Dai <qiufang.dai@amlogic.com> 10 */ 11 12 #include <linux/clk-provider.h> 13 #include <linux/init.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 17 #include "clk-input.h" 18 #include "clk-regmap.h" 19 #include "clk-pll.h" 20 #include "clk-mpll.h" 21 #include "axg.h" 22 #include "meson-eeclk.h" 23 24 static DEFINE_SPINLOCK(meson_clk_lock); 25 26 static struct clk_regmap axg_fixed_pll_dco = { 27 .data = &(struct meson_clk_pll_data){ 28 .en = { 29 .reg_off = HHI_MPLL_CNTL, 30 .shift = 30, 31 .width = 1, 32 }, 33 .m = { 34 .reg_off = HHI_MPLL_CNTL, 35 .shift = 0, 36 .width = 9, 37 }, 38 .n = { 39 .reg_off = HHI_MPLL_CNTL, 40 .shift = 9, 41 .width = 5, 42 }, 43 .frac = { 44 .reg_off = HHI_MPLL_CNTL2, 45 .shift = 0, 46 .width = 12, 47 }, 48 .l = { 49 .reg_off = HHI_MPLL_CNTL, 50 .shift = 31, 51 .width = 1, 52 }, 53 .rst = { 54 .reg_off = HHI_MPLL_CNTL, 55 .shift = 29, 56 .width = 1, 57 }, 58 }, 59 .hw.init = &(struct clk_init_data){ 60 .name = "fixed_pll_dco", 61 .ops = &meson_clk_pll_ro_ops, 62 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 63 .num_parents = 1, 64 }, 65 }; 66 67 static struct clk_regmap axg_fixed_pll = { 68 .data = &(struct clk_regmap_div_data){ 69 .offset = HHI_MPLL_CNTL, 70 .shift = 16, 71 .width = 2, 72 .flags = CLK_DIVIDER_POWER_OF_TWO, 73 }, 74 .hw.init = &(struct clk_init_data){ 75 .name = "fixed_pll", 76 .ops = &clk_regmap_divider_ro_ops, 77 .parent_names = (const char *[]){ "fixed_pll_dco" }, 78 .num_parents = 1, 79 /* 80 * This clock won't ever change at runtime so 81 * CLK_SET_RATE_PARENT is not required 82 */ 83 }, 84 }; 85 86 static struct clk_regmap axg_sys_pll_dco = { 87 .data = &(struct meson_clk_pll_data){ 88 .en = { 89 .reg_off = HHI_SYS_PLL_CNTL, 90 .shift = 30, 91 .width = 1, 92 }, 93 .m = { 94 .reg_off = HHI_SYS_PLL_CNTL, 95 .shift = 0, 96 .width = 9, 97 }, 98 .n = { 99 .reg_off = HHI_SYS_PLL_CNTL, 100 .shift = 9, 101 .width = 5, 102 }, 103 .l = { 104 .reg_off = HHI_SYS_PLL_CNTL, 105 .shift = 31, 106 .width = 1, 107 }, 108 .rst = { 109 .reg_off = HHI_SYS_PLL_CNTL, 110 .shift = 29, 111 .width = 1, 112 }, 113 }, 114 .hw.init = &(struct clk_init_data){ 115 .name = "sys_pll_dco", 116 .ops = &meson_clk_pll_ro_ops, 117 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 118 .num_parents = 1, 119 }, 120 }; 121 122 static struct clk_regmap axg_sys_pll = { 123 .data = &(struct clk_regmap_div_data){ 124 .offset = HHI_SYS_PLL_CNTL, 125 .shift = 16, 126 .width = 2, 127 .flags = CLK_DIVIDER_POWER_OF_TWO, 128 }, 129 .hw.init = &(struct clk_init_data){ 130 .name = "sys_pll", 131 .ops = &clk_regmap_divider_ro_ops, 132 .parent_names = (const char *[]){ "sys_pll_dco" }, 133 .num_parents = 1, 134 .flags = CLK_SET_RATE_PARENT, 135 }, 136 }; 137 138 static const struct pll_params_table axg_gp0_pll_params_table[] = { 139 PLL_PARAMS(40, 1), 140 PLL_PARAMS(41, 1), 141 PLL_PARAMS(42, 1), 142 PLL_PARAMS(43, 1), 143 PLL_PARAMS(44, 1), 144 PLL_PARAMS(45, 1), 145 PLL_PARAMS(46, 1), 146 PLL_PARAMS(47, 1), 147 PLL_PARAMS(48, 1), 148 PLL_PARAMS(49, 1), 149 PLL_PARAMS(50, 1), 150 PLL_PARAMS(51, 1), 151 PLL_PARAMS(52, 1), 152 PLL_PARAMS(53, 1), 153 PLL_PARAMS(54, 1), 154 PLL_PARAMS(55, 1), 155 PLL_PARAMS(56, 1), 156 PLL_PARAMS(57, 1), 157 PLL_PARAMS(58, 1), 158 PLL_PARAMS(59, 1), 159 PLL_PARAMS(60, 1), 160 PLL_PARAMS(61, 1), 161 PLL_PARAMS(62, 1), 162 PLL_PARAMS(63, 1), 163 PLL_PARAMS(64, 1), 164 PLL_PARAMS(65, 1), 165 PLL_PARAMS(66, 1), 166 PLL_PARAMS(67, 1), 167 PLL_PARAMS(68, 1), 168 { /* sentinel */ }, 169 }; 170 171 static const struct reg_sequence axg_gp0_init_regs[] = { 172 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 }, 173 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, 174 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, 175 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, 176 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, 177 }; 178 179 static struct clk_regmap axg_gp0_pll_dco = { 180 .data = &(struct meson_clk_pll_data){ 181 .en = { 182 .reg_off = HHI_GP0_PLL_CNTL, 183 .shift = 30, 184 .width = 1, 185 }, 186 .m = { 187 .reg_off = HHI_GP0_PLL_CNTL, 188 .shift = 0, 189 .width = 9, 190 }, 191 .n = { 192 .reg_off = HHI_GP0_PLL_CNTL, 193 .shift = 9, 194 .width = 5, 195 }, 196 .frac = { 197 .reg_off = HHI_GP0_PLL_CNTL1, 198 .shift = 0, 199 .width = 10, 200 }, 201 .l = { 202 .reg_off = HHI_GP0_PLL_CNTL, 203 .shift = 31, 204 .width = 1, 205 }, 206 .rst = { 207 .reg_off = HHI_GP0_PLL_CNTL, 208 .shift = 29, 209 .width = 1, 210 }, 211 .table = axg_gp0_pll_params_table, 212 .init_regs = axg_gp0_init_regs, 213 .init_count = ARRAY_SIZE(axg_gp0_init_regs), 214 }, 215 .hw.init = &(struct clk_init_data){ 216 .name = "gp0_pll_dco", 217 .ops = &meson_clk_pll_ops, 218 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 219 .num_parents = 1, 220 }, 221 }; 222 223 static struct clk_regmap axg_gp0_pll = { 224 .data = &(struct clk_regmap_div_data){ 225 .offset = HHI_GP0_PLL_CNTL, 226 .shift = 16, 227 .width = 2, 228 .flags = CLK_DIVIDER_POWER_OF_TWO, 229 }, 230 .hw.init = &(struct clk_init_data){ 231 .name = "gp0_pll", 232 .ops = &clk_regmap_divider_ops, 233 .parent_names = (const char *[]){ "gp0_pll_dco" }, 234 .num_parents = 1, 235 .flags = CLK_SET_RATE_PARENT, 236 }, 237 }; 238 239 static const struct reg_sequence axg_hifi_init_regs[] = { 240 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0xc084b000 }, 241 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0xb75020be }, 242 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 }, 243 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0xc000004d }, 244 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x00058000 }, 245 }; 246 247 static struct clk_regmap axg_hifi_pll_dco = { 248 .data = &(struct meson_clk_pll_data){ 249 .en = { 250 .reg_off = HHI_HIFI_PLL_CNTL, 251 .shift = 30, 252 .width = 1, 253 }, 254 .m = { 255 .reg_off = HHI_HIFI_PLL_CNTL, 256 .shift = 0, 257 .width = 9, 258 }, 259 .n = { 260 .reg_off = HHI_HIFI_PLL_CNTL, 261 .shift = 9, 262 .width = 5, 263 }, 264 .frac = { 265 .reg_off = HHI_HIFI_PLL_CNTL5, 266 .shift = 0, 267 .width = 13, 268 }, 269 .l = { 270 .reg_off = HHI_HIFI_PLL_CNTL, 271 .shift = 31, 272 .width = 1, 273 }, 274 .rst = { 275 .reg_off = HHI_HIFI_PLL_CNTL, 276 .shift = 29, 277 .width = 1, 278 }, 279 .table = axg_gp0_pll_params_table, 280 .init_regs = axg_hifi_init_regs, 281 .init_count = ARRAY_SIZE(axg_hifi_init_regs), 282 .flags = CLK_MESON_PLL_ROUND_CLOSEST, 283 }, 284 .hw.init = &(struct clk_init_data){ 285 .name = "hifi_pll_dco", 286 .ops = &meson_clk_pll_ops, 287 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 288 .num_parents = 1, 289 }, 290 }; 291 292 static struct clk_regmap axg_hifi_pll = { 293 .data = &(struct clk_regmap_div_data){ 294 .offset = HHI_HIFI_PLL_CNTL, 295 .shift = 16, 296 .width = 2, 297 .flags = CLK_DIVIDER_POWER_OF_TWO, 298 }, 299 .hw.init = &(struct clk_init_data){ 300 .name = "hifi_pll", 301 .ops = &clk_regmap_divider_ops, 302 .parent_names = (const char *[]){ "hifi_pll_dco" }, 303 .num_parents = 1, 304 .flags = CLK_SET_RATE_PARENT, 305 }, 306 }; 307 308 static struct clk_fixed_factor axg_fclk_div2_div = { 309 .mult = 1, 310 .div = 2, 311 .hw.init = &(struct clk_init_data){ 312 .name = "fclk_div2_div", 313 .ops = &clk_fixed_factor_ops, 314 .parent_names = (const char *[]){ "fixed_pll" }, 315 .num_parents = 1, 316 }, 317 }; 318 319 static struct clk_regmap axg_fclk_div2 = { 320 .data = &(struct clk_regmap_gate_data){ 321 .offset = HHI_MPLL_CNTL6, 322 .bit_idx = 27, 323 }, 324 .hw.init = &(struct clk_init_data){ 325 .name = "fclk_div2", 326 .ops = &clk_regmap_gate_ops, 327 .parent_names = (const char *[]){ "fclk_div2_div" }, 328 .num_parents = 1, 329 .flags = CLK_IS_CRITICAL, 330 }, 331 }; 332 333 static struct clk_fixed_factor axg_fclk_div3_div = { 334 .mult = 1, 335 .div = 3, 336 .hw.init = &(struct clk_init_data){ 337 .name = "fclk_div3_div", 338 .ops = &clk_fixed_factor_ops, 339 .parent_names = (const char *[]){ "fixed_pll" }, 340 .num_parents = 1, 341 }, 342 }; 343 344 static struct clk_regmap axg_fclk_div3 = { 345 .data = &(struct clk_regmap_gate_data){ 346 .offset = HHI_MPLL_CNTL6, 347 .bit_idx = 28, 348 }, 349 .hw.init = &(struct clk_init_data){ 350 .name = "fclk_div3", 351 .ops = &clk_regmap_gate_ops, 352 .parent_names = (const char *[]){ "fclk_div3_div" }, 353 .num_parents = 1, 354 /* 355 * FIXME: 356 * This clock, as fdiv2, is used by the SCPI FW and is required 357 * by the platform to operate correctly. 358 * Until the following condition are met, we need this clock to 359 * be marked as critical: 360 * a) The SCPI generic driver claims and enable all the clocks 361 * it needs 362 * b) CCF has a clock hand-off mechanism to make the sure the 363 * clock stays on until the proper driver comes along 364 */ 365 .flags = CLK_IS_CRITICAL, 366 }, 367 }; 368 369 static struct clk_fixed_factor axg_fclk_div4_div = { 370 .mult = 1, 371 .div = 4, 372 .hw.init = &(struct clk_init_data){ 373 .name = "fclk_div4_div", 374 .ops = &clk_fixed_factor_ops, 375 .parent_names = (const char *[]){ "fixed_pll" }, 376 .num_parents = 1, 377 }, 378 }; 379 380 static struct clk_regmap axg_fclk_div4 = { 381 .data = &(struct clk_regmap_gate_data){ 382 .offset = HHI_MPLL_CNTL6, 383 .bit_idx = 29, 384 }, 385 .hw.init = &(struct clk_init_data){ 386 .name = "fclk_div4", 387 .ops = &clk_regmap_gate_ops, 388 .parent_names = (const char *[]){ "fclk_div4_div" }, 389 .num_parents = 1, 390 }, 391 }; 392 393 static struct clk_fixed_factor axg_fclk_div5_div = { 394 .mult = 1, 395 .div = 5, 396 .hw.init = &(struct clk_init_data){ 397 .name = "fclk_div5_div", 398 .ops = &clk_fixed_factor_ops, 399 .parent_names = (const char *[]){ "fixed_pll" }, 400 .num_parents = 1, 401 }, 402 }; 403 404 static struct clk_regmap axg_fclk_div5 = { 405 .data = &(struct clk_regmap_gate_data){ 406 .offset = HHI_MPLL_CNTL6, 407 .bit_idx = 30, 408 }, 409 .hw.init = &(struct clk_init_data){ 410 .name = "fclk_div5", 411 .ops = &clk_regmap_gate_ops, 412 .parent_names = (const char *[]){ "fclk_div5_div" }, 413 .num_parents = 1, 414 }, 415 }; 416 417 static struct clk_fixed_factor axg_fclk_div7_div = { 418 .mult = 1, 419 .div = 7, 420 .hw.init = &(struct clk_init_data){ 421 .name = "fclk_div7_div", 422 .ops = &clk_fixed_factor_ops, 423 .parent_names = (const char *[]){ "fixed_pll" }, 424 .num_parents = 1, 425 }, 426 }; 427 428 static struct clk_regmap axg_fclk_div7 = { 429 .data = &(struct clk_regmap_gate_data){ 430 .offset = HHI_MPLL_CNTL6, 431 .bit_idx = 31, 432 }, 433 .hw.init = &(struct clk_init_data){ 434 .name = "fclk_div7", 435 .ops = &clk_regmap_gate_ops, 436 .parent_names = (const char *[]){ "fclk_div7_div" }, 437 .num_parents = 1, 438 }, 439 }; 440 441 static struct clk_regmap axg_mpll_prediv = { 442 .data = &(struct clk_regmap_div_data){ 443 .offset = HHI_MPLL_CNTL5, 444 .shift = 12, 445 .width = 1, 446 }, 447 .hw.init = &(struct clk_init_data){ 448 .name = "mpll_prediv", 449 .ops = &clk_regmap_divider_ro_ops, 450 .parent_names = (const char *[]){ "fixed_pll" }, 451 .num_parents = 1, 452 }, 453 }; 454 455 static struct clk_regmap axg_mpll0_div = { 456 .data = &(struct meson_clk_mpll_data){ 457 .sdm = { 458 .reg_off = HHI_MPLL_CNTL7, 459 .shift = 0, 460 .width = 14, 461 }, 462 .sdm_en = { 463 .reg_off = HHI_MPLL_CNTL7, 464 .shift = 15, 465 .width = 1, 466 }, 467 .n2 = { 468 .reg_off = HHI_MPLL_CNTL7, 469 .shift = 16, 470 .width = 9, 471 }, 472 .ssen = { 473 .reg_off = HHI_MPLL_CNTL, 474 .shift = 25, 475 .width = 1, 476 }, 477 .misc = { 478 .reg_off = HHI_PLL_TOP_MISC, 479 .shift = 0, 480 .width = 1, 481 }, 482 .lock = &meson_clk_lock, 483 .flags = CLK_MESON_MPLL_ROUND_CLOSEST, 484 }, 485 .hw.init = &(struct clk_init_data){ 486 .name = "mpll0_div", 487 .ops = &meson_clk_mpll_ops, 488 .parent_names = (const char *[]){ "mpll_prediv" }, 489 .num_parents = 1, 490 }, 491 }; 492 493 static struct clk_regmap axg_mpll0 = { 494 .data = &(struct clk_regmap_gate_data){ 495 .offset = HHI_MPLL_CNTL7, 496 .bit_idx = 14, 497 }, 498 .hw.init = &(struct clk_init_data){ 499 .name = "mpll0", 500 .ops = &clk_regmap_gate_ops, 501 .parent_names = (const char *[]){ "mpll0_div" }, 502 .num_parents = 1, 503 .flags = CLK_SET_RATE_PARENT, 504 }, 505 }; 506 507 static struct clk_regmap axg_mpll1_div = { 508 .data = &(struct meson_clk_mpll_data){ 509 .sdm = { 510 .reg_off = HHI_MPLL_CNTL8, 511 .shift = 0, 512 .width = 14, 513 }, 514 .sdm_en = { 515 .reg_off = HHI_MPLL_CNTL8, 516 .shift = 15, 517 .width = 1, 518 }, 519 .n2 = { 520 .reg_off = HHI_MPLL_CNTL8, 521 .shift = 16, 522 .width = 9, 523 }, 524 .misc = { 525 .reg_off = HHI_PLL_TOP_MISC, 526 .shift = 1, 527 .width = 1, 528 }, 529 .lock = &meson_clk_lock, 530 .flags = CLK_MESON_MPLL_ROUND_CLOSEST, 531 }, 532 .hw.init = &(struct clk_init_data){ 533 .name = "mpll1_div", 534 .ops = &meson_clk_mpll_ops, 535 .parent_names = (const char *[]){ "mpll_prediv" }, 536 .num_parents = 1, 537 }, 538 }; 539 540 static struct clk_regmap axg_mpll1 = { 541 .data = &(struct clk_regmap_gate_data){ 542 .offset = HHI_MPLL_CNTL8, 543 .bit_idx = 14, 544 }, 545 .hw.init = &(struct clk_init_data){ 546 .name = "mpll1", 547 .ops = &clk_regmap_gate_ops, 548 .parent_names = (const char *[]){ "mpll1_div" }, 549 .num_parents = 1, 550 .flags = CLK_SET_RATE_PARENT, 551 }, 552 }; 553 554 static struct clk_regmap axg_mpll2_div = { 555 .data = &(struct meson_clk_mpll_data){ 556 .sdm = { 557 .reg_off = HHI_MPLL_CNTL9, 558 .shift = 0, 559 .width = 14, 560 }, 561 .sdm_en = { 562 .reg_off = HHI_MPLL_CNTL9, 563 .shift = 15, 564 .width = 1, 565 }, 566 .n2 = { 567 .reg_off = HHI_MPLL_CNTL9, 568 .shift = 16, 569 .width = 9, 570 }, 571 .misc = { 572 .reg_off = HHI_PLL_TOP_MISC, 573 .shift = 2, 574 .width = 1, 575 }, 576 .lock = &meson_clk_lock, 577 .flags = CLK_MESON_MPLL_ROUND_CLOSEST, 578 }, 579 .hw.init = &(struct clk_init_data){ 580 .name = "mpll2_div", 581 .ops = &meson_clk_mpll_ops, 582 .parent_names = (const char *[]){ "mpll_prediv" }, 583 .num_parents = 1, 584 }, 585 }; 586 587 static struct clk_regmap axg_mpll2 = { 588 .data = &(struct clk_regmap_gate_data){ 589 .offset = HHI_MPLL_CNTL9, 590 .bit_idx = 14, 591 }, 592 .hw.init = &(struct clk_init_data){ 593 .name = "mpll2", 594 .ops = &clk_regmap_gate_ops, 595 .parent_names = (const char *[]){ "mpll2_div" }, 596 .num_parents = 1, 597 .flags = CLK_SET_RATE_PARENT, 598 }, 599 }; 600 601 static struct clk_regmap axg_mpll3_div = { 602 .data = &(struct meson_clk_mpll_data){ 603 .sdm = { 604 .reg_off = HHI_MPLL3_CNTL0, 605 .shift = 12, 606 .width = 14, 607 }, 608 .sdm_en = { 609 .reg_off = HHI_MPLL3_CNTL0, 610 .shift = 11, 611 .width = 1, 612 }, 613 .n2 = { 614 .reg_off = HHI_MPLL3_CNTL0, 615 .shift = 2, 616 .width = 9, 617 }, 618 .misc = { 619 .reg_off = HHI_PLL_TOP_MISC, 620 .shift = 3, 621 .width = 1, 622 }, 623 .lock = &meson_clk_lock, 624 .flags = CLK_MESON_MPLL_ROUND_CLOSEST, 625 }, 626 .hw.init = &(struct clk_init_data){ 627 .name = "mpll3_div", 628 .ops = &meson_clk_mpll_ops, 629 .parent_names = (const char *[]){ "mpll_prediv" }, 630 .num_parents = 1, 631 }, 632 }; 633 634 static struct clk_regmap axg_mpll3 = { 635 .data = &(struct clk_regmap_gate_data){ 636 .offset = HHI_MPLL3_CNTL0, 637 .bit_idx = 0, 638 }, 639 .hw.init = &(struct clk_init_data){ 640 .name = "mpll3", 641 .ops = &clk_regmap_gate_ops, 642 .parent_names = (const char *[]){ "mpll3_div" }, 643 .num_parents = 1, 644 .flags = CLK_SET_RATE_PARENT, 645 }, 646 }; 647 648 static const struct pll_params_table axg_pcie_pll_params_table[] = { 649 { 650 .m = 200, 651 .n = 3, 652 }, 653 { /* sentinel */ }, 654 }; 655 656 static const struct reg_sequence axg_pcie_init_regs[] = { 657 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x0084a2aa }, 658 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0xb75020be }, 659 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x0a47488e }, 660 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0xc000004d }, 661 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x00078000 }, 662 { .reg = HHI_PCIE_PLL_CNTL6, .def = 0x002323c6 }, 663 { .reg = HHI_PCIE_PLL_CNTL, .def = 0x400106c8 }, 664 }; 665 666 static struct clk_regmap axg_pcie_pll_dco = { 667 .data = &(struct meson_clk_pll_data){ 668 .en = { 669 .reg_off = HHI_PCIE_PLL_CNTL, 670 .shift = 30, 671 .width = 1, 672 }, 673 .m = { 674 .reg_off = HHI_PCIE_PLL_CNTL, 675 .shift = 0, 676 .width = 9, 677 }, 678 .n = { 679 .reg_off = HHI_PCIE_PLL_CNTL, 680 .shift = 9, 681 .width = 5, 682 }, 683 .frac = { 684 .reg_off = HHI_PCIE_PLL_CNTL1, 685 .shift = 0, 686 .width = 12, 687 }, 688 .l = { 689 .reg_off = HHI_PCIE_PLL_CNTL, 690 .shift = 31, 691 .width = 1, 692 }, 693 .rst = { 694 .reg_off = HHI_PCIE_PLL_CNTL, 695 .shift = 29, 696 .width = 1, 697 }, 698 .table = axg_pcie_pll_params_table, 699 .init_regs = axg_pcie_init_regs, 700 .init_count = ARRAY_SIZE(axg_pcie_init_regs), 701 }, 702 .hw.init = &(struct clk_init_data){ 703 .name = "pcie_pll_dco", 704 .ops = &meson_clk_pll_ops, 705 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 706 .num_parents = 1, 707 }, 708 }; 709 710 static struct clk_regmap axg_pcie_pll_od = { 711 .data = &(struct clk_regmap_div_data){ 712 .offset = HHI_PCIE_PLL_CNTL, 713 .shift = 16, 714 .width = 2, 715 .flags = CLK_DIVIDER_POWER_OF_TWO, 716 }, 717 .hw.init = &(struct clk_init_data){ 718 .name = "pcie_pll_od", 719 .ops = &clk_regmap_divider_ops, 720 .parent_names = (const char *[]){ "pcie_pll_dco" }, 721 .num_parents = 1, 722 .flags = CLK_SET_RATE_PARENT, 723 }, 724 }; 725 726 static struct clk_regmap axg_pcie_pll = { 727 .data = &(struct clk_regmap_div_data){ 728 .offset = HHI_PCIE_PLL_CNTL6, 729 .shift = 6, 730 .width = 2, 731 .flags = CLK_DIVIDER_POWER_OF_TWO, 732 }, 733 .hw.init = &(struct clk_init_data){ 734 .name = "pcie_pll", 735 .ops = &clk_regmap_divider_ops, 736 .parent_names = (const char *[]){ "pcie_pll_od" }, 737 .num_parents = 1, 738 .flags = CLK_SET_RATE_PARENT, 739 }, 740 }; 741 742 static struct clk_regmap axg_pcie_mux = { 743 .data = &(struct clk_regmap_mux_data){ 744 .offset = HHI_PCIE_PLL_CNTL6, 745 .mask = 0x1, 746 .shift = 2, 747 /* skip the parent mpll3, reserved for debug */ 748 .table = (u32[]){ 1 }, 749 }, 750 .hw.init = &(struct clk_init_data){ 751 .name = "pcie_mux", 752 .ops = &clk_regmap_mux_ops, 753 .parent_names = (const char *[]){ "pcie_pll" }, 754 .num_parents = 1, 755 .flags = CLK_SET_RATE_PARENT, 756 }, 757 }; 758 759 static struct clk_regmap axg_pcie_ref = { 760 .data = &(struct clk_regmap_mux_data){ 761 .offset = HHI_PCIE_PLL_CNTL6, 762 .mask = 0x1, 763 .shift = 1, 764 /* skip the parent 0, reserved for debug */ 765 .table = (u32[]){ 1 }, 766 }, 767 .hw.init = &(struct clk_init_data){ 768 .name = "pcie_ref", 769 .ops = &clk_regmap_mux_ops, 770 .parent_names = (const char *[]){ "pcie_mux" }, 771 .num_parents = 1, 772 .flags = CLK_SET_RATE_PARENT, 773 }, 774 }; 775 776 static struct clk_regmap axg_pcie_cml_en0 = { 777 .data = &(struct clk_regmap_gate_data){ 778 .offset = HHI_PCIE_PLL_CNTL6, 779 .bit_idx = 4, 780 }, 781 .hw.init = &(struct clk_init_data) { 782 .name = "pcie_cml_en0", 783 .ops = &clk_regmap_gate_ops, 784 .parent_names = (const char *[]){ "pcie_ref" }, 785 .num_parents = 1, 786 .flags = CLK_SET_RATE_PARENT, 787 788 }, 789 }; 790 791 static struct clk_regmap axg_pcie_cml_en1 = { 792 .data = &(struct clk_regmap_gate_data){ 793 .offset = HHI_PCIE_PLL_CNTL6, 794 .bit_idx = 3, 795 }, 796 .hw.init = &(struct clk_init_data) { 797 .name = "pcie_cml_en1", 798 .ops = &clk_regmap_gate_ops, 799 .parent_names = (const char *[]){ "pcie_ref" }, 800 .num_parents = 1, 801 .flags = CLK_SET_RATE_PARENT, 802 }, 803 }; 804 805 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; 806 static const char * const clk81_parent_names[] = { 807 IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", 808 "fclk_div3", "fclk_div5" 809 }; 810 811 static struct clk_regmap axg_mpeg_clk_sel = { 812 .data = &(struct clk_regmap_mux_data){ 813 .offset = HHI_MPEG_CLK_CNTL, 814 .mask = 0x7, 815 .shift = 12, 816 .table = mux_table_clk81, 817 }, 818 .hw.init = &(struct clk_init_data){ 819 .name = "mpeg_clk_sel", 820 .ops = &clk_regmap_mux_ro_ops, 821 .parent_names = clk81_parent_names, 822 .num_parents = ARRAY_SIZE(clk81_parent_names), 823 }, 824 }; 825 826 static struct clk_regmap axg_mpeg_clk_div = { 827 .data = &(struct clk_regmap_div_data){ 828 .offset = HHI_MPEG_CLK_CNTL, 829 .shift = 0, 830 .width = 7, 831 }, 832 .hw.init = &(struct clk_init_data){ 833 .name = "mpeg_clk_div", 834 .ops = &clk_regmap_divider_ops, 835 .parent_names = (const char *[]){ "mpeg_clk_sel" }, 836 .num_parents = 1, 837 .flags = CLK_SET_RATE_PARENT, 838 }, 839 }; 840 841 static struct clk_regmap axg_clk81 = { 842 .data = &(struct clk_regmap_gate_data){ 843 .offset = HHI_MPEG_CLK_CNTL, 844 .bit_idx = 7, 845 }, 846 .hw.init = &(struct clk_init_data){ 847 .name = "clk81", 848 .ops = &clk_regmap_gate_ops, 849 .parent_names = (const char *[]){ "mpeg_clk_div" }, 850 .num_parents = 1, 851 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), 852 }, 853 }; 854 855 static const char * const axg_sd_emmc_clk0_parent_names[] = { 856 IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7", 857 858 /* 859 * Following these parent clocks, we should also have had mpll2, mpll3 860 * and gp0_pll but these clocks are too precious to be used here. All 861 * the necessary rates for MMC and NAND operation can be acheived using 862 * xtal or fclk_div clocks 863 */ 864 }; 865 866 /* SDcard clock */ 867 static struct clk_regmap axg_sd_emmc_b_clk0_sel = { 868 .data = &(struct clk_regmap_mux_data){ 869 .offset = HHI_SD_EMMC_CLK_CNTL, 870 .mask = 0x7, 871 .shift = 25, 872 }, 873 .hw.init = &(struct clk_init_data) { 874 .name = "sd_emmc_b_clk0_sel", 875 .ops = &clk_regmap_mux_ops, 876 .parent_names = axg_sd_emmc_clk0_parent_names, 877 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names), 878 .flags = CLK_SET_RATE_PARENT, 879 }, 880 }; 881 882 static struct clk_regmap axg_sd_emmc_b_clk0_div = { 883 .data = &(struct clk_regmap_div_data){ 884 .offset = HHI_SD_EMMC_CLK_CNTL, 885 .shift = 16, 886 .width = 7, 887 .flags = CLK_DIVIDER_ROUND_CLOSEST, 888 }, 889 .hw.init = &(struct clk_init_data) { 890 .name = "sd_emmc_b_clk0_div", 891 .ops = &clk_regmap_divider_ops, 892 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" }, 893 .num_parents = 1, 894 .flags = CLK_SET_RATE_PARENT, 895 }, 896 }; 897 898 static struct clk_regmap axg_sd_emmc_b_clk0 = { 899 .data = &(struct clk_regmap_gate_data){ 900 .offset = HHI_SD_EMMC_CLK_CNTL, 901 .bit_idx = 23, 902 }, 903 .hw.init = &(struct clk_init_data){ 904 .name = "sd_emmc_b_clk0", 905 .ops = &clk_regmap_gate_ops, 906 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" }, 907 .num_parents = 1, 908 .flags = CLK_SET_RATE_PARENT, 909 }, 910 }; 911 912 /* EMMC/NAND clock */ 913 static struct clk_regmap axg_sd_emmc_c_clk0_sel = { 914 .data = &(struct clk_regmap_mux_data){ 915 .offset = HHI_NAND_CLK_CNTL, 916 .mask = 0x7, 917 .shift = 9, 918 }, 919 .hw.init = &(struct clk_init_data) { 920 .name = "sd_emmc_c_clk0_sel", 921 .ops = &clk_regmap_mux_ops, 922 .parent_names = axg_sd_emmc_clk0_parent_names, 923 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names), 924 .flags = CLK_SET_RATE_PARENT, 925 }, 926 }; 927 928 static struct clk_regmap axg_sd_emmc_c_clk0_div = { 929 .data = &(struct clk_regmap_div_data){ 930 .offset = HHI_NAND_CLK_CNTL, 931 .shift = 0, 932 .width = 7, 933 .flags = CLK_DIVIDER_ROUND_CLOSEST, 934 }, 935 .hw.init = &(struct clk_init_data) { 936 .name = "sd_emmc_c_clk0_div", 937 .ops = &clk_regmap_divider_ops, 938 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" }, 939 .num_parents = 1, 940 .flags = CLK_SET_RATE_PARENT, 941 }, 942 }; 943 944 static struct clk_regmap axg_sd_emmc_c_clk0 = { 945 .data = &(struct clk_regmap_gate_data){ 946 .offset = HHI_NAND_CLK_CNTL, 947 .bit_idx = 7, 948 }, 949 .hw.init = &(struct clk_init_data){ 950 .name = "sd_emmc_c_clk0", 951 .ops = &clk_regmap_gate_ops, 952 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" }, 953 .num_parents = 1, 954 .flags = CLK_SET_RATE_PARENT, 955 }, 956 }; 957 958 static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8, 959 9, 10, 11, 13, 14, }; 960 static const char * const gen_clk_parent_names[] = { 961 IN_PREFIX "xtal", "hifi_pll", "mpll0", "mpll1", "mpll2", "mpll3", 962 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll", 963 }; 964 965 static struct clk_regmap axg_gen_clk_sel = { 966 .data = &(struct clk_regmap_mux_data){ 967 .offset = HHI_GEN_CLK_CNTL, 968 .mask = 0xf, 969 .shift = 12, 970 .table = mux_table_gen_clk, 971 }, 972 .hw.init = &(struct clk_init_data){ 973 .name = "gen_clk_sel", 974 .ops = &clk_regmap_mux_ops, 975 /* 976 * bits 15:12 selects from 14 possible parents: 977 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt], 978 * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4, 979 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll 980 */ 981 .parent_names = gen_clk_parent_names, 982 .num_parents = ARRAY_SIZE(gen_clk_parent_names), 983 }, 984 }; 985 986 static struct clk_regmap axg_gen_clk_div = { 987 .data = &(struct clk_regmap_div_data){ 988 .offset = HHI_GEN_CLK_CNTL, 989 .shift = 0, 990 .width = 11, 991 }, 992 .hw.init = &(struct clk_init_data){ 993 .name = "gen_clk_div", 994 .ops = &clk_regmap_divider_ops, 995 .parent_names = (const char *[]){ "gen_clk_sel" }, 996 .num_parents = 1, 997 .flags = CLK_SET_RATE_PARENT, 998 }, 999 }; 1000 1001 static struct clk_regmap axg_gen_clk = { 1002 .data = &(struct clk_regmap_gate_data){ 1003 .offset = HHI_GEN_CLK_CNTL, 1004 .bit_idx = 7, 1005 }, 1006 .hw.init = &(struct clk_init_data){ 1007 .name = "gen_clk", 1008 .ops = &clk_regmap_gate_ops, 1009 .parent_names = (const char *[]){ "gen_clk_div" }, 1010 .num_parents = 1, 1011 .flags = CLK_SET_RATE_PARENT, 1012 }, 1013 }; 1014 1015 /* Everything Else (EE) domain gates */ 1016 static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0); 1017 static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2); 1018 static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3); 1019 static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5); 1020 static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6); 1021 static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7); 1022 static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8); 1023 static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9); 1024 static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12); 1025 static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13); 1026 static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14); 1027 static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15); 1028 static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16); 1029 static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17); 1030 static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19); 1031 static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23); 1032 static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25); 1033 static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26); 1034 static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27); 1035 static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30); 1036 1037 static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0); 1038 static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3); 1039 static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16); 1040 static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20); 1041 static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21); 1042 static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22); 1043 static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23); 1044 static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26); 1045 static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29); 1046 static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30); 1047 static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31); 1048 1049 static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1); 1050 static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); 1051 static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8); 1052 static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9); 1053 static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11); 1054 static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25); 1055 static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); 1056 static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30); 1057 static MESON_GATE(axg_mipi_enable, HHI_MIPI_CNTL0, 29); 1058 1059 /* Always On (AO) domain gates */ 1060 1061 static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0); 1062 static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1); 1063 static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2); 1064 static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3); 1065 static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4); 1066 1067 /* Array of all clocks provided by this provider */ 1068 1069 static struct clk_hw_onecell_data axg_hw_onecell_data = { 1070 .hws = { 1071 [CLKID_SYS_PLL] = &axg_sys_pll.hw, 1072 [CLKID_FIXED_PLL] = &axg_fixed_pll.hw, 1073 [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw, 1074 [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw, 1075 [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw, 1076 [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw, 1077 [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw, 1078 [CLKID_GP0_PLL] = &axg_gp0_pll.hw, 1079 [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw, 1080 [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw, 1081 [CLKID_CLK81] = &axg_clk81.hw, 1082 [CLKID_MPLL0] = &axg_mpll0.hw, 1083 [CLKID_MPLL1] = &axg_mpll1.hw, 1084 [CLKID_MPLL2] = &axg_mpll2.hw, 1085 [CLKID_MPLL3] = &axg_mpll3.hw, 1086 [CLKID_DDR] = &axg_ddr.hw, 1087 [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw, 1088 [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw, 1089 [CLKID_ISA] = &axg_isa.hw, 1090 [CLKID_PL301] = &axg_pl301.hw, 1091 [CLKID_PERIPHS] = &axg_periphs.hw, 1092 [CLKID_SPICC0] = &axg_spicc_0.hw, 1093 [CLKID_I2C] = &axg_i2c.hw, 1094 [CLKID_RNG0] = &axg_rng0.hw, 1095 [CLKID_UART0] = &axg_uart0.hw, 1096 [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw, 1097 [CLKID_SPICC1] = &axg_spicc_1.hw, 1098 [CLKID_PCIE_A] = &axg_pcie_a.hw, 1099 [CLKID_PCIE_B] = &axg_pcie_b.hw, 1100 [CLKID_HIU_IFACE] = &axg_hiu_reg.hw, 1101 [CLKID_ASSIST_MISC] = &axg_assist_misc.hw, 1102 [CLKID_SD_EMMC_B] = &axg_emmc_b.hw, 1103 [CLKID_SD_EMMC_C] = &axg_emmc_c.hw, 1104 [CLKID_DMA] = &axg_dma.hw, 1105 [CLKID_SPI] = &axg_spi.hw, 1106 [CLKID_AUDIO] = &axg_audio.hw, 1107 [CLKID_ETH] = &axg_eth_core.hw, 1108 [CLKID_UART1] = &axg_uart1.hw, 1109 [CLKID_G2D] = &axg_g2d.hw, 1110 [CLKID_USB0] = &axg_usb0.hw, 1111 [CLKID_USB1] = &axg_usb1.hw, 1112 [CLKID_RESET] = &axg_reset.hw, 1113 [CLKID_USB] = &axg_usb_general.hw, 1114 [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw, 1115 [CLKID_EFUSE] = &axg_efuse.hw, 1116 [CLKID_BOOT_ROM] = &axg_boot_rom.hw, 1117 [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw, 1118 [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw, 1119 [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw, 1120 [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw, 1121 [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw, 1122 [CLKID_VPU_INTR] = &axg_vpu_intr.hw, 1123 [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw, 1124 [CLKID_GIC] = &axg_gic.hw, 1125 [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw, 1126 [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw, 1127 [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw, 1128 [CLKID_AO_IFACE] = &axg_ao_iface.hw, 1129 [CLKID_AO_I2C] = &axg_ao_i2c.hw, 1130 [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw, 1131 [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw, 1132 [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw, 1133 [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw, 1134 [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw, 1135 [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw, 1136 [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw, 1137 [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw, 1138 [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw, 1139 [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw, 1140 [CLKID_HIFI_PLL] = &axg_hifi_pll.hw, 1141 [CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw, 1142 [CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw, 1143 [CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw, 1144 [CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw, 1145 [CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw, 1146 [CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw, 1147 [CLKID_PCIE_PLL] = &axg_pcie_pll.hw, 1148 [CLKID_PCIE_MUX] = &axg_pcie_mux.hw, 1149 [CLKID_PCIE_REF] = &axg_pcie_ref.hw, 1150 [CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw, 1151 [CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw, 1152 [CLKID_MIPI_ENABLE] = &axg_mipi_enable.hw, 1153 [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw, 1154 [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw, 1155 [CLKID_GEN_CLK] = &axg_gen_clk.hw, 1156 [CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw, 1157 [CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw, 1158 [CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw, 1159 [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw, 1160 [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw, 1161 [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw, 1162 [NR_CLKS] = NULL, 1163 }, 1164 .num = NR_CLKS, 1165 }; 1166 1167 /* Convenience table to populate regmap in .probe */ 1168 static struct clk_regmap *const axg_clk_regmaps[] = { 1169 &axg_clk81, 1170 &axg_ddr, 1171 &axg_audio_locker, 1172 &axg_mipi_dsi_host, 1173 &axg_isa, 1174 &axg_pl301, 1175 &axg_periphs, 1176 &axg_spicc_0, 1177 &axg_i2c, 1178 &axg_rng0, 1179 &axg_uart0, 1180 &axg_mipi_dsi_phy, 1181 &axg_spicc_1, 1182 &axg_pcie_a, 1183 &axg_pcie_b, 1184 &axg_hiu_reg, 1185 &axg_assist_misc, 1186 &axg_emmc_b, 1187 &axg_emmc_c, 1188 &axg_dma, 1189 &axg_spi, 1190 &axg_audio, 1191 &axg_eth_core, 1192 &axg_uart1, 1193 &axg_g2d, 1194 &axg_usb0, 1195 &axg_usb1, 1196 &axg_reset, 1197 &axg_usb_general, 1198 &axg_ahb_arb0, 1199 &axg_efuse, 1200 &axg_boot_rom, 1201 &axg_ahb_data_bus, 1202 &axg_ahb_ctrl_bus, 1203 &axg_usb1_to_ddr, 1204 &axg_usb0_to_ddr, 1205 &axg_mmc_pclk, 1206 &axg_vpu_intr, 1207 &axg_sec_ahb_ahb3_bridge, 1208 &axg_gic, 1209 &axg_ao_media_cpu, 1210 &axg_ao_ahb_sram, 1211 &axg_ao_ahb_bus, 1212 &axg_ao_iface, 1213 &axg_ao_i2c, 1214 &axg_sd_emmc_b_clk0, 1215 &axg_sd_emmc_c_clk0, 1216 &axg_mpeg_clk_div, 1217 &axg_sd_emmc_b_clk0_div, 1218 &axg_sd_emmc_c_clk0_div, 1219 &axg_mpeg_clk_sel, 1220 &axg_sd_emmc_b_clk0_sel, 1221 &axg_sd_emmc_c_clk0_sel, 1222 &axg_mpll0, 1223 &axg_mpll1, 1224 &axg_mpll2, 1225 &axg_mpll3, 1226 &axg_mpll0_div, 1227 &axg_mpll1_div, 1228 &axg_mpll2_div, 1229 &axg_mpll3_div, 1230 &axg_fixed_pll, 1231 &axg_sys_pll, 1232 &axg_gp0_pll, 1233 &axg_hifi_pll, 1234 &axg_mpll_prediv, 1235 &axg_fclk_div2, 1236 &axg_fclk_div3, 1237 &axg_fclk_div4, 1238 &axg_fclk_div5, 1239 &axg_fclk_div7, 1240 &axg_pcie_pll_dco, 1241 &axg_pcie_pll_od, 1242 &axg_pcie_pll, 1243 &axg_pcie_mux, 1244 &axg_pcie_ref, 1245 &axg_pcie_cml_en0, 1246 &axg_pcie_cml_en1, 1247 &axg_mipi_enable, 1248 &axg_gen_clk_sel, 1249 &axg_gen_clk_div, 1250 &axg_gen_clk, 1251 &axg_fixed_pll_dco, 1252 &axg_sys_pll_dco, 1253 &axg_gp0_pll_dco, 1254 &axg_hifi_pll_dco, 1255 &axg_pcie_pll_dco, 1256 &axg_pcie_pll_od, 1257 }; 1258 1259 static const struct meson_eeclkc_data axg_clkc_data = { 1260 .regmap_clks = axg_clk_regmaps, 1261 .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps), 1262 .hw_onecell_data = &axg_hw_onecell_data, 1263 }; 1264 1265 1266 static const struct of_device_id clkc_match_table[] = { 1267 { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data }, 1268 {} 1269 }; 1270 1271 static struct platform_driver axg_driver = { 1272 .probe = meson_eeclkc_probe, 1273 .driver = { 1274 .name = "axg-clkc", 1275 .of_match_table = clkc_match_table, 1276 }, 1277 }; 1278 1279 builtin_platform_driver(axg_driver); 1280