1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AmLogic Meson-AXG Clock Controller Driver 4 * 5 * Copyright (c) 2016 Baylibre SAS. 6 * Author: Michael Turquette <mturquette@baylibre.com> 7 * 8 * Copyright (c) 2017 Amlogic, inc. 9 * Author: Qiufang Dai <qiufang.dai@amlogic.com> 10 */ 11 12 #include <linux/clk-provider.h> 13 #include <linux/init.h> 14 #include <linux/mod_devicetable.h> 15 #include <linux/platform_device.h> 16 #include <linux/module.h> 17 18 #include "clk-regmap.h" 19 #include "clk-pll.h" 20 #include "clk-mpll.h" 21 #include "axg.h" 22 #include "meson-eeclk.h" 23 24 #include <dt-bindings/clock/axg-clkc.h> 25 26 static DEFINE_SPINLOCK(meson_clk_lock); 27 28 static struct clk_regmap axg_fixed_pll_dco = { 29 .data = &(struct meson_clk_pll_data){ 30 .en = { 31 .reg_off = HHI_MPLL_CNTL, 32 .shift = 30, 33 .width = 1, 34 }, 35 .m = { 36 .reg_off = HHI_MPLL_CNTL, 37 .shift = 0, 38 .width = 9, 39 }, 40 .n = { 41 .reg_off = HHI_MPLL_CNTL, 42 .shift = 9, 43 .width = 5, 44 }, 45 .frac = { 46 .reg_off = HHI_MPLL_CNTL2, 47 .shift = 0, 48 .width = 12, 49 }, 50 .l = { 51 .reg_off = HHI_MPLL_CNTL, 52 .shift = 31, 53 .width = 1, 54 }, 55 .rst = { 56 .reg_off = HHI_MPLL_CNTL, 57 .shift = 29, 58 .width = 1, 59 }, 60 }, 61 .hw.init = &(struct clk_init_data){ 62 .name = "fixed_pll_dco", 63 .ops = &meson_clk_pll_ro_ops, 64 .parent_data = &(const struct clk_parent_data) { 65 .fw_name = "xtal", 66 }, 67 .num_parents = 1, 68 }, 69 }; 70 71 static struct clk_regmap axg_fixed_pll = { 72 .data = &(struct clk_regmap_div_data){ 73 .offset = HHI_MPLL_CNTL, 74 .shift = 16, 75 .width = 2, 76 .flags = CLK_DIVIDER_POWER_OF_TWO, 77 }, 78 .hw.init = &(struct clk_init_data){ 79 .name = "fixed_pll", 80 .ops = &clk_regmap_divider_ro_ops, 81 .parent_hws = (const struct clk_hw *[]) { 82 &axg_fixed_pll_dco.hw 83 }, 84 .num_parents = 1, 85 /* 86 * This clock won't ever change at runtime so 87 * CLK_SET_RATE_PARENT is not required 88 */ 89 }, 90 }; 91 92 static struct clk_regmap axg_sys_pll_dco = { 93 .data = &(struct meson_clk_pll_data){ 94 .en = { 95 .reg_off = HHI_SYS_PLL_CNTL, 96 .shift = 30, 97 .width = 1, 98 }, 99 .m = { 100 .reg_off = HHI_SYS_PLL_CNTL, 101 .shift = 0, 102 .width = 9, 103 }, 104 .n = { 105 .reg_off = HHI_SYS_PLL_CNTL, 106 .shift = 9, 107 .width = 5, 108 }, 109 .l = { 110 .reg_off = HHI_SYS_PLL_CNTL, 111 .shift = 31, 112 .width = 1, 113 }, 114 .rst = { 115 .reg_off = HHI_SYS_PLL_CNTL, 116 .shift = 29, 117 .width = 1, 118 }, 119 }, 120 .hw.init = &(struct clk_init_data){ 121 .name = "sys_pll_dco", 122 .ops = &meson_clk_pll_ro_ops, 123 .parent_data = &(const struct clk_parent_data) { 124 .fw_name = "xtal", 125 }, 126 .num_parents = 1, 127 }, 128 }; 129 130 static struct clk_regmap axg_sys_pll = { 131 .data = &(struct clk_regmap_div_data){ 132 .offset = HHI_SYS_PLL_CNTL, 133 .shift = 16, 134 .width = 2, 135 .flags = CLK_DIVIDER_POWER_OF_TWO, 136 }, 137 .hw.init = &(struct clk_init_data){ 138 .name = "sys_pll", 139 .ops = &clk_regmap_divider_ro_ops, 140 .parent_hws = (const struct clk_hw *[]) { 141 &axg_sys_pll_dco.hw 142 }, 143 .num_parents = 1, 144 .flags = CLK_SET_RATE_PARENT, 145 }, 146 }; 147 148 static const struct pll_params_table axg_gp0_pll_params_table[] = { 149 PLL_PARAMS(40, 1), 150 PLL_PARAMS(41, 1), 151 PLL_PARAMS(42, 1), 152 PLL_PARAMS(43, 1), 153 PLL_PARAMS(44, 1), 154 PLL_PARAMS(45, 1), 155 PLL_PARAMS(46, 1), 156 PLL_PARAMS(47, 1), 157 PLL_PARAMS(48, 1), 158 PLL_PARAMS(49, 1), 159 PLL_PARAMS(50, 1), 160 PLL_PARAMS(51, 1), 161 PLL_PARAMS(52, 1), 162 PLL_PARAMS(53, 1), 163 PLL_PARAMS(54, 1), 164 PLL_PARAMS(55, 1), 165 PLL_PARAMS(56, 1), 166 PLL_PARAMS(57, 1), 167 PLL_PARAMS(58, 1), 168 PLL_PARAMS(59, 1), 169 PLL_PARAMS(60, 1), 170 PLL_PARAMS(61, 1), 171 PLL_PARAMS(62, 1), 172 PLL_PARAMS(63, 1), 173 PLL_PARAMS(64, 1), 174 PLL_PARAMS(65, 1), 175 PLL_PARAMS(66, 1), 176 PLL_PARAMS(67, 1), 177 PLL_PARAMS(68, 1), 178 { /* sentinel */ }, 179 }; 180 181 static const struct reg_sequence axg_gp0_init_regs[] = { 182 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 }, 183 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, 184 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, 185 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, 186 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, 187 }; 188 189 static struct clk_regmap axg_gp0_pll_dco = { 190 .data = &(struct meson_clk_pll_data){ 191 .en = { 192 .reg_off = HHI_GP0_PLL_CNTL, 193 .shift = 30, 194 .width = 1, 195 }, 196 .m = { 197 .reg_off = HHI_GP0_PLL_CNTL, 198 .shift = 0, 199 .width = 9, 200 }, 201 .n = { 202 .reg_off = HHI_GP0_PLL_CNTL, 203 .shift = 9, 204 .width = 5, 205 }, 206 .frac = { 207 .reg_off = HHI_GP0_PLL_CNTL1, 208 .shift = 0, 209 .width = 10, 210 }, 211 .l = { 212 .reg_off = HHI_GP0_PLL_CNTL, 213 .shift = 31, 214 .width = 1, 215 }, 216 .rst = { 217 .reg_off = HHI_GP0_PLL_CNTL, 218 .shift = 29, 219 .width = 1, 220 }, 221 .table = axg_gp0_pll_params_table, 222 .init_regs = axg_gp0_init_regs, 223 .init_count = ARRAY_SIZE(axg_gp0_init_regs), 224 }, 225 .hw.init = &(struct clk_init_data){ 226 .name = "gp0_pll_dco", 227 .ops = &meson_clk_pll_ops, 228 .parent_data = &(const struct clk_parent_data) { 229 .fw_name = "xtal", 230 }, 231 .num_parents = 1, 232 }, 233 }; 234 235 static struct clk_regmap axg_gp0_pll = { 236 .data = &(struct clk_regmap_div_data){ 237 .offset = HHI_GP0_PLL_CNTL, 238 .shift = 16, 239 .width = 2, 240 .flags = CLK_DIVIDER_POWER_OF_TWO, 241 }, 242 .hw.init = &(struct clk_init_data){ 243 .name = "gp0_pll", 244 .ops = &clk_regmap_divider_ops, 245 .parent_hws = (const struct clk_hw *[]) { 246 &axg_gp0_pll_dco.hw 247 }, 248 .num_parents = 1, 249 .flags = CLK_SET_RATE_PARENT, 250 }, 251 }; 252 253 static const struct reg_sequence axg_hifi_init_regs[] = { 254 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0xc084b000 }, 255 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0xb75020be }, 256 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 }, 257 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0xc000004d }, 258 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x00058000 }, 259 }; 260 261 static struct clk_regmap axg_hifi_pll_dco = { 262 .data = &(struct meson_clk_pll_data){ 263 .en = { 264 .reg_off = HHI_HIFI_PLL_CNTL, 265 .shift = 30, 266 .width = 1, 267 }, 268 .m = { 269 .reg_off = HHI_HIFI_PLL_CNTL, 270 .shift = 0, 271 .width = 9, 272 }, 273 .n = { 274 .reg_off = HHI_HIFI_PLL_CNTL, 275 .shift = 9, 276 .width = 5, 277 }, 278 .frac = { 279 .reg_off = HHI_HIFI_PLL_CNTL5, 280 .shift = 0, 281 .width = 13, 282 }, 283 .l = { 284 .reg_off = HHI_HIFI_PLL_CNTL, 285 .shift = 31, 286 .width = 1, 287 }, 288 .rst = { 289 .reg_off = HHI_HIFI_PLL_CNTL, 290 .shift = 29, 291 .width = 1, 292 }, 293 .table = axg_gp0_pll_params_table, 294 .init_regs = axg_hifi_init_regs, 295 .init_count = ARRAY_SIZE(axg_hifi_init_regs), 296 .flags = CLK_MESON_PLL_ROUND_CLOSEST, 297 }, 298 .hw.init = &(struct clk_init_data){ 299 .name = "hifi_pll_dco", 300 .ops = &meson_clk_pll_ops, 301 .parent_data = &(const struct clk_parent_data) { 302 .fw_name = "xtal", 303 }, 304 .num_parents = 1, 305 }, 306 }; 307 308 static struct clk_regmap axg_hifi_pll = { 309 .data = &(struct clk_regmap_div_data){ 310 .offset = HHI_HIFI_PLL_CNTL, 311 .shift = 16, 312 .width = 2, 313 .flags = CLK_DIVIDER_POWER_OF_TWO, 314 }, 315 .hw.init = &(struct clk_init_data){ 316 .name = "hifi_pll", 317 .ops = &clk_regmap_divider_ops, 318 .parent_hws = (const struct clk_hw *[]) { 319 &axg_hifi_pll_dco.hw 320 }, 321 .num_parents = 1, 322 .flags = CLK_SET_RATE_PARENT, 323 }, 324 }; 325 326 static struct clk_fixed_factor axg_fclk_div2_div = { 327 .mult = 1, 328 .div = 2, 329 .hw.init = &(struct clk_init_data){ 330 .name = "fclk_div2_div", 331 .ops = &clk_fixed_factor_ops, 332 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw }, 333 .num_parents = 1, 334 }, 335 }; 336 337 static struct clk_regmap axg_fclk_div2 = { 338 .data = &(struct clk_regmap_gate_data){ 339 .offset = HHI_MPLL_CNTL6, 340 .bit_idx = 27, 341 }, 342 .hw.init = &(struct clk_init_data){ 343 .name = "fclk_div2", 344 .ops = &clk_regmap_gate_ops, 345 .parent_hws = (const struct clk_hw *[]) { 346 &axg_fclk_div2_div.hw 347 }, 348 .num_parents = 1, 349 .flags = CLK_IS_CRITICAL, 350 }, 351 }; 352 353 static struct clk_fixed_factor axg_fclk_div3_div = { 354 .mult = 1, 355 .div = 3, 356 .hw.init = &(struct clk_init_data){ 357 .name = "fclk_div3_div", 358 .ops = &clk_fixed_factor_ops, 359 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw }, 360 .num_parents = 1, 361 }, 362 }; 363 364 static struct clk_regmap axg_fclk_div3 = { 365 .data = &(struct clk_regmap_gate_data){ 366 .offset = HHI_MPLL_CNTL6, 367 .bit_idx = 28, 368 }, 369 .hw.init = &(struct clk_init_data){ 370 .name = "fclk_div3", 371 .ops = &clk_regmap_gate_ops, 372 .parent_hws = (const struct clk_hw *[]) { 373 &axg_fclk_div3_div.hw 374 }, 375 .num_parents = 1, 376 /* 377 * FIXME: 378 * This clock, as fdiv2, is used by the SCPI FW and is required 379 * by the platform to operate correctly. 380 * Until the following condition are met, we need this clock to 381 * be marked as critical: 382 * a) The SCPI generic driver claims and enable all the clocks 383 * it needs 384 * b) CCF has a clock hand-off mechanism to make the sure the 385 * clock stays on until the proper driver comes along 386 */ 387 .flags = CLK_IS_CRITICAL, 388 }, 389 }; 390 391 static struct clk_fixed_factor axg_fclk_div4_div = { 392 .mult = 1, 393 .div = 4, 394 .hw.init = &(struct clk_init_data){ 395 .name = "fclk_div4_div", 396 .ops = &clk_fixed_factor_ops, 397 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw }, 398 .num_parents = 1, 399 }, 400 }; 401 402 static struct clk_regmap axg_fclk_div4 = { 403 .data = &(struct clk_regmap_gate_data){ 404 .offset = HHI_MPLL_CNTL6, 405 .bit_idx = 29, 406 }, 407 .hw.init = &(struct clk_init_data){ 408 .name = "fclk_div4", 409 .ops = &clk_regmap_gate_ops, 410 .parent_hws = (const struct clk_hw *[]) { 411 &axg_fclk_div4_div.hw 412 }, 413 .num_parents = 1, 414 }, 415 }; 416 417 static struct clk_fixed_factor axg_fclk_div5_div = { 418 .mult = 1, 419 .div = 5, 420 .hw.init = &(struct clk_init_data){ 421 .name = "fclk_div5_div", 422 .ops = &clk_fixed_factor_ops, 423 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw }, 424 .num_parents = 1, 425 }, 426 }; 427 428 static struct clk_regmap axg_fclk_div5 = { 429 .data = &(struct clk_regmap_gate_data){ 430 .offset = HHI_MPLL_CNTL6, 431 .bit_idx = 30, 432 }, 433 .hw.init = &(struct clk_init_data){ 434 .name = "fclk_div5", 435 .ops = &clk_regmap_gate_ops, 436 .parent_hws = (const struct clk_hw *[]) { 437 &axg_fclk_div5_div.hw 438 }, 439 .num_parents = 1, 440 }, 441 }; 442 443 static struct clk_fixed_factor axg_fclk_div7_div = { 444 .mult = 1, 445 .div = 7, 446 .hw.init = &(struct clk_init_data){ 447 .name = "fclk_div7_div", 448 .ops = &clk_fixed_factor_ops, 449 .parent_hws = (const struct clk_hw *[]) { 450 &axg_fixed_pll.hw 451 }, 452 .num_parents = 1, 453 }, 454 }; 455 456 static struct clk_regmap axg_fclk_div7 = { 457 .data = &(struct clk_regmap_gate_data){ 458 .offset = HHI_MPLL_CNTL6, 459 .bit_idx = 31, 460 }, 461 .hw.init = &(struct clk_init_data){ 462 .name = "fclk_div7", 463 .ops = &clk_regmap_gate_ops, 464 .parent_hws = (const struct clk_hw *[]) { 465 &axg_fclk_div7_div.hw 466 }, 467 .num_parents = 1, 468 }, 469 }; 470 471 static struct clk_regmap axg_mpll_prediv = { 472 .data = &(struct clk_regmap_div_data){ 473 .offset = HHI_MPLL_CNTL5, 474 .shift = 12, 475 .width = 1, 476 }, 477 .hw.init = &(struct clk_init_data){ 478 .name = "mpll_prediv", 479 .ops = &clk_regmap_divider_ro_ops, 480 .parent_hws = (const struct clk_hw *[]) { 481 &axg_fixed_pll.hw 482 }, 483 .num_parents = 1, 484 }, 485 }; 486 487 static struct clk_regmap axg_mpll0_div = { 488 .data = &(struct meson_clk_mpll_data){ 489 .sdm = { 490 .reg_off = HHI_MPLL_CNTL7, 491 .shift = 0, 492 .width = 14, 493 }, 494 .sdm_en = { 495 .reg_off = HHI_MPLL_CNTL7, 496 .shift = 15, 497 .width = 1, 498 }, 499 .n2 = { 500 .reg_off = HHI_MPLL_CNTL7, 501 .shift = 16, 502 .width = 9, 503 }, 504 .misc = { 505 .reg_off = HHI_PLL_TOP_MISC, 506 .shift = 0, 507 .width = 1, 508 }, 509 .lock = &meson_clk_lock, 510 .flags = CLK_MESON_MPLL_ROUND_CLOSEST, 511 }, 512 .hw.init = &(struct clk_init_data){ 513 .name = "mpll0_div", 514 .ops = &meson_clk_mpll_ops, 515 .parent_hws = (const struct clk_hw *[]) { 516 &axg_mpll_prediv.hw 517 }, 518 .num_parents = 1, 519 }, 520 }; 521 522 static struct clk_regmap axg_mpll0 = { 523 .data = &(struct clk_regmap_gate_data){ 524 .offset = HHI_MPLL_CNTL7, 525 .bit_idx = 14, 526 }, 527 .hw.init = &(struct clk_init_data){ 528 .name = "mpll0", 529 .ops = &clk_regmap_gate_ops, 530 .parent_hws = (const struct clk_hw *[]) { 531 &axg_mpll0_div.hw 532 }, 533 .num_parents = 1, 534 .flags = CLK_SET_RATE_PARENT, 535 }, 536 }; 537 538 static struct clk_regmap axg_mpll1_div = { 539 .data = &(struct meson_clk_mpll_data){ 540 .sdm = { 541 .reg_off = HHI_MPLL_CNTL8, 542 .shift = 0, 543 .width = 14, 544 }, 545 .sdm_en = { 546 .reg_off = HHI_MPLL_CNTL8, 547 .shift = 15, 548 .width = 1, 549 }, 550 .n2 = { 551 .reg_off = HHI_MPLL_CNTL8, 552 .shift = 16, 553 .width = 9, 554 }, 555 .misc = { 556 .reg_off = HHI_PLL_TOP_MISC, 557 .shift = 1, 558 .width = 1, 559 }, 560 .lock = &meson_clk_lock, 561 .flags = CLK_MESON_MPLL_ROUND_CLOSEST, 562 }, 563 .hw.init = &(struct clk_init_data){ 564 .name = "mpll1_div", 565 .ops = &meson_clk_mpll_ops, 566 .parent_hws = (const struct clk_hw *[]) { 567 &axg_mpll_prediv.hw 568 }, 569 .num_parents = 1, 570 }, 571 }; 572 573 static struct clk_regmap axg_mpll1 = { 574 .data = &(struct clk_regmap_gate_data){ 575 .offset = HHI_MPLL_CNTL8, 576 .bit_idx = 14, 577 }, 578 .hw.init = &(struct clk_init_data){ 579 .name = "mpll1", 580 .ops = &clk_regmap_gate_ops, 581 .parent_hws = (const struct clk_hw *[]) { 582 &axg_mpll1_div.hw 583 }, 584 .num_parents = 1, 585 .flags = CLK_SET_RATE_PARENT, 586 }, 587 }; 588 589 static struct clk_regmap axg_mpll2_div = { 590 .data = &(struct meson_clk_mpll_data){ 591 .sdm = { 592 .reg_off = HHI_MPLL_CNTL9, 593 .shift = 0, 594 .width = 14, 595 }, 596 .sdm_en = { 597 .reg_off = HHI_MPLL_CNTL9, 598 .shift = 15, 599 .width = 1, 600 }, 601 .n2 = { 602 .reg_off = HHI_MPLL_CNTL9, 603 .shift = 16, 604 .width = 9, 605 }, 606 .ssen = { 607 .reg_off = HHI_MPLL_CNTL, 608 .shift = 25, 609 .width = 1, 610 }, 611 .misc = { 612 .reg_off = HHI_PLL_TOP_MISC, 613 .shift = 2, 614 .width = 1, 615 }, 616 .lock = &meson_clk_lock, 617 .flags = CLK_MESON_MPLL_ROUND_CLOSEST, 618 }, 619 .hw.init = &(struct clk_init_data){ 620 .name = "mpll2_div", 621 .ops = &meson_clk_mpll_ops, 622 .parent_hws = (const struct clk_hw *[]) { 623 &axg_mpll_prediv.hw 624 }, 625 .num_parents = 1, 626 }, 627 }; 628 629 static struct clk_regmap axg_mpll2 = { 630 .data = &(struct clk_regmap_gate_data){ 631 .offset = HHI_MPLL_CNTL9, 632 .bit_idx = 14, 633 }, 634 .hw.init = &(struct clk_init_data){ 635 .name = "mpll2", 636 .ops = &clk_regmap_gate_ops, 637 .parent_hws = (const struct clk_hw *[]) { 638 &axg_mpll2_div.hw 639 }, 640 .num_parents = 1, 641 .flags = CLK_SET_RATE_PARENT, 642 }, 643 }; 644 645 static struct clk_regmap axg_mpll3_div = { 646 .data = &(struct meson_clk_mpll_data){ 647 .sdm = { 648 .reg_off = HHI_MPLL3_CNTL0, 649 .shift = 12, 650 .width = 14, 651 }, 652 .sdm_en = { 653 .reg_off = HHI_MPLL3_CNTL0, 654 .shift = 11, 655 .width = 1, 656 }, 657 .n2 = { 658 .reg_off = HHI_MPLL3_CNTL0, 659 .shift = 2, 660 .width = 9, 661 }, 662 .misc = { 663 .reg_off = HHI_PLL_TOP_MISC, 664 .shift = 3, 665 .width = 1, 666 }, 667 .lock = &meson_clk_lock, 668 .flags = CLK_MESON_MPLL_ROUND_CLOSEST, 669 }, 670 .hw.init = &(struct clk_init_data){ 671 .name = "mpll3_div", 672 .ops = &meson_clk_mpll_ops, 673 .parent_hws = (const struct clk_hw *[]) { 674 &axg_mpll_prediv.hw 675 }, 676 .num_parents = 1, 677 }, 678 }; 679 680 static struct clk_regmap axg_mpll3 = { 681 .data = &(struct clk_regmap_gate_data){ 682 .offset = HHI_MPLL3_CNTL0, 683 .bit_idx = 0, 684 }, 685 .hw.init = &(struct clk_init_data){ 686 .name = "mpll3", 687 .ops = &clk_regmap_gate_ops, 688 .parent_hws = (const struct clk_hw *[]) { 689 &axg_mpll3_div.hw 690 }, 691 .num_parents = 1, 692 .flags = CLK_SET_RATE_PARENT, 693 }, 694 }; 695 696 static const struct pll_params_table axg_pcie_pll_params_table[] = { 697 { 698 .m = 200, 699 .n = 3, 700 }, 701 { /* sentinel */ }, 702 }; 703 704 static const struct reg_sequence axg_pcie_init_regs[] = { 705 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x0084a2aa }, 706 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0xb75020be }, 707 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x0a47488e }, 708 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0xc000004d }, 709 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x00078000 }, 710 { .reg = HHI_PCIE_PLL_CNTL6, .def = 0x002323c6 }, 711 { .reg = HHI_PCIE_PLL_CNTL, .def = 0x400106c8 }, 712 }; 713 714 static struct clk_regmap axg_pcie_pll_dco = { 715 .data = &(struct meson_clk_pll_data){ 716 .en = { 717 .reg_off = HHI_PCIE_PLL_CNTL, 718 .shift = 30, 719 .width = 1, 720 }, 721 .m = { 722 .reg_off = HHI_PCIE_PLL_CNTL, 723 .shift = 0, 724 .width = 9, 725 }, 726 .n = { 727 .reg_off = HHI_PCIE_PLL_CNTL, 728 .shift = 9, 729 .width = 5, 730 }, 731 .frac = { 732 .reg_off = HHI_PCIE_PLL_CNTL1, 733 .shift = 0, 734 .width = 12, 735 }, 736 .l = { 737 .reg_off = HHI_PCIE_PLL_CNTL, 738 .shift = 31, 739 .width = 1, 740 }, 741 .rst = { 742 .reg_off = HHI_PCIE_PLL_CNTL, 743 .shift = 29, 744 .width = 1, 745 }, 746 .table = axg_pcie_pll_params_table, 747 .init_regs = axg_pcie_init_regs, 748 .init_count = ARRAY_SIZE(axg_pcie_init_regs), 749 }, 750 .hw.init = &(struct clk_init_data){ 751 .name = "pcie_pll_dco", 752 .ops = &meson_clk_pll_ops, 753 .parent_data = &(const struct clk_parent_data) { 754 .fw_name = "xtal", 755 }, 756 .num_parents = 1, 757 }, 758 }; 759 760 static struct clk_regmap axg_pcie_pll_od = { 761 .data = &(struct clk_regmap_div_data){ 762 .offset = HHI_PCIE_PLL_CNTL, 763 .shift = 16, 764 .width = 2, 765 .flags = CLK_DIVIDER_POWER_OF_TWO, 766 }, 767 .hw.init = &(struct clk_init_data){ 768 .name = "pcie_pll_od", 769 .ops = &clk_regmap_divider_ops, 770 .parent_hws = (const struct clk_hw *[]) { 771 &axg_pcie_pll_dco.hw 772 }, 773 .num_parents = 1, 774 .flags = CLK_SET_RATE_PARENT, 775 }, 776 }; 777 778 static struct clk_regmap axg_pcie_pll = { 779 .data = &(struct clk_regmap_div_data){ 780 .offset = HHI_PCIE_PLL_CNTL6, 781 .shift = 6, 782 .width = 2, 783 .flags = CLK_DIVIDER_POWER_OF_TWO, 784 }, 785 .hw.init = &(struct clk_init_data){ 786 .name = "pcie_pll", 787 .ops = &clk_regmap_divider_ops, 788 .parent_hws = (const struct clk_hw *[]) { 789 &axg_pcie_pll_od.hw 790 }, 791 .num_parents = 1, 792 .flags = CLK_SET_RATE_PARENT, 793 }, 794 }; 795 796 static struct clk_regmap axg_pcie_mux = { 797 .data = &(struct clk_regmap_mux_data){ 798 .offset = HHI_PCIE_PLL_CNTL6, 799 .mask = 0x1, 800 .shift = 2, 801 /* skip the parent mpll3, reserved for debug */ 802 .table = (u32[]){ 1 }, 803 }, 804 .hw.init = &(struct clk_init_data){ 805 .name = "pcie_mux", 806 .ops = &clk_regmap_mux_ops, 807 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_pll.hw }, 808 .num_parents = 1, 809 .flags = CLK_SET_RATE_PARENT, 810 }, 811 }; 812 813 static struct clk_regmap axg_pcie_ref = { 814 .data = &(struct clk_regmap_mux_data){ 815 .offset = HHI_PCIE_PLL_CNTL6, 816 .mask = 0x1, 817 .shift = 1, 818 /* skip the parent 0, reserved for debug */ 819 .table = (u32[]){ 1 }, 820 }, 821 .hw.init = &(struct clk_init_data){ 822 .name = "pcie_ref", 823 .ops = &clk_regmap_mux_ops, 824 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_mux.hw }, 825 .num_parents = 1, 826 .flags = CLK_SET_RATE_PARENT, 827 }, 828 }; 829 830 static struct clk_regmap axg_pcie_cml_en0 = { 831 .data = &(struct clk_regmap_gate_data){ 832 .offset = HHI_PCIE_PLL_CNTL6, 833 .bit_idx = 4, 834 }, 835 .hw.init = &(struct clk_init_data) { 836 .name = "pcie_cml_en0", 837 .ops = &clk_regmap_gate_ops, 838 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw }, 839 .num_parents = 1, 840 .flags = CLK_SET_RATE_PARENT, 841 842 }, 843 }; 844 845 static struct clk_regmap axg_pcie_cml_en1 = { 846 .data = &(struct clk_regmap_gate_data){ 847 .offset = HHI_PCIE_PLL_CNTL6, 848 .bit_idx = 3, 849 }, 850 .hw.init = &(struct clk_init_data) { 851 .name = "pcie_cml_en1", 852 .ops = &clk_regmap_gate_ops, 853 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw }, 854 .num_parents = 1, 855 .flags = CLK_SET_RATE_PARENT, 856 }, 857 }; 858 859 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; 860 static const struct clk_parent_data clk81_parent_data[] = { 861 { .fw_name = "xtal", }, 862 { .hw = &axg_fclk_div7.hw }, 863 { .hw = &axg_mpll1.hw }, 864 { .hw = &axg_mpll2.hw }, 865 { .hw = &axg_fclk_div4.hw }, 866 { .hw = &axg_fclk_div3.hw }, 867 { .hw = &axg_fclk_div5.hw }, 868 }; 869 870 static struct clk_regmap axg_mpeg_clk_sel = { 871 .data = &(struct clk_regmap_mux_data){ 872 .offset = HHI_MPEG_CLK_CNTL, 873 .mask = 0x7, 874 .shift = 12, 875 .table = mux_table_clk81, 876 }, 877 .hw.init = &(struct clk_init_data){ 878 .name = "mpeg_clk_sel", 879 .ops = &clk_regmap_mux_ro_ops, 880 .parent_data = clk81_parent_data, 881 .num_parents = ARRAY_SIZE(clk81_parent_data), 882 }, 883 }; 884 885 static struct clk_regmap axg_mpeg_clk_div = { 886 .data = &(struct clk_regmap_div_data){ 887 .offset = HHI_MPEG_CLK_CNTL, 888 .shift = 0, 889 .width = 7, 890 }, 891 .hw.init = &(struct clk_init_data){ 892 .name = "mpeg_clk_div", 893 .ops = &clk_regmap_divider_ops, 894 .parent_hws = (const struct clk_hw *[]) { 895 &axg_mpeg_clk_sel.hw 896 }, 897 .num_parents = 1, 898 .flags = CLK_SET_RATE_PARENT, 899 }, 900 }; 901 902 static struct clk_regmap axg_clk81 = { 903 .data = &(struct clk_regmap_gate_data){ 904 .offset = HHI_MPEG_CLK_CNTL, 905 .bit_idx = 7, 906 }, 907 .hw.init = &(struct clk_init_data){ 908 .name = "clk81", 909 .ops = &clk_regmap_gate_ops, 910 .parent_hws = (const struct clk_hw *[]) { 911 &axg_mpeg_clk_div.hw 912 }, 913 .num_parents = 1, 914 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), 915 }, 916 }; 917 918 static const struct clk_parent_data axg_sd_emmc_clk0_parent_data[] = { 919 { .fw_name = "xtal", }, 920 { .hw = &axg_fclk_div2.hw }, 921 { .hw = &axg_fclk_div3.hw }, 922 { .hw = &axg_fclk_div5.hw }, 923 { .hw = &axg_fclk_div7.hw }, 924 /* 925 * Following these parent clocks, we should also have had mpll2, mpll3 926 * and gp0_pll but these clocks are too precious to be used here. All 927 * the necessary rates for MMC and NAND operation can be acheived using 928 * xtal or fclk_div clocks 929 */ 930 }; 931 932 /* SDcard clock */ 933 static struct clk_regmap axg_sd_emmc_b_clk0_sel = { 934 .data = &(struct clk_regmap_mux_data){ 935 .offset = HHI_SD_EMMC_CLK_CNTL, 936 .mask = 0x7, 937 .shift = 25, 938 }, 939 .hw.init = &(struct clk_init_data) { 940 .name = "sd_emmc_b_clk0_sel", 941 .ops = &clk_regmap_mux_ops, 942 .parent_data = axg_sd_emmc_clk0_parent_data, 943 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data), 944 .flags = CLK_SET_RATE_PARENT, 945 }, 946 }; 947 948 static struct clk_regmap axg_sd_emmc_b_clk0_div = { 949 .data = &(struct clk_regmap_div_data){ 950 .offset = HHI_SD_EMMC_CLK_CNTL, 951 .shift = 16, 952 .width = 7, 953 .flags = CLK_DIVIDER_ROUND_CLOSEST, 954 }, 955 .hw.init = &(struct clk_init_data) { 956 .name = "sd_emmc_b_clk0_div", 957 .ops = &clk_regmap_divider_ops, 958 .parent_hws = (const struct clk_hw *[]) { 959 &axg_sd_emmc_b_clk0_sel.hw 960 }, 961 .num_parents = 1, 962 .flags = CLK_SET_RATE_PARENT, 963 }, 964 }; 965 966 static struct clk_regmap axg_sd_emmc_b_clk0 = { 967 .data = &(struct clk_regmap_gate_data){ 968 .offset = HHI_SD_EMMC_CLK_CNTL, 969 .bit_idx = 23, 970 }, 971 .hw.init = &(struct clk_init_data){ 972 .name = "sd_emmc_b_clk0", 973 .ops = &clk_regmap_gate_ops, 974 .parent_hws = (const struct clk_hw *[]) { 975 &axg_sd_emmc_b_clk0_div.hw 976 }, 977 .num_parents = 1, 978 .flags = CLK_SET_RATE_PARENT, 979 }, 980 }; 981 982 /* EMMC/NAND clock */ 983 static struct clk_regmap axg_sd_emmc_c_clk0_sel = { 984 .data = &(struct clk_regmap_mux_data){ 985 .offset = HHI_NAND_CLK_CNTL, 986 .mask = 0x7, 987 .shift = 9, 988 }, 989 .hw.init = &(struct clk_init_data) { 990 .name = "sd_emmc_c_clk0_sel", 991 .ops = &clk_regmap_mux_ops, 992 .parent_data = axg_sd_emmc_clk0_parent_data, 993 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data), 994 .flags = CLK_SET_RATE_PARENT, 995 }, 996 }; 997 998 static struct clk_regmap axg_sd_emmc_c_clk0_div = { 999 .data = &(struct clk_regmap_div_data){ 1000 .offset = HHI_NAND_CLK_CNTL, 1001 .shift = 0, 1002 .width = 7, 1003 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1004 }, 1005 .hw.init = &(struct clk_init_data) { 1006 .name = "sd_emmc_c_clk0_div", 1007 .ops = &clk_regmap_divider_ops, 1008 .parent_hws = (const struct clk_hw *[]) { 1009 &axg_sd_emmc_c_clk0_sel.hw 1010 }, 1011 .num_parents = 1, 1012 .flags = CLK_SET_RATE_PARENT, 1013 }, 1014 }; 1015 1016 static struct clk_regmap axg_sd_emmc_c_clk0 = { 1017 .data = &(struct clk_regmap_gate_data){ 1018 .offset = HHI_NAND_CLK_CNTL, 1019 .bit_idx = 7, 1020 }, 1021 .hw.init = &(struct clk_init_data){ 1022 .name = "sd_emmc_c_clk0", 1023 .ops = &clk_regmap_gate_ops, 1024 .parent_hws = (const struct clk_hw *[]) { 1025 &axg_sd_emmc_c_clk0_div.hw 1026 }, 1027 .num_parents = 1, 1028 .flags = CLK_SET_RATE_PARENT, 1029 }, 1030 }; 1031 1032 /* VPU Clock */ 1033 1034 static const struct clk_hw *axg_vpu_parent_hws[] = { 1035 &axg_fclk_div4.hw, 1036 &axg_fclk_div3.hw, 1037 &axg_fclk_div5.hw, 1038 &axg_fclk_div7.hw, 1039 }; 1040 1041 static struct clk_regmap axg_vpu_0_sel = { 1042 .data = &(struct clk_regmap_mux_data){ 1043 .offset = HHI_VPU_CLK_CNTL, 1044 .mask = 0x3, 1045 .shift = 9, 1046 }, 1047 .hw.init = &(struct clk_init_data){ 1048 .name = "vpu_0_sel", 1049 .ops = &clk_regmap_mux_ops, 1050 .parent_hws = axg_vpu_parent_hws, 1051 .num_parents = ARRAY_SIZE(axg_vpu_parent_hws), 1052 /* We need a specific parent for VPU clock source, let it be set in DT */ 1053 .flags = CLK_SET_RATE_NO_REPARENT, 1054 }, 1055 }; 1056 1057 static struct clk_regmap axg_vpu_0_div = { 1058 .data = &(struct clk_regmap_div_data){ 1059 .offset = HHI_VPU_CLK_CNTL, 1060 .shift = 0, 1061 .width = 7, 1062 }, 1063 .hw.init = &(struct clk_init_data){ 1064 .name = "vpu_0_div", 1065 .ops = &clk_regmap_divider_ops, 1066 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_0_sel.hw }, 1067 .num_parents = 1, 1068 .flags = CLK_SET_RATE_PARENT, 1069 }, 1070 }; 1071 1072 static struct clk_regmap axg_vpu_0 = { 1073 .data = &(struct clk_regmap_gate_data){ 1074 .offset = HHI_VPU_CLK_CNTL, 1075 .bit_idx = 8, 1076 }, 1077 .hw.init = &(struct clk_init_data) { 1078 .name = "vpu_0", 1079 .ops = &clk_regmap_gate_ops, 1080 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_0_div.hw }, 1081 .num_parents = 1, 1082 /* 1083 * We want to avoid CCF to disable the VPU clock if 1084 * display has been set by Bootloader 1085 */ 1086 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1087 }, 1088 }; 1089 1090 static struct clk_regmap axg_vpu_1_sel = { 1091 .data = &(struct clk_regmap_mux_data){ 1092 .offset = HHI_VPU_CLK_CNTL, 1093 .mask = 0x3, 1094 .shift = 25, 1095 }, 1096 .hw.init = &(struct clk_init_data){ 1097 .name = "vpu_1_sel", 1098 .ops = &clk_regmap_mux_ops, 1099 .parent_hws = axg_vpu_parent_hws, 1100 .num_parents = ARRAY_SIZE(axg_vpu_parent_hws), 1101 /* We need a specific parent for VPU clock source, let it be set in DT */ 1102 .flags = CLK_SET_RATE_NO_REPARENT, 1103 }, 1104 }; 1105 1106 static struct clk_regmap axg_vpu_1_div = { 1107 .data = &(struct clk_regmap_div_data){ 1108 .offset = HHI_VPU_CLK_CNTL, 1109 .shift = 16, 1110 .width = 7, 1111 }, 1112 .hw.init = &(struct clk_init_data){ 1113 .name = "vpu_1_div", 1114 .ops = &clk_regmap_divider_ops, 1115 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_1_sel.hw }, 1116 .num_parents = 1, 1117 .flags = CLK_SET_RATE_PARENT, 1118 }, 1119 }; 1120 1121 static struct clk_regmap axg_vpu_1 = { 1122 .data = &(struct clk_regmap_gate_data){ 1123 .offset = HHI_VPU_CLK_CNTL, 1124 .bit_idx = 24, 1125 }, 1126 .hw.init = &(struct clk_init_data) { 1127 .name = "vpu_1", 1128 .ops = &clk_regmap_gate_ops, 1129 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_1_div.hw }, 1130 .num_parents = 1, 1131 /* 1132 * We want to avoid CCF to disable the VPU clock if 1133 * display has been set by Bootloader 1134 */ 1135 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1136 }, 1137 }; 1138 1139 static struct clk_regmap axg_vpu = { 1140 .data = &(struct clk_regmap_mux_data){ 1141 .offset = HHI_VPU_CLK_CNTL, 1142 .mask = 1, 1143 .shift = 31, 1144 }, 1145 .hw.init = &(struct clk_init_data){ 1146 .name = "vpu", 1147 .ops = &clk_regmap_mux_ops, 1148 .parent_hws = (const struct clk_hw *[]) { 1149 &axg_vpu_0.hw, 1150 &axg_vpu_1.hw 1151 }, 1152 .num_parents = 2, 1153 .flags = CLK_SET_RATE_NO_REPARENT, 1154 }, 1155 }; 1156 1157 /* VAPB Clock */ 1158 1159 static struct clk_regmap axg_vapb_0_sel = { 1160 .data = &(struct clk_regmap_mux_data){ 1161 .offset = HHI_VAPBCLK_CNTL, 1162 .mask = 0x3, 1163 .shift = 9, 1164 }, 1165 .hw.init = &(struct clk_init_data){ 1166 .name = "vapb_0_sel", 1167 .ops = &clk_regmap_mux_ops, 1168 .parent_hws = axg_vpu_parent_hws, 1169 .num_parents = ARRAY_SIZE(axg_vpu_parent_hws), 1170 .flags = CLK_SET_RATE_NO_REPARENT, 1171 }, 1172 }; 1173 1174 static struct clk_regmap axg_vapb_0_div = { 1175 .data = &(struct clk_regmap_div_data){ 1176 .offset = HHI_VAPBCLK_CNTL, 1177 .shift = 0, 1178 .width = 7, 1179 }, 1180 .hw.init = &(struct clk_init_data){ 1181 .name = "vapb_0_div", 1182 .ops = &clk_regmap_divider_ops, 1183 .parent_hws = (const struct clk_hw *[]) { 1184 &axg_vapb_0_sel.hw 1185 }, 1186 .num_parents = 1, 1187 .flags = CLK_SET_RATE_PARENT, 1188 }, 1189 }; 1190 1191 static struct clk_regmap axg_vapb_0 = { 1192 .data = &(struct clk_regmap_gate_data){ 1193 .offset = HHI_VAPBCLK_CNTL, 1194 .bit_idx = 8, 1195 }, 1196 .hw.init = &(struct clk_init_data) { 1197 .name = "vapb_0", 1198 .ops = &clk_regmap_gate_ops, 1199 .parent_hws = (const struct clk_hw *[]) { 1200 &axg_vapb_0_div.hw 1201 }, 1202 .num_parents = 1, 1203 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1204 }, 1205 }; 1206 1207 static struct clk_regmap axg_vapb_1_sel = { 1208 .data = &(struct clk_regmap_mux_data){ 1209 .offset = HHI_VAPBCLK_CNTL, 1210 .mask = 0x3, 1211 .shift = 25, 1212 }, 1213 .hw.init = &(struct clk_init_data){ 1214 .name = "vapb_1_sel", 1215 .ops = &clk_regmap_mux_ops, 1216 .parent_hws = axg_vpu_parent_hws, 1217 .num_parents = ARRAY_SIZE(axg_vpu_parent_hws), 1218 .flags = CLK_SET_RATE_NO_REPARENT, 1219 }, 1220 }; 1221 1222 static struct clk_regmap axg_vapb_1_div = { 1223 .data = &(struct clk_regmap_div_data){ 1224 .offset = HHI_VAPBCLK_CNTL, 1225 .shift = 16, 1226 .width = 7, 1227 }, 1228 .hw.init = &(struct clk_init_data){ 1229 .name = "vapb_1_div", 1230 .ops = &clk_regmap_divider_ops, 1231 .parent_hws = (const struct clk_hw *[]) { 1232 &axg_vapb_1_sel.hw 1233 }, 1234 .num_parents = 1, 1235 .flags = CLK_SET_RATE_PARENT, 1236 }, 1237 }; 1238 1239 static struct clk_regmap axg_vapb_1 = { 1240 .data = &(struct clk_regmap_gate_data){ 1241 .offset = HHI_VAPBCLK_CNTL, 1242 .bit_idx = 24, 1243 }, 1244 .hw.init = &(struct clk_init_data) { 1245 .name = "vapb_1", 1246 .ops = &clk_regmap_gate_ops, 1247 .parent_hws = (const struct clk_hw *[]) { 1248 &axg_vapb_1_div.hw 1249 }, 1250 .num_parents = 1, 1251 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1252 }, 1253 }; 1254 1255 static struct clk_regmap axg_vapb_sel = { 1256 .data = &(struct clk_regmap_mux_data){ 1257 .offset = HHI_VAPBCLK_CNTL, 1258 .mask = 1, 1259 .shift = 31, 1260 }, 1261 .hw.init = &(struct clk_init_data){ 1262 .name = "vapb_sel", 1263 .ops = &clk_regmap_mux_ops, 1264 .parent_hws = (const struct clk_hw *[]) { 1265 &axg_vapb_0.hw, 1266 &axg_vapb_1.hw 1267 }, 1268 .num_parents = 2, 1269 .flags = CLK_SET_RATE_NO_REPARENT, 1270 }, 1271 }; 1272 1273 static struct clk_regmap axg_vapb = { 1274 .data = &(struct clk_regmap_gate_data){ 1275 .offset = HHI_VAPBCLK_CNTL, 1276 .bit_idx = 30, 1277 }, 1278 .hw.init = &(struct clk_init_data) { 1279 .name = "vapb", 1280 .ops = &clk_regmap_gate_ops, 1281 .parent_hws = (const struct clk_hw *[]) { &axg_vapb_sel.hw }, 1282 .num_parents = 1, 1283 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1284 }, 1285 }; 1286 1287 /* Video Clocks */ 1288 1289 static const struct clk_hw *axg_vclk_parent_hws[] = { 1290 &axg_gp0_pll.hw, 1291 &axg_fclk_div4.hw, 1292 &axg_fclk_div3.hw, 1293 &axg_fclk_div5.hw, 1294 &axg_fclk_div2.hw, 1295 &axg_fclk_div7.hw, 1296 &axg_mpll1.hw, 1297 }; 1298 1299 static struct clk_regmap axg_vclk_sel = { 1300 .data = &(struct clk_regmap_mux_data){ 1301 .offset = HHI_VID_CLK_CNTL, 1302 .mask = 0x7, 1303 .shift = 16, 1304 }, 1305 .hw.init = &(struct clk_init_data){ 1306 .name = "vclk_sel", 1307 .ops = &clk_regmap_mux_ops, 1308 .parent_hws = axg_vclk_parent_hws, 1309 .num_parents = ARRAY_SIZE(axg_vclk_parent_hws), 1310 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1311 }, 1312 }; 1313 1314 static struct clk_regmap axg_vclk2_sel = { 1315 .data = &(struct clk_regmap_mux_data){ 1316 .offset = HHI_VIID_CLK_CNTL, 1317 .mask = 0x7, 1318 .shift = 16, 1319 }, 1320 .hw.init = &(struct clk_init_data){ 1321 .name = "vclk2_sel", 1322 .ops = &clk_regmap_mux_ops, 1323 .parent_hws = axg_vclk_parent_hws, 1324 .num_parents = ARRAY_SIZE(axg_vclk_parent_hws), 1325 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1326 }, 1327 }; 1328 1329 static struct clk_regmap axg_vclk_input = { 1330 .data = &(struct clk_regmap_gate_data){ 1331 .offset = HHI_VID_CLK_DIV, 1332 .bit_idx = 16, 1333 }, 1334 .hw.init = &(struct clk_init_data) { 1335 .name = "vclk_input", 1336 .ops = &clk_regmap_gate_ops, 1337 .parent_hws = (const struct clk_hw *[]) { &axg_vclk_sel.hw }, 1338 .num_parents = 1, 1339 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1340 }, 1341 }; 1342 1343 static struct clk_regmap axg_vclk2_input = { 1344 .data = &(struct clk_regmap_gate_data){ 1345 .offset = HHI_VIID_CLK_DIV, 1346 .bit_idx = 16, 1347 }, 1348 .hw.init = &(struct clk_init_data) { 1349 .name = "vclk2_input", 1350 .ops = &clk_regmap_gate_ops, 1351 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2_sel.hw }, 1352 .num_parents = 1, 1353 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1354 }, 1355 }; 1356 1357 static struct clk_regmap axg_vclk_div = { 1358 .data = &(struct clk_regmap_div_data){ 1359 .offset = HHI_VID_CLK_DIV, 1360 .shift = 0, 1361 .width = 8, 1362 }, 1363 .hw.init = &(struct clk_init_data){ 1364 .name = "vclk_div", 1365 .ops = &clk_regmap_divider_ops, 1366 .parent_hws = (const struct clk_hw *[]) { 1367 &axg_vclk_input.hw 1368 }, 1369 .num_parents = 1, 1370 .flags = CLK_GET_RATE_NOCACHE, 1371 }, 1372 }; 1373 1374 static struct clk_regmap axg_vclk2_div = { 1375 .data = &(struct clk_regmap_div_data){ 1376 .offset = HHI_VIID_CLK_DIV, 1377 .shift = 0, 1378 .width = 8, 1379 }, 1380 .hw.init = &(struct clk_init_data){ 1381 .name = "vclk2_div", 1382 .ops = &clk_regmap_divider_ops, 1383 .parent_hws = (const struct clk_hw *[]) { 1384 &axg_vclk2_input.hw 1385 }, 1386 .num_parents = 1, 1387 .flags = CLK_GET_RATE_NOCACHE, 1388 }, 1389 }; 1390 1391 static struct clk_regmap axg_vclk = { 1392 .data = &(struct clk_regmap_gate_data){ 1393 .offset = HHI_VID_CLK_CNTL, 1394 .bit_idx = 19, 1395 }, 1396 .hw.init = &(struct clk_init_data) { 1397 .name = "vclk", 1398 .ops = &clk_regmap_gate_ops, 1399 .parent_hws = (const struct clk_hw *[]) { &axg_vclk_div.hw }, 1400 .num_parents = 1, 1401 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1402 }, 1403 }; 1404 1405 static struct clk_regmap axg_vclk2 = { 1406 .data = &(struct clk_regmap_gate_data){ 1407 .offset = HHI_VIID_CLK_CNTL, 1408 .bit_idx = 19, 1409 }, 1410 .hw.init = &(struct clk_init_data) { 1411 .name = "vclk2", 1412 .ops = &clk_regmap_gate_ops, 1413 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2_div.hw }, 1414 .num_parents = 1, 1415 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1416 }, 1417 }; 1418 1419 static struct clk_regmap axg_vclk_div1 = { 1420 .data = &(struct clk_regmap_gate_data){ 1421 .offset = HHI_VID_CLK_CNTL, 1422 .bit_idx = 0, 1423 }, 1424 .hw.init = &(struct clk_init_data) { 1425 .name = "vclk_div1", 1426 .ops = &clk_regmap_gate_ops, 1427 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw }, 1428 .num_parents = 1, 1429 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1430 }, 1431 }; 1432 1433 static struct clk_regmap axg_vclk_div2_en = { 1434 .data = &(struct clk_regmap_gate_data){ 1435 .offset = HHI_VID_CLK_CNTL, 1436 .bit_idx = 1, 1437 }, 1438 .hw.init = &(struct clk_init_data) { 1439 .name = "vclk_div2_en", 1440 .ops = &clk_regmap_gate_ops, 1441 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw }, 1442 .num_parents = 1, 1443 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1444 }, 1445 }; 1446 1447 static struct clk_regmap axg_vclk_div4_en = { 1448 .data = &(struct clk_regmap_gate_data){ 1449 .offset = HHI_VID_CLK_CNTL, 1450 .bit_idx = 2, 1451 }, 1452 .hw.init = &(struct clk_init_data) { 1453 .name = "vclk_div4_en", 1454 .ops = &clk_regmap_gate_ops, 1455 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw }, 1456 .num_parents = 1, 1457 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1458 }, 1459 }; 1460 1461 static struct clk_regmap axg_vclk_div6_en = { 1462 .data = &(struct clk_regmap_gate_data){ 1463 .offset = HHI_VID_CLK_CNTL, 1464 .bit_idx = 3, 1465 }, 1466 .hw.init = &(struct clk_init_data) { 1467 .name = "vclk_div6_en", 1468 .ops = &clk_regmap_gate_ops, 1469 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw }, 1470 .num_parents = 1, 1471 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1472 }, 1473 }; 1474 1475 static struct clk_regmap axg_vclk_div12_en = { 1476 .data = &(struct clk_regmap_gate_data){ 1477 .offset = HHI_VID_CLK_CNTL, 1478 .bit_idx = 4, 1479 }, 1480 .hw.init = &(struct clk_init_data) { 1481 .name = "vclk_div12_en", 1482 .ops = &clk_regmap_gate_ops, 1483 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw }, 1484 .num_parents = 1, 1485 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1486 }, 1487 }; 1488 1489 static struct clk_regmap axg_vclk2_div1 = { 1490 .data = &(struct clk_regmap_gate_data){ 1491 .offset = HHI_VIID_CLK_CNTL, 1492 .bit_idx = 0, 1493 }, 1494 .hw.init = &(struct clk_init_data) { 1495 .name = "vclk2_div1", 1496 .ops = &clk_regmap_gate_ops, 1497 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw }, 1498 .num_parents = 1, 1499 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1500 }, 1501 }; 1502 1503 static struct clk_regmap axg_vclk2_div2_en = { 1504 .data = &(struct clk_regmap_gate_data){ 1505 .offset = HHI_VIID_CLK_CNTL, 1506 .bit_idx = 1, 1507 }, 1508 .hw.init = &(struct clk_init_data) { 1509 .name = "vclk2_div2_en", 1510 .ops = &clk_regmap_gate_ops, 1511 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw }, 1512 .num_parents = 1, 1513 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1514 }, 1515 }; 1516 1517 static struct clk_regmap axg_vclk2_div4_en = { 1518 .data = &(struct clk_regmap_gate_data){ 1519 .offset = HHI_VIID_CLK_CNTL, 1520 .bit_idx = 2, 1521 }, 1522 .hw.init = &(struct clk_init_data) { 1523 .name = "vclk2_div4_en", 1524 .ops = &clk_regmap_gate_ops, 1525 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw }, 1526 .num_parents = 1, 1527 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1528 }, 1529 }; 1530 1531 static struct clk_regmap axg_vclk2_div6_en = { 1532 .data = &(struct clk_regmap_gate_data){ 1533 .offset = HHI_VIID_CLK_CNTL, 1534 .bit_idx = 3, 1535 }, 1536 .hw.init = &(struct clk_init_data) { 1537 .name = "vclk2_div6_en", 1538 .ops = &clk_regmap_gate_ops, 1539 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw }, 1540 .num_parents = 1, 1541 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1542 }, 1543 }; 1544 1545 static struct clk_regmap axg_vclk2_div12_en = { 1546 .data = &(struct clk_regmap_gate_data){ 1547 .offset = HHI_VIID_CLK_CNTL, 1548 .bit_idx = 4, 1549 }, 1550 .hw.init = &(struct clk_init_data) { 1551 .name = "vclk2_div12_en", 1552 .ops = &clk_regmap_gate_ops, 1553 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw }, 1554 .num_parents = 1, 1555 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1556 }, 1557 }; 1558 1559 static struct clk_fixed_factor axg_vclk_div2 = { 1560 .mult = 1, 1561 .div = 2, 1562 .hw.init = &(struct clk_init_data){ 1563 .name = "vclk_div2", 1564 .ops = &clk_fixed_factor_ops, 1565 .parent_hws = (const struct clk_hw *[]) { 1566 &axg_vclk_div2_en.hw 1567 }, 1568 .num_parents = 1, 1569 }, 1570 }; 1571 1572 static struct clk_fixed_factor axg_vclk_div4 = { 1573 .mult = 1, 1574 .div = 4, 1575 .hw.init = &(struct clk_init_data){ 1576 .name = "vclk_div4", 1577 .ops = &clk_fixed_factor_ops, 1578 .parent_hws = (const struct clk_hw *[]) { 1579 &axg_vclk_div4_en.hw 1580 }, 1581 .num_parents = 1, 1582 }, 1583 }; 1584 1585 static struct clk_fixed_factor axg_vclk_div6 = { 1586 .mult = 1, 1587 .div = 6, 1588 .hw.init = &(struct clk_init_data){ 1589 .name = "vclk_div6", 1590 .ops = &clk_fixed_factor_ops, 1591 .parent_hws = (const struct clk_hw *[]) { 1592 &axg_vclk_div6_en.hw 1593 }, 1594 .num_parents = 1, 1595 }, 1596 }; 1597 1598 static struct clk_fixed_factor axg_vclk_div12 = { 1599 .mult = 1, 1600 .div = 12, 1601 .hw.init = &(struct clk_init_data){ 1602 .name = "vclk_div12", 1603 .ops = &clk_fixed_factor_ops, 1604 .parent_hws = (const struct clk_hw *[]) { 1605 &axg_vclk_div12_en.hw 1606 }, 1607 .num_parents = 1, 1608 }, 1609 }; 1610 1611 static struct clk_fixed_factor axg_vclk2_div2 = { 1612 .mult = 1, 1613 .div = 2, 1614 .hw.init = &(struct clk_init_data){ 1615 .name = "vclk2_div2", 1616 .ops = &clk_fixed_factor_ops, 1617 .parent_hws = (const struct clk_hw *[]) { 1618 &axg_vclk2_div2_en.hw 1619 }, 1620 .num_parents = 1, 1621 }, 1622 }; 1623 1624 static struct clk_fixed_factor axg_vclk2_div4 = { 1625 .mult = 1, 1626 .div = 4, 1627 .hw.init = &(struct clk_init_data){ 1628 .name = "vclk2_div4", 1629 .ops = &clk_fixed_factor_ops, 1630 .parent_hws = (const struct clk_hw *[]) { 1631 &axg_vclk2_div4_en.hw 1632 }, 1633 .num_parents = 1, 1634 }, 1635 }; 1636 1637 static struct clk_fixed_factor axg_vclk2_div6 = { 1638 .mult = 1, 1639 .div = 6, 1640 .hw.init = &(struct clk_init_data){ 1641 .name = "vclk2_div6", 1642 .ops = &clk_fixed_factor_ops, 1643 .parent_hws = (const struct clk_hw *[]) { 1644 &axg_vclk2_div6_en.hw 1645 }, 1646 .num_parents = 1, 1647 }, 1648 }; 1649 1650 static struct clk_fixed_factor axg_vclk2_div12 = { 1651 .mult = 1, 1652 .div = 12, 1653 .hw.init = &(struct clk_init_data){ 1654 .name = "vclk2_div12", 1655 .ops = &clk_fixed_factor_ops, 1656 .parent_hws = (const struct clk_hw *[]) { 1657 &axg_vclk2_div12_en.hw 1658 }, 1659 .num_parents = 1, 1660 }, 1661 }; 1662 1663 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 1664 static const struct clk_hw *axg_cts_parent_hws[] = { 1665 &axg_vclk_div1.hw, 1666 &axg_vclk_div2.hw, 1667 &axg_vclk_div4.hw, 1668 &axg_vclk_div6.hw, 1669 &axg_vclk_div12.hw, 1670 &axg_vclk2_div1.hw, 1671 &axg_vclk2_div2.hw, 1672 &axg_vclk2_div4.hw, 1673 &axg_vclk2_div6.hw, 1674 &axg_vclk2_div12.hw, 1675 }; 1676 1677 static struct clk_regmap axg_cts_encl_sel = { 1678 .data = &(struct clk_regmap_mux_data){ 1679 .offset = HHI_VIID_CLK_DIV, 1680 .mask = 0xf, 1681 .shift = 12, 1682 .table = mux_table_cts_sel, 1683 }, 1684 .hw.init = &(struct clk_init_data){ 1685 .name = "cts_encl_sel", 1686 .ops = &clk_regmap_mux_ops, 1687 .parent_hws = axg_cts_parent_hws, 1688 .num_parents = ARRAY_SIZE(axg_cts_parent_hws), 1689 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1690 }, 1691 }; 1692 1693 static struct clk_regmap axg_cts_encl = { 1694 .data = &(struct clk_regmap_gate_data){ 1695 .offset = HHI_VID_CLK_CNTL2, 1696 .bit_idx = 3, 1697 }, 1698 .hw.init = &(struct clk_init_data) { 1699 .name = "cts_encl", 1700 .ops = &clk_regmap_gate_ops, 1701 .parent_hws = (const struct clk_hw *[]) { 1702 &axg_cts_encl_sel.hw 1703 }, 1704 .num_parents = 1, 1705 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1706 }, 1707 }; 1708 1709 /* MIPI DSI Host Clock */ 1710 1711 static u32 mux_table_axg_vdin_meas[] = { 0, 1, 2, 3, 6, 7 }; 1712 static const struct clk_parent_data axg_vdin_meas_parent_data[] = { 1713 { .fw_name = "xtal", }, 1714 { .hw = &axg_fclk_div4.hw }, 1715 { .hw = &axg_fclk_div3.hw }, 1716 { .hw = &axg_fclk_div5.hw }, 1717 { .hw = &axg_fclk_div2.hw }, 1718 { .hw = &axg_fclk_div7.hw }, 1719 }; 1720 1721 static struct clk_regmap axg_vdin_meas_sel = { 1722 .data = &(struct clk_regmap_mux_data){ 1723 .offset = HHI_VDIN_MEAS_CLK_CNTL, 1724 .mask = 0x7, 1725 .shift = 21, 1726 .flags = CLK_MUX_ROUND_CLOSEST, 1727 .table = mux_table_axg_vdin_meas, 1728 }, 1729 .hw.init = &(struct clk_init_data){ 1730 .name = "vdin_meas_sel", 1731 .ops = &clk_regmap_mux_ops, 1732 .parent_data = axg_vdin_meas_parent_data, 1733 .num_parents = ARRAY_SIZE(axg_vdin_meas_parent_data), 1734 .flags = CLK_SET_RATE_PARENT, 1735 }, 1736 }; 1737 1738 static struct clk_regmap axg_vdin_meas_div = { 1739 .data = &(struct clk_regmap_div_data){ 1740 .offset = HHI_VDIN_MEAS_CLK_CNTL, 1741 .shift = 12, 1742 .width = 7, 1743 }, 1744 .hw.init = &(struct clk_init_data){ 1745 .name = "vdin_meas_div", 1746 .ops = &clk_regmap_divider_ops, 1747 .parent_hws = (const struct clk_hw *[]) { 1748 &axg_vdin_meas_sel.hw }, 1749 .num_parents = 1, 1750 .flags = CLK_SET_RATE_PARENT, 1751 }, 1752 }; 1753 1754 static struct clk_regmap axg_vdin_meas = { 1755 .data = &(struct clk_regmap_gate_data){ 1756 .offset = HHI_VDIN_MEAS_CLK_CNTL, 1757 .bit_idx = 20, 1758 }, 1759 .hw.init = &(struct clk_init_data) { 1760 .name = "vdin_meas", 1761 .ops = &clk_regmap_gate_ops, 1762 .parent_hws = (const struct clk_hw *[]) { 1763 &axg_vdin_meas_div.hw }, 1764 .num_parents = 1, 1765 .flags = CLK_SET_RATE_PARENT, 1766 }, 1767 }; 1768 1769 static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8, 1770 9, 10, 11, 13, 14, }; 1771 static const struct clk_parent_data gen_clk_parent_data[] = { 1772 { .fw_name = "xtal", }, 1773 { .hw = &axg_hifi_pll.hw }, 1774 { .hw = &axg_mpll0.hw }, 1775 { .hw = &axg_mpll1.hw }, 1776 { .hw = &axg_mpll2.hw }, 1777 { .hw = &axg_mpll3.hw }, 1778 { .hw = &axg_fclk_div4.hw }, 1779 { .hw = &axg_fclk_div3.hw }, 1780 { .hw = &axg_fclk_div5.hw }, 1781 { .hw = &axg_fclk_div7.hw }, 1782 { .hw = &axg_gp0_pll.hw }, 1783 }; 1784 1785 static struct clk_regmap axg_gen_clk_sel = { 1786 .data = &(struct clk_regmap_mux_data){ 1787 .offset = HHI_GEN_CLK_CNTL, 1788 .mask = 0xf, 1789 .shift = 12, 1790 .table = mux_table_gen_clk, 1791 }, 1792 .hw.init = &(struct clk_init_data){ 1793 .name = "gen_clk_sel", 1794 .ops = &clk_regmap_mux_ops, 1795 /* 1796 * bits 15:12 selects from 14 possible parents: 1797 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt], 1798 * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4, 1799 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll 1800 */ 1801 .parent_data = gen_clk_parent_data, 1802 .num_parents = ARRAY_SIZE(gen_clk_parent_data), 1803 }, 1804 }; 1805 1806 static struct clk_regmap axg_gen_clk_div = { 1807 .data = &(struct clk_regmap_div_data){ 1808 .offset = HHI_GEN_CLK_CNTL, 1809 .shift = 0, 1810 .width = 11, 1811 }, 1812 .hw.init = &(struct clk_init_data){ 1813 .name = "gen_clk_div", 1814 .ops = &clk_regmap_divider_ops, 1815 .parent_hws = (const struct clk_hw *[]) { 1816 &axg_gen_clk_sel.hw 1817 }, 1818 .num_parents = 1, 1819 .flags = CLK_SET_RATE_PARENT, 1820 }, 1821 }; 1822 1823 static struct clk_regmap axg_gen_clk = { 1824 .data = &(struct clk_regmap_gate_data){ 1825 .offset = HHI_GEN_CLK_CNTL, 1826 .bit_idx = 7, 1827 }, 1828 .hw.init = &(struct clk_init_data){ 1829 .name = "gen_clk", 1830 .ops = &clk_regmap_gate_ops, 1831 .parent_hws = (const struct clk_hw *[]) { 1832 &axg_gen_clk_div.hw 1833 }, 1834 .num_parents = 1, 1835 .flags = CLK_SET_RATE_PARENT, 1836 }, 1837 }; 1838 1839 #define MESON_GATE(_name, _reg, _bit) \ 1840 MESON_PCLK(_name, _reg, _bit, &axg_clk81.hw) 1841 1842 /* Everything Else (EE) domain gates */ 1843 static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0); 1844 static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2); 1845 static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3); 1846 static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5); 1847 static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6); 1848 static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7); 1849 static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8); 1850 static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9); 1851 static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12); 1852 static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13); 1853 static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14); 1854 static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15); 1855 static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16); 1856 static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17); 1857 static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19); 1858 static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23); 1859 static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25); 1860 static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26); 1861 static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27); 1862 static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30); 1863 1864 static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0); 1865 static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3); 1866 static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16); 1867 static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20); 1868 static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21); 1869 static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22); 1870 static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23); 1871 static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26); 1872 static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29); 1873 static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30); 1874 static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31); 1875 1876 static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1); 1877 static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); 1878 static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8); 1879 static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9); 1880 static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11); 1881 static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25); 1882 static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); 1883 static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30); 1884 1885 /* Always On (AO) domain gates */ 1886 1887 static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0); 1888 static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1); 1889 static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2); 1890 static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3); 1891 static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4); 1892 1893 /* Array of all clocks provided by this provider */ 1894 1895 static struct clk_hw *axg_hw_clks[] = { 1896 [CLKID_SYS_PLL] = &axg_sys_pll.hw, 1897 [CLKID_FIXED_PLL] = &axg_fixed_pll.hw, 1898 [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw, 1899 [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw, 1900 [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw, 1901 [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw, 1902 [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw, 1903 [CLKID_GP0_PLL] = &axg_gp0_pll.hw, 1904 [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw, 1905 [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw, 1906 [CLKID_CLK81] = &axg_clk81.hw, 1907 [CLKID_MPLL0] = &axg_mpll0.hw, 1908 [CLKID_MPLL1] = &axg_mpll1.hw, 1909 [CLKID_MPLL2] = &axg_mpll2.hw, 1910 [CLKID_MPLL3] = &axg_mpll3.hw, 1911 [CLKID_DDR] = &axg_ddr.hw, 1912 [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw, 1913 [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw, 1914 [CLKID_ISA] = &axg_isa.hw, 1915 [CLKID_PL301] = &axg_pl301.hw, 1916 [CLKID_PERIPHS] = &axg_periphs.hw, 1917 [CLKID_SPICC0] = &axg_spicc_0.hw, 1918 [CLKID_I2C] = &axg_i2c.hw, 1919 [CLKID_RNG0] = &axg_rng0.hw, 1920 [CLKID_UART0] = &axg_uart0.hw, 1921 [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw, 1922 [CLKID_SPICC1] = &axg_spicc_1.hw, 1923 [CLKID_PCIE_A] = &axg_pcie_a.hw, 1924 [CLKID_PCIE_B] = &axg_pcie_b.hw, 1925 [CLKID_HIU_IFACE] = &axg_hiu_reg.hw, 1926 [CLKID_ASSIST_MISC] = &axg_assist_misc.hw, 1927 [CLKID_SD_EMMC_B] = &axg_emmc_b.hw, 1928 [CLKID_SD_EMMC_C] = &axg_emmc_c.hw, 1929 [CLKID_DMA] = &axg_dma.hw, 1930 [CLKID_SPI] = &axg_spi.hw, 1931 [CLKID_AUDIO] = &axg_audio.hw, 1932 [CLKID_ETH] = &axg_eth_core.hw, 1933 [CLKID_UART1] = &axg_uart1.hw, 1934 [CLKID_G2D] = &axg_g2d.hw, 1935 [CLKID_USB0] = &axg_usb0.hw, 1936 [CLKID_USB1] = &axg_usb1.hw, 1937 [CLKID_RESET] = &axg_reset.hw, 1938 [CLKID_USB] = &axg_usb_general.hw, 1939 [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw, 1940 [CLKID_EFUSE] = &axg_efuse.hw, 1941 [CLKID_BOOT_ROM] = &axg_boot_rom.hw, 1942 [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw, 1943 [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw, 1944 [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw, 1945 [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw, 1946 [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw, 1947 [CLKID_VPU_INTR] = &axg_vpu_intr.hw, 1948 [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw, 1949 [CLKID_GIC] = &axg_gic.hw, 1950 [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw, 1951 [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw, 1952 [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw, 1953 [CLKID_AO_IFACE] = &axg_ao_iface.hw, 1954 [CLKID_AO_I2C] = &axg_ao_i2c.hw, 1955 [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw, 1956 [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw, 1957 [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw, 1958 [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw, 1959 [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw, 1960 [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw, 1961 [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw, 1962 [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw, 1963 [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw, 1964 [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw, 1965 [CLKID_HIFI_PLL] = &axg_hifi_pll.hw, 1966 [CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw, 1967 [CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw, 1968 [CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw, 1969 [CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw, 1970 [CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw, 1971 [CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw, 1972 [CLKID_PCIE_PLL] = &axg_pcie_pll.hw, 1973 [CLKID_PCIE_MUX] = &axg_pcie_mux.hw, 1974 [CLKID_PCIE_REF] = &axg_pcie_ref.hw, 1975 [CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw, 1976 [CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw, 1977 [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw, 1978 [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw, 1979 [CLKID_GEN_CLK] = &axg_gen_clk.hw, 1980 [CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw, 1981 [CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw, 1982 [CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw, 1983 [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw, 1984 [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw, 1985 [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw, 1986 [CLKID_VPU_0_DIV] = &axg_vpu_0_div.hw, 1987 [CLKID_VPU_0_SEL] = &axg_vpu_0_sel.hw, 1988 [CLKID_VPU_0] = &axg_vpu_0.hw, 1989 [CLKID_VPU_1_DIV] = &axg_vpu_1_div.hw, 1990 [CLKID_VPU_1_SEL] = &axg_vpu_1_sel.hw, 1991 [CLKID_VPU_1] = &axg_vpu_1.hw, 1992 [CLKID_VPU] = &axg_vpu.hw, 1993 [CLKID_VAPB_0_DIV] = &axg_vapb_0_div.hw, 1994 [CLKID_VAPB_0_SEL] = &axg_vapb_0_sel.hw, 1995 [CLKID_VAPB_0] = &axg_vapb_0.hw, 1996 [CLKID_VAPB_1_DIV] = &axg_vapb_1_div.hw, 1997 [CLKID_VAPB_1_SEL] = &axg_vapb_1_sel.hw, 1998 [CLKID_VAPB_1] = &axg_vapb_1.hw, 1999 [CLKID_VAPB_SEL] = &axg_vapb_sel.hw, 2000 [CLKID_VAPB] = &axg_vapb.hw, 2001 [CLKID_VCLK] = &axg_vclk.hw, 2002 [CLKID_VCLK2] = &axg_vclk2.hw, 2003 [CLKID_VCLK_SEL] = &axg_vclk_sel.hw, 2004 [CLKID_VCLK2_SEL] = &axg_vclk2_sel.hw, 2005 [CLKID_VCLK_INPUT] = &axg_vclk_input.hw, 2006 [CLKID_VCLK2_INPUT] = &axg_vclk2_input.hw, 2007 [CLKID_VCLK_DIV] = &axg_vclk_div.hw, 2008 [CLKID_VCLK2_DIV] = &axg_vclk2_div.hw, 2009 [CLKID_VCLK_DIV2_EN] = &axg_vclk_div2_en.hw, 2010 [CLKID_VCLK_DIV4_EN] = &axg_vclk_div4_en.hw, 2011 [CLKID_VCLK_DIV6_EN] = &axg_vclk_div6_en.hw, 2012 [CLKID_VCLK_DIV12_EN] = &axg_vclk_div12_en.hw, 2013 [CLKID_VCLK2_DIV2_EN] = &axg_vclk2_div2_en.hw, 2014 [CLKID_VCLK2_DIV4_EN] = &axg_vclk2_div4_en.hw, 2015 [CLKID_VCLK2_DIV6_EN] = &axg_vclk2_div6_en.hw, 2016 [CLKID_VCLK2_DIV12_EN] = &axg_vclk2_div12_en.hw, 2017 [CLKID_VCLK_DIV1] = &axg_vclk_div1.hw, 2018 [CLKID_VCLK_DIV2] = &axg_vclk_div2.hw, 2019 [CLKID_VCLK_DIV4] = &axg_vclk_div4.hw, 2020 [CLKID_VCLK_DIV6] = &axg_vclk_div6.hw, 2021 [CLKID_VCLK_DIV12] = &axg_vclk_div12.hw, 2022 [CLKID_VCLK2_DIV1] = &axg_vclk2_div1.hw, 2023 [CLKID_VCLK2_DIV2] = &axg_vclk2_div2.hw, 2024 [CLKID_VCLK2_DIV4] = &axg_vclk2_div4.hw, 2025 [CLKID_VCLK2_DIV6] = &axg_vclk2_div6.hw, 2026 [CLKID_VCLK2_DIV12] = &axg_vclk2_div12.hw, 2027 [CLKID_CTS_ENCL_SEL] = &axg_cts_encl_sel.hw, 2028 [CLKID_CTS_ENCL] = &axg_cts_encl.hw, 2029 [CLKID_VDIN_MEAS_SEL] = &axg_vdin_meas_sel.hw, 2030 [CLKID_VDIN_MEAS_DIV] = &axg_vdin_meas_div.hw, 2031 [CLKID_VDIN_MEAS] = &axg_vdin_meas.hw, 2032 }; 2033 2034 /* Convenience table to populate regmap in .probe */ 2035 static struct clk_regmap *const axg_clk_regmaps[] = { 2036 &axg_clk81, 2037 &axg_ddr, 2038 &axg_audio_locker, 2039 &axg_mipi_dsi_host, 2040 &axg_isa, 2041 &axg_pl301, 2042 &axg_periphs, 2043 &axg_spicc_0, 2044 &axg_i2c, 2045 &axg_rng0, 2046 &axg_uart0, 2047 &axg_mipi_dsi_phy, 2048 &axg_spicc_1, 2049 &axg_pcie_a, 2050 &axg_pcie_b, 2051 &axg_hiu_reg, 2052 &axg_assist_misc, 2053 &axg_emmc_b, 2054 &axg_emmc_c, 2055 &axg_dma, 2056 &axg_spi, 2057 &axg_audio, 2058 &axg_eth_core, 2059 &axg_uart1, 2060 &axg_g2d, 2061 &axg_usb0, 2062 &axg_usb1, 2063 &axg_reset, 2064 &axg_usb_general, 2065 &axg_ahb_arb0, 2066 &axg_efuse, 2067 &axg_boot_rom, 2068 &axg_ahb_data_bus, 2069 &axg_ahb_ctrl_bus, 2070 &axg_usb1_to_ddr, 2071 &axg_usb0_to_ddr, 2072 &axg_mmc_pclk, 2073 &axg_vpu_intr, 2074 &axg_sec_ahb_ahb3_bridge, 2075 &axg_gic, 2076 &axg_ao_media_cpu, 2077 &axg_ao_ahb_sram, 2078 &axg_ao_ahb_bus, 2079 &axg_ao_iface, 2080 &axg_ao_i2c, 2081 &axg_sd_emmc_b_clk0, 2082 &axg_sd_emmc_c_clk0, 2083 &axg_mpeg_clk_div, 2084 &axg_sd_emmc_b_clk0_div, 2085 &axg_sd_emmc_c_clk0_div, 2086 &axg_mpeg_clk_sel, 2087 &axg_sd_emmc_b_clk0_sel, 2088 &axg_sd_emmc_c_clk0_sel, 2089 &axg_mpll0, 2090 &axg_mpll1, 2091 &axg_mpll2, 2092 &axg_mpll3, 2093 &axg_mpll0_div, 2094 &axg_mpll1_div, 2095 &axg_mpll2_div, 2096 &axg_mpll3_div, 2097 &axg_fixed_pll, 2098 &axg_sys_pll, 2099 &axg_gp0_pll, 2100 &axg_hifi_pll, 2101 &axg_mpll_prediv, 2102 &axg_fclk_div2, 2103 &axg_fclk_div3, 2104 &axg_fclk_div4, 2105 &axg_fclk_div5, 2106 &axg_fclk_div7, 2107 &axg_pcie_pll_dco, 2108 &axg_pcie_pll_od, 2109 &axg_pcie_pll, 2110 &axg_pcie_mux, 2111 &axg_pcie_ref, 2112 &axg_pcie_cml_en0, 2113 &axg_pcie_cml_en1, 2114 &axg_gen_clk_sel, 2115 &axg_gen_clk_div, 2116 &axg_gen_clk, 2117 &axg_fixed_pll_dco, 2118 &axg_sys_pll_dco, 2119 &axg_gp0_pll_dco, 2120 &axg_hifi_pll_dco, 2121 &axg_pcie_pll_dco, 2122 &axg_pcie_pll_od, 2123 &axg_vpu_0_div, 2124 &axg_vpu_0_sel, 2125 &axg_vpu_0, 2126 &axg_vpu_1_div, 2127 &axg_vpu_1_sel, 2128 &axg_vpu_1, 2129 &axg_vpu, 2130 &axg_vapb_0_div, 2131 &axg_vapb_0_sel, 2132 &axg_vapb_0, 2133 &axg_vapb_1_div, 2134 &axg_vapb_1_sel, 2135 &axg_vapb_1, 2136 &axg_vapb_sel, 2137 &axg_vapb, 2138 &axg_vclk, 2139 &axg_vclk2, 2140 &axg_vclk_sel, 2141 &axg_vclk2_sel, 2142 &axg_vclk_input, 2143 &axg_vclk2_input, 2144 &axg_vclk_div, 2145 &axg_vclk_div1, 2146 &axg_vclk2_div, 2147 &axg_vclk2_div1, 2148 &axg_vclk_div2_en, 2149 &axg_vclk_div4_en, 2150 &axg_vclk_div6_en, 2151 &axg_vclk_div12_en, 2152 &axg_vclk2_div2_en, 2153 &axg_vclk2_div4_en, 2154 &axg_vclk2_div6_en, 2155 &axg_vclk2_div12_en, 2156 &axg_cts_encl_sel, 2157 &axg_cts_encl, 2158 &axg_vdin_meas_sel, 2159 &axg_vdin_meas_div, 2160 &axg_vdin_meas, 2161 }; 2162 2163 static const struct meson_eeclkc_data axg_clkc_data = { 2164 .regmap_clks = axg_clk_regmaps, 2165 .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps), 2166 .hw_clks = { 2167 .hws = axg_hw_clks, 2168 .num = ARRAY_SIZE(axg_hw_clks), 2169 }, 2170 }; 2171 2172 2173 static const struct of_device_id clkc_match_table[] = { 2174 { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data }, 2175 {} 2176 }; 2177 MODULE_DEVICE_TABLE(of, clkc_match_table); 2178 2179 static struct platform_driver axg_driver = { 2180 .probe = meson_eeclkc_probe, 2181 .driver = { 2182 .name = "axg-clkc", 2183 .of_match_table = clkc_match_table, 2184 }, 2185 }; 2186 module_platform_driver(axg_driver); 2187 2188 MODULE_DESCRIPTION("Amlogic AXG Main Clock Controller driver"); 2189 MODULE_LICENSE("GPL"); 2190