1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AmLogic Meson-AXG Clock Controller Driver 4 * 5 * Copyright (c) 2016 Baylibre SAS. 6 * Author: Michael Turquette <mturquette@baylibre.com> 7 * 8 * Copyright (c) 2017 Amlogic, inc. 9 * Author: Qiufang Dai <qiufang.dai@amlogic.com> 10 */ 11 12 #include <linux/clk-provider.h> 13 #include <linux/init.h> 14 #include <linux/mod_devicetable.h> 15 #include <linux/platform_device.h> 16 #include <linux/module.h> 17 18 #include "clk-regmap.h" 19 #include "clk-pll.h" 20 #include "clk-mpll.h" 21 #include "meson-eeclk.h" 22 23 #include <dt-bindings/clock/axg-clkc.h> 24 25 #define HHI_GP0_PLL_CNTL 0x40 26 #define HHI_GP0_PLL_CNTL2 0x44 27 #define HHI_GP0_PLL_CNTL3 0x48 28 #define HHI_GP0_PLL_CNTL4 0x4c 29 #define HHI_GP0_PLL_CNTL5 0x50 30 #define HHI_GP0_PLL_STS 0x54 31 #define HHI_GP0_PLL_CNTL1 0x58 32 #define HHI_HIFI_PLL_CNTL 0x80 33 #define HHI_HIFI_PLL_CNTL2 0x84 34 #define HHI_HIFI_PLL_CNTL3 0x88 35 #define HHI_HIFI_PLL_CNTL4 0x8C 36 #define HHI_HIFI_PLL_CNTL5 0x90 37 #define HHI_HIFI_PLL_STS 0x94 38 #define HHI_HIFI_PLL_CNTL1 0x98 39 40 #define HHI_XTAL_DIVN_CNTL 0xbc 41 #define HHI_GCLK2_MPEG0 0xc0 42 #define HHI_GCLK2_MPEG1 0xc4 43 #define HHI_GCLK2_MPEG2 0xc8 44 #define HHI_GCLK2_OTHER 0xd0 45 #define HHI_GCLK2_AO 0xd4 46 #define HHI_PCIE_PLL_CNTL 0xd8 47 #define HHI_PCIE_PLL_CNTL1 0xdC 48 #define HHI_PCIE_PLL_CNTL2 0xe0 49 #define HHI_PCIE_PLL_CNTL3 0xe4 50 #define HHI_PCIE_PLL_CNTL4 0xe8 51 #define HHI_PCIE_PLL_CNTL5 0xec 52 #define HHI_PCIE_PLL_CNTL6 0xf0 53 #define HHI_PCIE_PLL_STS 0xf4 54 55 #define HHI_MEM_PD_REG0 0x100 56 #define HHI_VPU_MEM_PD_REG0 0x104 57 #define HHI_VIID_CLK_DIV 0x128 58 #define HHI_VIID_CLK_CNTL 0x12c 59 60 #define HHI_GCLK_MPEG0 0x140 61 #define HHI_GCLK_MPEG1 0x144 62 #define HHI_GCLK_MPEG2 0x148 63 #define HHI_GCLK_OTHER 0x150 64 #define HHI_GCLK_AO 0x154 65 #define HHI_SYS_CPU_CLK_CNTL1 0x15c 66 #define HHI_SYS_CPU_RESET_CNTL 0x160 67 #define HHI_VID_CLK_DIV 0x164 68 #define HHI_SPICC_HCLK_CNTL 0x168 69 70 #define HHI_MPEG_CLK_CNTL 0x174 71 #define HHI_VID_CLK_CNTL 0x17c 72 #define HHI_TS_CLK_CNTL 0x190 73 #define HHI_VID_CLK_CNTL2 0x194 74 #define HHI_SYS_CPU_CLK_CNTL0 0x19c 75 #define HHI_VID_PLL_CLK_DIV 0x1a0 76 #define HHI_VPU_CLK_CNTL 0x1bC 77 78 #define HHI_VAPBCLK_CNTL 0x1F4 79 80 #define HHI_GEN_CLK_CNTL 0x228 81 82 #define HHI_VDIN_MEAS_CLK_CNTL 0x250 83 #define HHI_NAND_CLK_CNTL 0x25C 84 #define HHI_SD_EMMC_CLK_CNTL 0x264 85 86 #define HHI_MPLL_CNTL 0x280 87 #define HHI_MPLL_CNTL2 0x284 88 #define HHI_MPLL_CNTL3 0x288 89 #define HHI_MPLL_CNTL4 0x28C 90 #define HHI_MPLL_CNTL5 0x290 91 #define HHI_MPLL_CNTL6 0x294 92 #define HHI_MPLL_CNTL7 0x298 93 #define HHI_MPLL_CNTL8 0x29C 94 #define HHI_MPLL_CNTL9 0x2A0 95 #define HHI_MPLL_CNTL10 0x2A4 96 97 #define HHI_MPLL3_CNTL0 0x2E0 98 #define HHI_MPLL3_CNTL1 0x2E4 99 #define HHI_PLL_TOP_MISC 0x2E8 100 101 #define HHI_SYS_PLL_CNTL1 0x2FC 102 #define HHI_SYS_PLL_CNTL 0x300 103 #define HHI_SYS_PLL_CNTL2 0x304 104 #define HHI_SYS_PLL_CNTL3 0x308 105 #define HHI_SYS_PLL_CNTL4 0x30c 106 #define HHI_SYS_PLL_CNTL5 0x310 107 #define HHI_SYS_PLL_STS 0x314 108 #define HHI_DPLL_TOP_I 0x318 109 #define HHI_DPLL_TOP2_I 0x31C 110 111 static struct clk_regmap axg_fixed_pll_dco = { 112 .data = &(struct meson_clk_pll_data){ 113 .en = { 114 .reg_off = HHI_MPLL_CNTL, 115 .shift = 30, 116 .width = 1, 117 }, 118 .m = { 119 .reg_off = HHI_MPLL_CNTL, 120 .shift = 0, 121 .width = 9, 122 }, 123 .n = { 124 .reg_off = HHI_MPLL_CNTL, 125 .shift = 9, 126 .width = 5, 127 }, 128 .frac = { 129 .reg_off = HHI_MPLL_CNTL2, 130 .shift = 0, 131 .width = 12, 132 }, 133 .l = { 134 .reg_off = HHI_MPLL_CNTL, 135 .shift = 31, 136 .width = 1, 137 }, 138 .rst = { 139 .reg_off = HHI_MPLL_CNTL, 140 .shift = 29, 141 .width = 1, 142 }, 143 }, 144 .hw.init = &(struct clk_init_data){ 145 .name = "fixed_pll_dco", 146 .ops = &meson_clk_pll_ro_ops, 147 .parent_data = &(const struct clk_parent_data) { 148 .fw_name = "xtal", 149 }, 150 .num_parents = 1, 151 }, 152 }; 153 154 static struct clk_regmap axg_fixed_pll = { 155 .data = &(struct clk_regmap_div_data){ 156 .offset = HHI_MPLL_CNTL, 157 .shift = 16, 158 .width = 2, 159 .flags = CLK_DIVIDER_POWER_OF_TWO, 160 }, 161 .hw.init = &(struct clk_init_data){ 162 .name = "fixed_pll", 163 .ops = &clk_regmap_divider_ro_ops, 164 .parent_hws = (const struct clk_hw *[]) { 165 &axg_fixed_pll_dco.hw 166 }, 167 .num_parents = 1, 168 /* 169 * This clock won't ever change at runtime so 170 * CLK_SET_RATE_PARENT is not required 171 */ 172 }, 173 }; 174 175 static struct clk_regmap axg_sys_pll_dco = { 176 .data = &(struct meson_clk_pll_data){ 177 .en = { 178 .reg_off = HHI_SYS_PLL_CNTL, 179 .shift = 30, 180 .width = 1, 181 }, 182 .m = { 183 .reg_off = HHI_SYS_PLL_CNTL, 184 .shift = 0, 185 .width = 9, 186 }, 187 .n = { 188 .reg_off = HHI_SYS_PLL_CNTL, 189 .shift = 9, 190 .width = 5, 191 }, 192 .l = { 193 .reg_off = HHI_SYS_PLL_CNTL, 194 .shift = 31, 195 .width = 1, 196 }, 197 .rst = { 198 .reg_off = HHI_SYS_PLL_CNTL, 199 .shift = 29, 200 .width = 1, 201 }, 202 }, 203 .hw.init = &(struct clk_init_data){ 204 .name = "sys_pll_dco", 205 .ops = &meson_clk_pll_ro_ops, 206 .parent_data = &(const struct clk_parent_data) { 207 .fw_name = "xtal", 208 }, 209 .num_parents = 1, 210 }, 211 }; 212 213 static struct clk_regmap axg_sys_pll = { 214 .data = &(struct clk_regmap_div_data){ 215 .offset = HHI_SYS_PLL_CNTL, 216 .shift = 16, 217 .width = 2, 218 .flags = CLK_DIVIDER_POWER_OF_TWO, 219 }, 220 .hw.init = &(struct clk_init_data){ 221 .name = "sys_pll", 222 .ops = &clk_regmap_divider_ro_ops, 223 .parent_hws = (const struct clk_hw *[]) { 224 &axg_sys_pll_dco.hw 225 }, 226 .num_parents = 1, 227 .flags = CLK_SET_RATE_PARENT, 228 }, 229 }; 230 231 static const struct pll_params_table axg_gp0_pll_params_table[] = { 232 PLL_PARAMS(40, 1), 233 PLL_PARAMS(41, 1), 234 PLL_PARAMS(42, 1), 235 PLL_PARAMS(43, 1), 236 PLL_PARAMS(44, 1), 237 PLL_PARAMS(45, 1), 238 PLL_PARAMS(46, 1), 239 PLL_PARAMS(47, 1), 240 PLL_PARAMS(48, 1), 241 PLL_PARAMS(49, 1), 242 PLL_PARAMS(50, 1), 243 PLL_PARAMS(51, 1), 244 PLL_PARAMS(52, 1), 245 PLL_PARAMS(53, 1), 246 PLL_PARAMS(54, 1), 247 PLL_PARAMS(55, 1), 248 PLL_PARAMS(56, 1), 249 PLL_PARAMS(57, 1), 250 PLL_PARAMS(58, 1), 251 PLL_PARAMS(59, 1), 252 PLL_PARAMS(60, 1), 253 PLL_PARAMS(61, 1), 254 PLL_PARAMS(62, 1), 255 PLL_PARAMS(63, 1), 256 PLL_PARAMS(64, 1), 257 PLL_PARAMS(65, 1), 258 PLL_PARAMS(66, 1), 259 PLL_PARAMS(67, 1), 260 PLL_PARAMS(68, 1), 261 { /* sentinel */ }, 262 }; 263 264 static const struct reg_sequence axg_gp0_init_regs[] = { 265 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 }, 266 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, 267 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, 268 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, 269 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, 270 }; 271 272 static struct clk_regmap axg_gp0_pll_dco = { 273 .data = &(struct meson_clk_pll_data){ 274 .en = { 275 .reg_off = HHI_GP0_PLL_CNTL, 276 .shift = 30, 277 .width = 1, 278 }, 279 .m = { 280 .reg_off = HHI_GP0_PLL_CNTL, 281 .shift = 0, 282 .width = 9, 283 }, 284 .n = { 285 .reg_off = HHI_GP0_PLL_CNTL, 286 .shift = 9, 287 .width = 5, 288 }, 289 .frac = { 290 .reg_off = HHI_GP0_PLL_CNTL1, 291 .shift = 0, 292 .width = 10, 293 }, 294 .l = { 295 .reg_off = HHI_GP0_PLL_CNTL, 296 .shift = 31, 297 .width = 1, 298 }, 299 .rst = { 300 .reg_off = HHI_GP0_PLL_CNTL, 301 .shift = 29, 302 .width = 1, 303 }, 304 .table = axg_gp0_pll_params_table, 305 .init_regs = axg_gp0_init_regs, 306 .init_count = ARRAY_SIZE(axg_gp0_init_regs), 307 }, 308 .hw.init = &(struct clk_init_data){ 309 .name = "gp0_pll_dco", 310 .ops = &meson_clk_pll_ops, 311 .parent_data = &(const struct clk_parent_data) { 312 .fw_name = "xtal", 313 }, 314 .num_parents = 1, 315 }, 316 }; 317 318 static struct clk_regmap axg_gp0_pll = { 319 .data = &(struct clk_regmap_div_data){ 320 .offset = HHI_GP0_PLL_CNTL, 321 .shift = 16, 322 .width = 2, 323 .flags = CLK_DIVIDER_POWER_OF_TWO, 324 }, 325 .hw.init = &(struct clk_init_data){ 326 .name = "gp0_pll", 327 .ops = &clk_regmap_divider_ops, 328 .parent_hws = (const struct clk_hw *[]) { 329 &axg_gp0_pll_dco.hw 330 }, 331 .num_parents = 1, 332 .flags = CLK_SET_RATE_PARENT, 333 }, 334 }; 335 336 static const struct reg_sequence axg_hifi_init_regs[] = { 337 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0xc084b000 }, 338 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0xb75020be }, 339 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 }, 340 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0xc000004d }, 341 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x00058000 }, 342 }; 343 344 static struct clk_regmap axg_hifi_pll_dco = { 345 .data = &(struct meson_clk_pll_data){ 346 .en = { 347 .reg_off = HHI_HIFI_PLL_CNTL, 348 .shift = 30, 349 .width = 1, 350 }, 351 .m = { 352 .reg_off = HHI_HIFI_PLL_CNTL, 353 .shift = 0, 354 .width = 9, 355 }, 356 .n = { 357 .reg_off = HHI_HIFI_PLL_CNTL, 358 .shift = 9, 359 .width = 5, 360 }, 361 .frac = { 362 .reg_off = HHI_HIFI_PLL_CNTL5, 363 .shift = 0, 364 .width = 13, 365 }, 366 .l = { 367 .reg_off = HHI_HIFI_PLL_CNTL, 368 .shift = 31, 369 .width = 1, 370 }, 371 .rst = { 372 .reg_off = HHI_HIFI_PLL_CNTL, 373 .shift = 29, 374 .width = 1, 375 }, 376 .table = axg_gp0_pll_params_table, 377 .init_regs = axg_hifi_init_regs, 378 .init_count = ARRAY_SIZE(axg_hifi_init_regs), 379 .flags = CLK_MESON_PLL_ROUND_CLOSEST, 380 }, 381 .hw.init = &(struct clk_init_data){ 382 .name = "hifi_pll_dco", 383 .ops = &meson_clk_pll_ops, 384 .parent_data = &(const struct clk_parent_data) { 385 .fw_name = "xtal", 386 }, 387 .num_parents = 1, 388 }, 389 }; 390 391 static struct clk_regmap axg_hifi_pll = { 392 .data = &(struct clk_regmap_div_data){ 393 .offset = HHI_HIFI_PLL_CNTL, 394 .shift = 16, 395 .width = 2, 396 .flags = CLK_DIVIDER_POWER_OF_TWO, 397 }, 398 .hw.init = &(struct clk_init_data){ 399 .name = "hifi_pll", 400 .ops = &clk_regmap_divider_ops, 401 .parent_hws = (const struct clk_hw *[]) { 402 &axg_hifi_pll_dco.hw 403 }, 404 .num_parents = 1, 405 .flags = CLK_SET_RATE_PARENT, 406 }, 407 }; 408 409 static struct clk_fixed_factor axg_fclk_div2_div = { 410 .mult = 1, 411 .div = 2, 412 .hw.init = &(struct clk_init_data){ 413 .name = "fclk_div2_div", 414 .ops = &clk_fixed_factor_ops, 415 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw }, 416 .num_parents = 1, 417 }, 418 }; 419 420 static struct clk_regmap axg_fclk_div2 = { 421 .data = &(struct clk_regmap_gate_data){ 422 .offset = HHI_MPLL_CNTL6, 423 .bit_idx = 27, 424 }, 425 .hw.init = &(struct clk_init_data){ 426 .name = "fclk_div2", 427 .ops = &clk_regmap_gate_ops, 428 .parent_hws = (const struct clk_hw *[]) { 429 &axg_fclk_div2_div.hw 430 }, 431 .num_parents = 1, 432 .flags = CLK_IS_CRITICAL, 433 }, 434 }; 435 436 static struct clk_fixed_factor axg_fclk_div3_div = { 437 .mult = 1, 438 .div = 3, 439 .hw.init = &(struct clk_init_data){ 440 .name = "fclk_div3_div", 441 .ops = &clk_fixed_factor_ops, 442 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw }, 443 .num_parents = 1, 444 }, 445 }; 446 447 static struct clk_regmap axg_fclk_div3 = { 448 .data = &(struct clk_regmap_gate_data){ 449 .offset = HHI_MPLL_CNTL6, 450 .bit_idx = 28, 451 }, 452 .hw.init = &(struct clk_init_data){ 453 .name = "fclk_div3", 454 .ops = &clk_regmap_gate_ops, 455 .parent_hws = (const struct clk_hw *[]) { 456 &axg_fclk_div3_div.hw 457 }, 458 .num_parents = 1, 459 /* 460 * FIXME: 461 * This clock, as fdiv2, is used by the SCPI FW and is required 462 * by the platform to operate correctly. 463 * Until the following condition are met, we need this clock to 464 * be marked as critical: 465 * a) The SCPI generic driver claims and enable all the clocks 466 * it needs 467 * b) CCF has a clock hand-off mechanism to make the sure the 468 * clock stays on until the proper driver comes along 469 */ 470 .flags = CLK_IS_CRITICAL, 471 }, 472 }; 473 474 static struct clk_fixed_factor axg_fclk_div4_div = { 475 .mult = 1, 476 .div = 4, 477 .hw.init = &(struct clk_init_data){ 478 .name = "fclk_div4_div", 479 .ops = &clk_fixed_factor_ops, 480 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw }, 481 .num_parents = 1, 482 }, 483 }; 484 485 static struct clk_regmap axg_fclk_div4 = { 486 .data = &(struct clk_regmap_gate_data){ 487 .offset = HHI_MPLL_CNTL6, 488 .bit_idx = 29, 489 }, 490 .hw.init = &(struct clk_init_data){ 491 .name = "fclk_div4", 492 .ops = &clk_regmap_gate_ops, 493 .parent_hws = (const struct clk_hw *[]) { 494 &axg_fclk_div4_div.hw 495 }, 496 .num_parents = 1, 497 }, 498 }; 499 500 static struct clk_fixed_factor axg_fclk_div5_div = { 501 .mult = 1, 502 .div = 5, 503 .hw.init = &(struct clk_init_data){ 504 .name = "fclk_div5_div", 505 .ops = &clk_fixed_factor_ops, 506 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw }, 507 .num_parents = 1, 508 }, 509 }; 510 511 static struct clk_regmap axg_fclk_div5 = { 512 .data = &(struct clk_regmap_gate_data){ 513 .offset = HHI_MPLL_CNTL6, 514 .bit_idx = 30, 515 }, 516 .hw.init = &(struct clk_init_data){ 517 .name = "fclk_div5", 518 .ops = &clk_regmap_gate_ops, 519 .parent_hws = (const struct clk_hw *[]) { 520 &axg_fclk_div5_div.hw 521 }, 522 .num_parents = 1, 523 }, 524 }; 525 526 static struct clk_fixed_factor axg_fclk_div7_div = { 527 .mult = 1, 528 .div = 7, 529 .hw.init = &(struct clk_init_data){ 530 .name = "fclk_div7_div", 531 .ops = &clk_fixed_factor_ops, 532 .parent_hws = (const struct clk_hw *[]) { 533 &axg_fixed_pll.hw 534 }, 535 .num_parents = 1, 536 }, 537 }; 538 539 static struct clk_regmap axg_fclk_div7 = { 540 .data = &(struct clk_regmap_gate_data){ 541 .offset = HHI_MPLL_CNTL6, 542 .bit_idx = 31, 543 }, 544 .hw.init = &(struct clk_init_data){ 545 .name = "fclk_div7", 546 .ops = &clk_regmap_gate_ops, 547 .parent_hws = (const struct clk_hw *[]) { 548 &axg_fclk_div7_div.hw 549 }, 550 .num_parents = 1, 551 }, 552 }; 553 554 static struct clk_regmap axg_mpll_prediv = { 555 .data = &(struct clk_regmap_div_data){ 556 .offset = HHI_MPLL_CNTL5, 557 .shift = 12, 558 .width = 1, 559 }, 560 .hw.init = &(struct clk_init_data){ 561 .name = "mpll_prediv", 562 .ops = &clk_regmap_divider_ro_ops, 563 .parent_hws = (const struct clk_hw *[]) { 564 &axg_fixed_pll.hw 565 }, 566 .num_parents = 1, 567 }, 568 }; 569 570 static struct clk_regmap axg_mpll0_div = { 571 .data = &(struct meson_clk_mpll_data){ 572 .sdm = { 573 .reg_off = HHI_MPLL_CNTL7, 574 .shift = 0, 575 .width = 14, 576 }, 577 .sdm_en = { 578 .reg_off = HHI_MPLL_CNTL7, 579 .shift = 15, 580 .width = 1, 581 }, 582 .n2 = { 583 .reg_off = HHI_MPLL_CNTL7, 584 .shift = 16, 585 .width = 9, 586 }, 587 .misc = { 588 .reg_off = HHI_PLL_TOP_MISC, 589 .shift = 0, 590 .width = 1, 591 }, 592 .flags = CLK_MESON_MPLL_ROUND_CLOSEST, 593 }, 594 .hw.init = &(struct clk_init_data){ 595 .name = "mpll0_div", 596 .ops = &meson_clk_mpll_ops, 597 .parent_hws = (const struct clk_hw *[]) { 598 &axg_mpll_prediv.hw 599 }, 600 .num_parents = 1, 601 }, 602 }; 603 604 static struct clk_regmap axg_mpll0 = { 605 .data = &(struct clk_regmap_gate_data){ 606 .offset = HHI_MPLL_CNTL7, 607 .bit_idx = 14, 608 }, 609 .hw.init = &(struct clk_init_data){ 610 .name = "mpll0", 611 .ops = &clk_regmap_gate_ops, 612 .parent_hws = (const struct clk_hw *[]) { 613 &axg_mpll0_div.hw 614 }, 615 .num_parents = 1, 616 .flags = CLK_SET_RATE_PARENT, 617 }, 618 }; 619 620 static struct clk_regmap axg_mpll1_div = { 621 .data = &(struct meson_clk_mpll_data){ 622 .sdm = { 623 .reg_off = HHI_MPLL_CNTL8, 624 .shift = 0, 625 .width = 14, 626 }, 627 .sdm_en = { 628 .reg_off = HHI_MPLL_CNTL8, 629 .shift = 15, 630 .width = 1, 631 }, 632 .n2 = { 633 .reg_off = HHI_MPLL_CNTL8, 634 .shift = 16, 635 .width = 9, 636 }, 637 .misc = { 638 .reg_off = HHI_PLL_TOP_MISC, 639 .shift = 1, 640 .width = 1, 641 }, 642 .flags = CLK_MESON_MPLL_ROUND_CLOSEST, 643 }, 644 .hw.init = &(struct clk_init_data){ 645 .name = "mpll1_div", 646 .ops = &meson_clk_mpll_ops, 647 .parent_hws = (const struct clk_hw *[]) { 648 &axg_mpll_prediv.hw 649 }, 650 .num_parents = 1, 651 }, 652 }; 653 654 static struct clk_regmap axg_mpll1 = { 655 .data = &(struct clk_regmap_gate_data){ 656 .offset = HHI_MPLL_CNTL8, 657 .bit_idx = 14, 658 }, 659 .hw.init = &(struct clk_init_data){ 660 .name = "mpll1", 661 .ops = &clk_regmap_gate_ops, 662 .parent_hws = (const struct clk_hw *[]) { 663 &axg_mpll1_div.hw 664 }, 665 .num_parents = 1, 666 .flags = CLK_SET_RATE_PARENT, 667 }, 668 }; 669 670 static struct clk_regmap axg_mpll2_div = { 671 .data = &(struct meson_clk_mpll_data){ 672 .sdm = { 673 .reg_off = HHI_MPLL_CNTL9, 674 .shift = 0, 675 .width = 14, 676 }, 677 .sdm_en = { 678 .reg_off = HHI_MPLL_CNTL9, 679 .shift = 15, 680 .width = 1, 681 }, 682 .n2 = { 683 .reg_off = HHI_MPLL_CNTL9, 684 .shift = 16, 685 .width = 9, 686 }, 687 .ssen = { 688 .reg_off = HHI_MPLL_CNTL, 689 .shift = 25, 690 .width = 1, 691 }, 692 .misc = { 693 .reg_off = HHI_PLL_TOP_MISC, 694 .shift = 2, 695 .width = 1, 696 }, 697 .flags = CLK_MESON_MPLL_ROUND_CLOSEST, 698 }, 699 .hw.init = &(struct clk_init_data){ 700 .name = "mpll2_div", 701 .ops = &meson_clk_mpll_ops, 702 .parent_hws = (const struct clk_hw *[]) { 703 &axg_mpll_prediv.hw 704 }, 705 .num_parents = 1, 706 }, 707 }; 708 709 static struct clk_regmap axg_mpll2 = { 710 .data = &(struct clk_regmap_gate_data){ 711 .offset = HHI_MPLL_CNTL9, 712 .bit_idx = 14, 713 }, 714 .hw.init = &(struct clk_init_data){ 715 .name = "mpll2", 716 .ops = &clk_regmap_gate_ops, 717 .parent_hws = (const struct clk_hw *[]) { 718 &axg_mpll2_div.hw 719 }, 720 .num_parents = 1, 721 .flags = CLK_SET_RATE_PARENT, 722 }, 723 }; 724 725 static struct clk_regmap axg_mpll3_div = { 726 .data = &(struct meson_clk_mpll_data){ 727 .sdm = { 728 .reg_off = HHI_MPLL3_CNTL0, 729 .shift = 12, 730 .width = 14, 731 }, 732 .sdm_en = { 733 .reg_off = HHI_MPLL3_CNTL0, 734 .shift = 11, 735 .width = 1, 736 }, 737 .n2 = { 738 .reg_off = HHI_MPLL3_CNTL0, 739 .shift = 2, 740 .width = 9, 741 }, 742 .misc = { 743 .reg_off = HHI_PLL_TOP_MISC, 744 .shift = 3, 745 .width = 1, 746 }, 747 .flags = CLK_MESON_MPLL_ROUND_CLOSEST, 748 }, 749 .hw.init = &(struct clk_init_data){ 750 .name = "mpll3_div", 751 .ops = &meson_clk_mpll_ops, 752 .parent_hws = (const struct clk_hw *[]) { 753 &axg_mpll_prediv.hw 754 }, 755 .num_parents = 1, 756 }, 757 }; 758 759 static struct clk_regmap axg_mpll3 = { 760 .data = &(struct clk_regmap_gate_data){ 761 .offset = HHI_MPLL3_CNTL0, 762 .bit_idx = 0, 763 }, 764 .hw.init = &(struct clk_init_data){ 765 .name = "mpll3", 766 .ops = &clk_regmap_gate_ops, 767 .parent_hws = (const struct clk_hw *[]) { 768 &axg_mpll3_div.hw 769 }, 770 .num_parents = 1, 771 .flags = CLK_SET_RATE_PARENT, 772 }, 773 }; 774 775 static const struct pll_params_table axg_pcie_pll_params_table[] = { 776 { 777 .m = 200, 778 .n = 3, 779 }, 780 { /* sentinel */ }, 781 }; 782 783 static const struct reg_sequence axg_pcie_init_regs[] = { 784 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x0084a2aa }, 785 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0xb75020be }, 786 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x0a47488e }, 787 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0xc000004d }, 788 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x00078000 }, 789 { .reg = HHI_PCIE_PLL_CNTL6, .def = 0x002323c6 }, 790 { .reg = HHI_PCIE_PLL_CNTL, .def = 0x400106c8 }, 791 }; 792 793 static struct clk_regmap axg_pcie_pll_dco = { 794 .data = &(struct meson_clk_pll_data){ 795 .en = { 796 .reg_off = HHI_PCIE_PLL_CNTL, 797 .shift = 30, 798 .width = 1, 799 }, 800 .m = { 801 .reg_off = HHI_PCIE_PLL_CNTL, 802 .shift = 0, 803 .width = 9, 804 }, 805 .n = { 806 .reg_off = HHI_PCIE_PLL_CNTL, 807 .shift = 9, 808 .width = 5, 809 }, 810 .frac = { 811 .reg_off = HHI_PCIE_PLL_CNTL1, 812 .shift = 0, 813 .width = 12, 814 }, 815 .l = { 816 .reg_off = HHI_PCIE_PLL_CNTL, 817 .shift = 31, 818 .width = 1, 819 }, 820 .rst = { 821 .reg_off = HHI_PCIE_PLL_CNTL, 822 .shift = 29, 823 .width = 1, 824 }, 825 .table = axg_pcie_pll_params_table, 826 .init_regs = axg_pcie_init_regs, 827 .init_count = ARRAY_SIZE(axg_pcie_init_regs), 828 }, 829 .hw.init = &(struct clk_init_data){ 830 .name = "pcie_pll_dco", 831 .ops = &meson_clk_pll_ops, 832 .parent_data = &(const struct clk_parent_data) { 833 .fw_name = "xtal", 834 }, 835 .num_parents = 1, 836 }, 837 }; 838 839 static struct clk_regmap axg_pcie_pll_od = { 840 .data = &(struct clk_regmap_div_data){ 841 .offset = HHI_PCIE_PLL_CNTL, 842 .shift = 16, 843 .width = 2, 844 .flags = CLK_DIVIDER_POWER_OF_TWO, 845 }, 846 .hw.init = &(struct clk_init_data){ 847 .name = "pcie_pll_od", 848 .ops = &clk_regmap_divider_ops, 849 .parent_hws = (const struct clk_hw *[]) { 850 &axg_pcie_pll_dco.hw 851 }, 852 .num_parents = 1, 853 .flags = CLK_SET_RATE_PARENT, 854 }, 855 }; 856 857 static struct clk_regmap axg_pcie_pll = { 858 .data = &(struct clk_regmap_div_data){ 859 .offset = HHI_PCIE_PLL_CNTL6, 860 .shift = 6, 861 .width = 2, 862 .flags = CLK_DIVIDER_POWER_OF_TWO, 863 }, 864 .hw.init = &(struct clk_init_data){ 865 .name = "pcie_pll", 866 .ops = &clk_regmap_divider_ops, 867 .parent_hws = (const struct clk_hw *[]) { 868 &axg_pcie_pll_od.hw 869 }, 870 .num_parents = 1, 871 .flags = CLK_SET_RATE_PARENT, 872 }, 873 }; 874 875 static struct clk_regmap axg_pcie_mux = { 876 .data = &(struct clk_regmap_mux_data){ 877 .offset = HHI_PCIE_PLL_CNTL6, 878 .mask = 0x1, 879 .shift = 2, 880 /* skip the parent mpll3, reserved for debug */ 881 .table = (u32[]){ 1 }, 882 }, 883 .hw.init = &(struct clk_init_data){ 884 .name = "pcie_mux", 885 .ops = &clk_regmap_mux_ops, 886 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_pll.hw }, 887 .num_parents = 1, 888 .flags = CLK_SET_RATE_PARENT, 889 }, 890 }; 891 892 static struct clk_regmap axg_pcie_ref = { 893 .data = &(struct clk_regmap_mux_data){ 894 .offset = HHI_PCIE_PLL_CNTL6, 895 .mask = 0x1, 896 .shift = 1, 897 /* skip the parent 0, reserved for debug */ 898 .table = (u32[]){ 1 }, 899 }, 900 .hw.init = &(struct clk_init_data){ 901 .name = "pcie_ref", 902 .ops = &clk_regmap_mux_ops, 903 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_mux.hw }, 904 .num_parents = 1, 905 .flags = CLK_SET_RATE_PARENT, 906 }, 907 }; 908 909 static struct clk_regmap axg_pcie_cml_en0 = { 910 .data = &(struct clk_regmap_gate_data){ 911 .offset = HHI_PCIE_PLL_CNTL6, 912 .bit_idx = 4, 913 }, 914 .hw.init = &(struct clk_init_data) { 915 .name = "pcie_cml_en0", 916 .ops = &clk_regmap_gate_ops, 917 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw }, 918 .num_parents = 1, 919 .flags = CLK_SET_RATE_PARENT, 920 921 }, 922 }; 923 924 static struct clk_regmap axg_pcie_cml_en1 = { 925 .data = &(struct clk_regmap_gate_data){ 926 .offset = HHI_PCIE_PLL_CNTL6, 927 .bit_idx = 3, 928 }, 929 .hw.init = &(struct clk_init_data) { 930 .name = "pcie_cml_en1", 931 .ops = &clk_regmap_gate_ops, 932 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw }, 933 .num_parents = 1, 934 .flags = CLK_SET_RATE_PARENT, 935 }, 936 }; 937 938 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; 939 static const struct clk_parent_data clk81_parent_data[] = { 940 { .fw_name = "xtal", }, 941 { .hw = &axg_fclk_div7.hw }, 942 { .hw = &axg_mpll1.hw }, 943 { .hw = &axg_mpll2.hw }, 944 { .hw = &axg_fclk_div4.hw }, 945 { .hw = &axg_fclk_div3.hw }, 946 { .hw = &axg_fclk_div5.hw }, 947 }; 948 949 static struct clk_regmap axg_mpeg_clk_sel = { 950 .data = &(struct clk_regmap_mux_data){ 951 .offset = HHI_MPEG_CLK_CNTL, 952 .mask = 0x7, 953 .shift = 12, 954 .table = mux_table_clk81, 955 }, 956 .hw.init = &(struct clk_init_data){ 957 .name = "mpeg_clk_sel", 958 .ops = &clk_regmap_mux_ro_ops, 959 .parent_data = clk81_parent_data, 960 .num_parents = ARRAY_SIZE(clk81_parent_data), 961 }, 962 }; 963 964 static struct clk_regmap axg_mpeg_clk_div = { 965 .data = &(struct clk_regmap_div_data){ 966 .offset = HHI_MPEG_CLK_CNTL, 967 .shift = 0, 968 .width = 7, 969 }, 970 .hw.init = &(struct clk_init_data){ 971 .name = "mpeg_clk_div", 972 .ops = &clk_regmap_divider_ops, 973 .parent_hws = (const struct clk_hw *[]) { 974 &axg_mpeg_clk_sel.hw 975 }, 976 .num_parents = 1, 977 .flags = CLK_SET_RATE_PARENT, 978 }, 979 }; 980 981 static struct clk_regmap axg_clk81 = { 982 .data = &(struct clk_regmap_gate_data){ 983 .offset = HHI_MPEG_CLK_CNTL, 984 .bit_idx = 7, 985 }, 986 .hw.init = &(struct clk_init_data){ 987 .name = "clk81", 988 .ops = &clk_regmap_gate_ops, 989 .parent_hws = (const struct clk_hw *[]) { 990 &axg_mpeg_clk_div.hw 991 }, 992 .num_parents = 1, 993 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), 994 }, 995 }; 996 997 static const struct clk_parent_data axg_sd_emmc_clk0_parent_data[] = { 998 { .fw_name = "xtal", }, 999 { .hw = &axg_fclk_div2.hw }, 1000 { .hw = &axg_fclk_div3.hw }, 1001 { .hw = &axg_fclk_div5.hw }, 1002 { .hw = &axg_fclk_div7.hw }, 1003 /* 1004 * Following these parent clocks, we should also have had mpll2, mpll3 1005 * and gp0_pll but these clocks are too precious to be used here. All 1006 * the necessary rates for MMC and NAND operation can be achieved using 1007 * xtal or fclk_div clocks 1008 */ 1009 }; 1010 1011 /* SDcard clock */ 1012 static struct clk_regmap axg_sd_emmc_b_clk0_sel = { 1013 .data = &(struct clk_regmap_mux_data){ 1014 .offset = HHI_SD_EMMC_CLK_CNTL, 1015 .mask = 0x7, 1016 .shift = 25, 1017 }, 1018 .hw.init = &(struct clk_init_data) { 1019 .name = "sd_emmc_b_clk0_sel", 1020 .ops = &clk_regmap_mux_ops, 1021 .parent_data = axg_sd_emmc_clk0_parent_data, 1022 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data), 1023 .flags = CLK_SET_RATE_PARENT, 1024 }, 1025 }; 1026 1027 static struct clk_regmap axg_sd_emmc_b_clk0_div = { 1028 .data = &(struct clk_regmap_div_data){ 1029 .offset = HHI_SD_EMMC_CLK_CNTL, 1030 .shift = 16, 1031 .width = 7, 1032 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1033 }, 1034 .hw.init = &(struct clk_init_data) { 1035 .name = "sd_emmc_b_clk0_div", 1036 .ops = &clk_regmap_divider_ops, 1037 .parent_hws = (const struct clk_hw *[]) { 1038 &axg_sd_emmc_b_clk0_sel.hw 1039 }, 1040 .num_parents = 1, 1041 .flags = CLK_SET_RATE_PARENT, 1042 }, 1043 }; 1044 1045 static struct clk_regmap axg_sd_emmc_b_clk0 = { 1046 .data = &(struct clk_regmap_gate_data){ 1047 .offset = HHI_SD_EMMC_CLK_CNTL, 1048 .bit_idx = 23, 1049 }, 1050 .hw.init = &(struct clk_init_data){ 1051 .name = "sd_emmc_b_clk0", 1052 .ops = &clk_regmap_gate_ops, 1053 .parent_hws = (const struct clk_hw *[]) { 1054 &axg_sd_emmc_b_clk0_div.hw 1055 }, 1056 .num_parents = 1, 1057 .flags = CLK_SET_RATE_PARENT, 1058 }, 1059 }; 1060 1061 /* EMMC/NAND clock */ 1062 static struct clk_regmap axg_sd_emmc_c_clk0_sel = { 1063 .data = &(struct clk_regmap_mux_data){ 1064 .offset = HHI_NAND_CLK_CNTL, 1065 .mask = 0x7, 1066 .shift = 9, 1067 }, 1068 .hw.init = &(struct clk_init_data) { 1069 .name = "sd_emmc_c_clk0_sel", 1070 .ops = &clk_regmap_mux_ops, 1071 .parent_data = axg_sd_emmc_clk0_parent_data, 1072 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data), 1073 .flags = CLK_SET_RATE_PARENT, 1074 }, 1075 }; 1076 1077 static struct clk_regmap axg_sd_emmc_c_clk0_div = { 1078 .data = &(struct clk_regmap_div_data){ 1079 .offset = HHI_NAND_CLK_CNTL, 1080 .shift = 0, 1081 .width = 7, 1082 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1083 }, 1084 .hw.init = &(struct clk_init_data) { 1085 .name = "sd_emmc_c_clk0_div", 1086 .ops = &clk_regmap_divider_ops, 1087 .parent_hws = (const struct clk_hw *[]) { 1088 &axg_sd_emmc_c_clk0_sel.hw 1089 }, 1090 .num_parents = 1, 1091 .flags = CLK_SET_RATE_PARENT, 1092 }, 1093 }; 1094 1095 static struct clk_regmap axg_sd_emmc_c_clk0 = { 1096 .data = &(struct clk_regmap_gate_data){ 1097 .offset = HHI_NAND_CLK_CNTL, 1098 .bit_idx = 7, 1099 }, 1100 .hw.init = &(struct clk_init_data){ 1101 .name = "sd_emmc_c_clk0", 1102 .ops = &clk_regmap_gate_ops, 1103 .parent_hws = (const struct clk_hw *[]) { 1104 &axg_sd_emmc_c_clk0_div.hw 1105 }, 1106 .num_parents = 1, 1107 .flags = CLK_SET_RATE_PARENT, 1108 }, 1109 }; 1110 1111 /* VPU Clock */ 1112 1113 static const struct clk_hw *axg_vpu_parent_hws[] = { 1114 &axg_fclk_div4.hw, 1115 &axg_fclk_div3.hw, 1116 &axg_fclk_div5.hw, 1117 &axg_fclk_div7.hw, 1118 }; 1119 1120 static struct clk_regmap axg_vpu_0_sel = { 1121 .data = &(struct clk_regmap_mux_data){ 1122 .offset = HHI_VPU_CLK_CNTL, 1123 .mask = 0x3, 1124 .shift = 9, 1125 }, 1126 .hw.init = &(struct clk_init_data){ 1127 .name = "vpu_0_sel", 1128 .ops = &clk_regmap_mux_ops, 1129 .parent_hws = axg_vpu_parent_hws, 1130 .num_parents = ARRAY_SIZE(axg_vpu_parent_hws), 1131 /* We need a specific parent for VPU clock source, let it be set in DT */ 1132 .flags = CLK_SET_RATE_NO_REPARENT, 1133 }, 1134 }; 1135 1136 static struct clk_regmap axg_vpu_0_div = { 1137 .data = &(struct clk_regmap_div_data){ 1138 .offset = HHI_VPU_CLK_CNTL, 1139 .shift = 0, 1140 .width = 7, 1141 }, 1142 .hw.init = &(struct clk_init_data){ 1143 .name = "vpu_0_div", 1144 .ops = &clk_regmap_divider_ops, 1145 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_0_sel.hw }, 1146 .num_parents = 1, 1147 .flags = CLK_SET_RATE_PARENT, 1148 }, 1149 }; 1150 1151 static struct clk_regmap axg_vpu_0 = { 1152 .data = &(struct clk_regmap_gate_data){ 1153 .offset = HHI_VPU_CLK_CNTL, 1154 .bit_idx = 8, 1155 }, 1156 .hw.init = &(struct clk_init_data) { 1157 .name = "vpu_0", 1158 .ops = &clk_regmap_gate_ops, 1159 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_0_div.hw }, 1160 .num_parents = 1, 1161 /* 1162 * We want to avoid CCF to disable the VPU clock if 1163 * display has been set by Bootloader 1164 */ 1165 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1166 }, 1167 }; 1168 1169 static struct clk_regmap axg_vpu_1_sel = { 1170 .data = &(struct clk_regmap_mux_data){ 1171 .offset = HHI_VPU_CLK_CNTL, 1172 .mask = 0x3, 1173 .shift = 25, 1174 }, 1175 .hw.init = &(struct clk_init_data){ 1176 .name = "vpu_1_sel", 1177 .ops = &clk_regmap_mux_ops, 1178 .parent_hws = axg_vpu_parent_hws, 1179 .num_parents = ARRAY_SIZE(axg_vpu_parent_hws), 1180 /* We need a specific parent for VPU clock source, let it be set in DT */ 1181 .flags = CLK_SET_RATE_NO_REPARENT, 1182 }, 1183 }; 1184 1185 static struct clk_regmap axg_vpu_1_div = { 1186 .data = &(struct clk_regmap_div_data){ 1187 .offset = HHI_VPU_CLK_CNTL, 1188 .shift = 16, 1189 .width = 7, 1190 }, 1191 .hw.init = &(struct clk_init_data){ 1192 .name = "vpu_1_div", 1193 .ops = &clk_regmap_divider_ops, 1194 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_1_sel.hw }, 1195 .num_parents = 1, 1196 .flags = CLK_SET_RATE_PARENT, 1197 }, 1198 }; 1199 1200 static struct clk_regmap axg_vpu_1 = { 1201 .data = &(struct clk_regmap_gate_data){ 1202 .offset = HHI_VPU_CLK_CNTL, 1203 .bit_idx = 24, 1204 }, 1205 .hw.init = &(struct clk_init_data) { 1206 .name = "vpu_1", 1207 .ops = &clk_regmap_gate_ops, 1208 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_1_div.hw }, 1209 .num_parents = 1, 1210 /* 1211 * We want to avoid CCF to disable the VPU clock if 1212 * display has been set by Bootloader 1213 */ 1214 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1215 }, 1216 }; 1217 1218 static struct clk_regmap axg_vpu = { 1219 .data = &(struct clk_regmap_mux_data){ 1220 .offset = HHI_VPU_CLK_CNTL, 1221 .mask = 1, 1222 .shift = 31, 1223 }, 1224 .hw.init = &(struct clk_init_data){ 1225 .name = "vpu", 1226 .ops = &clk_regmap_mux_ops, 1227 .parent_hws = (const struct clk_hw *[]) { 1228 &axg_vpu_0.hw, 1229 &axg_vpu_1.hw 1230 }, 1231 .num_parents = 2, 1232 .flags = CLK_SET_RATE_NO_REPARENT, 1233 }, 1234 }; 1235 1236 /* VAPB Clock */ 1237 1238 static struct clk_regmap axg_vapb_0_sel = { 1239 .data = &(struct clk_regmap_mux_data){ 1240 .offset = HHI_VAPBCLK_CNTL, 1241 .mask = 0x3, 1242 .shift = 9, 1243 }, 1244 .hw.init = &(struct clk_init_data){ 1245 .name = "vapb_0_sel", 1246 .ops = &clk_regmap_mux_ops, 1247 .parent_hws = axg_vpu_parent_hws, 1248 .num_parents = ARRAY_SIZE(axg_vpu_parent_hws), 1249 .flags = CLK_SET_RATE_NO_REPARENT, 1250 }, 1251 }; 1252 1253 static struct clk_regmap axg_vapb_0_div = { 1254 .data = &(struct clk_regmap_div_data){ 1255 .offset = HHI_VAPBCLK_CNTL, 1256 .shift = 0, 1257 .width = 7, 1258 }, 1259 .hw.init = &(struct clk_init_data){ 1260 .name = "vapb_0_div", 1261 .ops = &clk_regmap_divider_ops, 1262 .parent_hws = (const struct clk_hw *[]) { 1263 &axg_vapb_0_sel.hw 1264 }, 1265 .num_parents = 1, 1266 .flags = CLK_SET_RATE_PARENT, 1267 }, 1268 }; 1269 1270 static struct clk_regmap axg_vapb_0 = { 1271 .data = &(struct clk_regmap_gate_data){ 1272 .offset = HHI_VAPBCLK_CNTL, 1273 .bit_idx = 8, 1274 }, 1275 .hw.init = &(struct clk_init_data) { 1276 .name = "vapb_0", 1277 .ops = &clk_regmap_gate_ops, 1278 .parent_hws = (const struct clk_hw *[]) { 1279 &axg_vapb_0_div.hw 1280 }, 1281 .num_parents = 1, 1282 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1283 }, 1284 }; 1285 1286 static struct clk_regmap axg_vapb_1_sel = { 1287 .data = &(struct clk_regmap_mux_data){ 1288 .offset = HHI_VAPBCLK_CNTL, 1289 .mask = 0x3, 1290 .shift = 25, 1291 }, 1292 .hw.init = &(struct clk_init_data){ 1293 .name = "vapb_1_sel", 1294 .ops = &clk_regmap_mux_ops, 1295 .parent_hws = axg_vpu_parent_hws, 1296 .num_parents = ARRAY_SIZE(axg_vpu_parent_hws), 1297 .flags = CLK_SET_RATE_NO_REPARENT, 1298 }, 1299 }; 1300 1301 static struct clk_regmap axg_vapb_1_div = { 1302 .data = &(struct clk_regmap_div_data){ 1303 .offset = HHI_VAPBCLK_CNTL, 1304 .shift = 16, 1305 .width = 7, 1306 }, 1307 .hw.init = &(struct clk_init_data){ 1308 .name = "vapb_1_div", 1309 .ops = &clk_regmap_divider_ops, 1310 .parent_hws = (const struct clk_hw *[]) { 1311 &axg_vapb_1_sel.hw 1312 }, 1313 .num_parents = 1, 1314 .flags = CLK_SET_RATE_PARENT, 1315 }, 1316 }; 1317 1318 static struct clk_regmap axg_vapb_1 = { 1319 .data = &(struct clk_regmap_gate_data){ 1320 .offset = HHI_VAPBCLK_CNTL, 1321 .bit_idx = 24, 1322 }, 1323 .hw.init = &(struct clk_init_data) { 1324 .name = "vapb_1", 1325 .ops = &clk_regmap_gate_ops, 1326 .parent_hws = (const struct clk_hw *[]) { 1327 &axg_vapb_1_div.hw 1328 }, 1329 .num_parents = 1, 1330 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1331 }, 1332 }; 1333 1334 static struct clk_regmap axg_vapb_sel = { 1335 .data = &(struct clk_regmap_mux_data){ 1336 .offset = HHI_VAPBCLK_CNTL, 1337 .mask = 1, 1338 .shift = 31, 1339 }, 1340 .hw.init = &(struct clk_init_data){ 1341 .name = "vapb_sel", 1342 .ops = &clk_regmap_mux_ops, 1343 .parent_hws = (const struct clk_hw *[]) { 1344 &axg_vapb_0.hw, 1345 &axg_vapb_1.hw 1346 }, 1347 .num_parents = 2, 1348 .flags = CLK_SET_RATE_NO_REPARENT, 1349 }, 1350 }; 1351 1352 static struct clk_regmap axg_vapb = { 1353 .data = &(struct clk_regmap_gate_data){ 1354 .offset = HHI_VAPBCLK_CNTL, 1355 .bit_idx = 30, 1356 }, 1357 .hw.init = &(struct clk_init_data) { 1358 .name = "vapb", 1359 .ops = &clk_regmap_gate_ops, 1360 .parent_hws = (const struct clk_hw *[]) { &axg_vapb_sel.hw }, 1361 .num_parents = 1, 1362 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1363 }, 1364 }; 1365 1366 /* Video Clocks */ 1367 1368 static const struct clk_hw *axg_vclk_parent_hws[] = { 1369 &axg_gp0_pll.hw, 1370 &axg_fclk_div4.hw, 1371 &axg_fclk_div3.hw, 1372 &axg_fclk_div5.hw, 1373 &axg_fclk_div2.hw, 1374 &axg_fclk_div7.hw, 1375 &axg_mpll1.hw, 1376 }; 1377 1378 static struct clk_regmap axg_vclk_sel = { 1379 .data = &(struct clk_regmap_mux_data){ 1380 .offset = HHI_VID_CLK_CNTL, 1381 .mask = 0x7, 1382 .shift = 16, 1383 }, 1384 .hw.init = &(struct clk_init_data){ 1385 .name = "vclk_sel", 1386 .ops = &clk_regmap_mux_ops, 1387 .parent_hws = axg_vclk_parent_hws, 1388 .num_parents = ARRAY_SIZE(axg_vclk_parent_hws), 1389 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1390 }, 1391 }; 1392 1393 static struct clk_regmap axg_vclk2_sel = { 1394 .data = &(struct clk_regmap_mux_data){ 1395 .offset = HHI_VIID_CLK_CNTL, 1396 .mask = 0x7, 1397 .shift = 16, 1398 }, 1399 .hw.init = &(struct clk_init_data){ 1400 .name = "vclk2_sel", 1401 .ops = &clk_regmap_mux_ops, 1402 .parent_hws = axg_vclk_parent_hws, 1403 .num_parents = ARRAY_SIZE(axg_vclk_parent_hws), 1404 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1405 }, 1406 }; 1407 1408 static struct clk_regmap axg_vclk_input = { 1409 .data = &(struct clk_regmap_gate_data){ 1410 .offset = HHI_VID_CLK_DIV, 1411 .bit_idx = 16, 1412 }, 1413 .hw.init = &(struct clk_init_data) { 1414 .name = "vclk_input", 1415 .ops = &clk_regmap_gate_ops, 1416 .parent_hws = (const struct clk_hw *[]) { &axg_vclk_sel.hw }, 1417 .num_parents = 1, 1418 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1419 }, 1420 }; 1421 1422 static struct clk_regmap axg_vclk2_input = { 1423 .data = &(struct clk_regmap_gate_data){ 1424 .offset = HHI_VIID_CLK_DIV, 1425 .bit_idx = 16, 1426 }, 1427 .hw.init = &(struct clk_init_data) { 1428 .name = "vclk2_input", 1429 .ops = &clk_regmap_gate_ops, 1430 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2_sel.hw }, 1431 .num_parents = 1, 1432 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1433 }, 1434 }; 1435 1436 static struct clk_regmap axg_vclk_div = { 1437 .data = &(struct clk_regmap_div_data){ 1438 .offset = HHI_VID_CLK_DIV, 1439 .shift = 0, 1440 .width = 8, 1441 }, 1442 .hw.init = &(struct clk_init_data){ 1443 .name = "vclk_div", 1444 .ops = &clk_regmap_divider_ops, 1445 .parent_hws = (const struct clk_hw *[]) { 1446 &axg_vclk_input.hw 1447 }, 1448 .num_parents = 1, 1449 .flags = CLK_GET_RATE_NOCACHE, 1450 }, 1451 }; 1452 1453 static struct clk_regmap axg_vclk2_div = { 1454 .data = &(struct clk_regmap_div_data){ 1455 .offset = HHI_VIID_CLK_DIV, 1456 .shift = 0, 1457 .width = 8, 1458 }, 1459 .hw.init = &(struct clk_init_data){ 1460 .name = "vclk2_div", 1461 .ops = &clk_regmap_divider_ops, 1462 .parent_hws = (const struct clk_hw *[]) { 1463 &axg_vclk2_input.hw 1464 }, 1465 .num_parents = 1, 1466 .flags = CLK_GET_RATE_NOCACHE, 1467 }, 1468 }; 1469 1470 static struct clk_regmap axg_vclk = { 1471 .data = &(struct clk_regmap_gate_data){ 1472 .offset = HHI_VID_CLK_CNTL, 1473 .bit_idx = 19, 1474 }, 1475 .hw.init = &(struct clk_init_data) { 1476 .name = "vclk", 1477 .ops = &clk_regmap_gate_ops, 1478 .parent_hws = (const struct clk_hw *[]) { &axg_vclk_div.hw }, 1479 .num_parents = 1, 1480 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1481 }, 1482 }; 1483 1484 static struct clk_regmap axg_vclk2 = { 1485 .data = &(struct clk_regmap_gate_data){ 1486 .offset = HHI_VIID_CLK_CNTL, 1487 .bit_idx = 19, 1488 }, 1489 .hw.init = &(struct clk_init_data) { 1490 .name = "vclk2", 1491 .ops = &clk_regmap_gate_ops, 1492 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2_div.hw }, 1493 .num_parents = 1, 1494 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1495 }, 1496 }; 1497 1498 static struct clk_regmap axg_vclk_div1 = { 1499 .data = &(struct clk_regmap_gate_data){ 1500 .offset = HHI_VID_CLK_CNTL, 1501 .bit_idx = 0, 1502 }, 1503 .hw.init = &(struct clk_init_data) { 1504 .name = "vclk_div1", 1505 .ops = &clk_regmap_gate_ops, 1506 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw }, 1507 .num_parents = 1, 1508 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1509 }, 1510 }; 1511 1512 static struct clk_regmap axg_vclk_div2_en = { 1513 .data = &(struct clk_regmap_gate_data){ 1514 .offset = HHI_VID_CLK_CNTL, 1515 .bit_idx = 1, 1516 }, 1517 .hw.init = &(struct clk_init_data) { 1518 .name = "vclk_div2_en", 1519 .ops = &clk_regmap_gate_ops, 1520 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw }, 1521 .num_parents = 1, 1522 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1523 }, 1524 }; 1525 1526 static struct clk_regmap axg_vclk_div4_en = { 1527 .data = &(struct clk_regmap_gate_data){ 1528 .offset = HHI_VID_CLK_CNTL, 1529 .bit_idx = 2, 1530 }, 1531 .hw.init = &(struct clk_init_data) { 1532 .name = "vclk_div4_en", 1533 .ops = &clk_regmap_gate_ops, 1534 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw }, 1535 .num_parents = 1, 1536 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1537 }, 1538 }; 1539 1540 static struct clk_regmap axg_vclk_div6_en = { 1541 .data = &(struct clk_regmap_gate_data){ 1542 .offset = HHI_VID_CLK_CNTL, 1543 .bit_idx = 3, 1544 }, 1545 .hw.init = &(struct clk_init_data) { 1546 .name = "vclk_div6_en", 1547 .ops = &clk_regmap_gate_ops, 1548 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw }, 1549 .num_parents = 1, 1550 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1551 }, 1552 }; 1553 1554 static struct clk_regmap axg_vclk_div12_en = { 1555 .data = &(struct clk_regmap_gate_data){ 1556 .offset = HHI_VID_CLK_CNTL, 1557 .bit_idx = 4, 1558 }, 1559 .hw.init = &(struct clk_init_data) { 1560 .name = "vclk_div12_en", 1561 .ops = &clk_regmap_gate_ops, 1562 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw }, 1563 .num_parents = 1, 1564 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1565 }, 1566 }; 1567 1568 static struct clk_regmap axg_vclk2_div1 = { 1569 .data = &(struct clk_regmap_gate_data){ 1570 .offset = HHI_VIID_CLK_CNTL, 1571 .bit_idx = 0, 1572 }, 1573 .hw.init = &(struct clk_init_data) { 1574 .name = "vclk2_div1", 1575 .ops = &clk_regmap_gate_ops, 1576 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw }, 1577 .num_parents = 1, 1578 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1579 }, 1580 }; 1581 1582 static struct clk_regmap axg_vclk2_div2_en = { 1583 .data = &(struct clk_regmap_gate_data){ 1584 .offset = HHI_VIID_CLK_CNTL, 1585 .bit_idx = 1, 1586 }, 1587 .hw.init = &(struct clk_init_data) { 1588 .name = "vclk2_div2_en", 1589 .ops = &clk_regmap_gate_ops, 1590 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw }, 1591 .num_parents = 1, 1592 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1593 }, 1594 }; 1595 1596 static struct clk_regmap axg_vclk2_div4_en = { 1597 .data = &(struct clk_regmap_gate_data){ 1598 .offset = HHI_VIID_CLK_CNTL, 1599 .bit_idx = 2, 1600 }, 1601 .hw.init = &(struct clk_init_data) { 1602 .name = "vclk2_div4_en", 1603 .ops = &clk_regmap_gate_ops, 1604 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw }, 1605 .num_parents = 1, 1606 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1607 }, 1608 }; 1609 1610 static struct clk_regmap axg_vclk2_div6_en = { 1611 .data = &(struct clk_regmap_gate_data){ 1612 .offset = HHI_VIID_CLK_CNTL, 1613 .bit_idx = 3, 1614 }, 1615 .hw.init = &(struct clk_init_data) { 1616 .name = "vclk2_div6_en", 1617 .ops = &clk_regmap_gate_ops, 1618 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw }, 1619 .num_parents = 1, 1620 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1621 }, 1622 }; 1623 1624 static struct clk_regmap axg_vclk2_div12_en = { 1625 .data = &(struct clk_regmap_gate_data){ 1626 .offset = HHI_VIID_CLK_CNTL, 1627 .bit_idx = 4, 1628 }, 1629 .hw.init = &(struct clk_init_data) { 1630 .name = "vclk2_div12_en", 1631 .ops = &clk_regmap_gate_ops, 1632 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw }, 1633 .num_parents = 1, 1634 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1635 }, 1636 }; 1637 1638 static struct clk_fixed_factor axg_vclk_div2 = { 1639 .mult = 1, 1640 .div = 2, 1641 .hw.init = &(struct clk_init_data){ 1642 .name = "vclk_div2", 1643 .ops = &clk_fixed_factor_ops, 1644 .parent_hws = (const struct clk_hw *[]) { 1645 &axg_vclk_div2_en.hw 1646 }, 1647 .num_parents = 1, 1648 }, 1649 }; 1650 1651 static struct clk_fixed_factor axg_vclk_div4 = { 1652 .mult = 1, 1653 .div = 4, 1654 .hw.init = &(struct clk_init_data){ 1655 .name = "vclk_div4", 1656 .ops = &clk_fixed_factor_ops, 1657 .parent_hws = (const struct clk_hw *[]) { 1658 &axg_vclk_div4_en.hw 1659 }, 1660 .num_parents = 1, 1661 }, 1662 }; 1663 1664 static struct clk_fixed_factor axg_vclk_div6 = { 1665 .mult = 1, 1666 .div = 6, 1667 .hw.init = &(struct clk_init_data){ 1668 .name = "vclk_div6", 1669 .ops = &clk_fixed_factor_ops, 1670 .parent_hws = (const struct clk_hw *[]) { 1671 &axg_vclk_div6_en.hw 1672 }, 1673 .num_parents = 1, 1674 }, 1675 }; 1676 1677 static struct clk_fixed_factor axg_vclk_div12 = { 1678 .mult = 1, 1679 .div = 12, 1680 .hw.init = &(struct clk_init_data){ 1681 .name = "vclk_div12", 1682 .ops = &clk_fixed_factor_ops, 1683 .parent_hws = (const struct clk_hw *[]) { 1684 &axg_vclk_div12_en.hw 1685 }, 1686 .num_parents = 1, 1687 }, 1688 }; 1689 1690 static struct clk_fixed_factor axg_vclk2_div2 = { 1691 .mult = 1, 1692 .div = 2, 1693 .hw.init = &(struct clk_init_data){ 1694 .name = "vclk2_div2", 1695 .ops = &clk_fixed_factor_ops, 1696 .parent_hws = (const struct clk_hw *[]) { 1697 &axg_vclk2_div2_en.hw 1698 }, 1699 .num_parents = 1, 1700 }, 1701 }; 1702 1703 static struct clk_fixed_factor axg_vclk2_div4 = { 1704 .mult = 1, 1705 .div = 4, 1706 .hw.init = &(struct clk_init_data){ 1707 .name = "vclk2_div4", 1708 .ops = &clk_fixed_factor_ops, 1709 .parent_hws = (const struct clk_hw *[]) { 1710 &axg_vclk2_div4_en.hw 1711 }, 1712 .num_parents = 1, 1713 }, 1714 }; 1715 1716 static struct clk_fixed_factor axg_vclk2_div6 = { 1717 .mult = 1, 1718 .div = 6, 1719 .hw.init = &(struct clk_init_data){ 1720 .name = "vclk2_div6", 1721 .ops = &clk_fixed_factor_ops, 1722 .parent_hws = (const struct clk_hw *[]) { 1723 &axg_vclk2_div6_en.hw 1724 }, 1725 .num_parents = 1, 1726 }, 1727 }; 1728 1729 static struct clk_fixed_factor axg_vclk2_div12 = { 1730 .mult = 1, 1731 .div = 12, 1732 .hw.init = &(struct clk_init_data){ 1733 .name = "vclk2_div12", 1734 .ops = &clk_fixed_factor_ops, 1735 .parent_hws = (const struct clk_hw *[]) { 1736 &axg_vclk2_div12_en.hw 1737 }, 1738 .num_parents = 1, 1739 }, 1740 }; 1741 1742 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 1743 static const struct clk_hw *axg_cts_parent_hws[] = { 1744 &axg_vclk_div1.hw, 1745 &axg_vclk_div2.hw, 1746 &axg_vclk_div4.hw, 1747 &axg_vclk_div6.hw, 1748 &axg_vclk_div12.hw, 1749 &axg_vclk2_div1.hw, 1750 &axg_vclk2_div2.hw, 1751 &axg_vclk2_div4.hw, 1752 &axg_vclk2_div6.hw, 1753 &axg_vclk2_div12.hw, 1754 }; 1755 1756 static struct clk_regmap axg_cts_encl_sel = { 1757 .data = &(struct clk_regmap_mux_data){ 1758 .offset = HHI_VIID_CLK_DIV, 1759 .mask = 0xf, 1760 .shift = 12, 1761 .table = mux_table_cts_sel, 1762 }, 1763 .hw.init = &(struct clk_init_data){ 1764 .name = "cts_encl_sel", 1765 .ops = &clk_regmap_mux_ops, 1766 .parent_hws = axg_cts_parent_hws, 1767 .num_parents = ARRAY_SIZE(axg_cts_parent_hws), 1768 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1769 }, 1770 }; 1771 1772 static struct clk_regmap axg_cts_encl = { 1773 .data = &(struct clk_regmap_gate_data){ 1774 .offset = HHI_VID_CLK_CNTL2, 1775 .bit_idx = 3, 1776 }, 1777 .hw.init = &(struct clk_init_data) { 1778 .name = "cts_encl", 1779 .ops = &clk_regmap_gate_ops, 1780 .parent_hws = (const struct clk_hw *[]) { 1781 &axg_cts_encl_sel.hw 1782 }, 1783 .num_parents = 1, 1784 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1785 }, 1786 }; 1787 1788 /* MIPI DSI Host Clock */ 1789 1790 static u32 mux_table_axg_vdin_meas[] = { 0, 1, 2, 3, 6, 7 }; 1791 static const struct clk_parent_data axg_vdin_meas_parent_data[] = { 1792 { .fw_name = "xtal", }, 1793 { .hw = &axg_fclk_div4.hw }, 1794 { .hw = &axg_fclk_div3.hw }, 1795 { .hw = &axg_fclk_div5.hw }, 1796 { .hw = &axg_fclk_div2.hw }, 1797 { .hw = &axg_fclk_div7.hw }, 1798 }; 1799 1800 static struct clk_regmap axg_vdin_meas_sel = { 1801 .data = &(struct clk_regmap_mux_data){ 1802 .offset = HHI_VDIN_MEAS_CLK_CNTL, 1803 .mask = 0x7, 1804 .shift = 21, 1805 .flags = CLK_MUX_ROUND_CLOSEST, 1806 .table = mux_table_axg_vdin_meas, 1807 }, 1808 .hw.init = &(struct clk_init_data){ 1809 .name = "vdin_meas_sel", 1810 .ops = &clk_regmap_mux_ops, 1811 .parent_data = axg_vdin_meas_parent_data, 1812 .num_parents = ARRAY_SIZE(axg_vdin_meas_parent_data), 1813 .flags = CLK_SET_RATE_PARENT, 1814 }, 1815 }; 1816 1817 static struct clk_regmap axg_vdin_meas_div = { 1818 .data = &(struct clk_regmap_div_data){ 1819 .offset = HHI_VDIN_MEAS_CLK_CNTL, 1820 .shift = 12, 1821 .width = 7, 1822 }, 1823 .hw.init = &(struct clk_init_data){ 1824 .name = "vdin_meas_div", 1825 .ops = &clk_regmap_divider_ops, 1826 .parent_hws = (const struct clk_hw *[]) { 1827 &axg_vdin_meas_sel.hw }, 1828 .num_parents = 1, 1829 .flags = CLK_SET_RATE_PARENT, 1830 }, 1831 }; 1832 1833 static struct clk_regmap axg_vdin_meas = { 1834 .data = &(struct clk_regmap_gate_data){ 1835 .offset = HHI_VDIN_MEAS_CLK_CNTL, 1836 .bit_idx = 20, 1837 }, 1838 .hw.init = &(struct clk_init_data) { 1839 .name = "vdin_meas", 1840 .ops = &clk_regmap_gate_ops, 1841 .parent_hws = (const struct clk_hw *[]) { 1842 &axg_vdin_meas_div.hw }, 1843 .num_parents = 1, 1844 .flags = CLK_SET_RATE_PARENT, 1845 }, 1846 }; 1847 1848 static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8, 1849 9, 10, 11, 13, 14, }; 1850 static const struct clk_parent_data gen_clk_parent_data[] = { 1851 { .fw_name = "xtal", }, 1852 { .hw = &axg_hifi_pll.hw }, 1853 { .hw = &axg_mpll0.hw }, 1854 { .hw = &axg_mpll1.hw }, 1855 { .hw = &axg_mpll2.hw }, 1856 { .hw = &axg_mpll3.hw }, 1857 { .hw = &axg_fclk_div4.hw }, 1858 { .hw = &axg_fclk_div3.hw }, 1859 { .hw = &axg_fclk_div5.hw }, 1860 { .hw = &axg_fclk_div7.hw }, 1861 { .hw = &axg_gp0_pll.hw }, 1862 }; 1863 1864 static struct clk_regmap axg_gen_clk_sel = { 1865 .data = &(struct clk_regmap_mux_data){ 1866 .offset = HHI_GEN_CLK_CNTL, 1867 .mask = 0xf, 1868 .shift = 12, 1869 .table = mux_table_gen_clk, 1870 }, 1871 .hw.init = &(struct clk_init_data){ 1872 .name = "gen_clk_sel", 1873 .ops = &clk_regmap_mux_ops, 1874 /* 1875 * bits 15:12 selects from 14 possible parents: 1876 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt], 1877 * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4, 1878 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll 1879 */ 1880 .parent_data = gen_clk_parent_data, 1881 .num_parents = ARRAY_SIZE(gen_clk_parent_data), 1882 }, 1883 }; 1884 1885 static struct clk_regmap axg_gen_clk_div = { 1886 .data = &(struct clk_regmap_div_data){ 1887 .offset = HHI_GEN_CLK_CNTL, 1888 .shift = 0, 1889 .width = 11, 1890 }, 1891 .hw.init = &(struct clk_init_data){ 1892 .name = "gen_clk_div", 1893 .ops = &clk_regmap_divider_ops, 1894 .parent_hws = (const struct clk_hw *[]) { 1895 &axg_gen_clk_sel.hw 1896 }, 1897 .num_parents = 1, 1898 .flags = CLK_SET_RATE_PARENT, 1899 }, 1900 }; 1901 1902 static struct clk_regmap axg_gen_clk = { 1903 .data = &(struct clk_regmap_gate_data){ 1904 .offset = HHI_GEN_CLK_CNTL, 1905 .bit_idx = 7, 1906 }, 1907 .hw.init = &(struct clk_init_data){ 1908 .name = "gen_clk", 1909 .ops = &clk_regmap_gate_ops, 1910 .parent_hws = (const struct clk_hw *[]) { 1911 &axg_gen_clk_div.hw 1912 }, 1913 .num_parents = 1, 1914 .flags = CLK_SET_RATE_PARENT, 1915 }, 1916 }; 1917 1918 #define MESON_GATE(_name, _reg, _bit) \ 1919 MESON_PCLK(_name, _reg, _bit, &axg_clk81.hw) 1920 1921 /* Everything Else (EE) domain gates */ 1922 static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0); 1923 static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2); 1924 static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3); 1925 static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5); 1926 static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6); 1927 static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7); 1928 static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8); 1929 static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9); 1930 static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12); 1931 static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13); 1932 static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14); 1933 static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15); 1934 static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16); 1935 static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17); 1936 static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19); 1937 static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23); 1938 static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25); 1939 static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26); 1940 static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27); 1941 static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30); 1942 1943 static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0); 1944 static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3); 1945 static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16); 1946 static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20); 1947 static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21); 1948 static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22); 1949 static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23); 1950 static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26); 1951 static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29); 1952 static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30); 1953 static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31); 1954 1955 static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1); 1956 static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); 1957 static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8); 1958 static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9); 1959 static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11); 1960 static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25); 1961 static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); 1962 static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30); 1963 1964 /* Always On (AO) domain gates */ 1965 1966 static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0); 1967 static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1); 1968 static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2); 1969 static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3); 1970 static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4); 1971 1972 /* Array of all clocks provided by this provider */ 1973 1974 static struct clk_hw *axg_hw_clks[] = { 1975 [CLKID_SYS_PLL] = &axg_sys_pll.hw, 1976 [CLKID_FIXED_PLL] = &axg_fixed_pll.hw, 1977 [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw, 1978 [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw, 1979 [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw, 1980 [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw, 1981 [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw, 1982 [CLKID_GP0_PLL] = &axg_gp0_pll.hw, 1983 [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw, 1984 [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw, 1985 [CLKID_CLK81] = &axg_clk81.hw, 1986 [CLKID_MPLL0] = &axg_mpll0.hw, 1987 [CLKID_MPLL1] = &axg_mpll1.hw, 1988 [CLKID_MPLL2] = &axg_mpll2.hw, 1989 [CLKID_MPLL3] = &axg_mpll3.hw, 1990 [CLKID_DDR] = &axg_ddr.hw, 1991 [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw, 1992 [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw, 1993 [CLKID_ISA] = &axg_isa.hw, 1994 [CLKID_PL301] = &axg_pl301.hw, 1995 [CLKID_PERIPHS] = &axg_periphs.hw, 1996 [CLKID_SPICC0] = &axg_spicc_0.hw, 1997 [CLKID_I2C] = &axg_i2c.hw, 1998 [CLKID_RNG0] = &axg_rng0.hw, 1999 [CLKID_UART0] = &axg_uart0.hw, 2000 [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw, 2001 [CLKID_SPICC1] = &axg_spicc_1.hw, 2002 [CLKID_PCIE_A] = &axg_pcie_a.hw, 2003 [CLKID_PCIE_B] = &axg_pcie_b.hw, 2004 [CLKID_HIU_IFACE] = &axg_hiu_reg.hw, 2005 [CLKID_ASSIST_MISC] = &axg_assist_misc.hw, 2006 [CLKID_SD_EMMC_B] = &axg_emmc_b.hw, 2007 [CLKID_SD_EMMC_C] = &axg_emmc_c.hw, 2008 [CLKID_DMA] = &axg_dma.hw, 2009 [CLKID_SPI] = &axg_spi.hw, 2010 [CLKID_AUDIO] = &axg_audio.hw, 2011 [CLKID_ETH] = &axg_eth_core.hw, 2012 [CLKID_UART1] = &axg_uart1.hw, 2013 [CLKID_G2D] = &axg_g2d.hw, 2014 [CLKID_USB0] = &axg_usb0.hw, 2015 [CLKID_USB1] = &axg_usb1.hw, 2016 [CLKID_RESET] = &axg_reset.hw, 2017 [CLKID_USB] = &axg_usb_general.hw, 2018 [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw, 2019 [CLKID_EFUSE] = &axg_efuse.hw, 2020 [CLKID_BOOT_ROM] = &axg_boot_rom.hw, 2021 [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw, 2022 [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw, 2023 [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw, 2024 [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw, 2025 [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw, 2026 [CLKID_VPU_INTR] = &axg_vpu_intr.hw, 2027 [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw, 2028 [CLKID_GIC] = &axg_gic.hw, 2029 [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw, 2030 [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw, 2031 [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw, 2032 [CLKID_AO_IFACE] = &axg_ao_iface.hw, 2033 [CLKID_AO_I2C] = &axg_ao_i2c.hw, 2034 [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw, 2035 [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw, 2036 [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw, 2037 [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw, 2038 [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw, 2039 [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw, 2040 [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw, 2041 [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw, 2042 [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw, 2043 [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw, 2044 [CLKID_HIFI_PLL] = &axg_hifi_pll.hw, 2045 [CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw, 2046 [CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw, 2047 [CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw, 2048 [CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw, 2049 [CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw, 2050 [CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw, 2051 [CLKID_PCIE_PLL] = &axg_pcie_pll.hw, 2052 [CLKID_PCIE_MUX] = &axg_pcie_mux.hw, 2053 [CLKID_PCIE_REF] = &axg_pcie_ref.hw, 2054 [CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw, 2055 [CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw, 2056 [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw, 2057 [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw, 2058 [CLKID_GEN_CLK] = &axg_gen_clk.hw, 2059 [CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw, 2060 [CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw, 2061 [CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw, 2062 [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw, 2063 [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw, 2064 [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw, 2065 [CLKID_VPU_0_DIV] = &axg_vpu_0_div.hw, 2066 [CLKID_VPU_0_SEL] = &axg_vpu_0_sel.hw, 2067 [CLKID_VPU_0] = &axg_vpu_0.hw, 2068 [CLKID_VPU_1_DIV] = &axg_vpu_1_div.hw, 2069 [CLKID_VPU_1_SEL] = &axg_vpu_1_sel.hw, 2070 [CLKID_VPU_1] = &axg_vpu_1.hw, 2071 [CLKID_VPU] = &axg_vpu.hw, 2072 [CLKID_VAPB_0_DIV] = &axg_vapb_0_div.hw, 2073 [CLKID_VAPB_0_SEL] = &axg_vapb_0_sel.hw, 2074 [CLKID_VAPB_0] = &axg_vapb_0.hw, 2075 [CLKID_VAPB_1_DIV] = &axg_vapb_1_div.hw, 2076 [CLKID_VAPB_1_SEL] = &axg_vapb_1_sel.hw, 2077 [CLKID_VAPB_1] = &axg_vapb_1.hw, 2078 [CLKID_VAPB_SEL] = &axg_vapb_sel.hw, 2079 [CLKID_VAPB] = &axg_vapb.hw, 2080 [CLKID_VCLK] = &axg_vclk.hw, 2081 [CLKID_VCLK2] = &axg_vclk2.hw, 2082 [CLKID_VCLK_SEL] = &axg_vclk_sel.hw, 2083 [CLKID_VCLK2_SEL] = &axg_vclk2_sel.hw, 2084 [CLKID_VCLK_INPUT] = &axg_vclk_input.hw, 2085 [CLKID_VCLK2_INPUT] = &axg_vclk2_input.hw, 2086 [CLKID_VCLK_DIV] = &axg_vclk_div.hw, 2087 [CLKID_VCLK2_DIV] = &axg_vclk2_div.hw, 2088 [CLKID_VCLK_DIV2_EN] = &axg_vclk_div2_en.hw, 2089 [CLKID_VCLK_DIV4_EN] = &axg_vclk_div4_en.hw, 2090 [CLKID_VCLK_DIV6_EN] = &axg_vclk_div6_en.hw, 2091 [CLKID_VCLK_DIV12_EN] = &axg_vclk_div12_en.hw, 2092 [CLKID_VCLK2_DIV2_EN] = &axg_vclk2_div2_en.hw, 2093 [CLKID_VCLK2_DIV4_EN] = &axg_vclk2_div4_en.hw, 2094 [CLKID_VCLK2_DIV6_EN] = &axg_vclk2_div6_en.hw, 2095 [CLKID_VCLK2_DIV12_EN] = &axg_vclk2_div12_en.hw, 2096 [CLKID_VCLK_DIV1] = &axg_vclk_div1.hw, 2097 [CLKID_VCLK_DIV2] = &axg_vclk_div2.hw, 2098 [CLKID_VCLK_DIV4] = &axg_vclk_div4.hw, 2099 [CLKID_VCLK_DIV6] = &axg_vclk_div6.hw, 2100 [CLKID_VCLK_DIV12] = &axg_vclk_div12.hw, 2101 [CLKID_VCLK2_DIV1] = &axg_vclk2_div1.hw, 2102 [CLKID_VCLK2_DIV2] = &axg_vclk2_div2.hw, 2103 [CLKID_VCLK2_DIV4] = &axg_vclk2_div4.hw, 2104 [CLKID_VCLK2_DIV6] = &axg_vclk2_div6.hw, 2105 [CLKID_VCLK2_DIV12] = &axg_vclk2_div12.hw, 2106 [CLKID_CTS_ENCL_SEL] = &axg_cts_encl_sel.hw, 2107 [CLKID_CTS_ENCL] = &axg_cts_encl.hw, 2108 [CLKID_VDIN_MEAS_SEL] = &axg_vdin_meas_sel.hw, 2109 [CLKID_VDIN_MEAS_DIV] = &axg_vdin_meas_div.hw, 2110 [CLKID_VDIN_MEAS] = &axg_vdin_meas.hw, 2111 }; 2112 2113 static const struct meson_eeclkc_data axg_clkc_data = { 2114 .hw_clks = { 2115 .hws = axg_hw_clks, 2116 .num = ARRAY_SIZE(axg_hw_clks), 2117 }, 2118 }; 2119 2120 2121 static const struct of_device_id clkc_match_table[] = { 2122 { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data }, 2123 {} 2124 }; 2125 MODULE_DEVICE_TABLE(of, clkc_match_table); 2126 2127 static struct platform_driver axg_driver = { 2128 .probe = meson_eeclkc_probe, 2129 .driver = { 2130 .name = "axg-clkc", 2131 .of_match_table = clkc_match_table, 2132 }, 2133 }; 2134 module_platform_driver(axg_driver); 2135 2136 MODULE_DESCRIPTION("Amlogic AXG Main Clock Controller driver"); 2137 MODULE_LICENSE("GPL"); 2138 MODULE_IMPORT_NS("CLK_MESON"); 2139