1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* 3 * Copyright (c) 2018 BayLibre, SAS. 4 * Author: Jerome Brunet <jbrunet@baylibre.com> 5 */ 6 7 #ifndef __AXG_AUDIO_CLKC_H 8 #define __AXG_AUDIO_CLKC_H 9 10 /* 11 * Audio Clock register offsets 12 * 13 * Register offsets from the datasheet must be multiplied by 4 before 14 * to get the right offset 15 */ 16 #define AUDIO_CLK_GATE_EN 0x000 17 #define AUDIO_MCLK_A_CTRL 0x004 18 #define AUDIO_MCLK_B_CTRL 0x008 19 #define AUDIO_MCLK_C_CTRL 0x00C 20 #define AUDIO_MCLK_D_CTRL 0x010 21 #define AUDIO_MCLK_E_CTRL 0x014 22 #define AUDIO_MCLK_F_CTRL 0x018 23 #define AUDIO_MST_PAD_CTRL0 0x01c 24 #define AUDIO_MST_PAD_CTRL1 0x020 25 #define AUDIO_SW_RESET 0x024 26 #define AUDIO_MST_A_SCLK_CTRL0 0x040 27 #define AUDIO_MST_A_SCLK_CTRL1 0x044 28 #define AUDIO_MST_B_SCLK_CTRL0 0x048 29 #define AUDIO_MST_B_SCLK_CTRL1 0x04C 30 #define AUDIO_MST_C_SCLK_CTRL0 0x050 31 #define AUDIO_MST_C_SCLK_CTRL1 0x054 32 #define AUDIO_MST_D_SCLK_CTRL0 0x058 33 #define AUDIO_MST_D_SCLK_CTRL1 0x05C 34 #define AUDIO_MST_E_SCLK_CTRL0 0x060 35 #define AUDIO_MST_E_SCLK_CTRL1 0x064 36 #define AUDIO_MST_F_SCLK_CTRL0 0x068 37 #define AUDIO_MST_F_SCLK_CTRL1 0x06C 38 #define AUDIO_CLK_TDMIN_A_CTRL 0x080 39 #define AUDIO_CLK_TDMIN_B_CTRL 0x084 40 #define AUDIO_CLK_TDMIN_C_CTRL 0x088 41 #define AUDIO_CLK_TDMIN_LB_CTRL 0x08C 42 #define AUDIO_CLK_TDMOUT_A_CTRL 0x090 43 #define AUDIO_CLK_TDMOUT_B_CTRL 0x094 44 #define AUDIO_CLK_TDMOUT_C_CTRL 0x098 45 #define AUDIO_CLK_SPDIFIN_CTRL 0x09C 46 #define AUDIO_CLK_SPDIFOUT_CTRL 0x0A0 47 #define AUDIO_CLK_RESAMPLE_CTRL 0x0A4 48 #define AUDIO_CLK_LOCKER_CTRL 0x0A8 49 #define AUDIO_CLK_PDMIN_CTRL0 0x0AC 50 #define AUDIO_CLK_PDMIN_CTRL1 0x0B0 51 #define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4 52 53 /* SM1 introduce new register and some shifts :( */ 54 #define AUDIO_CLK_GATE_EN1 0x004 55 #define AUDIO_SM1_MCLK_A_CTRL 0x008 56 #define AUDIO_SM1_MCLK_B_CTRL 0x00C 57 #define AUDIO_SM1_MCLK_C_CTRL 0x010 58 #define AUDIO_SM1_MCLK_D_CTRL 0x014 59 #define AUDIO_SM1_MCLK_E_CTRL 0x018 60 #define AUDIO_SM1_MCLK_F_CTRL 0x01C 61 #define AUDIO_SM1_MST_PAD_CTRL0 0x020 62 #define AUDIO_SM1_MST_PAD_CTRL1 0x024 63 #define AUDIO_SM1_SW_RESET0 0x028 64 #define AUDIO_SM1_SW_RESET1 0x02C 65 #define AUDIO_CLK81_CTRL 0x030 66 #define AUDIO_CLK81_EN 0x034 67 #define AUDIO_EARCRX_CMDC_CLK_CTRL 0x0D0 68 #define AUDIO_EARCRX_DMAC_CLK_CTRL 0x0D4 69 70 #endif /*__AXG_AUDIO_CLKC_H */ 71