1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Copyright (c) 2018 BayLibre, SAS. 4 * Author: Jerome Brunet <jbrunet@baylibre.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/init.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 #include <linux/reset.h> 15 #include <linux/reset-controller.h> 16 #include <linux/slab.h> 17 18 #include <soc/amlogic/reset-meson-aux.h> 19 20 #include "meson-clkc-utils.h" 21 #include "axg-audio.h" 22 #include "clk-regmap.h" 23 #include "clk-phase.h" 24 #include "sclk-div.h" 25 26 #include <dt-bindings/clock/axg-audio-clkc.h> 27 28 #define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \ 29 .data = &(struct clk_regmap_gate_data){ \ 30 .offset = (_reg), \ 31 .bit_idx = (_bit), \ 32 }, \ 33 .hw.init = &(struct clk_init_data) { \ 34 .name = "aud_"#_name, \ 35 .ops = &clk_regmap_gate_ops, \ 36 .parent_names = (const char *[]){ #_pname }, \ 37 .num_parents = 1, \ 38 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \ 39 }, \ 40 } 41 42 #define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) { \ 43 .data = &(struct clk_regmap_mux_data){ \ 44 .offset = (_reg), \ 45 .mask = (_mask), \ 46 .shift = (_shift), \ 47 .flags = (_dflags), \ 48 }, \ 49 .hw.init = &(struct clk_init_data){ \ 50 .name = "aud_"#_name, \ 51 .ops = &clk_regmap_mux_ops, \ 52 .parent_data = _pdata, \ 53 .num_parents = ARRAY_SIZE(_pdata), \ 54 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \ 55 }, \ 56 } 57 58 #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \ 59 .data = &(struct clk_regmap_div_data){ \ 60 .offset = (_reg), \ 61 .shift = (_shift), \ 62 .width = (_width), \ 63 .flags = (_dflags), \ 64 }, \ 65 .hw.init = &(struct clk_init_data){ \ 66 .name = "aud_"#_name, \ 67 .ops = &clk_regmap_divider_ops, \ 68 .parent_names = (const char *[]){ #_pname }, \ 69 .num_parents = 1, \ 70 .flags = (_iflags), \ 71 }, \ 72 } 73 74 #define AUD_PCLK_GATE(_name, _reg, _bit) { \ 75 .data = &(struct clk_regmap_gate_data){ \ 76 .offset = (_reg), \ 77 .bit_idx = (_bit), \ 78 }, \ 79 .hw.init = &(struct clk_init_data) { \ 80 .name = "aud_"#_name, \ 81 .ops = &clk_regmap_gate_ops, \ 82 .parent_names = (const char *[]){ "aud_top" }, \ 83 .num_parents = 1, \ 84 }, \ 85 } 86 87 #define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \ 88 _hi_shift, _hi_width, _pname, _iflags) { \ 89 .data = &(struct meson_sclk_div_data) { \ 90 .div = { \ 91 .reg_off = (_reg), \ 92 .shift = (_div_shift), \ 93 .width = (_div_width), \ 94 }, \ 95 .hi = { \ 96 .reg_off = (_reg), \ 97 .shift = (_hi_shift), \ 98 .width = (_hi_width), \ 99 }, \ 100 }, \ 101 .hw.init = &(struct clk_init_data) { \ 102 .name = "aud_"#_name, \ 103 .ops = &meson_sclk_div_ops, \ 104 .parent_names = (const char *[]){ #_pname }, \ 105 .num_parents = 1, \ 106 .flags = (_iflags), \ 107 }, \ 108 } 109 110 #define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \ 111 _pname, _iflags) { \ 112 .data = &(struct meson_clk_triphase_data) { \ 113 .ph0 = { \ 114 .reg_off = (_reg), \ 115 .shift = (_shift0), \ 116 .width = (_width), \ 117 }, \ 118 .ph1 = { \ 119 .reg_off = (_reg), \ 120 .shift = (_shift1), \ 121 .width = (_width), \ 122 }, \ 123 .ph2 = { \ 124 .reg_off = (_reg), \ 125 .shift = (_shift2), \ 126 .width = (_width), \ 127 }, \ 128 }, \ 129 .hw.init = &(struct clk_init_data) { \ 130 .name = "aud_"#_name, \ 131 .ops = &meson_clk_triphase_ops, \ 132 .parent_names = (const char *[]){ #_pname }, \ 133 .num_parents = 1, \ 134 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \ 135 }, \ 136 } 137 138 #define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) { \ 139 .data = &(struct meson_clk_phase_data) { \ 140 .ph = { \ 141 .reg_off = (_reg), \ 142 .shift = (_shift), \ 143 .width = (_width), \ 144 }, \ 145 }, \ 146 .hw.init = &(struct clk_init_data) { \ 147 .name = "aud_"#_name, \ 148 .ops = &meson_clk_phase_ops, \ 149 .parent_names = (const char *[]){ #_pname }, \ 150 .num_parents = 1, \ 151 .flags = (_iflags), \ 152 }, \ 153 } 154 155 #define AUD_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, _pname, \ 156 _iflags) { \ 157 .data = &(struct meson_sclk_ws_inv_data) { \ 158 .ph = { \ 159 .reg_off = (_reg), \ 160 .shift = (_shift_ph), \ 161 .width = (_width), \ 162 }, \ 163 .ws = { \ 164 .reg_off = (_reg), \ 165 .shift = (_shift_ws), \ 166 .width = (_width), \ 167 }, \ 168 }, \ 169 .hw.init = &(struct clk_init_data) { \ 170 .name = "aud_"#_name, \ 171 .ops = &meson_clk_phase_ops, \ 172 .parent_names = (const char *[]){ #_pname }, \ 173 .num_parents = 1, \ 174 .flags = (_iflags), \ 175 }, \ 176 } 177 178 /* Audio Master Clocks */ 179 static const struct clk_parent_data mst_mux_parent_data[] = { 180 { .fw_name = "mst_in0", }, 181 { .fw_name = "mst_in1", }, 182 { .fw_name = "mst_in2", }, 183 { .fw_name = "mst_in3", }, 184 { .fw_name = "mst_in4", }, 185 { .fw_name = "mst_in5", }, 186 { .fw_name = "mst_in6", }, 187 { .fw_name = "mst_in7", }, 188 }; 189 190 #define AUD_MST_MUX(_name, _reg, _flag) \ 191 AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \ 192 mst_mux_parent_data, 0) 193 #define AUD_MST_DIV(_name, _reg, _flag) \ 194 AUD_DIV(_name##_div, _reg, 0, 16, _flag, \ 195 aud_##_name##_sel, CLK_SET_RATE_PARENT) 196 #define AUD_MST_MCLK_GATE(_name, _reg) \ 197 AUD_GATE(_name, _reg, 31, aud_##_name##_div, \ 198 CLK_SET_RATE_PARENT) 199 200 #define AUD_MST_MCLK_MUX(_name, _reg) \ 201 AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST) 202 #define AUD_MST_MCLK_DIV(_name, _reg) \ 203 AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST) 204 205 #define AUD_MST_SYS_MUX(_name, _reg) \ 206 AUD_MST_MUX(_name, _reg, 0) 207 #define AUD_MST_SYS_DIV(_name, _reg) \ 208 AUD_MST_DIV(_name, _reg, 0) 209 210 /* Sample Clocks */ 211 #define AUD_MST_SCLK_PRE_EN(_name, _reg) \ 212 AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31, \ 213 aud_mst_##_name##_mclk, 0) 214 #define AUD_MST_SCLK_DIV(_name, _reg) \ 215 AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0, \ 216 aud_mst_##_name##_sclk_pre_en, \ 217 CLK_SET_RATE_PARENT) 218 #define AUD_MST_SCLK_POST_EN(_name, _reg) \ 219 AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30, \ 220 aud_mst_##_name##_sclk_div, CLK_SET_RATE_PARENT) 221 #define AUD_MST_SCLK(_name, _reg) \ 222 AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4, \ 223 aud_mst_##_name##_sclk_post_en, CLK_SET_RATE_PARENT) 224 225 #define AUD_MST_LRCLK_DIV(_name, _reg) \ 226 AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10, \ 227 aud_mst_##_name##_sclk_post_en, 0) 228 #define AUD_MST_LRCLK(_name, _reg) \ 229 AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5, \ 230 aud_mst_##_name##_lrclk_div, CLK_SET_RATE_PARENT) 231 232 /* TDM bit clock sources */ 233 static const struct clk_parent_data tdm_sclk_parent_data[] = { 234 { .name = "aud_mst_a_sclk", .index = -1, }, 235 { .name = "aud_mst_b_sclk", .index = -1, }, 236 { .name = "aud_mst_c_sclk", .index = -1, }, 237 { .name = "aud_mst_d_sclk", .index = -1, }, 238 { .name = "aud_mst_e_sclk", .index = -1, }, 239 { .name = "aud_mst_f_sclk", .index = -1, }, 240 { .fw_name = "slv_sclk0", }, 241 { .fw_name = "slv_sclk1", }, 242 { .fw_name = "slv_sclk2", }, 243 { .fw_name = "slv_sclk3", }, 244 { .fw_name = "slv_sclk4", }, 245 { .fw_name = "slv_sclk5", }, 246 { .fw_name = "slv_sclk6", }, 247 { .fw_name = "slv_sclk7", }, 248 { .fw_name = "slv_sclk8", }, 249 { .fw_name = "slv_sclk9", }, 250 }; 251 252 /* TDM sample clock sources */ 253 static const struct clk_parent_data tdm_lrclk_parent_data[] = { 254 { .name = "aud_mst_a_lrclk", .index = -1, }, 255 { .name = "aud_mst_b_lrclk", .index = -1, }, 256 { .name = "aud_mst_c_lrclk", .index = -1, }, 257 { .name = "aud_mst_d_lrclk", .index = -1, }, 258 { .name = "aud_mst_e_lrclk", .index = -1, }, 259 { .name = "aud_mst_f_lrclk", .index = -1, }, 260 { .fw_name = "slv_lrclk0", }, 261 { .fw_name = "slv_lrclk1", }, 262 { .fw_name = "slv_lrclk2", }, 263 { .fw_name = "slv_lrclk3", }, 264 { .fw_name = "slv_lrclk4", }, 265 { .fw_name = "slv_lrclk5", }, 266 { .fw_name = "slv_lrclk6", }, 267 { .fw_name = "slv_lrclk7", }, 268 { .fw_name = "slv_lrclk8", }, 269 { .fw_name = "slv_lrclk9", }, 270 }; 271 272 #define AUD_TDM_SCLK_MUX(_name, _reg) \ 273 AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24, \ 274 CLK_MUX_ROUND_CLOSEST, tdm_sclk_parent_data, 0) 275 #define AUD_TDM_SCLK_PRE_EN(_name, _reg) \ 276 AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31, \ 277 aud_tdm##_name##_sclk_sel, CLK_SET_RATE_PARENT) 278 #define AUD_TDM_SCLK_POST_EN(_name, _reg) \ 279 AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30, \ 280 aud_tdm##_name##_sclk_pre_en, CLK_SET_RATE_PARENT) 281 #define AUD_TDM_SCLK(_name, _reg) \ 282 AUD_PHASE(tdm##_name##_sclk, _reg, 1, 29, \ 283 aud_tdm##_name##_sclk_post_en, \ 284 CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT) 285 #define AUD_TDM_SCLK_WS(_name, _reg) \ 286 AUD_SCLK_WS(tdm##_name##_sclk, _reg, 1, 29, 28, \ 287 aud_tdm##_name##_sclk_post_en, \ 288 CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT) 289 290 #define AUD_TDM_LRLCK(_name, _reg) \ 291 AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \ 292 CLK_MUX_ROUND_CLOSEST, tdm_lrclk_parent_data, 0) 293 294 /* Pad master clock sources */ 295 static const struct clk_parent_data mclk_pad_ctrl_parent_data[] = { 296 { .name = "aud_mst_a_mclk", .index = -1, }, 297 { .name = "aud_mst_b_mclk", .index = -1, }, 298 { .name = "aud_mst_c_mclk", .index = -1, }, 299 { .name = "aud_mst_d_mclk", .index = -1, }, 300 { .name = "aud_mst_e_mclk", .index = -1, }, 301 { .name = "aud_mst_f_mclk", .index = -1, }, 302 }; 303 304 /* Pad bit clock sources */ 305 static const struct clk_parent_data sclk_pad_ctrl_parent_data[] = { 306 { .name = "aud_mst_a_sclk", .index = -1, }, 307 { .name = "aud_mst_b_sclk", .index = -1, }, 308 { .name = "aud_mst_c_sclk", .index = -1, }, 309 { .name = "aud_mst_d_sclk", .index = -1, }, 310 { .name = "aud_mst_e_sclk", .index = -1, }, 311 { .name = "aud_mst_f_sclk", .index = -1, }, 312 }; 313 314 /* Pad sample clock sources */ 315 static const struct clk_parent_data lrclk_pad_ctrl_parent_data[] = { 316 { .name = "aud_mst_a_lrclk", .index = -1, }, 317 { .name = "aud_mst_b_lrclk", .index = -1, }, 318 { .name = "aud_mst_c_lrclk", .index = -1, }, 319 { .name = "aud_mst_d_lrclk", .index = -1, }, 320 { .name = "aud_mst_e_lrclk", .index = -1, }, 321 { .name = "aud_mst_f_lrclk", .index = -1, }, 322 }; 323 324 #define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents) \ 325 AUD_MUX(_name, _reg, 0x7, _shift, 0, _parents, \ 326 CLK_SET_RATE_NO_REPARENT) 327 328 /* Common Clocks */ 329 static struct clk_regmap ddr_arb = 330 AUD_PCLK_GATE(ddr_arb, AUDIO_CLK_GATE_EN, 0); 331 static struct clk_regmap pdm = 332 AUD_PCLK_GATE(pdm, AUDIO_CLK_GATE_EN, 1); 333 static struct clk_regmap tdmin_a = 334 AUD_PCLK_GATE(tdmin_a, AUDIO_CLK_GATE_EN, 2); 335 static struct clk_regmap tdmin_b = 336 AUD_PCLK_GATE(tdmin_b, AUDIO_CLK_GATE_EN, 3); 337 static struct clk_regmap tdmin_c = 338 AUD_PCLK_GATE(tdmin_c, AUDIO_CLK_GATE_EN, 4); 339 static struct clk_regmap tdmin_lb = 340 AUD_PCLK_GATE(tdmin_lb, AUDIO_CLK_GATE_EN, 5); 341 static struct clk_regmap tdmout_a = 342 AUD_PCLK_GATE(tdmout_a, AUDIO_CLK_GATE_EN, 6); 343 static struct clk_regmap tdmout_b = 344 AUD_PCLK_GATE(tdmout_b, AUDIO_CLK_GATE_EN, 7); 345 static struct clk_regmap tdmout_c = 346 AUD_PCLK_GATE(tdmout_c, AUDIO_CLK_GATE_EN, 8); 347 static struct clk_regmap frddr_a = 348 AUD_PCLK_GATE(frddr_a, AUDIO_CLK_GATE_EN, 9); 349 static struct clk_regmap frddr_b = 350 AUD_PCLK_GATE(frddr_b, AUDIO_CLK_GATE_EN, 10); 351 static struct clk_regmap frddr_c = 352 AUD_PCLK_GATE(frddr_c, AUDIO_CLK_GATE_EN, 11); 353 static struct clk_regmap toddr_a = 354 AUD_PCLK_GATE(toddr_a, AUDIO_CLK_GATE_EN, 12); 355 static struct clk_regmap toddr_b = 356 AUD_PCLK_GATE(toddr_b, AUDIO_CLK_GATE_EN, 13); 357 static struct clk_regmap toddr_c = 358 AUD_PCLK_GATE(toddr_c, AUDIO_CLK_GATE_EN, 14); 359 static struct clk_regmap loopback = 360 AUD_PCLK_GATE(loopback, AUDIO_CLK_GATE_EN, 15); 361 static struct clk_regmap spdifin = 362 AUD_PCLK_GATE(spdifin, AUDIO_CLK_GATE_EN, 16); 363 static struct clk_regmap spdifout = 364 AUD_PCLK_GATE(spdifout, AUDIO_CLK_GATE_EN, 17); 365 static struct clk_regmap resample = 366 AUD_PCLK_GATE(resample, AUDIO_CLK_GATE_EN, 18); 367 static struct clk_regmap power_detect = 368 AUD_PCLK_GATE(power_detect, AUDIO_CLK_GATE_EN, 19); 369 370 static struct clk_regmap spdifout_clk_sel = 371 AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL); 372 static struct clk_regmap pdm_dclk_sel = 373 AUD_MST_MCLK_MUX(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0); 374 static struct clk_regmap spdifin_clk_sel = 375 AUD_MST_SYS_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL); 376 static struct clk_regmap pdm_sysclk_sel = 377 AUD_MST_SYS_MUX(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1); 378 static struct clk_regmap spdifout_b_clk_sel = 379 AUD_MST_MCLK_MUX(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL); 380 381 static struct clk_regmap spdifout_clk_div = 382 AUD_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL); 383 static struct clk_regmap pdm_dclk_div = 384 AUD_MST_MCLK_DIV(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0); 385 static struct clk_regmap spdifin_clk_div = 386 AUD_MST_SYS_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL); 387 static struct clk_regmap pdm_sysclk_div = 388 AUD_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1); 389 static struct clk_regmap spdifout_b_clk_div = 390 AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL); 391 392 static struct clk_regmap spdifout_clk = 393 AUD_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL); 394 static struct clk_regmap spdifin_clk = 395 AUD_MST_MCLK_GATE(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL); 396 static struct clk_regmap pdm_dclk = 397 AUD_MST_MCLK_GATE(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0); 398 static struct clk_regmap pdm_sysclk = 399 AUD_MST_MCLK_GATE(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1); 400 static struct clk_regmap spdifout_b_clk = 401 AUD_MST_MCLK_GATE(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL); 402 403 static struct clk_regmap mst_a_sclk_pre_en = 404 AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0); 405 static struct clk_regmap mst_b_sclk_pre_en = 406 AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0); 407 static struct clk_regmap mst_c_sclk_pre_en = 408 AUD_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0); 409 static struct clk_regmap mst_d_sclk_pre_en = 410 AUD_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0); 411 static struct clk_regmap mst_e_sclk_pre_en = 412 AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0); 413 static struct clk_regmap mst_f_sclk_pre_en = 414 AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0); 415 416 static struct clk_regmap mst_a_sclk_div = 417 AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0); 418 static struct clk_regmap mst_b_sclk_div = 419 AUD_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0); 420 static struct clk_regmap mst_c_sclk_div = 421 AUD_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0); 422 static struct clk_regmap mst_d_sclk_div = 423 AUD_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0); 424 static struct clk_regmap mst_e_sclk_div = 425 AUD_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0); 426 static struct clk_regmap mst_f_sclk_div = 427 AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0); 428 429 static struct clk_regmap mst_a_sclk_post_en = 430 AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0); 431 static struct clk_regmap mst_b_sclk_post_en = 432 AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0); 433 static struct clk_regmap mst_c_sclk_post_en = 434 AUD_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0); 435 static struct clk_regmap mst_d_sclk_post_en = 436 AUD_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0); 437 static struct clk_regmap mst_e_sclk_post_en = 438 AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0); 439 static struct clk_regmap mst_f_sclk_post_en = 440 AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0); 441 442 static struct clk_regmap mst_a_sclk = 443 AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1); 444 static struct clk_regmap mst_b_sclk = 445 AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1); 446 static struct clk_regmap mst_c_sclk = 447 AUD_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1); 448 static struct clk_regmap mst_d_sclk = 449 AUD_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1); 450 static struct clk_regmap mst_e_sclk = 451 AUD_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1); 452 static struct clk_regmap mst_f_sclk = 453 AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1); 454 455 static struct clk_regmap mst_a_lrclk_div = 456 AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0); 457 static struct clk_regmap mst_b_lrclk_div = 458 AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0); 459 static struct clk_regmap mst_c_lrclk_div = 460 AUD_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0); 461 static struct clk_regmap mst_d_lrclk_div = 462 AUD_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0); 463 static struct clk_regmap mst_e_lrclk_div = 464 AUD_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0); 465 static struct clk_regmap mst_f_lrclk_div = 466 AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0); 467 468 static struct clk_regmap mst_a_lrclk = 469 AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1); 470 static struct clk_regmap mst_b_lrclk = 471 AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1); 472 static struct clk_regmap mst_c_lrclk = 473 AUD_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1); 474 static struct clk_regmap mst_d_lrclk = 475 AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1); 476 static struct clk_regmap mst_e_lrclk = 477 AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1); 478 static struct clk_regmap mst_f_lrclk = 479 AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1); 480 481 static struct clk_regmap tdmin_a_sclk_sel = 482 AUD_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL); 483 static struct clk_regmap tdmin_b_sclk_sel = 484 AUD_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL); 485 static struct clk_regmap tdmin_c_sclk_sel = 486 AUD_TDM_SCLK_MUX(in_c, AUDIO_CLK_TDMIN_C_CTRL); 487 static struct clk_regmap tdmin_lb_sclk_sel = 488 AUD_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 489 static struct clk_regmap tdmout_a_sclk_sel = 490 AUD_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 491 static struct clk_regmap tdmout_b_sclk_sel = 492 AUD_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 493 static struct clk_regmap tdmout_c_sclk_sel = 494 AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 495 496 static struct clk_regmap tdmin_a_sclk_pre_en = 497 AUD_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL); 498 static struct clk_regmap tdmin_b_sclk_pre_en = 499 AUD_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL); 500 static struct clk_regmap tdmin_c_sclk_pre_en = 501 AUD_TDM_SCLK_PRE_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL); 502 static struct clk_regmap tdmin_lb_sclk_pre_en = 503 AUD_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 504 static struct clk_regmap tdmout_a_sclk_pre_en = 505 AUD_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 506 static struct clk_regmap tdmout_b_sclk_pre_en = 507 AUD_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 508 static struct clk_regmap tdmout_c_sclk_pre_en = 509 AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 510 511 static struct clk_regmap tdmin_a_sclk_post_en = 512 AUD_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL); 513 static struct clk_regmap tdmin_b_sclk_post_en = 514 AUD_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL); 515 static struct clk_regmap tdmin_c_sclk_post_en = 516 AUD_TDM_SCLK_POST_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL); 517 static struct clk_regmap tdmin_lb_sclk_post_en = 518 AUD_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 519 static struct clk_regmap tdmout_a_sclk_post_en = 520 AUD_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 521 static struct clk_regmap tdmout_b_sclk_post_en = 522 AUD_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 523 static struct clk_regmap tdmout_c_sclk_post_en = 524 AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 525 526 static struct clk_regmap tdmin_a_sclk = 527 AUD_TDM_SCLK(in_a, AUDIO_CLK_TDMIN_A_CTRL); 528 static struct clk_regmap tdmin_b_sclk = 529 AUD_TDM_SCLK(in_b, AUDIO_CLK_TDMIN_B_CTRL); 530 static struct clk_regmap tdmin_c_sclk = 531 AUD_TDM_SCLK(in_c, AUDIO_CLK_TDMIN_C_CTRL); 532 static struct clk_regmap tdmin_lb_sclk = 533 AUD_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 534 535 static struct clk_regmap tdmin_a_lrclk = 536 AUD_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL); 537 static struct clk_regmap tdmin_b_lrclk = 538 AUD_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL); 539 static struct clk_regmap tdmin_c_lrclk = 540 AUD_TDM_LRLCK(in_c, AUDIO_CLK_TDMIN_C_CTRL); 541 static struct clk_regmap tdmin_lb_lrclk = 542 AUD_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 543 static struct clk_regmap tdmout_a_lrclk = 544 AUD_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 545 static struct clk_regmap tdmout_b_lrclk = 546 AUD_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 547 static struct clk_regmap tdmout_c_lrclk = 548 AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 549 550 /* AXG Clocks */ 551 static struct clk_regmap axg_tdmout_a_sclk = 552 AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 553 static struct clk_regmap axg_tdmout_b_sclk = 554 AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 555 static struct clk_regmap axg_tdmout_c_sclk = 556 AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 557 558 /* AXG/G12A Clocks */ 559 static struct clk_hw axg_aud_top = { 560 .init = &(struct clk_init_data) { 561 /* Provide aud_top signal name on axg and g12a */ 562 .name = "aud_top", 563 .ops = &(const struct clk_ops) {}, 564 .parent_data = &(const struct clk_parent_data) { 565 .fw_name = "pclk", 566 }, 567 .num_parents = 1, 568 }, 569 }; 570 571 static struct clk_regmap mst_a_mclk_sel = 572 AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL); 573 static struct clk_regmap mst_b_mclk_sel = 574 AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL); 575 static struct clk_regmap mst_c_mclk_sel = 576 AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL); 577 static struct clk_regmap mst_d_mclk_sel = 578 AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL); 579 static struct clk_regmap mst_e_mclk_sel = 580 AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_MCLK_E_CTRL); 581 static struct clk_regmap mst_f_mclk_sel = 582 AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_MCLK_F_CTRL); 583 584 static struct clk_regmap mst_a_mclk_div = 585 AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL); 586 static struct clk_regmap mst_b_mclk_div = 587 AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL); 588 static struct clk_regmap mst_c_mclk_div = 589 AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_MCLK_C_CTRL); 590 static struct clk_regmap mst_d_mclk_div = 591 AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL); 592 static struct clk_regmap mst_e_mclk_div = 593 AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_MCLK_E_CTRL); 594 static struct clk_regmap mst_f_mclk_div = 595 AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_MCLK_F_CTRL); 596 597 static struct clk_regmap mst_a_mclk = 598 AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL); 599 static struct clk_regmap mst_b_mclk = 600 AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_MCLK_B_CTRL); 601 static struct clk_regmap mst_c_mclk = 602 AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_MCLK_C_CTRL); 603 static struct clk_regmap mst_d_mclk = 604 AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_MCLK_D_CTRL); 605 static struct clk_regmap mst_e_mclk = 606 AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_MCLK_E_CTRL); 607 static struct clk_regmap mst_f_mclk = 608 AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_MCLK_F_CTRL); 609 610 /* G12a clocks */ 611 static struct clk_regmap g12a_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL( 612 mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0, mclk_pad_ctrl_parent_data); 613 static struct clk_regmap g12a_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL( 614 mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4, mclk_pad_ctrl_parent_data); 615 static struct clk_regmap g12a_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL( 616 lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16, lrclk_pad_ctrl_parent_data); 617 static struct clk_regmap g12a_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL( 618 lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20, lrclk_pad_ctrl_parent_data); 619 static struct clk_regmap g12a_tdm_lrclk_pad_2 = AUD_TDM_PAD_CTRL( 620 lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24, lrclk_pad_ctrl_parent_data); 621 static struct clk_regmap g12a_tdm_sclk_pad_0 = AUD_TDM_PAD_CTRL( 622 sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0, sclk_pad_ctrl_parent_data); 623 static struct clk_regmap g12a_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL( 624 sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4, sclk_pad_ctrl_parent_data); 625 static struct clk_regmap g12a_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL( 626 sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data); 627 628 static struct clk_regmap g12a_tdmout_a_sclk = 629 AUD_TDM_SCLK_WS(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 630 static struct clk_regmap g12a_tdmout_b_sclk = 631 AUD_TDM_SCLK_WS(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 632 static struct clk_regmap g12a_tdmout_c_sclk = 633 AUD_TDM_SCLK_WS(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 634 635 static struct clk_regmap toram = 636 AUD_PCLK_GATE(toram, AUDIO_CLK_GATE_EN, 20); 637 static struct clk_regmap spdifout_b = 638 AUD_PCLK_GATE(spdifout_b, AUDIO_CLK_GATE_EN, 21); 639 static struct clk_regmap eqdrc = 640 AUD_PCLK_GATE(eqdrc, AUDIO_CLK_GATE_EN, 22); 641 642 /* SM1 Clocks */ 643 static struct clk_regmap sm1_clk81_en = { 644 .data = &(struct clk_regmap_gate_data){ 645 .offset = AUDIO_CLK81_EN, 646 .bit_idx = 31, 647 }, 648 .hw.init = &(struct clk_init_data) { 649 .name = "aud_clk81_en", 650 .ops = &clk_regmap_gate_ops, 651 .parent_data = &(const struct clk_parent_data) { 652 .fw_name = "pclk", 653 }, 654 .num_parents = 1, 655 }, 656 }; 657 658 static struct clk_regmap sm1_sysclk_a_div = { 659 .data = &(struct clk_regmap_div_data){ 660 .offset = AUDIO_CLK81_CTRL, 661 .shift = 0, 662 .width = 8, 663 }, 664 .hw.init = &(struct clk_init_data) { 665 .name = "aud_sysclk_a_div", 666 .ops = &clk_regmap_divider_ops, 667 .parent_hws = (const struct clk_hw *[]) { 668 &sm1_clk81_en.hw, 669 }, 670 .num_parents = 1, 671 .flags = CLK_SET_RATE_PARENT, 672 }, 673 }; 674 675 static struct clk_regmap sm1_sysclk_a_en = { 676 .data = &(struct clk_regmap_gate_data){ 677 .offset = AUDIO_CLK81_CTRL, 678 .bit_idx = 8, 679 }, 680 .hw.init = &(struct clk_init_data) { 681 .name = "aud_sysclk_a_en", 682 .ops = &clk_regmap_gate_ops, 683 .parent_hws = (const struct clk_hw *[]) { 684 &sm1_sysclk_a_div.hw, 685 }, 686 .num_parents = 1, 687 .flags = CLK_SET_RATE_PARENT, 688 }, 689 }; 690 691 static struct clk_regmap sm1_sysclk_b_div = { 692 .data = &(struct clk_regmap_div_data){ 693 .offset = AUDIO_CLK81_CTRL, 694 .shift = 16, 695 .width = 8, 696 }, 697 .hw.init = &(struct clk_init_data) { 698 .name = "aud_sysclk_b_div", 699 .ops = &clk_regmap_divider_ops, 700 .parent_hws = (const struct clk_hw *[]) { 701 &sm1_clk81_en.hw, 702 }, 703 .num_parents = 1, 704 .flags = CLK_SET_RATE_PARENT, 705 }, 706 }; 707 708 static struct clk_regmap sm1_sysclk_b_en = { 709 .data = &(struct clk_regmap_gate_data){ 710 .offset = AUDIO_CLK81_CTRL, 711 .bit_idx = 24, 712 }, 713 .hw.init = &(struct clk_init_data) { 714 .name = "aud_sysclk_b_en", 715 .ops = &clk_regmap_gate_ops, 716 .parent_hws = (const struct clk_hw *[]) { 717 &sm1_sysclk_b_div.hw, 718 }, 719 .num_parents = 1, 720 .flags = CLK_SET_RATE_PARENT, 721 }, 722 }; 723 724 static const struct clk_hw *sm1_aud_top_parents[] = { 725 &sm1_sysclk_a_en.hw, 726 &sm1_sysclk_b_en.hw, 727 }; 728 729 static struct clk_regmap sm1_aud_top = { 730 .data = &(struct clk_regmap_mux_data){ 731 .offset = AUDIO_CLK81_CTRL, 732 .mask = 0x1, 733 .shift = 31, 734 }, 735 .hw.init = &(struct clk_init_data){ 736 .name = "aud_top", 737 .ops = &clk_regmap_mux_ops, 738 .parent_hws = sm1_aud_top_parents, 739 .num_parents = ARRAY_SIZE(sm1_aud_top_parents), 740 .flags = CLK_SET_RATE_NO_REPARENT, 741 }, 742 }; 743 744 static struct clk_regmap resample_b = 745 AUD_PCLK_GATE(resample_b, AUDIO_CLK_GATE_EN, 26); 746 static struct clk_regmap tovad = 747 AUD_PCLK_GATE(tovad, AUDIO_CLK_GATE_EN, 27); 748 static struct clk_regmap locker = 749 AUD_PCLK_GATE(locker, AUDIO_CLK_GATE_EN, 28); 750 static struct clk_regmap spdifin_lb = 751 AUD_PCLK_GATE(spdifin_lb, AUDIO_CLK_GATE_EN, 29); 752 static struct clk_regmap frddr_d = 753 AUD_PCLK_GATE(frddr_d, AUDIO_CLK_GATE_EN1, 0); 754 static struct clk_regmap toddr_d = 755 AUD_PCLK_GATE(toddr_d, AUDIO_CLK_GATE_EN1, 1); 756 static struct clk_regmap loopback_b = 757 AUD_PCLK_GATE(loopback_b, AUDIO_CLK_GATE_EN1, 2); 758 static struct clk_regmap earcrx = 759 AUD_PCLK_GATE(earcrx, AUDIO_CLK_GATE_EN1, 6); 760 761 762 static struct clk_regmap sm1_mst_a_mclk_sel = 763 AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL); 764 static struct clk_regmap sm1_mst_b_mclk_sel = 765 AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL); 766 static struct clk_regmap sm1_mst_c_mclk_sel = 767 AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL); 768 static struct clk_regmap sm1_mst_d_mclk_sel = 769 AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL); 770 static struct clk_regmap sm1_mst_e_mclk_sel = 771 AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL); 772 static struct clk_regmap sm1_mst_f_mclk_sel = 773 AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL); 774 static struct clk_regmap sm1_earcrx_cmdc_clk_sel = 775 AUD_MST_MCLK_MUX(earcrx_cmdc_clk, AUDIO_EARCRX_CMDC_CLK_CTRL); 776 static struct clk_regmap sm1_earcrx_dmac_clk_sel = 777 AUD_MST_MCLK_MUX(earcrx_dmac_clk, AUDIO_EARCRX_DMAC_CLK_CTRL); 778 779 static struct clk_regmap sm1_mst_a_mclk_div = 780 AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL); 781 static struct clk_regmap sm1_mst_b_mclk_div = 782 AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL); 783 static struct clk_regmap sm1_mst_c_mclk_div = 784 AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL); 785 static struct clk_regmap sm1_mst_d_mclk_div = 786 AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL); 787 static struct clk_regmap sm1_mst_e_mclk_div = 788 AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL); 789 static struct clk_regmap sm1_mst_f_mclk_div = 790 AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL); 791 static struct clk_regmap sm1_earcrx_cmdc_clk_div = 792 AUD_MST_MCLK_DIV(earcrx_cmdc_clk, AUDIO_EARCRX_CMDC_CLK_CTRL); 793 static struct clk_regmap sm1_earcrx_dmac_clk_div = 794 AUD_MST_MCLK_DIV(earcrx_dmac_clk, AUDIO_EARCRX_DMAC_CLK_CTRL); 795 796 797 static struct clk_regmap sm1_mst_a_mclk = 798 AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL); 799 static struct clk_regmap sm1_mst_b_mclk = 800 AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL); 801 static struct clk_regmap sm1_mst_c_mclk = 802 AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL); 803 static struct clk_regmap sm1_mst_d_mclk = 804 AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL); 805 static struct clk_regmap sm1_mst_e_mclk = 806 AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL); 807 static struct clk_regmap sm1_mst_f_mclk = 808 AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL); 809 static struct clk_regmap sm1_earcrx_cmdc_clk = 810 AUD_MST_MCLK_GATE(earcrx_cmdc_clk, AUDIO_EARCRX_CMDC_CLK_CTRL); 811 static struct clk_regmap sm1_earcrx_dmac_clk = 812 AUD_MST_MCLK_GATE(earcrx_dmac_clk, AUDIO_EARCRX_DMAC_CLK_CTRL); 813 814 static struct clk_regmap sm1_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL( 815 tdm_mclk_pad_0, AUDIO_SM1_MST_PAD_CTRL0, 0, mclk_pad_ctrl_parent_data); 816 static struct clk_regmap sm1_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL( 817 tdm_mclk_pad_1, AUDIO_SM1_MST_PAD_CTRL0, 4, mclk_pad_ctrl_parent_data); 818 static struct clk_regmap sm1_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL( 819 tdm_lrclk_pad_0, AUDIO_SM1_MST_PAD_CTRL1, 16, lrclk_pad_ctrl_parent_data); 820 static struct clk_regmap sm1_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL( 821 tdm_lrclk_pad_1, AUDIO_SM1_MST_PAD_CTRL1, 20, lrclk_pad_ctrl_parent_data); 822 static struct clk_regmap sm1_tdm_lrclk_pad_2 = AUD_TDM_PAD_CTRL( 823 tdm_lrclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 24, lrclk_pad_ctrl_parent_data); 824 static struct clk_regmap sm1_tdm_sclk_pad_0 = AUD_TDM_PAD_CTRL( 825 tdm_sclk_pad_0, AUDIO_SM1_MST_PAD_CTRL1, 0, sclk_pad_ctrl_parent_data); 826 static struct clk_regmap sm1_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL( 827 tdm_sclk_pad_1, AUDIO_SM1_MST_PAD_CTRL1, 4, sclk_pad_ctrl_parent_data); 828 static struct clk_regmap sm1_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL( 829 tdm_sclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data); 830 831 /* 832 * Array of all clocks provided by this provider 833 * The input clocks of the controller will be populated at runtime 834 */ 835 static struct clk_hw *axg_audio_hw_clks[] = { 836 [AUD_CLKID_DDR_ARB] = &ddr_arb.hw, 837 [AUD_CLKID_PDM] = &pdm.hw, 838 [AUD_CLKID_TDMIN_A] = &tdmin_a.hw, 839 [AUD_CLKID_TDMIN_B] = &tdmin_b.hw, 840 [AUD_CLKID_TDMIN_C] = &tdmin_c.hw, 841 [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw, 842 [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw, 843 [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw, 844 [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw, 845 [AUD_CLKID_FRDDR_A] = &frddr_a.hw, 846 [AUD_CLKID_FRDDR_B] = &frddr_b.hw, 847 [AUD_CLKID_FRDDR_C] = &frddr_c.hw, 848 [AUD_CLKID_TODDR_A] = &toddr_a.hw, 849 [AUD_CLKID_TODDR_B] = &toddr_b.hw, 850 [AUD_CLKID_TODDR_C] = &toddr_c.hw, 851 [AUD_CLKID_LOOPBACK] = &loopback.hw, 852 [AUD_CLKID_SPDIFIN] = &spdifin.hw, 853 [AUD_CLKID_SPDIFOUT] = &spdifout.hw, 854 [AUD_CLKID_RESAMPLE] = &resample.hw, 855 [AUD_CLKID_POWER_DETECT] = &power_detect.hw, 856 [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw, 857 [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw, 858 [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw, 859 [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw, 860 [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw, 861 [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw, 862 [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw, 863 [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw, 864 [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw, 865 [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw, 866 [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw, 867 [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw, 868 [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw, 869 [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw, 870 [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw, 871 [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw, 872 [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw, 873 [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw, 874 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw, 875 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw, 876 [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw, 877 [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw, 878 [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw, 879 [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw, 880 [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw, 881 [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw, 882 [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw, 883 [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw, 884 [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw, 885 [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw, 886 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw, 887 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw, 888 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw, 889 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw, 890 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw, 891 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw, 892 [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw, 893 [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw, 894 [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw, 895 [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw, 896 [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw, 897 [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw, 898 [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw, 899 [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw, 900 [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw, 901 [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw, 902 [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw, 903 [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw, 904 [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw, 905 [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw, 906 [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw, 907 [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw, 908 [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw, 909 [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw, 910 [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw, 911 [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw, 912 [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw, 913 [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw, 914 [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw, 915 [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw, 916 [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw, 917 [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw, 918 [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw, 919 [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw, 920 [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw, 921 [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw, 922 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw, 923 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw, 924 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw, 925 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw, 926 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw, 927 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw, 928 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw, 929 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw, 930 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw, 931 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw, 932 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw, 933 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw, 934 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw, 935 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw, 936 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw, 937 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw, 938 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw, 939 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw, 940 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw, 941 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw, 942 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw, 943 [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw, 944 [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw, 945 [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw, 946 [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw, 947 [AUD_CLKID_TDMOUT_A_SCLK] = &axg_tdmout_a_sclk.hw, 948 [AUD_CLKID_TDMOUT_B_SCLK] = &axg_tdmout_b_sclk.hw, 949 [AUD_CLKID_TDMOUT_C_SCLK] = &axg_tdmout_c_sclk.hw, 950 [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw, 951 [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw, 952 [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw, 953 [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw, 954 [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw, 955 [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw, 956 [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw, 957 [AUD_CLKID_TOP] = &axg_aud_top, 958 }; 959 960 /* 961 * Array of all G12A clocks provided by this provider 962 * The input clocks of the controller will be populated at runtime 963 */ 964 static struct clk_hw *g12a_audio_hw_clks[] = { 965 [AUD_CLKID_DDR_ARB] = &ddr_arb.hw, 966 [AUD_CLKID_PDM] = &pdm.hw, 967 [AUD_CLKID_TDMIN_A] = &tdmin_a.hw, 968 [AUD_CLKID_TDMIN_B] = &tdmin_b.hw, 969 [AUD_CLKID_TDMIN_C] = &tdmin_c.hw, 970 [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw, 971 [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw, 972 [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw, 973 [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw, 974 [AUD_CLKID_FRDDR_A] = &frddr_a.hw, 975 [AUD_CLKID_FRDDR_B] = &frddr_b.hw, 976 [AUD_CLKID_FRDDR_C] = &frddr_c.hw, 977 [AUD_CLKID_TODDR_A] = &toddr_a.hw, 978 [AUD_CLKID_TODDR_B] = &toddr_b.hw, 979 [AUD_CLKID_TODDR_C] = &toddr_c.hw, 980 [AUD_CLKID_LOOPBACK] = &loopback.hw, 981 [AUD_CLKID_SPDIFIN] = &spdifin.hw, 982 [AUD_CLKID_SPDIFOUT] = &spdifout.hw, 983 [AUD_CLKID_RESAMPLE] = &resample.hw, 984 [AUD_CLKID_POWER_DETECT] = &power_detect.hw, 985 [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw, 986 [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw, 987 [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw, 988 [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw, 989 [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw, 990 [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw, 991 [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw, 992 [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw, 993 [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw, 994 [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw, 995 [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw, 996 [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw, 997 [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw, 998 [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw, 999 [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw, 1000 [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw, 1001 [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw, 1002 [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw, 1003 [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw, 1004 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw, 1005 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw, 1006 [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw, 1007 [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw, 1008 [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw, 1009 [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw, 1010 [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw, 1011 [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw, 1012 [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw, 1013 [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw, 1014 [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw, 1015 [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw, 1016 [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw, 1017 [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw, 1018 [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw, 1019 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw, 1020 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw, 1021 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw, 1022 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw, 1023 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw, 1024 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw, 1025 [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw, 1026 [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw, 1027 [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw, 1028 [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw, 1029 [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw, 1030 [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw, 1031 [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw, 1032 [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw, 1033 [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw, 1034 [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw, 1035 [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw, 1036 [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw, 1037 [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw, 1038 [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw, 1039 [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw, 1040 [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw, 1041 [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw, 1042 [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw, 1043 [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw, 1044 [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw, 1045 [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw, 1046 [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw, 1047 [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw, 1048 [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw, 1049 [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw, 1050 [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw, 1051 [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw, 1052 [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw, 1053 [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw, 1054 [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw, 1055 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw, 1056 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw, 1057 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw, 1058 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw, 1059 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw, 1060 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw, 1061 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw, 1062 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw, 1063 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw, 1064 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw, 1065 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw, 1066 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw, 1067 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw, 1068 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw, 1069 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw, 1070 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw, 1071 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw, 1072 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw, 1073 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw, 1074 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw, 1075 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw, 1076 [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw, 1077 [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw, 1078 [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw, 1079 [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw, 1080 [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw, 1081 [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw, 1082 [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw, 1083 [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw, 1084 [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw, 1085 [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw, 1086 [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw, 1087 [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw, 1088 [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw, 1089 [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw, 1090 [AUD_CLKID_TDM_MCLK_PAD0] = &g12a_tdm_mclk_pad_0.hw, 1091 [AUD_CLKID_TDM_MCLK_PAD1] = &g12a_tdm_mclk_pad_1.hw, 1092 [AUD_CLKID_TDM_LRCLK_PAD0] = &g12a_tdm_lrclk_pad_0.hw, 1093 [AUD_CLKID_TDM_LRCLK_PAD1] = &g12a_tdm_lrclk_pad_1.hw, 1094 [AUD_CLKID_TDM_LRCLK_PAD2] = &g12a_tdm_lrclk_pad_2.hw, 1095 [AUD_CLKID_TDM_SCLK_PAD0] = &g12a_tdm_sclk_pad_0.hw, 1096 [AUD_CLKID_TDM_SCLK_PAD1] = &g12a_tdm_sclk_pad_1.hw, 1097 [AUD_CLKID_TDM_SCLK_PAD2] = &g12a_tdm_sclk_pad_2.hw, 1098 [AUD_CLKID_TOP] = &axg_aud_top, 1099 }; 1100 1101 /* 1102 * Array of all SM1 clocks provided by this provider 1103 * The input clocks of the controller will be populated at runtime 1104 */ 1105 static struct clk_hw *sm1_audio_hw_clks[] = { 1106 [AUD_CLKID_DDR_ARB] = &ddr_arb.hw, 1107 [AUD_CLKID_PDM] = &pdm.hw, 1108 [AUD_CLKID_TDMIN_A] = &tdmin_a.hw, 1109 [AUD_CLKID_TDMIN_B] = &tdmin_b.hw, 1110 [AUD_CLKID_TDMIN_C] = &tdmin_c.hw, 1111 [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw, 1112 [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw, 1113 [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw, 1114 [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw, 1115 [AUD_CLKID_FRDDR_A] = &frddr_a.hw, 1116 [AUD_CLKID_FRDDR_B] = &frddr_b.hw, 1117 [AUD_CLKID_FRDDR_C] = &frddr_c.hw, 1118 [AUD_CLKID_TODDR_A] = &toddr_a.hw, 1119 [AUD_CLKID_TODDR_B] = &toddr_b.hw, 1120 [AUD_CLKID_TODDR_C] = &toddr_c.hw, 1121 [AUD_CLKID_LOOPBACK] = &loopback.hw, 1122 [AUD_CLKID_SPDIFIN] = &spdifin.hw, 1123 [AUD_CLKID_SPDIFOUT] = &spdifout.hw, 1124 [AUD_CLKID_RESAMPLE] = &resample.hw, 1125 [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw, 1126 [AUD_CLKID_MST_A_MCLK_SEL] = &sm1_mst_a_mclk_sel.hw, 1127 [AUD_CLKID_MST_B_MCLK_SEL] = &sm1_mst_b_mclk_sel.hw, 1128 [AUD_CLKID_MST_C_MCLK_SEL] = &sm1_mst_c_mclk_sel.hw, 1129 [AUD_CLKID_MST_D_MCLK_SEL] = &sm1_mst_d_mclk_sel.hw, 1130 [AUD_CLKID_MST_E_MCLK_SEL] = &sm1_mst_e_mclk_sel.hw, 1131 [AUD_CLKID_MST_F_MCLK_SEL] = &sm1_mst_f_mclk_sel.hw, 1132 [AUD_CLKID_MST_A_MCLK_DIV] = &sm1_mst_a_mclk_div.hw, 1133 [AUD_CLKID_MST_B_MCLK_DIV] = &sm1_mst_b_mclk_div.hw, 1134 [AUD_CLKID_MST_C_MCLK_DIV] = &sm1_mst_c_mclk_div.hw, 1135 [AUD_CLKID_MST_D_MCLK_DIV] = &sm1_mst_d_mclk_div.hw, 1136 [AUD_CLKID_MST_E_MCLK_DIV] = &sm1_mst_e_mclk_div.hw, 1137 [AUD_CLKID_MST_F_MCLK_DIV] = &sm1_mst_f_mclk_div.hw, 1138 [AUD_CLKID_MST_A_MCLK] = &sm1_mst_a_mclk.hw, 1139 [AUD_CLKID_MST_B_MCLK] = &sm1_mst_b_mclk.hw, 1140 [AUD_CLKID_MST_C_MCLK] = &sm1_mst_c_mclk.hw, 1141 [AUD_CLKID_MST_D_MCLK] = &sm1_mst_d_mclk.hw, 1142 [AUD_CLKID_MST_E_MCLK] = &sm1_mst_e_mclk.hw, 1143 [AUD_CLKID_MST_F_MCLK] = &sm1_mst_f_mclk.hw, 1144 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw, 1145 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw, 1146 [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw, 1147 [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw, 1148 [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw, 1149 [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw, 1150 [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw, 1151 [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw, 1152 [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw, 1153 [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw, 1154 [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw, 1155 [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw, 1156 [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw, 1157 [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw, 1158 [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw, 1159 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw, 1160 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw, 1161 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw, 1162 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw, 1163 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw, 1164 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw, 1165 [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw, 1166 [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw, 1167 [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw, 1168 [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw, 1169 [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw, 1170 [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw, 1171 [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw, 1172 [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw, 1173 [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw, 1174 [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw, 1175 [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw, 1176 [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw, 1177 [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw, 1178 [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw, 1179 [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw, 1180 [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw, 1181 [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw, 1182 [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw, 1183 [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw, 1184 [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw, 1185 [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw, 1186 [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw, 1187 [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw, 1188 [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw, 1189 [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw, 1190 [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw, 1191 [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw, 1192 [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw, 1193 [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw, 1194 [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw, 1195 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw, 1196 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw, 1197 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw, 1198 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw, 1199 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw, 1200 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw, 1201 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw, 1202 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw, 1203 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw, 1204 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw, 1205 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw, 1206 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw, 1207 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw, 1208 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw, 1209 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw, 1210 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw, 1211 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw, 1212 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw, 1213 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw, 1214 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw, 1215 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw, 1216 [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw, 1217 [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw, 1218 [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw, 1219 [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw, 1220 [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw, 1221 [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw, 1222 [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw, 1223 [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw, 1224 [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw, 1225 [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw, 1226 [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw, 1227 [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw, 1228 [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw, 1229 [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw, 1230 [AUD_CLKID_TDM_MCLK_PAD0] = &sm1_tdm_mclk_pad_0.hw, 1231 [AUD_CLKID_TDM_MCLK_PAD1] = &sm1_tdm_mclk_pad_1.hw, 1232 [AUD_CLKID_TDM_LRCLK_PAD0] = &sm1_tdm_lrclk_pad_0.hw, 1233 [AUD_CLKID_TDM_LRCLK_PAD1] = &sm1_tdm_lrclk_pad_1.hw, 1234 [AUD_CLKID_TDM_LRCLK_PAD2] = &sm1_tdm_lrclk_pad_2.hw, 1235 [AUD_CLKID_TDM_SCLK_PAD0] = &sm1_tdm_sclk_pad_0.hw, 1236 [AUD_CLKID_TDM_SCLK_PAD1] = &sm1_tdm_sclk_pad_1.hw, 1237 [AUD_CLKID_TDM_SCLK_PAD2] = &sm1_tdm_sclk_pad_2.hw, 1238 [AUD_CLKID_TOP] = &sm1_aud_top.hw, 1239 [AUD_CLKID_TORAM] = &toram.hw, 1240 [AUD_CLKID_EQDRC] = &eqdrc.hw, 1241 [AUD_CLKID_RESAMPLE_B] = &resample_b.hw, 1242 [AUD_CLKID_TOVAD] = &tovad.hw, 1243 [AUD_CLKID_LOCKER] = &locker.hw, 1244 [AUD_CLKID_SPDIFIN_LB] = &spdifin_lb.hw, 1245 [AUD_CLKID_FRDDR_D] = &frddr_d.hw, 1246 [AUD_CLKID_TODDR_D] = &toddr_d.hw, 1247 [AUD_CLKID_LOOPBACK_B] = &loopback_b.hw, 1248 [AUD_CLKID_CLK81_EN] = &sm1_clk81_en.hw, 1249 [AUD_CLKID_SYSCLK_A_DIV] = &sm1_sysclk_a_div.hw, 1250 [AUD_CLKID_SYSCLK_A_EN] = &sm1_sysclk_a_en.hw, 1251 [AUD_CLKID_SYSCLK_B_DIV] = &sm1_sysclk_b_div.hw, 1252 [AUD_CLKID_SYSCLK_B_EN] = &sm1_sysclk_b_en.hw, 1253 [AUD_CLKID_EARCRX] = &earcrx.hw, 1254 [AUD_CLKID_EARCRX_CMDC_SEL] = &sm1_earcrx_cmdc_clk_sel.hw, 1255 [AUD_CLKID_EARCRX_CMDC_DIV] = &sm1_earcrx_cmdc_clk_div.hw, 1256 [AUD_CLKID_EARCRX_CMDC] = &sm1_earcrx_cmdc_clk.hw, 1257 [AUD_CLKID_EARCRX_DMAC_SEL] = &sm1_earcrx_dmac_clk_sel.hw, 1258 [AUD_CLKID_EARCRX_DMAC_DIV] = &sm1_earcrx_dmac_clk_div.hw, 1259 [AUD_CLKID_EARCRX_DMAC] = &sm1_earcrx_dmac_clk.hw, 1260 }; 1261 1262 1263 /* Convenience table to populate regmap in .probe(). */ 1264 static struct clk_regmap *const axg_clk_regmaps[] = { 1265 &ddr_arb, 1266 &pdm, 1267 &tdmin_a, 1268 &tdmin_b, 1269 &tdmin_c, 1270 &tdmin_lb, 1271 &tdmout_a, 1272 &tdmout_b, 1273 &tdmout_c, 1274 &frddr_a, 1275 &frddr_b, 1276 &frddr_c, 1277 &toddr_a, 1278 &toddr_b, 1279 &toddr_c, 1280 &loopback, 1281 &spdifin, 1282 &spdifout, 1283 &resample, 1284 &power_detect, 1285 &mst_a_mclk_sel, 1286 &mst_b_mclk_sel, 1287 &mst_c_mclk_sel, 1288 &mst_d_mclk_sel, 1289 &mst_e_mclk_sel, 1290 &mst_f_mclk_sel, 1291 &mst_a_mclk_div, 1292 &mst_b_mclk_div, 1293 &mst_c_mclk_div, 1294 &mst_d_mclk_div, 1295 &mst_e_mclk_div, 1296 &mst_f_mclk_div, 1297 &mst_a_mclk, 1298 &mst_b_mclk, 1299 &mst_c_mclk, 1300 &mst_d_mclk, 1301 &mst_e_mclk, 1302 &mst_f_mclk, 1303 &spdifout_clk_sel, 1304 &spdifout_clk_div, 1305 &spdifout_clk, 1306 &spdifin_clk_sel, 1307 &spdifin_clk_div, 1308 &spdifin_clk, 1309 &pdm_dclk_sel, 1310 &pdm_dclk_div, 1311 &pdm_dclk, 1312 &pdm_sysclk_sel, 1313 &pdm_sysclk_div, 1314 &pdm_sysclk, 1315 &mst_a_sclk_pre_en, 1316 &mst_b_sclk_pre_en, 1317 &mst_c_sclk_pre_en, 1318 &mst_d_sclk_pre_en, 1319 &mst_e_sclk_pre_en, 1320 &mst_f_sclk_pre_en, 1321 &mst_a_sclk_div, 1322 &mst_b_sclk_div, 1323 &mst_c_sclk_div, 1324 &mst_d_sclk_div, 1325 &mst_e_sclk_div, 1326 &mst_f_sclk_div, 1327 &mst_a_sclk_post_en, 1328 &mst_b_sclk_post_en, 1329 &mst_c_sclk_post_en, 1330 &mst_d_sclk_post_en, 1331 &mst_e_sclk_post_en, 1332 &mst_f_sclk_post_en, 1333 &mst_a_sclk, 1334 &mst_b_sclk, 1335 &mst_c_sclk, 1336 &mst_d_sclk, 1337 &mst_e_sclk, 1338 &mst_f_sclk, 1339 &mst_a_lrclk_div, 1340 &mst_b_lrclk_div, 1341 &mst_c_lrclk_div, 1342 &mst_d_lrclk_div, 1343 &mst_e_lrclk_div, 1344 &mst_f_lrclk_div, 1345 &mst_a_lrclk, 1346 &mst_b_lrclk, 1347 &mst_c_lrclk, 1348 &mst_d_lrclk, 1349 &mst_e_lrclk, 1350 &mst_f_lrclk, 1351 &tdmin_a_sclk_sel, 1352 &tdmin_b_sclk_sel, 1353 &tdmin_c_sclk_sel, 1354 &tdmin_lb_sclk_sel, 1355 &tdmout_a_sclk_sel, 1356 &tdmout_b_sclk_sel, 1357 &tdmout_c_sclk_sel, 1358 &tdmin_a_sclk_pre_en, 1359 &tdmin_b_sclk_pre_en, 1360 &tdmin_c_sclk_pre_en, 1361 &tdmin_lb_sclk_pre_en, 1362 &tdmout_a_sclk_pre_en, 1363 &tdmout_b_sclk_pre_en, 1364 &tdmout_c_sclk_pre_en, 1365 &tdmin_a_sclk_post_en, 1366 &tdmin_b_sclk_post_en, 1367 &tdmin_c_sclk_post_en, 1368 &tdmin_lb_sclk_post_en, 1369 &tdmout_a_sclk_post_en, 1370 &tdmout_b_sclk_post_en, 1371 &tdmout_c_sclk_post_en, 1372 &tdmin_a_sclk, 1373 &tdmin_b_sclk, 1374 &tdmin_c_sclk, 1375 &tdmin_lb_sclk, 1376 &axg_tdmout_a_sclk, 1377 &axg_tdmout_b_sclk, 1378 &axg_tdmout_c_sclk, 1379 &tdmin_a_lrclk, 1380 &tdmin_b_lrclk, 1381 &tdmin_c_lrclk, 1382 &tdmin_lb_lrclk, 1383 &tdmout_a_lrclk, 1384 &tdmout_b_lrclk, 1385 &tdmout_c_lrclk, 1386 }; 1387 1388 static struct clk_regmap *const g12a_clk_regmaps[] = { 1389 &ddr_arb, 1390 &pdm, 1391 &tdmin_a, 1392 &tdmin_b, 1393 &tdmin_c, 1394 &tdmin_lb, 1395 &tdmout_a, 1396 &tdmout_b, 1397 &tdmout_c, 1398 &frddr_a, 1399 &frddr_b, 1400 &frddr_c, 1401 &toddr_a, 1402 &toddr_b, 1403 &toddr_c, 1404 &loopback, 1405 &spdifin, 1406 &spdifout, 1407 &resample, 1408 &power_detect, 1409 &spdifout_b, 1410 &mst_a_mclk_sel, 1411 &mst_b_mclk_sel, 1412 &mst_c_mclk_sel, 1413 &mst_d_mclk_sel, 1414 &mst_e_mclk_sel, 1415 &mst_f_mclk_sel, 1416 &mst_a_mclk_div, 1417 &mst_b_mclk_div, 1418 &mst_c_mclk_div, 1419 &mst_d_mclk_div, 1420 &mst_e_mclk_div, 1421 &mst_f_mclk_div, 1422 &mst_a_mclk, 1423 &mst_b_mclk, 1424 &mst_c_mclk, 1425 &mst_d_mclk, 1426 &mst_e_mclk, 1427 &mst_f_mclk, 1428 &spdifout_clk_sel, 1429 &spdifout_clk_div, 1430 &spdifout_clk, 1431 &spdifin_clk_sel, 1432 &spdifin_clk_div, 1433 &spdifin_clk, 1434 &pdm_dclk_sel, 1435 &pdm_dclk_div, 1436 &pdm_dclk, 1437 &pdm_sysclk_sel, 1438 &pdm_sysclk_div, 1439 &pdm_sysclk, 1440 &mst_a_sclk_pre_en, 1441 &mst_b_sclk_pre_en, 1442 &mst_c_sclk_pre_en, 1443 &mst_d_sclk_pre_en, 1444 &mst_e_sclk_pre_en, 1445 &mst_f_sclk_pre_en, 1446 &mst_a_sclk_div, 1447 &mst_b_sclk_div, 1448 &mst_c_sclk_div, 1449 &mst_d_sclk_div, 1450 &mst_e_sclk_div, 1451 &mst_f_sclk_div, 1452 &mst_a_sclk_post_en, 1453 &mst_b_sclk_post_en, 1454 &mst_c_sclk_post_en, 1455 &mst_d_sclk_post_en, 1456 &mst_e_sclk_post_en, 1457 &mst_f_sclk_post_en, 1458 &mst_a_sclk, 1459 &mst_b_sclk, 1460 &mst_c_sclk, 1461 &mst_d_sclk, 1462 &mst_e_sclk, 1463 &mst_f_sclk, 1464 &mst_a_lrclk_div, 1465 &mst_b_lrclk_div, 1466 &mst_c_lrclk_div, 1467 &mst_d_lrclk_div, 1468 &mst_e_lrclk_div, 1469 &mst_f_lrclk_div, 1470 &mst_a_lrclk, 1471 &mst_b_lrclk, 1472 &mst_c_lrclk, 1473 &mst_d_lrclk, 1474 &mst_e_lrclk, 1475 &mst_f_lrclk, 1476 &tdmin_a_sclk_sel, 1477 &tdmin_b_sclk_sel, 1478 &tdmin_c_sclk_sel, 1479 &tdmin_lb_sclk_sel, 1480 &tdmout_a_sclk_sel, 1481 &tdmout_b_sclk_sel, 1482 &tdmout_c_sclk_sel, 1483 &tdmin_a_sclk_pre_en, 1484 &tdmin_b_sclk_pre_en, 1485 &tdmin_c_sclk_pre_en, 1486 &tdmin_lb_sclk_pre_en, 1487 &tdmout_a_sclk_pre_en, 1488 &tdmout_b_sclk_pre_en, 1489 &tdmout_c_sclk_pre_en, 1490 &tdmin_a_sclk_post_en, 1491 &tdmin_b_sclk_post_en, 1492 &tdmin_c_sclk_post_en, 1493 &tdmin_lb_sclk_post_en, 1494 &tdmout_a_sclk_post_en, 1495 &tdmout_b_sclk_post_en, 1496 &tdmout_c_sclk_post_en, 1497 &tdmin_a_sclk, 1498 &tdmin_b_sclk, 1499 &tdmin_c_sclk, 1500 &tdmin_lb_sclk, 1501 &g12a_tdmout_a_sclk, 1502 &g12a_tdmout_b_sclk, 1503 &g12a_tdmout_c_sclk, 1504 &tdmin_a_lrclk, 1505 &tdmin_b_lrclk, 1506 &tdmin_c_lrclk, 1507 &tdmin_lb_lrclk, 1508 &tdmout_a_lrclk, 1509 &tdmout_b_lrclk, 1510 &tdmout_c_lrclk, 1511 &spdifout_b_clk_sel, 1512 &spdifout_b_clk_div, 1513 &spdifout_b_clk, 1514 &g12a_tdm_mclk_pad_0, 1515 &g12a_tdm_mclk_pad_1, 1516 &g12a_tdm_lrclk_pad_0, 1517 &g12a_tdm_lrclk_pad_1, 1518 &g12a_tdm_lrclk_pad_2, 1519 &g12a_tdm_sclk_pad_0, 1520 &g12a_tdm_sclk_pad_1, 1521 &g12a_tdm_sclk_pad_2, 1522 &toram, 1523 &eqdrc, 1524 }; 1525 1526 static struct clk_regmap *const sm1_clk_regmaps[] = { 1527 &ddr_arb, 1528 &pdm, 1529 &tdmin_a, 1530 &tdmin_b, 1531 &tdmin_c, 1532 &tdmin_lb, 1533 &tdmout_a, 1534 &tdmout_b, 1535 &tdmout_c, 1536 &frddr_a, 1537 &frddr_b, 1538 &frddr_c, 1539 &toddr_a, 1540 &toddr_b, 1541 &toddr_c, 1542 &loopback, 1543 &spdifin, 1544 &spdifout, 1545 &resample, 1546 &spdifout_b, 1547 &sm1_mst_a_mclk_sel, 1548 &sm1_mst_b_mclk_sel, 1549 &sm1_mst_c_mclk_sel, 1550 &sm1_mst_d_mclk_sel, 1551 &sm1_mst_e_mclk_sel, 1552 &sm1_mst_f_mclk_sel, 1553 &sm1_mst_a_mclk_div, 1554 &sm1_mst_b_mclk_div, 1555 &sm1_mst_c_mclk_div, 1556 &sm1_mst_d_mclk_div, 1557 &sm1_mst_e_mclk_div, 1558 &sm1_mst_f_mclk_div, 1559 &sm1_mst_a_mclk, 1560 &sm1_mst_b_mclk, 1561 &sm1_mst_c_mclk, 1562 &sm1_mst_d_mclk, 1563 &sm1_mst_e_mclk, 1564 &sm1_mst_f_mclk, 1565 &spdifout_clk_sel, 1566 &spdifout_clk_div, 1567 &spdifout_clk, 1568 &spdifin_clk_sel, 1569 &spdifin_clk_div, 1570 &spdifin_clk, 1571 &pdm_dclk_sel, 1572 &pdm_dclk_div, 1573 &pdm_dclk, 1574 &pdm_sysclk_sel, 1575 &pdm_sysclk_div, 1576 &pdm_sysclk, 1577 &mst_a_sclk_pre_en, 1578 &mst_b_sclk_pre_en, 1579 &mst_c_sclk_pre_en, 1580 &mst_d_sclk_pre_en, 1581 &mst_e_sclk_pre_en, 1582 &mst_f_sclk_pre_en, 1583 &mst_a_sclk_div, 1584 &mst_b_sclk_div, 1585 &mst_c_sclk_div, 1586 &mst_d_sclk_div, 1587 &mst_e_sclk_div, 1588 &mst_f_sclk_div, 1589 &mst_a_sclk_post_en, 1590 &mst_b_sclk_post_en, 1591 &mst_c_sclk_post_en, 1592 &mst_d_sclk_post_en, 1593 &mst_e_sclk_post_en, 1594 &mst_f_sclk_post_en, 1595 &mst_a_sclk, 1596 &mst_b_sclk, 1597 &mst_c_sclk, 1598 &mst_d_sclk, 1599 &mst_e_sclk, 1600 &mst_f_sclk, 1601 &mst_a_lrclk_div, 1602 &mst_b_lrclk_div, 1603 &mst_c_lrclk_div, 1604 &mst_d_lrclk_div, 1605 &mst_e_lrclk_div, 1606 &mst_f_lrclk_div, 1607 &mst_a_lrclk, 1608 &mst_b_lrclk, 1609 &mst_c_lrclk, 1610 &mst_d_lrclk, 1611 &mst_e_lrclk, 1612 &mst_f_lrclk, 1613 &tdmin_a_sclk_sel, 1614 &tdmin_b_sclk_sel, 1615 &tdmin_c_sclk_sel, 1616 &tdmin_lb_sclk_sel, 1617 &tdmout_a_sclk_sel, 1618 &tdmout_b_sclk_sel, 1619 &tdmout_c_sclk_sel, 1620 &tdmin_a_sclk_pre_en, 1621 &tdmin_b_sclk_pre_en, 1622 &tdmin_c_sclk_pre_en, 1623 &tdmin_lb_sclk_pre_en, 1624 &tdmout_a_sclk_pre_en, 1625 &tdmout_b_sclk_pre_en, 1626 &tdmout_c_sclk_pre_en, 1627 &tdmin_a_sclk_post_en, 1628 &tdmin_b_sclk_post_en, 1629 &tdmin_c_sclk_post_en, 1630 &tdmin_lb_sclk_post_en, 1631 &tdmout_a_sclk_post_en, 1632 &tdmout_b_sclk_post_en, 1633 &tdmout_c_sclk_post_en, 1634 &tdmin_a_sclk, 1635 &tdmin_b_sclk, 1636 &tdmin_c_sclk, 1637 &tdmin_lb_sclk, 1638 &g12a_tdmout_a_sclk, 1639 &g12a_tdmout_b_sclk, 1640 &g12a_tdmout_c_sclk, 1641 &tdmin_a_lrclk, 1642 &tdmin_b_lrclk, 1643 &tdmin_c_lrclk, 1644 &tdmin_lb_lrclk, 1645 &tdmout_a_lrclk, 1646 &tdmout_b_lrclk, 1647 &tdmout_c_lrclk, 1648 &spdifout_b_clk_sel, 1649 &spdifout_b_clk_div, 1650 &spdifout_b_clk, 1651 &sm1_tdm_mclk_pad_0, 1652 &sm1_tdm_mclk_pad_1, 1653 &sm1_tdm_lrclk_pad_0, 1654 &sm1_tdm_lrclk_pad_1, 1655 &sm1_tdm_lrclk_pad_2, 1656 &sm1_tdm_sclk_pad_0, 1657 &sm1_tdm_sclk_pad_1, 1658 &sm1_tdm_sclk_pad_2, 1659 &sm1_aud_top, 1660 &toram, 1661 &eqdrc, 1662 &resample_b, 1663 &tovad, 1664 &locker, 1665 &spdifin_lb, 1666 &frddr_d, 1667 &toddr_d, 1668 &loopback_b, 1669 &sm1_clk81_en, 1670 &sm1_sysclk_a_div, 1671 &sm1_sysclk_a_en, 1672 &sm1_sysclk_b_div, 1673 &sm1_sysclk_b_en, 1674 &earcrx, 1675 &sm1_earcrx_cmdc_clk_sel, 1676 &sm1_earcrx_cmdc_clk_div, 1677 &sm1_earcrx_cmdc_clk, 1678 &sm1_earcrx_dmac_clk_sel, 1679 &sm1_earcrx_dmac_clk_div, 1680 &sm1_earcrx_dmac_clk, 1681 }; 1682 1683 static struct regmap_config axg_audio_regmap_cfg = { 1684 .reg_bits = 32, 1685 .val_bits = 32, 1686 .reg_stride = 4, 1687 }; 1688 1689 struct audioclk_data { 1690 struct clk_regmap *const *regmap_clks; 1691 unsigned int regmap_clk_num; 1692 struct meson_clk_hw_data hw_clks; 1693 unsigned int max_register; 1694 const char *rst_drvname; 1695 }; 1696 1697 static int axg_audio_clkc_probe(struct platform_device *pdev) 1698 { 1699 struct device *dev = &pdev->dev; 1700 const struct audioclk_data *data; 1701 struct regmap *map; 1702 void __iomem *regs; 1703 struct clk_hw *hw; 1704 struct clk *clk; 1705 int ret, i; 1706 1707 data = of_device_get_match_data(dev); 1708 if (!data) 1709 return -EINVAL; 1710 1711 regs = devm_platform_ioremap_resource(pdev, 0); 1712 if (IS_ERR(regs)) 1713 return PTR_ERR(regs); 1714 1715 axg_audio_regmap_cfg.max_register = data->max_register; 1716 map = devm_regmap_init_mmio(dev, regs, &axg_audio_regmap_cfg); 1717 if (IS_ERR(map)) { 1718 dev_err(dev, "failed to init regmap: %ld\n", PTR_ERR(map)); 1719 return PTR_ERR(map); 1720 } 1721 1722 /* Get the mandatory peripheral clock */ 1723 clk = devm_clk_get_enabled(dev, "pclk"); 1724 if (IS_ERR(clk)) 1725 return PTR_ERR(clk); 1726 1727 ret = device_reset(dev); 1728 if (ret) { 1729 dev_err_probe(dev, ret, "failed to reset device\n"); 1730 return ret; 1731 } 1732 1733 /* Populate regmap for the regmap backed clocks */ 1734 for (i = 0; i < data->regmap_clk_num; i++) 1735 data->regmap_clks[i]->map = map; 1736 1737 /* Take care to skip the registered input clocks */ 1738 for (i = AUD_CLKID_DDR_ARB; i < data->hw_clks.num; i++) { 1739 const char *name; 1740 1741 hw = data->hw_clks.hws[i]; 1742 /* array might be sparse */ 1743 if (!hw) 1744 continue; 1745 1746 name = hw->init->name; 1747 1748 ret = devm_clk_hw_register(dev, hw); 1749 if (ret) { 1750 dev_err(dev, "failed to register clock %s\n", name); 1751 return ret; 1752 } 1753 } 1754 1755 ret = devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks); 1756 if (ret) 1757 return ret; 1758 1759 /* Register auxiliary reset driver when applicable */ 1760 if (data->rst_drvname) 1761 ret = devm_meson_rst_aux_register(dev, map, data->rst_drvname); 1762 1763 return ret; 1764 } 1765 1766 static const struct audioclk_data axg_audioclk_data = { 1767 .regmap_clks = axg_clk_regmaps, 1768 .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps), 1769 .hw_clks = { 1770 .hws = axg_audio_hw_clks, 1771 .num = ARRAY_SIZE(axg_audio_hw_clks), 1772 }, 1773 .max_register = AUDIO_CLK_PDMIN_CTRL1, 1774 }; 1775 1776 static const struct audioclk_data g12a_audioclk_data = { 1777 .regmap_clks = g12a_clk_regmaps, 1778 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps), 1779 .hw_clks = { 1780 .hws = g12a_audio_hw_clks, 1781 .num = ARRAY_SIZE(g12a_audio_hw_clks), 1782 }, 1783 .max_register = AUDIO_CLK_SPDIFOUT_B_CTRL, 1784 .rst_drvname = "rst-g12a", 1785 }; 1786 1787 static const struct audioclk_data sm1_audioclk_data = { 1788 .regmap_clks = sm1_clk_regmaps, 1789 .regmap_clk_num = ARRAY_SIZE(sm1_clk_regmaps), 1790 .hw_clks = { 1791 .hws = sm1_audio_hw_clks, 1792 .num = ARRAY_SIZE(sm1_audio_hw_clks), 1793 }, 1794 .max_register = AUDIO_EARCRX_DMAC_CLK_CTRL, 1795 .rst_drvname = "rst-sm1", 1796 }; 1797 1798 static const struct of_device_id clkc_match_table[] = { 1799 { 1800 .compatible = "amlogic,axg-audio-clkc", 1801 .data = &axg_audioclk_data 1802 }, { 1803 .compatible = "amlogic,g12a-audio-clkc", 1804 .data = &g12a_audioclk_data 1805 }, { 1806 .compatible = "amlogic,sm1-audio-clkc", 1807 .data = &sm1_audioclk_data 1808 }, {} 1809 }; 1810 MODULE_DEVICE_TABLE(of, clkc_match_table); 1811 1812 static struct platform_driver axg_audio_driver = { 1813 .probe = axg_audio_clkc_probe, 1814 .driver = { 1815 .name = "axg-audio-clkc", 1816 .of_match_table = clkc_match_table, 1817 }, 1818 }; 1819 module_platform_driver(axg_audio_driver); 1820 1821 MODULE_DESCRIPTION("Amlogic AXG/G12A/SM1 Audio Clock driver"); 1822 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>"); 1823 MODULE_LICENSE("GPL"); 1824 MODULE_IMPORT_NS(CLK_MESON); 1825