xref: /linux/drivers/clk/meson/axg-audio.c (revision 4b132aacb0768ac1e652cf517097ea6f237214b9)
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3  * Copyright (c) 2018 BayLibre, SAS.
4  * Author: Jerome Brunet <jbrunet@baylibre.com>
5  */
6 
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/init.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 #include <linux/reset.h>
15 #include <linux/reset-controller.h>
16 #include <linux/slab.h>
17 
18 #include "meson-clkc-utils.h"
19 #include "axg-audio.h"
20 #include "clk-regmap.h"
21 #include "clk-phase.h"
22 #include "sclk-div.h"
23 
24 #include <dt-bindings/clock/axg-audio-clkc.h>
25 
26 #define AUD_GATE(_name, _reg, _bit, _pname, _iflags) {			\
27 	.data = &(struct clk_regmap_gate_data){				\
28 		.offset = (_reg),					\
29 		.bit_idx = (_bit),					\
30 	},								\
31 	.hw.init = &(struct clk_init_data) {				\
32 		.name = "aud_"#_name,					\
33 		.ops = &clk_regmap_gate_ops,				\
34 		.parent_names = (const char *[]){ #_pname },		\
35 		.num_parents = 1,					\
36 		.flags = CLK_DUTY_CYCLE_PARENT | (_iflags),		\
37 	},								\
38 }
39 
40 #define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) {	\
41 	.data = &(struct clk_regmap_mux_data){				\
42 		.offset = (_reg),					\
43 		.mask = (_mask),					\
44 		.shift = (_shift),					\
45 		.flags = (_dflags),					\
46 	},								\
47 	.hw.init = &(struct clk_init_data){				\
48 		.name = "aud_"#_name,					\
49 		.ops = &clk_regmap_mux_ops,				\
50 		.parent_data = _pdata,					\
51 		.num_parents = ARRAY_SIZE(_pdata),			\
52 		.flags = CLK_DUTY_CYCLE_PARENT | (_iflags),		\
53 	},								\
54 }
55 
56 #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \
57 	.data = &(struct clk_regmap_div_data){				\
58 		.offset = (_reg),					\
59 		.shift = (_shift),					\
60 		.width = (_width),					\
61 		.flags = (_dflags),					\
62 	},								\
63 	.hw.init = &(struct clk_init_data){				\
64 		.name = "aud_"#_name,					\
65 		.ops = &clk_regmap_divider_ops,				\
66 		.parent_names = (const char *[]){ #_pname },		\
67 		.num_parents = 1,					\
68 		.flags = (_iflags),					\
69 	},								\
70 }
71 
72 #define AUD_PCLK_GATE(_name, _reg, _bit) {				\
73 	.data = &(struct clk_regmap_gate_data){				\
74 		.offset = (_reg),					\
75 		.bit_idx = (_bit),					\
76 	},								\
77 	.hw.init = &(struct clk_init_data) {				\
78 		.name = "aud_"#_name,					\
79 		.ops = &clk_regmap_gate_ops,				\
80 		.parent_names = (const char *[]){ "aud_top" },		\
81 		.num_parents = 1,					\
82 	},								\
83 }
84 
85 #define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width,		\
86 		     _hi_shift, _hi_width, _pname, _iflags) {		\
87 	.data = &(struct meson_sclk_div_data) {				\
88 		.div = {						\
89 			.reg_off = (_reg),				\
90 			.shift   = (_div_shift),			\
91 			.width   = (_div_width),			\
92 		},							\
93 		.hi = {							\
94 			.reg_off = (_reg),				\
95 			.shift   = (_hi_shift),				\
96 			.width   = (_hi_width),				\
97 		},							\
98 	},								\
99 	.hw.init = &(struct clk_init_data) {				\
100 		.name = "aud_"#_name,					\
101 		.ops = &meson_sclk_div_ops,				\
102 		.parent_names = (const char *[]){ #_pname },		\
103 		.num_parents = 1,					\
104 		.flags = (_iflags),					\
105 	},								\
106 }
107 
108 #define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2,	\
109 		     _pname, _iflags) {					\
110 	.data = &(struct meson_clk_triphase_data) {			\
111 		.ph0 = {						\
112 			.reg_off = (_reg),				\
113 			.shift   = (_shift0),				\
114 			.width   = (_width),				\
115 		},							\
116 		.ph1 = {						\
117 			.reg_off = (_reg),				\
118 			.shift   = (_shift1),				\
119 			.width   = (_width),				\
120 		},							\
121 		.ph2 = {						\
122 			.reg_off = (_reg),				\
123 			.shift   = (_shift2),				\
124 			.width   = (_width),				\
125 		},							\
126 	},								\
127 	.hw.init = &(struct clk_init_data) {				\
128 		.name = "aud_"#_name,					\
129 		.ops = &meson_clk_triphase_ops,				\
130 		.parent_names = (const char *[]){ #_pname },		\
131 		.num_parents = 1,					\
132 		.flags = CLK_DUTY_CYCLE_PARENT | (_iflags),		\
133 	},								\
134 }
135 
136 #define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) {	\
137 	.data = &(struct meson_clk_phase_data) {			\
138 		.ph = {							\
139 			.reg_off = (_reg),				\
140 			.shift   = (_shift),				\
141 			.width   = (_width),				\
142 		},							\
143 	},								\
144 	.hw.init = &(struct clk_init_data) {				\
145 		.name = "aud_"#_name,					\
146 		.ops = &meson_clk_phase_ops,				\
147 		.parent_names = (const char *[]){ #_pname },		\
148 		.num_parents = 1,					\
149 		.flags = (_iflags),					\
150 	},								\
151 }
152 
153 #define AUD_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, _pname,	\
154 		    _iflags) {						\
155 	.data = &(struct meson_sclk_ws_inv_data) {			\
156 		.ph = {							\
157 			.reg_off = (_reg),				\
158 			.shift   = (_shift_ph),				\
159 			.width   = (_width),				\
160 		},							\
161 		.ws = {							\
162 			.reg_off = (_reg),				\
163 			.shift   = (_shift_ws),				\
164 			.width   = (_width),				\
165 		},							\
166 	},								\
167 	.hw.init = &(struct clk_init_data) {				\
168 		.name = "aud_"#_name,					\
169 		.ops = &meson_clk_phase_ops,				\
170 		.parent_names = (const char *[]){ #_pname },		\
171 		.num_parents = 1,					\
172 		.flags = (_iflags),					\
173 	},								\
174 }
175 
176 /* Audio Master Clocks */
177 static const struct clk_parent_data mst_mux_parent_data[] = {
178 	{ .fw_name = "mst_in0", },
179 	{ .fw_name = "mst_in1", },
180 	{ .fw_name = "mst_in2", },
181 	{ .fw_name = "mst_in3", },
182 	{ .fw_name = "mst_in4", },
183 	{ .fw_name = "mst_in5", },
184 	{ .fw_name = "mst_in6", },
185 	{ .fw_name = "mst_in7", },
186 };
187 
188 #define AUD_MST_MUX(_name, _reg, _flag)					\
189 	AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag,			\
190 		mst_mux_parent_data, 0)
191 #define AUD_MST_DIV(_name, _reg, _flag)					\
192 	AUD_DIV(_name##_div, _reg, 0, 16, _flag,			\
193 		aud_##_name##_sel, CLK_SET_RATE_PARENT)
194 #define AUD_MST_MCLK_GATE(_name, _reg)					\
195 	AUD_GATE(_name, _reg, 31, aud_##_name##_div,			\
196 		 CLK_SET_RATE_PARENT)
197 
198 #define AUD_MST_MCLK_MUX(_name, _reg)					\
199 	AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
200 #define AUD_MST_MCLK_DIV(_name, _reg)					\
201 	AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
202 
203 #define AUD_MST_SYS_MUX(_name, _reg)					\
204 	AUD_MST_MUX(_name, _reg, 0)
205 #define AUD_MST_SYS_DIV(_name, _reg)					\
206 	AUD_MST_DIV(_name, _reg, 0)
207 
208 /* Sample Clocks */
209 #define AUD_MST_SCLK_PRE_EN(_name, _reg)				\
210 	AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31,			\
211 		 aud_mst_##_name##_mclk, 0)
212 #define AUD_MST_SCLK_DIV(_name, _reg)					\
213 	AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0,	\
214 		     aud_mst_##_name##_sclk_pre_en,			\
215 		     CLK_SET_RATE_PARENT)
216 #define AUD_MST_SCLK_POST_EN(_name, _reg)				\
217 	AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30,			\
218 		 aud_mst_##_name##_sclk_div, CLK_SET_RATE_PARENT)
219 #define AUD_MST_SCLK(_name, _reg)					\
220 	AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4,		\
221 		     aud_mst_##_name##_sclk_post_en, CLK_SET_RATE_PARENT)
222 
223 #define AUD_MST_LRCLK_DIV(_name, _reg)					\
224 	AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10,	\
225 		     aud_mst_##_name##_sclk_post_en, 0)
226 #define AUD_MST_LRCLK(_name, _reg)					\
227 	AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5,		\
228 		     aud_mst_##_name##_lrclk_div, CLK_SET_RATE_PARENT)
229 
230 /* TDM bit clock sources */
231 static const struct clk_parent_data tdm_sclk_parent_data[] = {
232 	{ .name = "aud_mst_a_sclk", .index = -1, },
233 	{ .name = "aud_mst_b_sclk", .index = -1, },
234 	{ .name = "aud_mst_c_sclk", .index = -1, },
235 	{ .name = "aud_mst_d_sclk", .index = -1, },
236 	{ .name = "aud_mst_e_sclk", .index = -1, },
237 	{ .name = "aud_mst_f_sclk", .index = -1, },
238 	{ .fw_name = "slv_sclk0", },
239 	{ .fw_name = "slv_sclk1", },
240 	{ .fw_name = "slv_sclk2", },
241 	{ .fw_name = "slv_sclk3", },
242 	{ .fw_name = "slv_sclk4", },
243 	{ .fw_name = "slv_sclk5", },
244 	{ .fw_name = "slv_sclk6", },
245 	{ .fw_name = "slv_sclk7", },
246 	{ .fw_name = "slv_sclk8", },
247 	{ .fw_name = "slv_sclk9", },
248 };
249 
250 /* TDM sample clock sources */
251 static const struct clk_parent_data tdm_lrclk_parent_data[] = {
252 	{ .name = "aud_mst_a_lrclk", .index = -1, },
253 	{ .name = "aud_mst_b_lrclk", .index = -1, },
254 	{ .name = "aud_mst_c_lrclk", .index = -1, },
255 	{ .name = "aud_mst_d_lrclk", .index = -1, },
256 	{ .name = "aud_mst_e_lrclk", .index = -1, },
257 	{ .name = "aud_mst_f_lrclk", .index = -1, },
258 	{ .fw_name = "slv_lrclk0", },
259 	{ .fw_name = "slv_lrclk1", },
260 	{ .fw_name = "slv_lrclk2", },
261 	{ .fw_name = "slv_lrclk3", },
262 	{ .fw_name = "slv_lrclk4", },
263 	{ .fw_name = "slv_lrclk5", },
264 	{ .fw_name = "slv_lrclk6", },
265 	{ .fw_name = "slv_lrclk7", },
266 	{ .fw_name = "slv_lrclk8", },
267 	{ .fw_name = "slv_lrclk9", },
268 };
269 
270 #define AUD_TDM_SCLK_MUX(_name, _reg)					\
271 	AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24,			\
272 		CLK_MUX_ROUND_CLOSEST, tdm_sclk_parent_data, 0)
273 #define AUD_TDM_SCLK_PRE_EN(_name, _reg)				\
274 	AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31,			\
275 		 aud_tdm##_name##_sclk_sel, CLK_SET_RATE_PARENT)
276 #define AUD_TDM_SCLK_POST_EN(_name, _reg)				\
277 	AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30,			\
278 		 aud_tdm##_name##_sclk_pre_en, CLK_SET_RATE_PARENT)
279 #define AUD_TDM_SCLK(_name, _reg)					\
280 	AUD_PHASE(tdm##_name##_sclk, _reg, 1, 29,			\
281 		  aud_tdm##_name##_sclk_post_en,			\
282 		  CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT)
283 #define AUD_TDM_SCLK_WS(_name, _reg)					\
284 	AUD_SCLK_WS(tdm##_name##_sclk, _reg, 1, 29, 28,			\
285 		    aud_tdm##_name##_sclk_post_en,			\
286 		    CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT)
287 
288 #define AUD_TDM_LRLCK(_name, _reg)					\
289 	AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20,			\
290 		CLK_MUX_ROUND_CLOSEST, tdm_lrclk_parent_data, 0)
291 
292 /* Pad master clock sources */
293 static const struct clk_parent_data mclk_pad_ctrl_parent_data[] = {
294 	{ .name = "aud_mst_a_mclk", .index = -1,  },
295 	{ .name = "aud_mst_b_mclk", .index = -1,  },
296 	{ .name = "aud_mst_c_mclk", .index = -1,  },
297 	{ .name = "aud_mst_d_mclk", .index = -1,  },
298 	{ .name = "aud_mst_e_mclk", .index = -1,  },
299 	{ .name = "aud_mst_f_mclk", .index = -1,  },
300 };
301 
302 /* Pad bit clock sources */
303 static const struct clk_parent_data sclk_pad_ctrl_parent_data[] = {
304 	{ .name = "aud_mst_a_sclk", .index = -1, },
305 	{ .name = "aud_mst_b_sclk", .index = -1, },
306 	{ .name = "aud_mst_c_sclk", .index = -1, },
307 	{ .name = "aud_mst_d_sclk", .index = -1, },
308 	{ .name = "aud_mst_e_sclk", .index = -1, },
309 	{ .name = "aud_mst_f_sclk", .index = -1, },
310 };
311 
312 /* Pad sample clock sources */
313 static const struct clk_parent_data lrclk_pad_ctrl_parent_data[] = {
314 	{ .name = "aud_mst_a_lrclk", .index = -1, },
315 	{ .name = "aud_mst_b_lrclk", .index = -1, },
316 	{ .name = "aud_mst_c_lrclk", .index = -1, },
317 	{ .name = "aud_mst_d_lrclk", .index = -1, },
318 	{ .name = "aud_mst_e_lrclk", .index = -1, },
319 	{ .name = "aud_mst_f_lrclk", .index = -1, },
320 };
321 
322 #define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents)		\
323 	AUD_MUX(_name, _reg, 0x7, _shift, 0, _parents,		\
324 		CLK_SET_RATE_NO_REPARENT)
325 
326 /* Common Clocks */
327 static struct clk_regmap ddr_arb =
328 	AUD_PCLK_GATE(ddr_arb, AUDIO_CLK_GATE_EN, 0);
329 static struct clk_regmap pdm =
330 	AUD_PCLK_GATE(pdm, AUDIO_CLK_GATE_EN, 1);
331 static struct clk_regmap tdmin_a =
332 	AUD_PCLK_GATE(tdmin_a, AUDIO_CLK_GATE_EN, 2);
333 static struct clk_regmap tdmin_b =
334 	AUD_PCLK_GATE(tdmin_b, AUDIO_CLK_GATE_EN, 3);
335 static struct clk_regmap tdmin_c =
336 	AUD_PCLK_GATE(tdmin_c, AUDIO_CLK_GATE_EN, 4);
337 static struct clk_regmap tdmin_lb =
338 	AUD_PCLK_GATE(tdmin_lb, AUDIO_CLK_GATE_EN, 5);
339 static struct clk_regmap tdmout_a =
340 	AUD_PCLK_GATE(tdmout_a, AUDIO_CLK_GATE_EN, 6);
341 static struct clk_regmap tdmout_b =
342 	AUD_PCLK_GATE(tdmout_b, AUDIO_CLK_GATE_EN, 7);
343 static struct clk_regmap tdmout_c =
344 	AUD_PCLK_GATE(tdmout_c, AUDIO_CLK_GATE_EN, 8);
345 static struct clk_regmap frddr_a =
346 	AUD_PCLK_GATE(frddr_a, AUDIO_CLK_GATE_EN, 9);
347 static struct clk_regmap frddr_b =
348 	AUD_PCLK_GATE(frddr_b, AUDIO_CLK_GATE_EN, 10);
349 static struct clk_regmap frddr_c =
350 	AUD_PCLK_GATE(frddr_c, AUDIO_CLK_GATE_EN, 11);
351 static struct clk_regmap toddr_a =
352 	AUD_PCLK_GATE(toddr_a, AUDIO_CLK_GATE_EN, 12);
353 static struct clk_regmap toddr_b =
354 	AUD_PCLK_GATE(toddr_b, AUDIO_CLK_GATE_EN, 13);
355 static struct clk_regmap toddr_c =
356 	AUD_PCLK_GATE(toddr_c, AUDIO_CLK_GATE_EN, 14);
357 static struct clk_regmap loopback =
358 	AUD_PCLK_GATE(loopback, AUDIO_CLK_GATE_EN, 15);
359 static struct clk_regmap spdifin =
360 	AUD_PCLK_GATE(spdifin, AUDIO_CLK_GATE_EN, 16);
361 static struct clk_regmap spdifout =
362 	AUD_PCLK_GATE(spdifout, AUDIO_CLK_GATE_EN, 17);
363 static struct clk_regmap resample =
364 	AUD_PCLK_GATE(resample, AUDIO_CLK_GATE_EN, 18);
365 static struct clk_regmap power_detect =
366 	AUD_PCLK_GATE(power_detect, AUDIO_CLK_GATE_EN, 19);
367 
368 static struct clk_regmap spdifout_clk_sel =
369 	AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
370 static struct clk_regmap pdm_dclk_sel =
371 	AUD_MST_MCLK_MUX(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
372 static struct clk_regmap spdifin_clk_sel =
373 	AUD_MST_SYS_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
374 static struct clk_regmap pdm_sysclk_sel =
375 	AUD_MST_SYS_MUX(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
376 static struct clk_regmap spdifout_b_clk_sel =
377 	AUD_MST_MCLK_MUX(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
378 
379 static struct clk_regmap spdifout_clk_div =
380 	AUD_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
381 static struct clk_regmap pdm_dclk_div =
382 	AUD_MST_MCLK_DIV(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
383 static struct clk_regmap spdifin_clk_div =
384 	AUD_MST_SYS_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
385 static struct clk_regmap pdm_sysclk_div =
386 	AUD_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
387 static struct clk_regmap spdifout_b_clk_div =
388 	AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
389 
390 static struct clk_regmap spdifout_clk =
391 	AUD_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
392 static struct clk_regmap spdifin_clk =
393 	AUD_MST_MCLK_GATE(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
394 static struct clk_regmap pdm_dclk =
395 	AUD_MST_MCLK_GATE(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
396 static struct clk_regmap pdm_sysclk =
397 	AUD_MST_MCLK_GATE(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
398 static struct clk_regmap spdifout_b_clk =
399 	AUD_MST_MCLK_GATE(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
400 
401 static struct clk_regmap mst_a_sclk_pre_en =
402 	AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);
403 static struct clk_regmap mst_b_sclk_pre_en =
404 	AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
405 static struct clk_regmap mst_c_sclk_pre_en =
406 	AUD_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0);
407 static struct clk_regmap mst_d_sclk_pre_en =
408 	AUD_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0);
409 static struct clk_regmap mst_e_sclk_pre_en =
410 	AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0);
411 static struct clk_regmap mst_f_sclk_pre_en =
412 	AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);
413 
414 static struct clk_regmap mst_a_sclk_div =
415 	AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
416 static struct clk_regmap mst_b_sclk_div =
417 	AUD_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
418 static struct clk_regmap mst_c_sclk_div =
419 	AUD_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
420 static struct clk_regmap mst_d_sclk_div =
421 	AUD_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
422 static struct clk_regmap mst_e_sclk_div =
423 	AUD_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
424 static struct clk_regmap mst_f_sclk_div =
425 	AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
426 
427 static struct clk_regmap mst_a_sclk_post_en =
428 	AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);
429 static struct clk_regmap mst_b_sclk_post_en =
430 	AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
431 static struct clk_regmap mst_c_sclk_post_en =
432 	AUD_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0);
433 static struct clk_regmap mst_d_sclk_post_en =
434 	AUD_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0);
435 static struct clk_regmap mst_e_sclk_post_en =
436 	AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);
437 static struct clk_regmap mst_f_sclk_post_en =
438 	AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);
439 
440 static struct clk_regmap mst_a_sclk =
441 	AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);
442 static struct clk_regmap mst_b_sclk =
443 	AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
444 static struct clk_regmap mst_c_sclk =
445 	AUD_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1);
446 static struct clk_regmap mst_d_sclk =
447 	AUD_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1);
448 static struct clk_regmap mst_e_sclk =
449 	AUD_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1);
450 static struct clk_regmap mst_f_sclk =
451 	AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1);
452 
453 static struct clk_regmap mst_a_lrclk_div =
454 	AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
455 static struct clk_regmap mst_b_lrclk_div =
456 	AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
457 static struct clk_regmap mst_c_lrclk_div =
458 	AUD_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
459 static struct clk_regmap mst_d_lrclk_div =
460 	AUD_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
461 static struct clk_regmap mst_e_lrclk_div =
462 	AUD_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
463 static struct clk_regmap mst_f_lrclk_div =
464 	AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
465 
466 static struct clk_regmap mst_a_lrclk =
467 	AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);
468 static struct clk_regmap mst_b_lrclk =
469 	AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
470 static struct clk_regmap mst_c_lrclk =
471 	AUD_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1);
472 static struct clk_regmap mst_d_lrclk =
473 	AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1);
474 static struct clk_regmap mst_e_lrclk =
475 	AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);
476 static struct clk_regmap mst_f_lrclk =
477 	AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);
478 
479 static struct clk_regmap tdmin_a_sclk_sel =
480 	AUD_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL);
481 static struct clk_regmap tdmin_b_sclk_sel =
482 	AUD_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL);
483 static struct clk_regmap tdmin_c_sclk_sel =
484 	AUD_TDM_SCLK_MUX(in_c, AUDIO_CLK_TDMIN_C_CTRL);
485 static struct clk_regmap tdmin_lb_sclk_sel =
486 	AUD_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
487 static struct clk_regmap tdmout_a_sclk_sel =
488 	AUD_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
489 static struct clk_regmap tdmout_b_sclk_sel =
490 	AUD_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
491 static struct clk_regmap tdmout_c_sclk_sel =
492 	AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
493 
494 static struct clk_regmap tdmin_a_sclk_pre_en =
495 	AUD_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
496 static struct clk_regmap tdmin_b_sclk_pre_en =
497 	AUD_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
498 static struct clk_regmap tdmin_c_sclk_pre_en =
499 	AUD_TDM_SCLK_PRE_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
500 static struct clk_regmap tdmin_lb_sclk_pre_en =
501 	AUD_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
502 static struct clk_regmap tdmout_a_sclk_pre_en =
503 	AUD_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
504 static struct clk_regmap tdmout_b_sclk_pre_en =
505 	AUD_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
506 static struct clk_regmap tdmout_c_sclk_pre_en =
507 	AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
508 
509 static struct clk_regmap tdmin_a_sclk_post_en =
510 	AUD_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
511 static struct clk_regmap tdmin_b_sclk_post_en =
512 	AUD_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
513 static struct clk_regmap tdmin_c_sclk_post_en =
514 	AUD_TDM_SCLK_POST_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
515 static struct clk_regmap tdmin_lb_sclk_post_en =
516 	AUD_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
517 static struct clk_regmap tdmout_a_sclk_post_en =
518 	AUD_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
519 static struct clk_regmap tdmout_b_sclk_post_en =
520 	AUD_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
521 static struct clk_regmap tdmout_c_sclk_post_en =
522 	AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
523 
524 static struct clk_regmap tdmin_a_sclk =
525 	AUD_TDM_SCLK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
526 static struct clk_regmap tdmin_b_sclk =
527 	AUD_TDM_SCLK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
528 static struct clk_regmap tdmin_c_sclk =
529 	AUD_TDM_SCLK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
530 static struct clk_regmap tdmin_lb_sclk =
531 	AUD_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
532 
533 static struct clk_regmap tdmin_a_lrclk =
534 	AUD_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
535 static struct clk_regmap tdmin_b_lrclk =
536 	AUD_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
537 static struct clk_regmap tdmin_c_lrclk =
538 	AUD_TDM_LRLCK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
539 static struct clk_regmap tdmin_lb_lrclk =
540 	AUD_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
541 static struct clk_regmap tdmout_a_lrclk =
542 	AUD_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
543 static struct clk_regmap tdmout_b_lrclk =
544 	AUD_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
545 static struct clk_regmap tdmout_c_lrclk =
546 	AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
547 
548 /* AXG Clocks */
549 static struct clk_regmap axg_tdmout_a_sclk =
550 	AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
551 static struct clk_regmap axg_tdmout_b_sclk =
552 	AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
553 static struct clk_regmap axg_tdmout_c_sclk =
554 	AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
555 
556 /* AXG/G12A Clocks */
557 static struct clk_hw axg_aud_top = {
558 	.init = &(struct clk_init_data) {
559 		/* Provide aud_top signal name on axg and g12a */
560 		.name = "aud_top",
561 		.ops = &(const struct clk_ops) {},
562 		.parent_data = &(const struct clk_parent_data) {
563 			.fw_name = "pclk",
564 		},
565 		.num_parents = 1,
566 	},
567 };
568 
569 static struct clk_regmap mst_a_mclk_sel =
570 	AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL);
571 static struct clk_regmap mst_b_mclk_sel =
572 	AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL);
573 static struct clk_regmap mst_c_mclk_sel =
574 	AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL);
575 static struct clk_regmap mst_d_mclk_sel =
576 	AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL);
577 static struct clk_regmap mst_e_mclk_sel =
578 	AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_MCLK_E_CTRL);
579 static struct clk_regmap mst_f_mclk_sel =
580 	AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_MCLK_F_CTRL);
581 
582 static struct clk_regmap mst_a_mclk_div =
583 	AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL);
584 static struct clk_regmap mst_b_mclk_div =
585 	AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL);
586 static struct clk_regmap mst_c_mclk_div =
587 	AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_MCLK_C_CTRL);
588 static struct clk_regmap mst_d_mclk_div =
589 	AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL);
590 static struct clk_regmap mst_e_mclk_div =
591 	AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_MCLK_E_CTRL);
592 static struct clk_regmap mst_f_mclk_div =
593 	AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_MCLK_F_CTRL);
594 
595 static struct clk_regmap mst_a_mclk =
596 	AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL);
597 static struct clk_regmap mst_b_mclk =
598 	AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_MCLK_B_CTRL);
599 static struct clk_regmap mst_c_mclk =
600 	AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_MCLK_C_CTRL);
601 static struct clk_regmap mst_d_mclk =
602 	AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_MCLK_D_CTRL);
603 static struct clk_regmap mst_e_mclk =
604 	AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_MCLK_E_CTRL);
605 static struct clk_regmap mst_f_mclk =
606 	AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_MCLK_F_CTRL);
607 
608 /* G12a clocks */
609 static struct clk_regmap g12a_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL(
610 	mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0, mclk_pad_ctrl_parent_data);
611 static struct clk_regmap g12a_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL(
612 	mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4, mclk_pad_ctrl_parent_data);
613 static struct clk_regmap g12a_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL(
614 	lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16, lrclk_pad_ctrl_parent_data);
615 static struct clk_regmap g12a_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL(
616 	lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20, lrclk_pad_ctrl_parent_data);
617 static struct clk_regmap g12a_tdm_lrclk_pad_2 = AUD_TDM_PAD_CTRL(
618 	lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24, lrclk_pad_ctrl_parent_data);
619 static struct clk_regmap g12a_tdm_sclk_pad_0 = AUD_TDM_PAD_CTRL(
620 	sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0, sclk_pad_ctrl_parent_data);
621 static struct clk_regmap g12a_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL(
622 	sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4, sclk_pad_ctrl_parent_data);
623 static struct clk_regmap g12a_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
624 	sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data);
625 
626 static struct clk_regmap g12a_tdmout_a_sclk =
627 	AUD_TDM_SCLK_WS(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
628 static struct clk_regmap g12a_tdmout_b_sclk =
629 	AUD_TDM_SCLK_WS(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
630 static struct clk_regmap g12a_tdmout_c_sclk =
631 	AUD_TDM_SCLK_WS(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
632 
633 static struct clk_regmap toram =
634 	AUD_PCLK_GATE(toram, AUDIO_CLK_GATE_EN, 20);
635 static struct clk_regmap spdifout_b =
636 	AUD_PCLK_GATE(spdifout_b, AUDIO_CLK_GATE_EN, 21);
637 static struct clk_regmap eqdrc =
638 	AUD_PCLK_GATE(eqdrc, AUDIO_CLK_GATE_EN, 22);
639 
640 /* SM1 Clocks */
641 static struct clk_regmap sm1_clk81_en = {
642 	.data = &(struct clk_regmap_gate_data){
643 		.offset = AUDIO_CLK81_EN,
644 		.bit_idx = 31,
645 	},
646 	.hw.init = &(struct clk_init_data) {
647 		.name = "aud_clk81_en",
648 		.ops = &clk_regmap_gate_ops,
649 		.parent_data = &(const struct clk_parent_data) {
650 			.fw_name = "pclk",
651 		},
652 		.num_parents = 1,
653 	},
654 };
655 
656 static struct clk_regmap sm1_sysclk_a_div = {
657 	.data = &(struct clk_regmap_div_data){
658 		.offset = AUDIO_CLK81_CTRL,
659 		.shift = 0,
660 		.width = 8,
661 	},
662 	.hw.init = &(struct clk_init_data) {
663 		.name = "aud_sysclk_a_div",
664 		.ops = &clk_regmap_divider_ops,
665 		.parent_hws = (const struct clk_hw *[]) {
666 			&sm1_clk81_en.hw,
667 		},
668 		.num_parents = 1,
669 		.flags = CLK_SET_RATE_PARENT,
670 	},
671 };
672 
673 static struct clk_regmap sm1_sysclk_a_en = {
674 	.data = &(struct clk_regmap_gate_data){
675 		.offset = AUDIO_CLK81_CTRL,
676 		.bit_idx = 8,
677 	},
678 	.hw.init = &(struct clk_init_data) {
679 		.name = "aud_sysclk_a_en",
680 		.ops = &clk_regmap_gate_ops,
681 		.parent_hws = (const struct clk_hw *[]) {
682 			&sm1_sysclk_a_div.hw,
683 		},
684 		.num_parents = 1,
685 		.flags = CLK_SET_RATE_PARENT,
686 	},
687 };
688 
689 static struct clk_regmap sm1_sysclk_b_div = {
690 	.data = &(struct clk_regmap_div_data){
691 		.offset = AUDIO_CLK81_CTRL,
692 		.shift = 16,
693 		.width = 8,
694 	},
695 	.hw.init = &(struct clk_init_data) {
696 		.name = "aud_sysclk_b_div",
697 		.ops = &clk_regmap_divider_ops,
698 		.parent_hws = (const struct clk_hw *[]) {
699 			&sm1_clk81_en.hw,
700 		},
701 		.num_parents = 1,
702 		.flags = CLK_SET_RATE_PARENT,
703 	},
704 };
705 
706 static struct clk_regmap sm1_sysclk_b_en = {
707 	.data = &(struct clk_regmap_gate_data){
708 		.offset = AUDIO_CLK81_CTRL,
709 		.bit_idx = 24,
710 	},
711 	.hw.init = &(struct clk_init_data) {
712 		.name = "aud_sysclk_b_en",
713 		.ops = &clk_regmap_gate_ops,
714 		.parent_hws = (const struct clk_hw *[]) {
715 			&sm1_sysclk_b_div.hw,
716 		},
717 		.num_parents = 1,
718 		.flags = CLK_SET_RATE_PARENT,
719 	},
720 };
721 
722 static const struct clk_hw *sm1_aud_top_parents[] = {
723 	&sm1_sysclk_a_en.hw,
724 	&sm1_sysclk_b_en.hw,
725 };
726 
727 static struct clk_regmap sm1_aud_top = {
728 	.data = &(struct clk_regmap_mux_data){
729 		.offset = AUDIO_CLK81_CTRL,
730 		.mask = 0x1,
731 		.shift = 31,
732 	},
733 	.hw.init = &(struct clk_init_data){
734 		.name = "aud_top",
735 		.ops = &clk_regmap_mux_ops,
736 		.parent_hws = sm1_aud_top_parents,
737 		.num_parents = ARRAY_SIZE(sm1_aud_top_parents),
738 		.flags = CLK_SET_RATE_NO_REPARENT,
739 	},
740 };
741 
742 static struct clk_regmap resample_b =
743 	AUD_PCLK_GATE(resample_b, AUDIO_CLK_GATE_EN, 26);
744 static struct clk_regmap tovad =
745 	AUD_PCLK_GATE(tovad, AUDIO_CLK_GATE_EN, 27);
746 static struct clk_regmap locker =
747 	AUD_PCLK_GATE(locker, AUDIO_CLK_GATE_EN, 28);
748 static struct clk_regmap spdifin_lb =
749 	AUD_PCLK_GATE(spdifin_lb, AUDIO_CLK_GATE_EN, 29);
750 static struct clk_regmap frddr_d =
751 	AUD_PCLK_GATE(frddr_d, AUDIO_CLK_GATE_EN1, 0);
752 static struct clk_regmap toddr_d =
753 	AUD_PCLK_GATE(toddr_d, AUDIO_CLK_GATE_EN1, 1);
754 static struct clk_regmap loopback_b =
755 	AUD_PCLK_GATE(loopback_b, AUDIO_CLK_GATE_EN1, 2);
756 
757 static struct clk_regmap sm1_mst_a_mclk_sel =
758 	AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
759 static struct clk_regmap sm1_mst_b_mclk_sel =
760 	AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
761 static struct clk_regmap sm1_mst_c_mclk_sel =
762 	AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
763 static struct clk_regmap sm1_mst_d_mclk_sel =
764 	AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
765 static struct clk_regmap sm1_mst_e_mclk_sel =
766 	AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
767 static struct clk_regmap sm1_mst_f_mclk_sel =
768 	AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
769 
770 static struct clk_regmap sm1_mst_a_mclk_div =
771 	AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
772 static struct clk_regmap sm1_mst_b_mclk_div =
773 	AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
774 static struct clk_regmap sm1_mst_c_mclk_div =
775 	AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
776 static struct clk_regmap sm1_mst_d_mclk_div =
777 	AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
778 static struct clk_regmap sm1_mst_e_mclk_div =
779 	AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
780 static struct clk_regmap sm1_mst_f_mclk_div =
781 	AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
782 
783 static struct clk_regmap sm1_mst_a_mclk =
784 	AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
785 static struct clk_regmap sm1_mst_b_mclk =
786 	AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
787 static struct clk_regmap sm1_mst_c_mclk =
788 	AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
789 static struct clk_regmap sm1_mst_d_mclk =
790 	AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
791 static struct clk_regmap sm1_mst_e_mclk =
792 	AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
793 static struct clk_regmap sm1_mst_f_mclk =
794 	AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
795 
796 static struct clk_regmap sm1_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL(
797 	tdm_mclk_pad_0, AUDIO_SM1_MST_PAD_CTRL0, 0, mclk_pad_ctrl_parent_data);
798 static struct clk_regmap sm1_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL(
799 	tdm_mclk_pad_1, AUDIO_SM1_MST_PAD_CTRL0, 4, mclk_pad_ctrl_parent_data);
800 static struct clk_regmap sm1_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL(
801 	tdm_lrclk_pad_0, AUDIO_SM1_MST_PAD_CTRL1, 16, lrclk_pad_ctrl_parent_data);
802 static struct clk_regmap sm1_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL(
803 	tdm_lrclk_pad_1, AUDIO_SM1_MST_PAD_CTRL1, 20, lrclk_pad_ctrl_parent_data);
804 static struct clk_regmap sm1_tdm_lrclk_pad_2 = AUD_TDM_PAD_CTRL(
805 	tdm_lrclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 24, lrclk_pad_ctrl_parent_data);
806 static struct clk_regmap sm1_tdm_sclk_pad_0 = AUD_TDM_PAD_CTRL(
807 	tdm_sclk_pad_0, AUDIO_SM1_MST_PAD_CTRL1, 0, sclk_pad_ctrl_parent_data);
808 static struct clk_regmap sm1_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL(
809 	tdm_sclk_pad_1, AUDIO_SM1_MST_PAD_CTRL1, 4, sclk_pad_ctrl_parent_data);
810 static struct clk_regmap sm1_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
811 	tdm_sclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data);
812 
813 /*
814  * Array of all clocks provided by this provider
815  * The input clocks of the controller will be populated at runtime
816  */
817 static struct clk_hw *axg_audio_hw_clks[] = {
818 	[AUD_CLKID_DDR_ARB]		= &ddr_arb.hw,
819 	[AUD_CLKID_PDM]			= &pdm.hw,
820 	[AUD_CLKID_TDMIN_A]		= &tdmin_a.hw,
821 	[AUD_CLKID_TDMIN_B]		= &tdmin_b.hw,
822 	[AUD_CLKID_TDMIN_C]		= &tdmin_c.hw,
823 	[AUD_CLKID_TDMIN_LB]		= &tdmin_lb.hw,
824 	[AUD_CLKID_TDMOUT_A]		= &tdmout_a.hw,
825 	[AUD_CLKID_TDMOUT_B]		= &tdmout_b.hw,
826 	[AUD_CLKID_TDMOUT_C]		= &tdmout_c.hw,
827 	[AUD_CLKID_FRDDR_A]		= &frddr_a.hw,
828 	[AUD_CLKID_FRDDR_B]		= &frddr_b.hw,
829 	[AUD_CLKID_FRDDR_C]		= &frddr_c.hw,
830 	[AUD_CLKID_TODDR_A]		= &toddr_a.hw,
831 	[AUD_CLKID_TODDR_B]		= &toddr_b.hw,
832 	[AUD_CLKID_TODDR_C]		= &toddr_c.hw,
833 	[AUD_CLKID_LOOPBACK]		= &loopback.hw,
834 	[AUD_CLKID_SPDIFIN]		= &spdifin.hw,
835 	[AUD_CLKID_SPDIFOUT]		= &spdifout.hw,
836 	[AUD_CLKID_RESAMPLE]		= &resample.hw,
837 	[AUD_CLKID_POWER_DETECT]	= &power_detect.hw,
838 	[AUD_CLKID_MST_A_MCLK_SEL]	= &mst_a_mclk_sel.hw,
839 	[AUD_CLKID_MST_B_MCLK_SEL]	= &mst_b_mclk_sel.hw,
840 	[AUD_CLKID_MST_C_MCLK_SEL]	= &mst_c_mclk_sel.hw,
841 	[AUD_CLKID_MST_D_MCLK_SEL]	= &mst_d_mclk_sel.hw,
842 	[AUD_CLKID_MST_E_MCLK_SEL]	= &mst_e_mclk_sel.hw,
843 	[AUD_CLKID_MST_F_MCLK_SEL]	= &mst_f_mclk_sel.hw,
844 	[AUD_CLKID_MST_A_MCLK_DIV]	= &mst_a_mclk_div.hw,
845 	[AUD_CLKID_MST_B_MCLK_DIV]	= &mst_b_mclk_div.hw,
846 	[AUD_CLKID_MST_C_MCLK_DIV]	= &mst_c_mclk_div.hw,
847 	[AUD_CLKID_MST_D_MCLK_DIV]	= &mst_d_mclk_div.hw,
848 	[AUD_CLKID_MST_E_MCLK_DIV]	= &mst_e_mclk_div.hw,
849 	[AUD_CLKID_MST_F_MCLK_DIV]	= &mst_f_mclk_div.hw,
850 	[AUD_CLKID_MST_A_MCLK]		= &mst_a_mclk.hw,
851 	[AUD_CLKID_MST_B_MCLK]		= &mst_b_mclk.hw,
852 	[AUD_CLKID_MST_C_MCLK]		= &mst_c_mclk.hw,
853 	[AUD_CLKID_MST_D_MCLK]		= &mst_d_mclk.hw,
854 	[AUD_CLKID_MST_E_MCLK]		= &mst_e_mclk.hw,
855 	[AUD_CLKID_MST_F_MCLK]		= &mst_f_mclk.hw,
856 	[AUD_CLKID_SPDIFOUT_CLK_SEL]	= &spdifout_clk_sel.hw,
857 	[AUD_CLKID_SPDIFOUT_CLK_DIV]	= &spdifout_clk_div.hw,
858 	[AUD_CLKID_SPDIFOUT_CLK]	= &spdifout_clk.hw,
859 	[AUD_CLKID_SPDIFIN_CLK_SEL]	= &spdifin_clk_sel.hw,
860 	[AUD_CLKID_SPDIFIN_CLK_DIV]	= &spdifin_clk_div.hw,
861 	[AUD_CLKID_SPDIFIN_CLK]		= &spdifin_clk.hw,
862 	[AUD_CLKID_PDM_DCLK_SEL]	= &pdm_dclk_sel.hw,
863 	[AUD_CLKID_PDM_DCLK_DIV]	= &pdm_dclk_div.hw,
864 	[AUD_CLKID_PDM_DCLK]		= &pdm_dclk.hw,
865 	[AUD_CLKID_PDM_SYSCLK_SEL]	= &pdm_sysclk_sel.hw,
866 	[AUD_CLKID_PDM_SYSCLK_DIV]	= &pdm_sysclk_div.hw,
867 	[AUD_CLKID_PDM_SYSCLK]		= &pdm_sysclk.hw,
868 	[AUD_CLKID_MST_A_SCLK_PRE_EN]	= &mst_a_sclk_pre_en.hw,
869 	[AUD_CLKID_MST_B_SCLK_PRE_EN]	= &mst_b_sclk_pre_en.hw,
870 	[AUD_CLKID_MST_C_SCLK_PRE_EN]	= &mst_c_sclk_pre_en.hw,
871 	[AUD_CLKID_MST_D_SCLK_PRE_EN]	= &mst_d_sclk_pre_en.hw,
872 	[AUD_CLKID_MST_E_SCLK_PRE_EN]	= &mst_e_sclk_pre_en.hw,
873 	[AUD_CLKID_MST_F_SCLK_PRE_EN]	= &mst_f_sclk_pre_en.hw,
874 	[AUD_CLKID_MST_A_SCLK_DIV]	= &mst_a_sclk_div.hw,
875 	[AUD_CLKID_MST_B_SCLK_DIV]	= &mst_b_sclk_div.hw,
876 	[AUD_CLKID_MST_C_SCLK_DIV]	= &mst_c_sclk_div.hw,
877 	[AUD_CLKID_MST_D_SCLK_DIV]	= &mst_d_sclk_div.hw,
878 	[AUD_CLKID_MST_E_SCLK_DIV]	= &mst_e_sclk_div.hw,
879 	[AUD_CLKID_MST_F_SCLK_DIV]	= &mst_f_sclk_div.hw,
880 	[AUD_CLKID_MST_A_SCLK_POST_EN]	= &mst_a_sclk_post_en.hw,
881 	[AUD_CLKID_MST_B_SCLK_POST_EN]	= &mst_b_sclk_post_en.hw,
882 	[AUD_CLKID_MST_C_SCLK_POST_EN]	= &mst_c_sclk_post_en.hw,
883 	[AUD_CLKID_MST_D_SCLK_POST_EN]	= &mst_d_sclk_post_en.hw,
884 	[AUD_CLKID_MST_E_SCLK_POST_EN]	= &mst_e_sclk_post_en.hw,
885 	[AUD_CLKID_MST_F_SCLK_POST_EN]	= &mst_f_sclk_post_en.hw,
886 	[AUD_CLKID_MST_A_SCLK]		= &mst_a_sclk.hw,
887 	[AUD_CLKID_MST_B_SCLK]		= &mst_b_sclk.hw,
888 	[AUD_CLKID_MST_C_SCLK]		= &mst_c_sclk.hw,
889 	[AUD_CLKID_MST_D_SCLK]		= &mst_d_sclk.hw,
890 	[AUD_CLKID_MST_E_SCLK]		= &mst_e_sclk.hw,
891 	[AUD_CLKID_MST_F_SCLK]		= &mst_f_sclk.hw,
892 	[AUD_CLKID_MST_A_LRCLK_DIV]	= &mst_a_lrclk_div.hw,
893 	[AUD_CLKID_MST_B_LRCLK_DIV]	= &mst_b_lrclk_div.hw,
894 	[AUD_CLKID_MST_C_LRCLK_DIV]	= &mst_c_lrclk_div.hw,
895 	[AUD_CLKID_MST_D_LRCLK_DIV]	= &mst_d_lrclk_div.hw,
896 	[AUD_CLKID_MST_E_LRCLK_DIV]	= &mst_e_lrclk_div.hw,
897 	[AUD_CLKID_MST_F_LRCLK_DIV]	= &mst_f_lrclk_div.hw,
898 	[AUD_CLKID_MST_A_LRCLK]		= &mst_a_lrclk.hw,
899 	[AUD_CLKID_MST_B_LRCLK]		= &mst_b_lrclk.hw,
900 	[AUD_CLKID_MST_C_LRCLK]		= &mst_c_lrclk.hw,
901 	[AUD_CLKID_MST_D_LRCLK]		= &mst_d_lrclk.hw,
902 	[AUD_CLKID_MST_E_LRCLK]		= &mst_e_lrclk.hw,
903 	[AUD_CLKID_MST_F_LRCLK]		= &mst_f_lrclk.hw,
904 	[AUD_CLKID_TDMIN_A_SCLK_SEL]	= &tdmin_a_sclk_sel.hw,
905 	[AUD_CLKID_TDMIN_B_SCLK_SEL]	= &tdmin_b_sclk_sel.hw,
906 	[AUD_CLKID_TDMIN_C_SCLK_SEL]	= &tdmin_c_sclk_sel.hw,
907 	[AUD_CLKID_TDMIN_LB_SCLK_SEL]	= &tdmin_lb_sclk_sel.hw,
908 	[AUD_CLKID_TDMOUT_A_SCLK_SEL]	= &tdmout_a_sclk_sel.hw,
909 	[AUD_CLKID_TDMOUT_B_SCLK_SEL]	= &tdmout_b_sclk_sel.hw,
910 	[AUD_CLKID_TDMOUT_C_SCLK_SEL]	= &tdmout_c_sclk_sel.hw,
911 	[AUD_CLKID_TDMIN_A_SCLK_PRE_EN]	= &tdmin_a_sclk_pre_en.hw,
912 	[AUD_CLKID_TDMIN_B_SCLK_PRE_EN]	= &tdmin_b_sclk_pre_en.hw,
913 	[AUD_CLKID_TDMIN_C_SCLK_PRE_EN]	= &tdmin_c_sclk_pre_en.hw,
914 	[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
915 	[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
916 	[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
917 	[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
918 	[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
919 	[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
920 	[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
921 	[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
922 	[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
923 	[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
924 	[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
925 	[AUD_CLKID_TDMIN_A_SCLK]	= &tdmin_a_sclk.hw,
926 	[AUD_CLKID_TDMIN_B_SCLK]	= &tdmin_b_sclk.hw,
927 	[AUD_CLKID_TDMIN_C_SCLK]	= &tdmin_c_sclk.hw,
928 	[AUD_CLKID_TDMIN_LB_SCLK]	= &tdmin_lb_sclk.hw,
929 	[AUD_CLKID_TDMOUT_A_SCLK]	= &axg_tdmout_a_sclk.hw,
930 	[AUD_CLKID_TDMOUT_B_SCLK]	= &axg_tdmout_b_sclk.hw,
931 	[AUD_CLKID_TDMOUT_C_SCLK]	= &axg_tdmout_c_sclk.hw,
932 	[AUD_CLKID_TDMIN_A_LRCLK]	= &tdmin_a_lrclk.hw,
933 	[AUD_CLKID_TDMIN_B_LRCLK]	= &tdmin_b_lrclk.hw,
934 	[AUD_CLKID_TDMIN_C_LRCLK]	= &tdmin_c_lrclk.hw,
935 	[AUD_CLKID_TDMIN_LB_LRCLK]	= &tdmin_lb_lrclk.hw,
936 	[AUD_CLKID_TDMOUT_A_LRCLK]	= &tdmout_a_lrclk.hw,
937 	[AUD_CLKID_TDMOUT_B_LRCLK]	= &tdmout_b_lrclk.hw,
938 	[AUD_CLKID_TDMOUT_C_LRCLK]	= &tdmout_c_lrclk.hw,
939 	[AUD_CLKID_TOP]			= &axg_aud_top,
940 };
941 
942 /*
943  * Array of all G12A clocks provided by this provider
944  * The input clocks of the controller will be populated at runtime
945  */
946 static struct clk_hw *g12a_audio_hw_clks[] = {
947 	[AUD_CLKID_DDR_ARB]		= &ddr_arb.hw,
948 	[AUD_CLKID_PDM]			= &pdm.hw,
949 	[AUD_CLKID_TDMIN_A]		= &tdmin_a.hw,
950 	[AUD_CLKID_TDMIN_B]		= &tdmin_b.hw,
951 	[AUD_CLKID_TDMIN_C]		= &tdmin_c.hw,
952 	[AUD_CLKID_TDMIN_LB]		= &tdmin_lb.hw,
953 	[AUD_CLKID_TDMOUT_A]		= &tdmout_a.hw,
954 	[AUD_CLKID_TDMOUT_B]		= &tdmout_b.hw,
955 	[AUD_CLKID_TDMOUT_C]		= &tdmout_c.hw,
956 	[AUD_CLKID_FRDDR_A]		= &frddr_a.hw,
957 	[AUD_CLKID_FRDDR_B]		= &frddr_b.hw,
958 	[AUD_CLKID_FRDDR_C]		= &frddr_c.hw,
959 	[AUD_CLKID_TODDR_A]		= &toddr_a.hw,
960 	[AUD_CLKID_TODDR_B]		= &toddr_b.hw,
961 	[AUD_CLKID_TODDR_C]		= &toddr_c.hw,
962 	[AUD_CLKID_LOOPBACK]		= &loopback.hw,
963 	[AUD_CLKID_SPDIFIN]		= &spdifin.hw,
964 	[AUD_CLKID_SPDIFOUT]		= &spdifout.hw,
965 	[AUD_CLKID_RESAMPLE]		= &resample.hw,
966 	[AUD_CLKID_POWER_DETECT]	= &power_detect.hw,
967 	[AUD_CLKID_SPDIFOUT_B]		= &spdifout_b.hw,
968 	[AUD_CLKID_MST_A_MCLK_SEL]	= &mst_a_mclk_sel.hw,
969 	[AUD_CLKID_MST_B_MCLK_SEL]	= &mst_b_mclk_sel.hw,
970 	[AUD_CLKID_MST_C_MCLK_SEL]	= &mst_c_mclk_sel.hw,
971 	[AUD_CLKID_MST_D_MCLK_SEL]	= &mst_d_mclk_sel.hw,
972 	[AUD_CLKID_MST_E_MCLK_SEL]	= &mst_e_mclk_sel.hw,
973 	[AUD_CLKID_MST_F_MCLK_SEL]	= &mst_f_mclk_sel.hw,
974 	[AUD_CLKID_MST_A_MCLK_DIV]	= &mst_a_mclk_div.hw,
975 	[AUD_CLKID_MST_B_MCLK_DIV]	= &mst_b_mclk_div.hw,
976 	[AUD_CLKID_MST_C_MCLK_DIV]	= &mst_c_mclk_div.hw,
977 	[AUD_CLKID_MST_D_MCLK_DIV]	= &mst_d_mclk_div.hw,
978 	[AUD_CLKID_MST_E_MCLK_DIV]	= &mst_e_mclk_div.hw,
979 	[AUD_CLKID_MST_F_MCLK_DIV]	= &mst_f_mclk_div.hw,
980 	[AUD_CLKID_MST_A_MCLK]		= &mst_a_mclk.hw,
981 	[AUD_CLKID_MST_B_MCLK]		= &mst_b_mclk.hw,
982 	[AUD_CLKID_MST_C_MCLK]		= &mst_c_mclk.hw,
983 	[AUD_CLKID_MST_D_MCLK]		= &mst_d_mclk.hw,
984 	[AUD_CLKID_MST_E_MCLK]		= &mst_e_mclk.hw,
985 	[AUD_CLKID_MST_F_MCLK]		= &mst_f_mclk.hw,
986 	[AUD_CLKID_SPDIFOUT_CLK_SEL]	= &spdifout_clk_sel.hw,
987 	[AUD_CLKID_SPDIFOUT_CLK_DIV]	= &spdifout_clk_div.hw,
988 	[AUD_CLKID_SPDIFOUT_CLK]	= &spdifout_clk.hw,
989 	[AUD_CLKID_SPDIFOUT_B_CLK_SEL]	= &spdifout_b_clk_sel.hw,
990 	[AUD_CLKID_SPDIFOUT_B_CLK_DIV]	= &spdifout_b_clk_div.hw,
991 	[AUD_CLKID_SPDIFOUT_B_CLK]	= &spdifout_b_clk.hw,
992 	[AUD_CLKID_SPDIFIN_CLK_SEL]	= &spdifin_clk_sel.hw,
993 	[AUD_CLKID_SPDIFIN_CLK_DIV]	= &spdifin_clk_div.hw,
994 	[AUD_CLKID_SPDIFIN_CLK]		= &spdifin_clk.hw,
995 	[AUD_CLKID_PDM_DCLK_SEL]	= &pdm_dclk_sel.hw,
996 	[AUD_CLKID_PDM_DCLK_DIV]	= &pdm_dclk_div.hw,
997 	[AUD_CLKID_PDM_DCLK]		= &pdm_dclk.hw,
998 	[AUD_CLKID_PDM_SYSCLK_SEL]	= &pdm_sysclk_sel.hw,
999 	[AUD_CLKID_PDM_SYSCLK_DIV]	= &pdm_sysclk_div.hw,
1000 	[AUD_CLKID_PDM_SYSCLK]		= &pdm_sysclk.hw,
1001 	[AUD_CLKID_MST_A_SCLK_PRE_EN]	= &mst_a_sclk_pre_en.hw,
1002 	[AUD_CLKID_MST_B_SCLK_PRE_EN]	= &mst_b_sclk_pre_en.hw,
1003 	[AUD_CLKID_MST_C_SCLK_PRE_EN]	= &mst_c_sclk_pre_en.hw,
1004 	[AUD_CLKID_MST_D_SCLK_PRE_EN]	= &mst_d_sclk_pre_en.hw,
1005 	[AUD_CLKID_MST_E_SCLK_PRE_EN]	= &mst_e_sclk_pre_en.hw,
1006 	[AUD_CLKID_MST_F_SCLK_PRE_EN]	= &mst_f_sclk_pre_en.hw,
1007 	[AUD_CLKID_MST_A_SCLK_DIV]	= &mst_a_sclk_div.hw,
1008 	[AUD_CLKID_MST_B_SCLK_DIV]	= &mst_b_sclk_div.hw,
1009 	[AUD_CLKID_MST_C_SCLK_DIV]	= &mst_c_sclk_div.hw,
1010 	[AUD_CLKID_MST_D_SCLK_DIV]	= &mst_d_sclk_div.hw,
1011 	[AUD_CLKID_MST_E_SCLK_DIV]	= &mst_e_sclk_div.hw,
1012 	[AUD_CLKID_MST_F_SCLK_DIV]	= &mst_f_sclk_div.hw,
1013 	[AUD_CLKID_MST_A_SCLK_POST_EN]	= &mst_a_sclk_post_en.hw,
1014 	[AUD_CLKID_MST_B_SCLK_POST_EN]	= &mst_b_sclk_post_en.hw,
1015 	[AUD_CLKID_MST_C_SCLK_POST_EN]	= &mst_c_sclk_post_en.hw,
1016 	[AUD_CLKID_MST_D_SCLK_POST_EN]	= &mst_d_sclk_post_en.hw,
1017 	[AUD_CLKID_MST_E_SCLK_POST_EN]	= &mst_e_sclk_post_en.hw,
1018 	[AUD_CLKID_MST_F_SCLK_POST_EN]	= &mst_f_sclk_post_en.hw,
1019 	[AUD_CLKID_MST_A_SCLK]		= &mst_a_sclk.hw,
1020 	[AUD_CLKID_MST_B_SCLK]		= &mst_b_sclk.hw,
1021 	[AUD_CLKID_MST_C_SCLK]		= &mst_c_sclk.hw,
1022 	[AUD_CLKID_MST_D_SCLK]		= &mst_d_sclk.hw,
1023 	[AUD_CLKID_MST_E_SCLK]		= &mst_e_sclk.hw,
1024 	[AUD_CLKID_MST_F_SCLK]		= &mst_f_sclk.hw,
1025 	[AUD_CLKID_MST_A_LRCLK_DIV]	= &mst_a_lrclk_div.hw,
1026 	[AUD_CLKID_MST_B_LRCLK_DIV]	= &mst_b_lrclk_div.hw,
1027 	[AUD_CLKID_MST_C_LRCLK_DIV]	= &mst_c_lrclk_div.hw,
1028 	[AUD_CLKID_MST_D_LRCLK_DIV]	= &mst_d_lrclk_div.hw,
1029 	[AUD_CLKID_MST_E_LRCLK_DIV]	= &mst_e_lrclk_div.hw,
1030 	[AUD_CLKID_MST_F_LRCLK_DIV]	= &mst_f_lrclk_div.hw,
1031 	[AUD_CLKID_MST_A_LRCLK]		= &mst_a_lrclk.hw,
1032 	[AUD_CLKID_MST_B_LRCLK]		= &mst_b_lrclk.hw,
1033 	[AUD_CLKID_MST_C_LRCLK]		= &mst_c_lrclk.hw,
1034 	[AUD_CLKID_MST_D_LRCLK]		= &mst_d_lrclk.hw,
1035 	[AUD_CLKID_MST_E_LRCLK]		= &mst_e_lrclk.hw,
1036 	[AUD_CLKID_MST_F_LRCLK]		= &mst_f_lrclk.hw,
1037 	[AUD_CLKID_TDMIN_A_SCLK_SEL]	= &tdmin_a_sclk_sel.hw,
1038 	[AUD_CLKID_TDMIN_B_SCLK_SEL]	= &tdmin_b_sclk_sel.hw,
1039 	[AUD_CLKID_TDMIN_C_SCLK_SEL]	= &tdmin_c_sclk_sel.hw,
1040 	[AUD_CLKID_TDMIN_LB_SCLK_SEL]	= &tdmin_lb_sclk_sel.hw,
1041 	[AUD_CLKID_TDMOUT_A_SCLK_SEL]	= &tdmout_a_sclk_sel.hw,
1042 	[AUD_CLKID_TDMOUT_B_SCLK_SEL]	= &tdmout_b_sclk_sel.hw,
1043 	[AUD_CLKID_TDMOUT_C_SCLK_SEL]	= &tdmout_c_sclk_sel.hw,
1044 	[AUD_CLKID_TDMIN_A_SCLK_PRE_EN]	= &tdmin_a_sclk_pre_en.hw,
1045 	[AUD_CLKID_TDMIN_B_SCLK_PRE_EN]	= &tdmin_b_sclk_pre_en.hw,
1046 	[AUD_CLKID_TDMIN_C_SCLK_PRE_EN]	= &tdmin_c_sclk_pre_en.hw,
1047 	[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
1048 	[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
1049 	[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
1050 	[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
1051 	[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
1052 	[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
1053 	[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
1054 	[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
1055 	[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
1056 	[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
1057 	[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
1058 	[AUD_CLKID_TDMIN_A_SCLK]	= &tdmin_a_sclk.hw,
1059 	[AUD_CLKID_TDMIN_B_SCLK]	= &tdmin_b_sclk.hw,
1060 	[AUD_CLKID_TDMIN_C_SCLK]	= &tdmin_c_sclk.hw,
1061 	[AUD_CLKID_TDMIN_LB_SCLK]	= &tdmin_lb_sclk.hw,
1062 	[AUD_CLKID_TDMOUT_A_SCLK]	= &g12a_tdmout_a_sclk.hw,
1063 	[AUD_CLKID_TDMOUT_B_SCLK]	= &g12a_tdmout_b_sclk.hw,
1064 	[AUD_CLKID_TDMOUT_C_SCLK]	= &g12a_tdmout_c_sclk.hw,
1065 	[AUD_CLKID_TDMIN_A_LRCLK]	= &tdmin_a_lrclk.hw,
1066 	[AUD_CLKID_TDMIN_B_LRCLK]	= &tdmin_b_lrclk.hw,
1067 	[AUD_CLKID_TDMIN_C_LRCLK]	= &tdmin_c_lrclk.hw,
1068 	[AUD_CLKID_TDMIN_LB_LRCLK]	= &tdmin_lb_lrclk.hw,
1069 	[AUD_CLKID_TDMOUT_A_LRCLK]	= &tdmout_a_lrclk.hw,
1070 	[AUD_CLKID_TDMOUT_B_LRCLK]	= &tdmout_b_lrclk.hw,
1071 	[AUD_CLKID_TDMOUT_C_LRCLK]	= &tdmout_c_lrclk.hw,
1072 	[AUD_CLKID_TDM_MCLK_PAD0]	= &g12a_tdm_mclk_pad_0.hw,
1073 	[AUD_CLKID_TDM_MCLK_PAD1]	= &g12a_tdm_mclk_pad_1.hw,
1074 	[AUD_CLKID_TDM_LRCLK_PAD0]	= &g12a_tdm_lrclk_pad_0.hw,
1075 	[AUD_CLKID_TDM_LRCLK_PAD1]	= &g12a_tdm_lrclk_pad_1.hw,
1076 	[AUD_CLKID_TDM_LRCLK_PAD2]	= &g12a_tdm_lrclk_pad_2.hw,
1077 	[AUD_CLKID_TDM_SCLK_PAD0]	= &g12a_tdm_sclk_pad_0.hw,
1078 	[AUD_CLKID_TDM_SCLK_PAD1]	= &g12a_tdm_sclk_pad_1.hw,
1079 	[AUD_CLKID_TDM_SCLK_PAD2]	= &g12a_tdm_sclk_pad_2.hw,
1080 	[AUD_CLKID_TOP]			= &axg_aud_top,
1081 };
1082 
1083 /*
1084  * Array of all SM1 clocks provided by this provider
1085  * The input clocks of the controller will be populated at runtime
1086  */
1087 static struct clk_hw *sm1_audio_hw_clks[] = {
1088 	[AUD_CLKID_DDR_ARB]		= &ddr_arb.hw,
1089 	[AUD_CLKID_PDM]			= &pdm.hw,
1090 	[AUD_CLKID_TDMIN_A]		= &tdmin_a.hw,
1091 	[AUD_CLKID_TDMIN_B]		= &tdmin_b.hw,
1092 	[AUD_CLKID_TDMIN_C]		= &tdmin_c.hw,
1093 	[AUD_CLKID_TDMIN_LB]		= &tdmin_lb.hw,
1094 	[AUD_CLKID_TDMOUT_A]		= &tdmout_a.hw,
1095 	[AUD_CLKID_TDMOUT_B]		= &tdmout_b.hw,
1096 	[AUD_CLKID_TDMOUT_C]		= &tdmout_c.hw,
1097 	[AUD_CLKID_FRDDR_A]		= &frddr_a.hw,
1098 	[AUD_CLKID_FRDDR_B]		= &frddr_b.hw,
1099 	[AUD_CLKID_FRDDR_C]		= &frddr_c.hw,
1100 	[AUD_CLKID_TODDR_A]		= &toddr_a.hw,
1101 	[AUD_CLKID_TODDR_B]		= &toddr_b.hw,
1102 	[AUD_CLKID_TODDR_C]		= &toddr_c.hw,
1103 	[AUD_CLKID_LOOPBACK]		= &loopback.hw,
1104 	[AUD_CLKID_SPDIFIN]		= &spdifin.hw,
1105 	[AUD_CLKID_SPDIFOUT]		= &spdifout.hw,
1106 	[AUD_CLKID_RESAMPLE]		= &resample.hw,
1107 	[AUD_CLKID_SPDIFOUT_B]		= &spdifout_b.hw,
1108 	[AUD_CLKID_MST_A_MCLK_SEL]	= &sm1_mst_a_mclk_sel.hw,
1109 	[AUD_CLKID_MST_B_MCLK_SEL]	= &sm1_mst_b_mclk_sel.hw,
1110 	[AUD_CLKID_MST_C_MCLK_SEL]	= &sm1_mst_c_mclk_sel.hw,
1111 	[AUD_CLKID_MST_D_MCLK_SEL]	= &sm1_mst_d_mclk_sel.hw,
1112 	[AUD_CLKID_MST_E_MCLK_SEL]	= &sm1_mst_e_mclk_sel.hw,
1113 	[AUD_CLKID_MST_F_MCLK_SEL]	= &sm1_mst_f_mclk_sel.hw,
1114 	[AUD_CLKID_MST_A_MCLK_DIV]	= &sm1_mst_a_mclk_div.hw,
1115 	[AUD_CLKID_MST_B_MCLK_DIV]	= &sm1_mst_b_mclk_div.hw,
1116 	[AUD_CLKID_MST_C_MCLK_DIV]	= &sm1_mst_c_mclk_div.hw,
1117 	[AUD_CLKID_MST_D_MCLK_DIV]	= &sm1_mst_d_mclk_div.hw,
1118 	[AUD_CLKID_MST_E_MCLK_DIV]	= &sm1_mst_e_mclk_div.hw,
1119 	[AUD_CLKID_MST_F_MCLK_DIV]	= &sm1_mst_f_mclk_div.hw,
1120 	[AUD_CLKID_MST_A_MCLK]		= &sm1_mst_a_mclk.hw,
1121 	[AUD_CLKID_MST_B_MCLK]		= &sm1_mst_b_mclk.hw,
1122 	[AUD_CLKID_MST_C_MCLK]		= &sm1_mst_c_mclk.hw,
1123 	[AUD_CLKID_MST_D_MCLK]		= &sm1_mst_d_mclk.hw,
1124 	[AUD_CLKID_MST_E_MCLK]		= &sm1_mst_e_mclk.hw,
1125 	[AUD_CLKID_MST_F_MCLK]		= &sm1_mst_f_mclk.hw,
1126 	[AUD_CLKID_SPDIFOUT_CLK_SEL]	= &spdifout_clk_sel.hw,
1127 	[AUD_CLKID_SPDIFOUT_CLK_DIV]	= &spdifout_clk_div.hw,
1128 	[AUD_CLKID_SPDIFOUT_CLK]	= &spdifout_clk.hw,
1129 	[AUD_CLKID_SPDIFOUT_B_CLK_SEL]	= &spdifout_b_clk_sel.hw,
1130 	[AUD_CLKID_SPDIFOUT_B_CLK_DIV]	= &spdifout_b_clk_div.hw,
1131 	[AUD_CLKID_SPDIFOUT_B_CLK]	= &spdifout_b_clk.hw,
1132 	[AUD_CLKID_SPDIFIN_CLK_SEL]	= &spdifin_clk_sel.hw,
1133 	[AUD_CLKID_SPDIFIN_CLK_DIV]	= &spdifin_clk_div.hw,
1134 	[AUD_CLKID_SPDIFIN_CLK]		= &spdifin_clk.hw,
1135 	[AUD_CLKID_PDM_DCLK_SEL]	= &pdm_dclk_sel.hw,
1136 	[AUD_CLKID_PDM_DCLK_DIV]	= &pdm_dclk_div.hw,
1137 	[AUD_CLKID_PDM_DCLK]		= &pdm_dclk.hw,
1138 	[AUD_CLKID_PDM_SYSCLK_SEL]	= &pdm_sysclk_sel.hw,
1139 	[AUD_CLKID_PDM_SYSCLK_DIV]	= &pdm_sysclk_div.hw,
1140 	[AUD_CLKID_PDM_SYSCLK]		= &pdm_sysclk.hw,
1141 	[AUD_CLKID_MST_A_SCLK_PRE_EN]	= &mst_a_sclk_pre_en.hw,
1142 	[AUD_CLKID_MST_B_SCLK_PRE_EN]	= &mst_b_sclk_pre_en.hw,
1143 	[AUD_CLKID_MST_C_SCLK_PRE_EN]	= &mst_c_sclk_pre_en.hw,
1144 	[AUD_CLKID_MST_D_SCLK_PRE_EN]	= &mst_d_sclk_pre_en.hw,
1145 	[AUD_CLKID_MST_E_SCLK_PRE_EN]	= &mst_e_sclk_pre_en.hw,
1146 	[AUD_CLKID_MST_F_SCLK_PRE_EN]	= &mst_f_sclk_pre_en.hw,
1147 	[AUD_CLKID_MST_A_SCLK_DIV]	= &mst_a_sclk_div.hw,
1148 	[AUD_CLKID_MST_B_SCLK_DIV]	= &mst_b_sclk_div.hw,
1149 	[AUD_CLKID_MST_C_SCLK_DIV]	= &mst_c_sclk_div.hw,
1150 	[AUD_CLKID_MST_D_SCLK_DIV]	= &mst_d_sclk_div.hw,
1151 	[AUD_CLKID_MST_E_SCLK_DIV]	= &mst_e_sclk_div.hw,
1152 	[AUD_CLKID_MST_F_SCLK_DIV]	= &mst_f_sclk_div.hw,
1153 	[AUD_CLKID_MST_A_SCLK_POST_EN]	= &mst_a_sclk_post_en.hw,
1154 	[AUD_CLKID_MST_B_SCLK_POST_EN]	= &mst_b_sclk_post_en.hw,
1155 	[AUD_CLKID_MST_C_SCLK_POST_EN]	= &mst_c_sclk_post_en.hw,
1156 	[AUD_CLKID_MST_D_SCLK_POST_EN]	= &mst_d_sclk_post_en.hw,
1157 	[AUD_CLKID_MST_E_SCLK_POST_EN]	= &mst_e_sclk_post_en.hw,
1158 	[AUD_CLKID_MST_F_SCLK_POST_EN]	= &mst_f_sclk_post_en.hw,
1159 	[AUD_CLKID_MST_A_SCLK]		= &mst_a_sclk.hw,
1160 	[AUD_CLKID_MST_B_SCLK]		= &mst_b_sclk.hw,
1161 	[AUD_CLKID_MST_C_SCLK]		= &mst_c_sclk.hw,
1162 	[AUD_CLKID_MST_D_SCLK]		= &mst_d_sclk.hw,
1163 	[AUD_CLKID_MST_E_SCLK]		= &mst_e_sclk.hw,
1164 	[AUD_CLKID_MST_F_SCLK]		= &mst_f_sclk.hw,
1165 	[AUD_CLKID_MST_A_LRCLK_DIV]	= &mst_a_lrclk_div.hw,
1166 	[AUD_CLKID_MST_B_LRCLK_DIV]	= &mst_b_lrclk_div.hw,
1167 	[AUD_CLKID_MST_C_LRCLK_DIV]	= &mst_c_lrclk_div.hw,
1168 	[AUD_CLKID_MST_D_LRCLK_DIV]	= &mst_d_lrclk_div.hw,
1169 	[AUD_CLKID_MST_E_LRCLK_DIV]	= &mst_e_lrclk_div.hw,
1170 	[AUD_CLKID_MST_F_LRCLK_DIV]	= &mst_f_lrclk_div.hw,
1171 	[AUD_CLKID_MST_A_LRCLK]		= &mst_a_lrclk.hw,
1172 	[AUD_CLKID_MST_B_LRCLK]		= &mst_b_lrclk.hw,
1173 	[AUD_CLKID_MST_C_LRCLK]		= &mst_c_lrclk.hw,
1174 	[AUD_CLKID_MST_D_LRCLK]		= &mst_d_lrclk.hw,
1175 	[AUD_CLKID_MST_E_LRCLK]		= &mst_e_lrclk.hw,
1176 	[AUD_CLKID_MST_F_LRCLK]		= &mst_f_lrclk.hw,
1177 	[AUD_CLKID_TDMIN_A_SCLK_SEL]	= &tdmin_a_sclk_sel.hw,
1178 	[AUD_CLKID_TDMIN_B_SCLK_SEL]	= &tdmin_b_sclk_sel.hw,
1179 	[AUD_CLKID_TDMIN_C_SCLK_SEL]	= &tdmin_c_sclk_sel.hw,
1180 	[AUD_CLKID_TDMIN_LB_SCLK_SEL]	= &tdmin_lb_sclk_sel.hw,
1181 	[AUD_CLKID_TDMOUT_A_SCLK_SEL]	= &tdmout_a_sclk_sel.hw,
1182 	[AUD_CLKID_TDMOUT_B_SCLK_SEL]	= &tdmout_b_sclk_sel.hw,
1183 	[AUD_CLKID_TDMOUT_C_SCLK_SEL]	= &tdmout_c_sclk_sel.hw,
1184 	[AUD_CLKID_TDMIN_A_SCLK_PRE_EN]	= &tdmin_a_sclk_pre_en.hw,
1185 	[AUD_CLKID_TDMIN_B_SCLK_PRE_EN]	= &tdmin_b_sclk_pre_en.hw,
1186 	[AUD_CLKID_TDMIN_C_SCLK_PRE_EN]	= &tdmin_c_sclk_pre_en.hw,
1187 	[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
1188 	[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
1189 	[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
1190 	[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
1191 	[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
1192 	[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
1193 	[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
1194 	[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
1195 	[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
1196 	[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
1197 	[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
1198 	[AUD_CLKID_TDMIN_A_SCLK]	= &tdmin_a_sclk.hw,
1199 	[AUD_CLKID_TDMIN_B_SCLK]	= &tdmin_b_sclk.hw,
1200 	[AUD_CLKID_TDMIN_C_SCLK]	= &tdmin_c_sclk.hw,
1201 	[AUD_CLKID_TDMIN_LB_SCLK]	= &tdmin_lb_sclk.hw,
1202 	[AUD_CLKID_TDMOUT_A_SCLK]	= &g12a_tdmout_a_sclk.hw,
1203 	[AUD_CLKID_TDMOUT_B_SCLK]	= &g12a_tdmout_b_sclk.hw,
1204 	[AUD_CLKID_TDMOUT_C_SCLK]	= &g12a_tdmout_c_sclk.hw,
1205 	[AUD_CLKID_TDMIN_A_LRCLK]	= &tdmin_a_lrclk.hw,
1206 	[AUD_CLKID_TDMIN_B_LRCLK]	= &tdmin_b_lrclk.hw,
1207 	[AUD_CLKID_TDMIN_C_LRCLK]	= &tdmin_c_lrclk.hw,
1208 	[AUD_CLKID_TDMIN_LB_LRCLK]	= &tdmin_lb_lrclk.hw,
1209 	[AUD_CLKID_TDMOUT_A_LRCLK]	= &tdmout_a_lrclk.hw,
1210 	[AUD_CLKID_TDMOUT_B_LRCLK]	= &tdmout_b_lrclk.hw,
1211 	[AUD_CLKID_TDMOUT_C_LRCLK]	= &tdmout_c_lrclk.hw,
1212 	[AUD_CLKID_TDM_MCLK_PAD0]	= &sm1_tdm_mclk_pad_0.hw,
1213 	[AUD_CLKID_TDM_MCLK_PAD1]	= &sm1_tdm_mclk_pad_1.hw,
1214 	[AUD_CLKID_TDM_LRCLK_PAD0]	= &sm1_tdm_lrclk_pad_0.hw,
1215 	[AUD_CLKID_TDM_LRCLK_PAD1]	= &sm1_tdm_lrclk_pad_1.hw,
1216 	[AUD_CLKID_TDM_LRCLK_PAD2]	= &sm1_tdm_lrclk_pad_2.hw,
1217 	[AUD_CLKID_TDM_SCLK_PAD0]	= &sm1_tdm_sclk_pad_0.hw,
1218 	[AUD_CLKID_TDM_SCLK_PAD1]	= &sm1_tdm_sclk_pad_1.hw,
1219 	[AUD_CLKID_TDM_SCLK_PAD2]	= &sm1_tdm_sclk_pad_2.hw,
1220 	[AUD_CLKID_TOP]			= &sm1_aud_top.hw,
1221 	[AUD_CLKID_TORAM]		= &toram.hw,
1222 	[AUD_CLKID_EQDRC]		= &eqdrc.hw,
1223 	[AUD_CLKID_RESAMPLE_B]		= &resample_b.hw,
1224 	[AUD_CLKID_TOVAD]		= &tovad.hw,
1225 	[AUD_CLKID_LOCKER]		= &locker.hw,
1226 	[AUD_CLKID_SPDIFIN_LB]		= &spdifin_lb.hw,
1227 	[AUD_CLKID_FRDDR_D]		= &frddr_d.hw,
1228 	[AUD_CLKID_TODDR_D]		= &toddr_d.hw,
1229 	[AUD_CLKID_LOOPBACK_B]		= &loopback_b.hw,
1230 	[AUD_CLKID_CLK81_EN]		= &sm1_clk81_en.hw,
1231 	[AUD_CLKID_SYSCLK_A_DIV]	= &sm1_sysclk_a_div.hw,
1232 	[AUD_CLKID_SYSCLK_A_EN]		= &sm1_sysclk_a_en.hw,
1233 	[AUD_CLKID_SYSCLK_B_DIV]	= &sm1_sysclk_b_div.hw,
1234 	[AUD_CLKID_SYSCLK_B_EN]		= &sm1_sysclk_b_en.hw,
1235 };
1236 
1237 
1238 /* Convenience table to populate regmap in .probe(). */
1239 static struct clk_regmap *const axg_clk_regmaps[] = {
1240 	&ddr_arb,
1241 	&pdm,
1242 	&tdmin_a,
1243 	&tdmin_b,
1244 	&tdmin_c,
1245 	&tdmin_lb,
1246 	&tdmout_a,
1247 	&tdmout_b,
1248 	&tdmout_c,
1249 	&frddr_a,
1250 	&frddr_b,
1251 	&frddr_c,
1252 	&toddr_a,
1253 	&toddr_b,
1254 	&toddr_c,
1255 	&loopback,
1256 	&spdifin,
1257 	&spdifout,
1258 	&resample,
1259 	&power_detect,
1260 	&mst_a_mclk_sel,
1261 	&mst_b_mclk_sel,
1262 	&mst_c_mclk_sel,
1263 	&mst_d_mclk_sel,
1264 	&mst_e_mclk_sel,
1265 	&mst_f_mclk_sel,
1266 	&mst_a_mclk_div,
1267 	&mst_b_mclk_div,
1268 	&mst_c_mclk_div,
1269 	&mst_d_mclk_div,
1270 	&mst_e_mclk_div,
1271 	&mst_f_mclk_div,
1272 	&mst_a_mclk,
1273 	&mst_b_mclk,
1274 	&mst_c_mclk,
1275 	&mst_d_mclk,
1276 	&mst_e_mclk,
1277 	&mst_f_mclk,
1278 	&spdifout_clk_sel,
1279 	&spdifout_clk_div,
1280 	&spdifout_clk,
1281 	&spdifin_clk_sel,
1282 	&spdifin_clk_div,
1283 	&spdifin_clk,
1284 	&pdm_dclk_sel,
1285 	&pdm_dclk_div,
1286 	&pdm_dclk,
1287 	&pdm_sysclk_sel,
1288 	&pdm_sysclk_div,
1289 	&pdm_sysclk,
1290 	&mst_a_sclk_pre_en,
1291 	&mst_b_sclk_pre_en,
1292 	&mst_c_sclk_pre_en,
1293 	&mst_d_sclk_pre_en,
1294 	&mst_e_sclk_pre_en,
1295 	&mst_f_sclk_pre_en,
1296 	&mst_a_sclk_div,
1297 	&mst_b_sclk_div,
1298 	&mst_c_sclk_div,
1299 	&mst_d_sclk_div,
1300 	&mst_e_sclk_div,
1301 	&mst_f_sclk_div,
1302 	&mst_a_sclk_post_en,
1303 	&mst_b_sclk_post_en,
1304 	&mst_c_sclk_post_en,
1305 	&mst_d_sclk_post_en,
1306 	&mst_e_sclk_post_en,
1307 	&mst_f_sclk_post_en,
1308 	&mst_a_sclk,
1309 	&mst_b_sclk,
1310 	&mst_c_sclk,
1311 	&mst_d_sclk,
1312 	&mst_e_sclk,
1313 	&mst_f_sclk,
1314 	&mst_a_lrclk_div,
1315 	&mst_b_lrclk_div,
1316 	&mst_c_lrclk_div,
1317 	&mst_d_lrclk_div,
1318 	&mst_e_lrclk_div,
1319 	&mst_f_lrclk_div,
1320 	&mst_a_lrclk,
1321 	&mst_b_lrclk,
1322 	&mst_c_lrclk,
1323 	&mst_d_lrclk,
1324 	&mst_e_lrclk,
1325 	&mst_f_lrclk,
1326 	&tdmin_a_sclk_sel,
1327 	&tdmin_b_sclk_sel,
1328 	&tdmin_c_sclk_sel,
1329 	&tdmin_lb_sclk_sel,
1330 	&tdmout_a_sclk_sel,
1331 	&tdmout_b_sclk_sel,
1332 	&tdmout_c_sclk_sel,
1333 	&tdmin_a_sclk_pre_en,
1334 	&tdmin_b_sclk_pre_en,
1335 	&tdmin_c_sclk_pre_en,
1336 	&tdmin_lb_sclk_pre_en,
1337 	&tdmout_a_sclk_pre_en,
1338 	&tdmout_b_sclk_pre_en,
1339 	&tdmout_c_sclk_pre_en,
1340 	&tdmin_a_sclk_post_en,
1341 	&tdmin_b_sclk_post_en,
1342 	&tdmin_c_sclk_post_en,
1343 	&tdmin_lb_sclk_post_en,
1344 	&tdmout_a_sclk_post_en,
1345 	&tdmout_b_sclk_post_en,
1346 	&tdmout_c_sclk_post_en,
1347 	&tdmin_a_sclk,
1348 	&tdmin_b_sclk,
1349 	&tdmin_c_sclk,
1350 	&tdmin_lb_sclk,
1351 	&axg_tdmout_a_sclk,
1352 	&axg_tdmout_b_sclk,
1353 	&axg_tdmout_c_sclk,
1354 	&tdmin_a_lrclk,
1355 	&tdmin_b_lrclk,
1356 	&tdmin_c_lrclk,
1357 	&tdmin_lb_lrclk,
1358 	&tdmout_a_lrclk,
1359 	&tdmout_b_lrclk,
1360 	&tdmout_c_lrclk,
1361 };
1362 
1363 static struct clk_regmap *const g12a_clk_regmaps[] = {
1364 	&ddr_arb,
1365 	&pdm,
1366 	&tdmin_a,
1367 	&tdmin_b,
1368 	&tdmin_c,
1369 	&tdmin_lb,
1370 	&tdmout_a,
1371 	&tdmout_b,
1372 	&tdmout_c,
1373 	&frddr_a,
1374 	&frddr_b,
1375 	&frddr_c,
1376 	&toddr_a,
1377 	&toddr_b,
1378 	&toddr_c,
1379 	&loopback,
1380 	&spdifin,
1381 	&spdifout,
1382 	&resample,
1383 	&power_detect,
1384 	&spdifout_b,
1385 	&mst_a_mclk_sel,
1386 	&mst_b_mclk_sel,
1387 	&mst_c_mclk_sel,
1388 	&mst_d_mclk_sel,
1389 	&mst_e_mclk_sel,
1390 	&mst_f_mclk_sel,
1391 	&mst_a_mclk_div,
1392 	&mst_b_mclk_div,
1393 	&mst_c_mclk_div,
1394 	&mst_d_mclk_div,
1395 	&mst_e_mclk_div,
1396 	&mst_f_mclk_div,
1397 	&mst_a_mclk,
1398 	&mst_b_mclk,
1399 	&mst_c_mclk,
1400 	&mst_d_mclk,
1401 	&mst_e_mclk,
1402 	&mst_f_mclk,
1403 	&spdifout_clk_sel,
1404 	&spdifout_clk_div,
1405 	&spdifout_clk,
1406 	&spdifin_clk_sel,
1407 	&spdifin_clk_div,
1408 	&spdifin_clk,
1409 	&pdm_dclk_sel,
1410 	&pdm_dclk_div,
1411 	&pdm_dclk,
1412 	&pdm_sysclk_sel,
1413 	&pdm_sysclk_div,
1414 	&pdm_sysclk,
1415 	&mst_a_sclk_pre_en,
1416 	&mst_b_sclk_pre_en,
1417 	&mst_c_sclk_pre_en,
1418 	&mst_d_sclk_pre_en,
1419 	&mst_e_sclk_pre_en,
1420 	&mst_f_sclk_pre_en,
1421 	&mst_a_sclk_div,
1422 	&mst_b_sclk_div,
1423 	&mst_c_sclk_div,
1424 	&mst_d_sclk_div,
1425 	&mst_e_sclk_div,
1426 	&mst_f_sclk_div,
1427 	&mst_a_sclk_post_en,
1428 	&mst_b_sclk_post_en,
1429 	&mst_c_sclk_post_en,
1430 	&mst_d_sclk_post_en,
1431 	&mst_e_sclk_post_en,
1432 	&mst_f_sclk_post_en,
1433 	&mst_a_sclk,
1434 	&mst_b_sclk,
1435 	&mst_c_sclk,
1436 	&mst_d_sclk,
1437 	&mst_e_sclk,
1438 	&mst_f_sclk,
1439 	&mst_a_lrclk_div,
1440 	&mst_b_lrclk_div,
1441 	&mst_c_lrclk_div,
1442 	&mst_d_lrclk_div,
1443 	&mst_e_lrclk_div,
1444 	&mst_f_lrclk_div,
1445 	&mst_a_lrclk,
1446 	&mst_b_lrclk,
1447 	&mst_c_lrclk,
1448 	&mst_d_lrclk,
1449 	&mst_e_lrclk,
1450 	&mst_f_lrclk,
1451 	&tdmin_a_sclk_sel,
1452 	&tdmin_b_sclk_sel,
1453 	&tdmin_c_sclk_sel,
1454 	&tdmin_lb_sclk_sel,
1455 	&tdmout_a_sclk_sel,
1456 	&tdmout_b_sclk_sel,
1457 	&tdmout_c_sclk_sel,
1458 	&tdmin_a_sclk_pre_en,
1459 	&tdmin_b_sclk_pre_en,
1460 	&tdmin_c_sclk_pre_en,
1461 	&tdmin_lb_sclk_pre_en,
1462 	&tdmout_a_sclk_pre_en,
1463 	&tdmout_b_sclk_pre_en,
1464 	&tdmout_c_sclk_pre_en,
1465 	&tdmin_a_sclk_post_en,
1466 	&tdmin_b_sclk_post_en,
1467 	&tdmin_c_sclk_post_en,
1468 	&tdmin_lb_sclk_post_en,
1469 	&tdmout_a_sclk_post_en,
1470 	&tdmout_b_sclk_post_en,
1471 	&tdmout_c_sclk_post_en,
1472 	&tdmin_a_sclk,
1473 	&tdmin_b_sclk,
1474 	&tdmin_c_sclk,
1475 	&tdmin_lb_sclk,
1476 	&g12a_tdmout_a_sclk,
1477 	&g12a_tdmout_b_sclk,
1478 	&g12a_tdmout_c_sclk,
1479 	&tdmin_a_lrclk,
1480 	&tdmin_b_lrclk,
1481 	&tdmin_c_lrclk,
1482 	&tdmin_lb_lrclk,
1483 	&tdmout_a_lrclk,
1484 	&tdmout_b_lrclk,
1485 	&tdmout_c_lrclk,
1486 	&spdifout_b_clk_sel,
1487 	&spdifout_b_clk_div,
1488 	&spdifout_b_clk,
1489 	&g12a_tdm_mclk_pad_0,
1490 	&g12a_tdm_mclk_pad_1,
1491 	&g12a_tdm_lrclk_pad_0,
1492 	&g12a_tdm_lrclk_pad_1,
1493 	&g12a_tdm_lrclk_pad_2,
1494 	&g12a_tdm_sclk_pad_0,
1495 	&g12a_tdm_sclk_pad_1,
1496 	&g12a_tdm_sclk_pad_2,
1497 	&toram,
1498 	&eqdrc,
1499 };
1500 
1501 static struct clk_regmap *const sm1_clk_regmaps[] = {
1502 	&ddr_arb,
1503 	&pdm,
1504 	&tdmin_a,
1505 	&tdmin_b,
1506 	&tdmin_c,
1507 	&tdmin_lb,
1508 	&tdmout_a,
1509 	&tdmout_b,
1510 	&tdmout_c,
1511 	&frddr_a,
1512 	&frddr_b,
1513 	&frddr_c,
1514 	&toddr_a,
1515 	&toddr_b,
1516 	&toddr_c,
1517 	&loopback,
1518 	&spdifin,
1519 	&spdifout,
1520 	&resample,
1521 	&spdifout_b,
1522 	&sm1_mst_a_mclk_sel,
1523 	&sm1_mst_b_mclk_sel,
1524 	&sm1_mst_c_mclk_sel,
1525 	&sm1_mst_d_mclk_sel,
1526 	&sm1_mst_e_mclk_sel,
1527 	&sm1_mst_f_mclk_sel,
1528 	&sm1_mst_a_mclk_div,
1529 	&sm1_mst_b_mclk_div,
1530 	&sm1_mst_c_mclk_div,
1531 	&sm1_mst_d_mclk_div,
1532 	&sm1_mst_e_mclk_div,
1533 	&sm1_mst_f_mclk_div,
1534 	&sm1_mst_a_mclk,
1535 	&sm1_mst_b_mclk,
1536 	&sm1_mst_c_mclk,
1537 	&sm1_mst_d_mclk,
1538 	&sm1_mst_e_mclk,
1539 	&sm1_mst_f_mclk,
1540 	&spdifout_clk_sel,
1541 	&spdifout_clk_div,
1542 	&spdifout_clk,
1543 	&spdifin_clk_sel,
1544 	&spdifin_clk_div,
1545 	&spdifin_clk,
1546 	&pdm_dclk_sel,
1547 	&pdm_dclk_div,
1548 	&pdm_dclk,
1549 	&pdm_sysclk_sel,
1550 	&pdm_sysclk_div,
1551 	&pdm_sysclk,
1552 	&mst_a_sclk_pre_en,
1553 	&mst_b_sclk_pre_en,
1554 	&mst_c_sclk_pre_en,
1555 	&mst_d_sclk_pre_en,
1556 	&mst_e_sclk_pre_en,
1557 	&mst_f_sclk_pre_en,
1558 	&mst_a_sclk_div,
1559 	&mst_b_sclk_div,
1560 	&mst_c_sclk_div,
1561 	&mst_d_sclk_div,
1562 	&mst_e_sclk_div,
1563 	&mst_f_sclk_div,
1564 	&mst_a_sclk_post_en,
1565 	&mst_b_sclk_post_en,
1566 	&mst_c_sclk_post_en,
1567 	&mst_d_sclk_post_en,
1568 	&mst_e_sclk_post_en,
1569 	&mst_f_sclk_post_en,
1570 	&mst_a_sclk,
1571 	&mst_b_sclk,
1572 	&mst_c_sclk,
1573 	&mst_d_sclk,
1574 	&mst_e_sclk,
1575 	&mst_f_sclk,
1576 	&mst_a_lrclk_div,
1577 	&mst_b_lrclk_div,
1578 	&mst_c_lrclk_div,
1579 	&mst_d_lrclk_div,
1580 	&mst_e_lrclk_div,
1581 	&mst_f_lrclk_div,
1582 	&mst_a_lrclk,
1583 	&mst_b_lrclk,
1584 	&mst_c_lrclk,
1585 	&mst_d_lrclk,
1586 	&mst_e_lrclk,
1587 	&mst_f_lrclk,
1588 	&tdmin_a_sclk_sel,
1589 	&tdmin_b_sclk_sel,
1590 	&tdmin_c_sclk_sel,
1591 	&tdmin_lb_sclk_sel,
1592 	&tdmout_a_sclk_sel,
1593 	&tdmout_b_sclk_sel,
1594 	&tdmout_c_sclk_sel,
1595 	&tdmin_a_sclk_pre_en,
1596 	&tdmin_b_sclk_pre_en,
1597 	&tdmin_c_sclk_pre_en,
1598 	&tdmin_lb_sclk_pre_en,
1599 	&tdmout_a_sclk_pre_en,
1600 	&tdmout_b_sclk_pre_en,
1601 	&tdmout_c_sclk_pre_en,
1602 	&tdmin_a_sclk_post_en,
1603 	&tdmin_b_sclk_post_en,
1604 	&tdmin_c_sclk_post_en,
1605 	&tdmin_lb_sclk_post_en,
1606 	&tdmout_a_sclk_post_en,
1607 	&tdmout_b_sclk_post_en,
1608 	&tdmout_c_sclk_post_en,
1609 	&tdmin_a_sclk,
1610 	&tdmin_b_sclk,
1611 	&tdmin_c_sclk,
1612 	&tdmin_lb_sclk,
1613 	&g12a_tdmout_a_sclk,
1614 	&g12a_tdmout_b_sclk,
1615 	&g12a_tdmout_c_sclk,
1616 	&tdmin_a_lrclk,
1617 	&tdmin_b_lrclk,
1618 	&tdmin_c_lrclk,
1619 	&tdmin_lb_lrclk,
1620 	&tdmout_a_lrclk,
1621 	&tdmout_b_lrclk,
1622 	&tdmout_c_lrclk,
1623 	&spdifout_b_clk_sel,
1624 	&spdifout_b_clk_div,
1625 	&spdifout_b_clk,
1626 	&sm1_tdm_mclk_pad_0,
1627 	&sm1_tdm_mclk_pad_1,
1628 	&sm1_tdm_lrclk_pad_0,
1629 	&sm1_tdm_lrclk_pad_1,
1630 	&sm1_tdm_lrclk_pad_2,
1631 	&sm1_tdm_sclk_pad_0,
1632 	&sm1_tdm_sclk_pad_1,
1633 	&sm1_tdm_sclk_pad_2,
1634 	&sm1_aud_top,
1635 	&toram,
1636 	&eqdrc,
1637 	&resample_b,
1638 	&tovad,
1639 	&locker,
1640 	&spdifin_lb,
1641 	&frddr_d,
1642 	&toddr_d,
1643 	&loopback_b,
1644 	&sm1_clk81_en,
1645 	&sm1_sysclk_a_div,
1646 	&sm1_sysclk_a_en,
1647 	&sm1_sysclk_b_div,
1648 	&sm1_sysclk_b_en,
1649 };
1650 
1651 struct axg_audio_reset_data {
1652 	struct reset_controller_dev rstc;
1653 	struct regmap *map;
1654 	unsigned int offset;
1655 };
1656 
1657 static void axg_audio_reset_reg_and_bit(struct axg_audio_reset_data *rst,
1658 					unsigned long id,
1659 					unsigned int *reg,
1660 					unsigned int *bit)
1661 {
1662 	unsigned int stride = regmap_get_reg_stride(rst->map);
1663 
1664 	*reg = (id / (stride * BITS_PER_BYTE)) * stride;
1665 	*reg += rst->offset;
1666 	*bit = id % (stride * BITS_PER_BYTE);
1667 }
1668 
1669 static int axg_audio_reset_update(struct reset_controller_dev *rcdev,
1670 				unsigned long id, bool assert)
1671 {
1672 	struct axg_audio_reset_data *rst =
1673 		container_of(rcdev, struct axg_audio_reset_data, rstc);
1674 	unsigned int offset, bit;
1675 
1676 	axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
1677 
1678 	regmap_update_bits(rst->map, offset, BIT(bit),
1679 			assert ? BIT(bit) : 0);
1680 
1681 	return 0;
1682 }
1683 
1684 static int axg_audio_reset_status(struct reset_controller_dev *rcdev,
1685 				unsigned long id)
1686 {
1687 	struct axg_audio_reset_data *rst =
1688 		container_of(rcdev, struct axg_audio_reset_data, rstc);
1689 	unsigned int val, offset, bit;
1690 
1691 	axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
1692 
1693 	regmap_read(rst->map, offset, &val);
1694 
1695 	return !!(val & BIT(bit));
1696 }
1697 
1698 static int axg_audio_reset_assert(struct reset_controller_dev *rcdev,
1699 				unsigned long id)
1700 {
1701 	return axg_audio_reset_update(rcdev, id, true);
1702 }
1703 
1704 static int axg_audio_reset_deassert(struct reset_controller_dev *rcdev,
1705 				unsigned long id)
1706 {
1707 	return axg_audio_reset_update(rcdev, id, false);
1708 }
1709 
1710 static int axg_audio_reset_toggle(struct reset_controller_dev *rcdev,
1711 				unsigned long id)
1712 {
1713 	int ret;
1714 
1715 	ret = axg_audio_reset_assert(rcdev, id);
1716 	if (ret)
1717 		return ret;
1718 
1719 	return axg_audio_reset_deassert(rcdev, id);
1720 }
1721 
1722 static const struct reset_control_ops axg_audio_rstc_ops = {
1723 	.assert = axg_audio_reset_assert,
1724 	.deassert = axg_audio_reset_deassert,
1725 	.reset = axg_audio_reset_toggle,
1726 	.status = axg_audio_reset_status,
1727 };
1728 
1729 static const struct regmap_config axg_audio_regmap_cfg = {
1730 	.reg_bits	= 32,
1731 	.val_bits	= 32,
1732 	.reg_stride	= 4,
1733 	.max_register	= AUDIO_CLK_SPDIFOUT_B_CTRL,
1734 };
1735 
1736 struct audioclk_data {
1737 	struct clk_regmap *const *regmap_clks;
1738 	unsigned int regmap_clk_num;
1739 	struct meson_clk_hw_data hw_clks;
1740 	unsigned int reset_offset;
1741 	unsigned int reset_num;
1742 };
1743 
1744 static int axg_audio_clkc_probe(struct platform_device *pdev)
1745 {
1746 	struct device *dev = &pdev->dev;
1747 	const struct audioclk_data *data;
1748 	struct axg_audio_reset_data *rst;
1749 	struct regmap *map;
1750 	void __iomem *regs;
1751 	struct clk_hw *hw;
1752 	struct clk *clk;
1753 	int ret, i;
1754 
1755 	data = of_device_get_match_data(dev);
1756 	if (!data)
1757 		return -EINVAL;
1758 
1759 	regs = devm_platform_ioremap_resource(pdev, 0);
1760 	if (IS_ERR(regs))
1761 		return PTR_ERR(regs);
1762 
1763 	map = devm_regmap_init_mmio(dev, regs, &axg_audio_regmap_cfg);
1764 	if (IS_ERR(map)) {
1765 		dev_err(dev, "failed to init regmap: %ld\n", PTR_ERR(map));
1766 		return PTR_ERR(map);
1767 	}
1768 
1769 	/* Get the mandatory peripheral clock */
1770 	clk = devm_clk_get_enabled(dev, "pclk");
1771 	if (IS_ERR(clk))
1772 		return PTR_ERR(clk);
1773 
1774 	ret = device_reset(dev);
1775 	if (ret) {
1776 		dev_err_probe(dev, ret, "failed to reset device\n");
1777 		return ret;
1778 	}
1779 
1780 	/* Populate regmap for the regmap backed clocks */
1781 	for (i = 0; i < data->regmap_clk_num; i++)
1782 		data->regmap_clks[i]->map = map;
1783 
1784 	/* Take care to skip the registered input clocks */
1785 	for (i = AUD_CLKID_DDR_ARB; i < data->hw_clks.num; i++) {
1786 		const char *name;
1787 
1788 		hw = data->hw_clks.hws[i];
1789 		/* array might be sparse */
1790 		if (!hw)
1791 			continue;
1792 
1793 		name = hw->init->name;
1794 
1795 		ret = devm_clk_hw_register(dev, hw);
1796 		if (ret) {
1797 			dev_err(dev, "failed to register clock %s\n", name);
1798 			return ret;
1799 		}
1800 	}
1801 
1802 	ret = devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
1803 	if (ret)
1804 		return ret;
1805 
1806 	/* Stop here if there is no reset */
1807 	if (!data->reset_num)
1808 		return 0;
1809 
1810 	rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
1811 	if (!rst)
1812 		return -ENOMEM;
1813 
1814 	rst->map = map;
1815 	rst->offset = data->reset_offset;
1816 	rst->rstc.nr_resets = data->reset_num;
1817 	rst->rstc.ops = &axg_audio_rstc_ops;
1818 	rst->rstc.of_node = dev->of_node;
1819 	rst->rstc.owner = THIS_MODULE;
1820 
1821 	return devm_reset_controller_register(dev, &rst->rstc);
1822 }
1823 
1824 static const struct audioclk_data axg_audioclk_data = {
1825 	.regmap_clks = axg_clk_regmaps,
1826 	.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
1827 	.hw_clks = {
1828 		.hws = axg_audio_hw_clks,
1829 		.num = ARRAY_SIZE(axg_audio_hw_clks),
1830 	},
1831 };
1832 
1833 static const struct audioclk_data g12a_audioclk_data = {
1834 	.regmap_clks = g12a_clk_regmaps,
1835 	.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
1836 	.hw_clks = {
1837 		.hws = g12a_audio_hw_clks,
1838 		.num = ARRAY_SIZE(g12a_audio_hw_clks),
1839 	},
1840 	.reset_offset = AUDIO_SW_RESET,
1841 	.reset_num = 26,
1842 };
1843 
1844 static const struct audioclk_data sm1_audioclk_data = {
1845 	.regmap_clks = sm1_clk_regmaps,
1846 	.regmap_clk_num = ARRAY_SIZE(sm1_clk_regmaps),
1847 	.hw_clks = {
1848 		.hws = sm1_audio_hw_clks,
1849 		.num = ARRAY_SIZE(sm1_audio_hw_clks),
1850 	},
1851 	.reset_offset = AUDIO_SM1_SW_RESET0,
1852 	.reset_num = 39,
1853 };
1854 
1855 static const struct of_device_id clkc_match_table[] = {
1856 	{
1857 		.compatible = "amlogic,axg-audio-clkc",
1858 		.data = &axg_audioclk_data
1859 	}, {
1860 		.compatible = "amlogic,g12a-audio-clkc",
1861 		.data = &g12a_audioclk_data
1862 	}, {
1863 		.compatible = "amlogic,sm1-audio-clkc",
1864 		.data = &sm1_audioclk_data
1865 	}, {}
1866 };
1867 MODULE_DEVICE_TABLE(of, clkc_match_table);
1868 
1869 static struct platform_driver axg_audio_driver = {
1870 	.probe		= axg_audio_clkc_probe,
1871 	.driver		= {
1872 		.name	= "axg-audio-clkc",
1873 		.of_match_table = clkc_match_table,
1874 	},
1875 };
1876 module_platform_driver(axg_audio_driver);
1877 
1878 MODULE_DESCRIPTION("Amlogic AXG/G12A/SM1 Audio Clock driver");
1879 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
1880 MODULE_LICENSE("GPL");
1881