1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved. 4 * Author: Jian Hu <jian.hu@amlogic.com> 5 * 6 * Copyright (c) 2023, SberDevices. All Rights Reserved. 7 * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru> 8 */ 9 10 #include <linux/clk-provider.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/platform_device.h> 13 #include "clk-dualdiv.h" 14 #include "clk-regmap.h" 15 #include "meson-clkc-utils.h" 16 17 #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h> 18 19 #define SYS_OSCIN_CTRL 0x0 20 #define RTC_BY_OSCIN_CTRL0 0x4 21 #define RTC_BY_OSCIN_CTRL1 0x8 22 #define RTC_CTRL 0xc 23 #define SYS_CLK_CTRL0 0x10 24 #define SYS_CLK_EN0 0x1c 25 #define SYS_CLK_EN1 0x20 26 #define AXI_CLK_EN 0x24 27 #define DSPA_CLK_EN 0x28 28 #define DSPB_CLK_EN 0x2c 29 #define DSPA_CLK_CTRL0 0x30 30 #define DSPB_CLK_CTRL0 0x34 31 #define CLK12_24_CTRL 0x38 32 #define GEN_CLK_CTRL 0x3c 33 #define SAR_ADC_CLK_CTRL 0xc0 34 #define PWM_CLK_AB_CTRL 0xc4 35 #define PWM_CLK_CD_CTRL 0xc8 36 #define PWM_CLK_EF_CTRL 0xcc 37 #define SPICC_CLK_CTRL 0xd0 38 #define TS_CLK_CTRL 0xd4 39 #define SPIFC_CLK_CTRL 0xd8 40 #define USB_BUSCLK_CTRL 0xdc 41 #define SD_EMMC_CLK_CTRL 0xe0 42 #define CECA_CLK_CTRL0 0xe4 43 #define CECA_CLK_CTRL1 0xe8 44 #define CECB_CLK_CTRL0 0xec 45 #define CECB_CLK_CTRL1 0xf0 46 #define PSRAM_CLK_CTRL 0xf4 47 #define DMC_CLK_CTRL 0xf8 48 49 static struct clk_regmap xtal_in = { 50 .data = &(struct clk_regmap_gate_data){ 51 .offset = SYS_OSCIN_CTRL, 52 .bit_idx = 0, 53 }, 54 .hw.init = &(struct clk_init_data) { 55 .name = "xtal_in", 56 .ops = &clk_regmap_gate_ro_ops, 57 .parent_data = &(const struct clk_parent_data) { 58 .fw_name = "xtal", 59 }, 60 .num_parents = 1, 61 }, 62 }; 63 64 static struct clk_regmap fixpll_in = { 65 .data = &(struct clk_regmap_gate_data){ 66 .offset = SYS_OSCIN_CTRL, 67 .bit_idx = 1, 68 }, 69 .hw.init = &(struct clk_init_data) { 70 .name = "fixpll_in", 71 .ops = &clk_regmap_gate_ro_ops, 72 .parent_data = &(const struct clk_parent_data) { 73 .fw_name = "xtal", 74 }, 75 .num_parents = 1, 76 }, 77 }; 78 79 static struct clk_regmap usb_phy_in = { 80 .data = &(struct clk_regmap_gate_data){ 81 .offset = SYS_OSCIN_CTRL, 82 .bit_idx = 2, 83 }, 84 .hw.init = &(struct clk_init_data) { 85 .name = "usb_phy_in", 86 .ops = &clk_regmap_gate_ops, 87 .parent_data = &(const struct clk_parent_data) { 88 .fw_name = "xtal", 89 }, 90 .num_parents = 1, 91 }, 92 }; 93 94 static struct clk_regmap usb_ctrl_in = { 95 .data = &(struct clk_regmap_gate_data){ 96 .offset = SYS_OSCIN_CTRL, 97 .bit_idx = 3, 98 }, 99 .hw.init = &(struct clk_init_data) { 100 .name = "usb_ctrl_in", 101 .ops = &clk_regmap_gate_ops, 102 .parent_data = &(const struct clk_parent_data) { 103 .fw_name = "xtal", 104 }, 105 .num_parents = 1, 106 }, 107 }; 108 109 static struct clk_regmap hifipll_in = { 110 .data = &(struct clk_regmap_gate_data){ 111 .offset = SYS_OSCIN_CTRL, 112 .bit_idx = 4, 113 }, 114 .hw.init = &(struct clk_init_data) { 115 .name = "hifipll_in", 116 .ops = &clk_regmap_gate_ops, 117 .parent_data = &(const struct clk_parent_data) { 118 .fw_name = "xtal", 119 }, 120 .num_parents = 1, 121 }, 122 }; 123 124 static struct clk_regmap syspll_in = { 125 .data = &(struct clk_regmap_gate_data){ 126 .offset = SYS_OSCIN_CTRL, 127 .bit_idx = 5, 128 }, 129 .hw.init = &(struct clk_init_data) { 130 .name = "syspll_in", 131 .ops = &clk_regmap_gate_ops, 132 .parent_data = &(const struct clk_parent_data) { 133 .fw_name = "xtal", 134 }, 135 .num_parents = 1, 136 }, 137 }; 138 139 static struct clk_regmap dds_in = { 140 .data = &(struct clk_regmap_gate_data){ 141 .offset = SYS_OSCIN_CTRL, 142 .bit_idx = 6, 143 }, 144 .hw.init = &(struct clk_init_data) { 145 .name = "dds_in", 146 .ops = &clk_regmap_gate_ops, 147 .parent_data = &(const struct clk_parent_data) { 148 .fw_name = "xtal", 149 }, 150 .num_parents = 1, 151 }, 152 }; 153 154 static struct clk_regmap rtc_32k_in = { 155 .data = &(struct clk_regmap_gate_data){ 156 .offset = RTC_BY_OSCIN_CTRL0, 157 .bit_idx = 31, 158 }, 159 .hw.init = &(struct clk_init_data) { 160 .name = "rtc_32k_in", 161 .ops = &clk_regmap_gate_ops, 162 .parent_data = &(const struct clk_parent_data) { 163 .fw_name = "xtal", 164 }, 165 .num_parents = 1, 166 }, 167 }; 168 169 static const struct meson_clk_dualdiv_param clk_32k_div_table[] = { 170 { 171 .dual = 1, 172 .n1 = 733, 173 .m1 = 8, 174 .n2 = 732, 175 .m2 = 11, 176 }, 177 {} 178 }; 179 180 static struct clk_regmap rtc_32k_div = { 181 .data = &(struct meson_clk_dualdiv_data){ 182 .n1 = { 183 .reg_off = RTC_BY_OSCIN_CTRL0, 184 .shift = 0, 185 .width = 12, 186 }, 187 .n2 = { 188 .reg_off = RTC_BY_OSCIN_CTRL0, 189 .shift = 12, 190 .width = 12, 191 }, 192 .m1 = { 193 .reg_off = RTC_BY_OSCIN_CTRL1, 194 .shift = 0, 195 .width = 12, 196 }, 197 .m2 = { 198 .reg_off = RTC_BY_OSCIN_CTRL1, 199 .shift = 12, 200 .width = 12, 201 }, 202 .dual = { 203 .reg_off = RTC_BY_OSCIN_CTRL0, 204 .shift = 28, 205 .width = 1, 206 }, 207 .table = clk_32k_div_table, 208 }, 209 .hw.init = &(struct clk_init_data){ 210 .name = "rtc_32k_div", 211 .ops = &meson_clk_dualdiv_ops, 212 .parent_hws = (const struct clk_hw *[]) { 213 &rtc_32k_in.hw 214 }, 215 .num_parents = 1, 216 }, 217 }; 218 219 static struct clk_regmap rtc_32k_xtal = { 220 .data = &(struct clk_regmap_gate_data){ 221 .offset = RTC_BY_OSCIN_CTRL1, 222 .bit_idx = 24, 223 }, 224 .hw.init = &(struct clk_init_data) { 225 .name = "rtc_32k_xtal", 226 .ops = &clk_regmap_gate_ops, 227 .parent_hws = (const struct clk_hw *[]) { 228 &rtc_32k_in.hw 229 }, 230 .num_parents = 1, 231 }, 232 }; 233 234 static struct clk_regmap rtc_32k_sel = { 235 .data = &(struct clk_regmap_mux_data) { 236 .offset = RTC_CTRL, 237 .mask = 0x3, 238 .shift = 0, 239 .flags = CLK_MUX_ROUND_CLOSEST, 240 }, 241 .hw.init = &(struct clk_init_data){ 242 .name = "rtc_32k_sel", 243 .ops = &clk_regmap_mux_ops, 244 .parent_hws = (const struct clk_hw *[]) { 245 &rtc_32k_xtal.hw, 246 &rtc_32k_div.hw, 247 }, 248 .num_parents = 2, 249 .flags = CLK_SET_RATE_PARENT, 250 }, 251 }; 252 253 static struct clk_regmap rtc = { 254 .data = &(struct clk_regmap_gate_data){ 255 .offset = RTC_BY_OSCIN_CTRL0, 256 .bit_idx = 30, 257 }, 258 .hw.init = &(struct clk_init_data){ 259 .name = "rtc", 260 .ops = &clk_regmap_gate_ops, 261 .parent_hws = (const struct clk_hw *[]) { 262 &rtc_32k_sel.hw 263 }, 264 .num_parents = 1, 265 .flags = CLK_SET_RATE_PARENT, 266 }, 267 }; 268 269 static u32 mux_table_sys[] = { 0, 1, 2, 3, 7 }; 270 static const struct clk_parent_data sys_parents[] = { 271 { .fw_name = "xtal" }, 272 { .fw_name = "fclk_div2" }, 273 { .fw_name = "fclk_div3" }, 274 { .fw_name = "fclk_div5" }, 275 { .hw = &rtc.hw }, 276 }; 277 278 static struct clk_regmap sys_b_sel = { 279 .data = &(struct clk_regmap_mux_data){ 280 .offset = SYS_CLK_CTRL0, 281 .mask = 0x7, 282 .shift = 26, 283 .table = mux_table_sys, 284 }, 285 .hw.init = &(struct clk_init_data){ 286 .name = "sys_b_sel", 287 .ops = &clk_regmap_mux_ro_ops, 288 .parent_data = sys_parents, 289 .num_parents = ARRAY_SIZE(sys_parents), 290 }, 291 }; 292 293 static struct clk_regmap sys_b_div = { 294 .data = &(struct clk_regmap_div_data){ 295 .offset = SYS_CLK_CTRL0, 296 .shift = 16, 297 .width = 10, 298 }, 299 .hw.init = &(struct clk_init_data){ 300 .name = "sys_b_div", 301 .ops = &clk_regmap_divider_ro_ops, 302 .parent_hws = (const struct clk_hw *[]) { 303 &sys_b_sel.hw 304 }, 305 .num_parents = 1, 306 .flags = CLK_SET_RATE_PARENT, 307 }, 308 }; 309 310 static struct clk_regmap sys_b = { 311 .data = &(struct clk_regmap_gate_data){ 312 .offset = SYS_CLK_CTRL0, 313 .bit_idx = 29, 314 }, 315 .hw.init = &(struct clk_init_data) { 316 .name = "sys_b", 317 .ops = &clk_regmap_gate_ro_ops, 318 .parent_hws = (const struct clk_hw *[]) { 319 &sys_b_div.hw 320 }, 321 .num_parents = 1, 322 .flags = CLK_SET_RATE_PARENT, 323 }, 324 }; 325 326 static struct clk_regmap sys_a_sel = { 327 .data = &(struct clk_regmap_mux_data){ 328 .offset = SYS_CLK_CTRL0, 329 .mask = 0x7, 330 .shift = 10, 331 .table = mux_table_sys, 332 }, 333 .hw.init = &(struct clk_init_data){ 334 .name = "sys_a_sel", 335 .ops = &clk_regmap_mux_ro_ops, 336 .parent_data = sys_parents, 337 .num_parents = ARRAY_SIZE(sys_parents), 338 }, 339 }; 340 341 static struct clk_regmap sys_a_div = { 342 .data = &(struct clk_regmap_div_data){ 343 .offset = SYS_CLK_CTRL0, 344 .shift = 0, 345 .width = 10, 346 }, 347 .hw.init = &(struct clk_init_data){ 348 .name = "sys_a_div", 349 .ops = &clk_regmap_divider_ro_ops, 350 .parent_hws = (const struct clk_hw *[]) { 351 &sys_a_sel.hw 352 }, 353 .num_parents = 1, 354 .flags = CLK_SET_RATE_PARENT, 355 }, 356 }; 357 358 static struct clk_regmap sys_a = { 359 .data = &(struct clk_regmap_gate_data){ 360 .offset = SYS_CLK_CTRL0, 361 .bit_idx = 13, 362 }, 363 .hw.init = &(struct clk_init_data) { 364 .name = "sys_a", 365 .ops = &clk_regmap_gate_ro_ops, 366 .parent_hws = (const struct clk_hw *[]) { 367 &sys_a_div.hw 368 }, 369 .num_parents = 1, 370 .flags = CLK_SET_RATE_PARENT, 371 }, 372 }; 373 374 static struct clk_regmap sys = { 375 .data = &(struct clk_regmap_mux_data){ 376 .offset = SYS_CLK_CTRL0, 377 .mask = 0x1, 378 .shift = 31, 379 }, 380 .hw.init = &(struct clk_init_data){ 381 .name = "sys", 382 .ops = &clk_regmap_mux_ro_ops, 383 .parent_hws = (const struct clk_hw *[]) { 384 &sys_a.hw, 385 &sys_b.hw, 386 }, 387 .num_parents = 2, 388 /* 389 * This clock is used by APB bus which is set in boot ROM code 390 * and is required by the platform to operate correctly. 391 * Until the following condition are met, we need this clock to 392 * be marked as critical: 393 * a) Mark the clock used by a firmware resource, if possible 394 * b) CCF has a clock hand-off mechanism to make the sure the 395 * clock stays on until the proper driver comes along 396 */ 397 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 398 }, 399 }; 400 401 static u32 mux_table_dsp_ab[] = { 0, 1, 2, 3, 4, 7 }; 402 static const struct clk_parent_data dsp_ab_parent_data[] = { 403 { .fw_name = "xtal", }, 404 { .fw_name = "fclk_div2", }, 405 { .fw_name = "fclk_div3", }, 406 { .fw_name = "fclk_div5", }, 407 { .fw_name = "hifi_pll", }, 408 { .hw = &rtc.hw }, 409 }; 410 411 static struct clk_regmap dspa_a_sel = { 412 .data = &(struct clk_regmap_mux_data){ 413 .offset = DSPA_CLK_CTRL0, 414 .mask = 0x7, 415 .shift = 10, 416 .table = mux_table_dsp_ab, 417 }, 418 .hw.init = &(struct clk_init_data){ 419 .name = "dspa_a_sel", 420 .ops = &clk_regmap_mux_ops, 421 .parent_data = dsp_ab_parent_data, 422 .num_parents = ARRAY_SIZE(dsp_ab_parent_data), 423 }, 424 }; 425 426 static struct clk_regmap dspa_a_div = { 427 .data = &(struct clk_regmap_div_data){ 428 .offset = DSPA_CLK_CTRL0, 429 .shift = 0, 430 .width = 10, 431 }, 432 .hw.init = &(struct clk_init_data){ 433 .name = "dspa_a_div", 434 .ops = &clk_regmap_divider_ops, 435 .parent_hws = (const struct clk_hw *[]) { 436 &dspa_a_sel.hw 437 }, 438 .num_parents = 1, 439 .flags = CLK_SET_RATE_PARENT, 440 }, 441 }; 442 443 static struct clk_regmap dspa_a = { 444 .data = &(struct clk_regmap_gate_data){ 445 .offset = DSPA_CLK_CTRL0, 446 .bit_idx = 13, 447 }, 448 .hw.init = &(struct clk_init_data) { 449 .name = "dspa_a", 450 .ops = &clk_regmap_gate_ops, 451 .parent_hws = (const struct clk_hw *[]) { 452 &dspa_a_div.hw 453 }, 454 .num_parents = 1, 455 .flags = CLK_SET_RATE_PARENT, 456 }, 457 }; 458 459 static struct clk_regmap dspa_b_sel = { 460 .data = &(struct clk_regmap_mux_data){ 461 .offset = DSPA_CLK_CTRL0, 462 .mask = 0x7, 463 .shift = 26, 464 .table = mux_table_dsp_ab, 465 }, 466 .hw.init = &(struct clk_init_data){ 467 .name = "dspa_b_sel", 468 .ops = &clk_regmap_mux_ops, 469 .parent_data = dsp_ab_parent_data, 470 .num_parents = ARRAY_SIZE(dsp_ab_parent_data), 471 }, 472 }; 473 474 static struct clk_regmap dspa_b_div = { 475 .data = &(struct clk_regmap_div_data){ 476 .offset = DSPA_CLK_CTRL0, 477 .shift = 16, 478 .width = 10, 479 }, 480 .hw.init = &(struct clk_init_data){ 481 .name = "dspa_b_div", 482 .ops = &clk_regmap_divider_ops, 483 .parent_hws = (const struct clk_hw *[]) { 484 &dspa_b_sel.hw 485 }, 486 .num_parents = 1, 487 .flags = CLK_SET_RATE_PARENT, 488 }, 489 }; 490 491 static struct clk_regmap dspa_b = { 492 .data = &(struct clk_regmap_gate_data){ 493 .offset = DSPA_CLK_CTRL0, 494 .bit_idx = 29, 495 }, 496 .hw.init = &(struct clk_init_data) { 497 .name = "dspa_b", 498 .ops = &clk_regmap_gate_ops, 499 .parent_hws = (const struct clk_hw *[]) { 500 &dspa_b_div.hw 501 }, 502 .num_parents = 1, 503 .flags = CLK_SET_RATE_PARENT, 504 }, 505 }; 506 507 static struct clk_regmap dspa_sel = { 508 .data = &(struct clk_regmap_mux_data){ 509 .offset = DSPA_CLK_CTRL0, 510 .mask = 0x1, 511 .shift = 15, 512 }, 513 .hw.init = &(struct clk_init_data){ 514 .name = "dspa_sel", 515 .ops = &clk_regmap_mux_ops, 516 .parent_hws = (const struct clk_hw *[]) { 517 &dspa_a.hw, 518 &dspa_b.hw, 519 }, 520 .num_parents = 2, 521 .flags = CLK_SET_RATE_PARENT, 522 }, 523 }; 524 525 static struct clk_regmap dspa_en = { 526 .data = &(struct clk_regmap_gate_data){ 527 .offset = DSPA_CLK_EN, 528 .bit_idx = 1, 529 }, 530 .hw.init = &(struct clk_init_data) { 531 .name = "dspa_en", 532 .ops = &clk_regmap_gate_ops, 533 .parent_hws = (const struct clk_hw *[]) { 534 &dspa_sel.hw 535 }, 536 .num_parents = 1, 537 .flags = CLK_SET_RATE_PARENT, 538 }, 539 }; 540 541 static struct clk_regmap dspa_en_nic = { 542 .data = &(struct clk_regmap_gate_data){ 543 .offset = DSPA_CLK_EN, 544 .bit_idx = 0, 545 }, 546 .hw.init = &(struct clk_init_data) { 547 .name = "dspa_en_nic", 548 .ops = &clk_regmap_gate_ops, 549 .parent_hws = (const struct clk_hw *[]) { 550 &dspa_sel.hw 551 }, 552 .num_parents = 1, 553 .flags = CLK_SET_RATE_PARENT, 554 }, 555 }; 556 557 static struct clk_regmap dspb_a_sel = { 558 .data = &(struct clk_regmap_mux_data){ 559 .offset = DSPB_CLK_CTRL0, 560 .mask = 0x7, 561 .shift = 10, 562 .table = mux_table_dsp_ab, 563 }, 564 .hw.init = &(struct clk_init_data){ 565 .name = "dspb_a_sel", 566 .ops = &clk_regmap_mux_ops, 567 .parent_data = dsp_ab_parent_data, 568 .num_parents = ARRAY_SIZE(dsp_ab_parent_data), 569 }, 570 }; 571 572 static struct clk_regmap dspb_a_div = { 573 .data = &(struct clk_regmap_div_data){ 574 .offset = DSPB_CLK_CTRL0, 575 .shift = 0, 576 .width = 10, 577 }, 578 .hw.init = &(struct clk_init_data){ 579 .name = "dspb_a_div", 580 .ops = &clk_regmap_divider_ops, 581 .parent_hws = (const struct clk_hw *[]) { 582 &dspb_a_sel.hw 583 }, 584 .num_parents = 1, 585 .flags = CLK_SET_RATE_PARENT, 586 }, 587 }; 588 589 static struct clk_regmap dspb_a = { 590 .data = &(struct clk_regmap_gate_data){ 591 .offset = DSPB_CLK_CTRL0, 592 .bit_idx = 13, 593 }, 594 .hw.init = &(struct clk_init_data) { 595 .name = "dspb_a", 596 .ops = &clk_regmap_gate_ops, 597 .parent_hws = (const struct clk_hw *[]) { 598 &dspb_a_div.hw 599 }, 600 .num_parents = 1, 601 .flags = CLK_SET_RATE_PARENT, 602 }, 603 }; 604 605 static struct clk_regmap dspb_b_sel = { 606 .data = &(struct clk_regmap_mux_data){ 607 .offset = DSPB_CLK_CTRL0, 608 .mask = 0x7, 609 .shift = 26, 610 .table = mux_table_dsp_ab, 611 }, 612 .hw.init = &(struct clk_init_data){ 613 .name = "dspb_b_sel", 614 .ops = &clk_regmap_mux_ops, 615 .parent_data = dsp_ab_parent_data, 616 .num_parents = ARRAY_SIZE(dsp_ab_parent_data), 617 }, 618 }; 619 620 static struct clk_regmap dspb_b_div = { 621 .data = &(struct clk_regmap_div_data){ 622 .offset = DSPB_CLK_CTRL0, 623 .shift = 16, 624 .width = 10, 625 }, 626 .hw.init = &(struct clk_init_data){ 627 .name = "dspb_b_div", 628 .ops = &clk_regmap_divider_ops, 629 .parent_hws = (const struct clk_hw *[]) { 630 &dspb_b_sel.hw 631 }, 632 .num_parents = 1, 633 .flags = CLK_SET_RATE_PARENT, 634 }, 635 }; 636 637 static struct clk_regmap dspb_b = { 638 .data = &(struct clk_regmap_gate_data){ 639 .offset = DSPB_CLK_CTRL0, 640 .bit_idx = 29, 641 }, 642 .hw.init = &(struct clk_init_data) { 643 .name = "dspb_b", 644 .ops = &clk_regmap_gate_ops, 645 .parent_hws = (const struct clk_hw *[]) { 646 &dspb_b_div.hw 647 }, 648 .num_parents = 1, 649 .flags = CLK_SET_RATE_PARENT, 650 }, 651 }; 652 653 static struct clk_regmap dspb_sel = { 654 .data = &(struct clk_regmap_mux_data){ 655 .offset = DSPB_CLK_CTRL0, 656 .mask = 0x1, 657 .shift = 15, 658 }, 659 .hw.init = &(struct clk_init_data){ 660 .name = "dspb_sel", 661 .ops = &clk_regmap_mux_ops, 662 .parent_hws = (const struct clk_hw *[]) { 663 &dspb_a.hw, 664 &dspb_b.hw, 665 }, 666 .num_parents = 2, 667 .flags = CLK_SET_RATE_PARENT, 668 }, 669 }; 670 671 static struct clk_regmap dspb_en = { 672 .data = &(struct clk_regmap_gate_data){ 673 .offset = DSPB_CLK_EN, 674 .bit_idx = 1, 675 }, 676 .hw.init = &(struct clk_init_data) { 677 .name = "dspb_en", 678 .ops = &clk_regmap_gate_ops, 679 .parent_hws = (const struct clk_hw *[]) { 680 &dspb_sel.hw 681 }, 682 .num_parents = 1, 683 .flags = CLK_SET_RATE_PARENT, 684 }, 685 }; 686 687 static struct clk_regmap dspb_en_nic = { 688 .data = &(struct clk_regmap_gate_data){ 689 .offset = DSPB_CLK_EN, 690 .bit_idx = 0, 691 }, 692 .hw.init = &(struct clk_init_data) { 693 .name = "dspb_en_nic", 694 .ops = &clk_regmap_gate_ops, 695 .parent_hws = (const struct clk_hw *[]) { 696 &dspb_sel.hw 697 }, 698 .num_parents = 1, 699 .flags = CLK_SET_RATE_PARENT, 700 }, 701 }; 702 703 static struct clk_regmap clk_24m = { 704 .data = &(struct clk_regmap_gate_data){ 705 .offset = CLK12_24_CTRL, 706 .bit_idx = 11, 707 }, 708 .hw.init = &(struct clk_init_data) { 709 .name = "24m", 710 .ops = &clk_regmap_gate_ops, 711 .parent_data = &(const struct clk_parent_data) { 712 .fw_name = "xtal", 713 }, 714 .num_parents = 1, 715 }, 716 }; 717 718 static struct clk_fixed_factor clk_24m_div2 = { 719 .mult = 1, 720 .div = 2, 721 .hw.init = &(struct clk_init_data){ 722 .name = "24m_div2", 723 .ops = &clk_fixed_factor_ops, 724 .parent_hws = (const struct clk_hw *[]) { 725 &clk_24m.hw 726 }, 727 .num_parents = 1, 728 }, 729 }; 730 731 static struct clk_regmap clk_12m = { 732 .data = &(struct clk_regmap_gate_data){ 733 .offset = CLK12_24_CTRL, 734 .bit_idx = 10, 735 }, 736 .hw.init = &(struct clk_init_data) { 737 .name = "12m", 738 .ops = &clk_regmap_gate_ops, 739 .parent_hws = (const struct clk_hw *[]) { 740 &clk_24m_div2.hw 741 }, 742 .num_parents = 1, 743 }, 744 }; 745 746 static struct clk_regmap fclk_div2_divn_pre = { 747 .data = &(struct clk_regmap_div_data){ 748 .offset = CLK12_24_CTRL, 749 .shift = 0, 750 .width = 8, 751 }, 752 .hw.init = &(struct clk_init_data){ 753 .name = "fclk_div2_divn_pre", 754 .ops = &clk_regmap_divider_ops, 755 .parent_data = &(const struct clk_parent_data) { 756 .fw_name = "fclk_div2", 757 }, 758 .num_parents = 1, 759 }, 760 }; 761 762 static struct clk_regmap fclk_div2_divn = { 763 .data = &(struct clk_regmap_gate_data){ 764 .offset = CLK12_24_CTRL, 765 .bit_idx = 12, 766 }, 767 .hw.init = &(struct clk_init_data){ 768 .name = "fclk_div2_divn", 769 .ops = &clk_regmap_gate_ops, 770 .parent_hws = (const struct clk_hw *[]) { 771 &fclk_div2_divn_pre.hw 772 }, 773 .num_parents = 1, 774 .flags = CLK_SET_RATE_PARENT, 775 }, 776 }; 777 778 /* 779 * the index 2 is sys_pll_div16, it will be implemented in the CPU clock driver, 780 * the index 4 is the clock measurement source, it's not supported yet 781 */ 782 static u32 gen_table[] = { 0, 1, 3, 5, 6, 7, 8 }; 783 static const struct clk_parent_data gen_parent_data[] = { 784 { .fw_name = "xtal", }, 785 { .hw = &rtc.hw }, 786 { .fw_name = "hifi_pll", }, 787 { .fw_name = "fclk_div2", }, 788 { .fw_name = "fclk_div3", }, 789 { .fw_name = "fclk_div5", }, 790 { .fw_name = "fclk_div7", }, 791 }; 792 793 static struct clk_regmap gen_sel = { 794 .data = &(struct clk_regmap_mux_data){ 795 .offset = GEN_CLK_CTRL, 796 .mask = 0xf, 797 .shift = 12, 798 .table = gen_table, 799 }, 800 .hw.init = &(struct clk_init_data){ 801 .name = "gen_sel", 802 .ops = &clk_regmap_mux_ops, 803 .parent_data = gen_parent_data, 804 .num_parents = ARRAY_SIZE(gen_parent_data), 805 /* 806 * The GEN clock can be connected to an external pad, so it 807 * may be set up directly from the device tree. Additionally, 808 * the GEN clock can be inherited from a more accurate RTC 809 * clock, so in certain situations, it may be necessary 810 * to freeze its parent. 811 */ 812 .flags = CLK_SET_RATE_NO_REPARENT, 813 }, 814 }; 815 816 static struct clk_regmap gen_div = { 817 .data = &(struct clk_regmap_div_data){ 818 .offset = GEN_CLK_CTRL, 819 .shift = 0, 820 .width = 11, 821 }, 822 .hw.init = &(struct clk_init_data){ 823 .name = "gen_div", 824 .ops = &clk_regmap_divider_ops, 825 .parent_hws = (const struct clk_hw *[]) { 826 &gen_sel.hw 827 }, 828 .num_parents = 1, 829 .flags = CLK_SET_RATE_PARENT, 830 }, 831 }; 832 833 static struct clk_regmap gen = { 834 .data = &(struct clk_regmap_gate_data){ 835 .offset = GEN_CLK_CTRL, 836 .bit_idx = 11, 837 }, 838 .hw.init = &(struct clk_init_data) { 839 .name = "gen", 840 .ops = &clk_regmap_gate_ops, 841 .parent_hws = (const struct clk_hw *[]) { 842 &gen_div.hw 843 }, 844 .num_parents = 1, 845 .flags = CLK_SET_RATE_PARENT, 846 }, 847 }; 848 849 static struct clk_regmap saradc_sel = { 850 .data = &(struct clk_regmap_mux_data){ 851 .offset = SAR_ADC_CLK_CTRL, 852 .mask = 0x1, 853 .shift = 9, 854 }, 855 .hw.init = &(struct clk_init_data){ 856 .name = "saradc_sel", 857 .ops = &clk_regmap_mux_ops, 858 .parent_data = (const struct clk_parent_data []) { 859 { .fw_name = "xtal", }, 860 { .hw = &sys.hw, }, 861 }, 862 .num_parents = 2, 863 }, 864 }; 865 866 static struct clk_regmap saradc_div = { 867 .data = &(struct clk_regmap_div_data){ 868 .offset = SAR_ADC_CLK_CTRL, 869 .shift = 0, 870 .width = 8, 871 }, 872 .hw.init = &(struct clk_init_data){ 873 .name = "saradc_div", 874 .ops = &clk_regmap_divider_ops, 875 .parent_hws = (const struct clk_hw *[]) { 876 &saradc_sel.hw 877 }, 878 .num_parents = 1, 879 .flags = CLK_SET_RATE_PARENT, 880 }, 881 }; 882 883 static struct clk_regmap saradc = { 884 .data = &(struct clk_regmap_gate_data){ 885 .offset = SAR_ADC_CLK_CTRL, 886 .bit_idx = 8, 887 }, 888 .hw.init = &(struct clk_init_data) { 889 .name = "saradc", 890 .ops = &clk_regmap_gate_ops, 891 .parent_hws = (const struct clk_hw *[]) { 892 &saradc_div.hw 893 }, 894 .num_parents = 1, 895 .flags = CLK_SET_RATE_PARENT, 896 }, 897 }; 898 899 static const struct clk_parent_data pwm_abcd_parents[] = { 900 { .fw_name = "xtal", }, 901 { .hw = &sys.hw }, 902 { .hw = &rtc.hw }, 903 }; 904 905 static struct clk_regmap pwm_a_sel = { 906 .data = &(struct clk_regmap_mux_data){ 907 .offset = PWM_CLK_AB_CTRL, 908 .mask = 0x1, 909 .shift = 9, 910 }, 911 .hw.init = &(struct clk_init_data){ 912 .name = "pwm_a_sel", 913 .ops = &clk_regmap_mux_ops, 914 .parent_data = pwm_abcd_parents, 915 .num_parents = ARRAY_SIZE(pwm_abcd_parents), 916 }, 917 }; 918 919 static struct clk_regmap pwm_a_div = { 920 .data = &(struct clk_regmap_div_data){ 921 .offset = PWM_CLK_AB_CTRL, 922 .shift = 0, 923 .width = 8, 924 }, 925 .hw.init = &(struct clk_init_data){ 926 .name = "pwm_a_div", 927 .ops = &clk_regmap_divider_ops, 928 .parent_hws = (const struct clk_hw *[]) { 929 &pwm_a_sel.hw 930 }, 931 .num_parents = 1, 932 .flags = CLK_SET_RATE_PARENT, 933 }, 934 }; 935 936 static struct clk_regmap pwm_a = { 937 .data = &(struct clk_regmap_gate_data){ 938 .offset = PWM_CLK_AB_CTRL, 939 .bit_idx = 8, 940 }, 941 .hw.init = &(struct clk_init_data) { 942 .name = "pwm_a", 943 .ops = &clk_regmap_gate_ops, 944 .parent_hws = (const struct clk_hw *[]) { 945 &pwm_a_div.hw 946 }, 947 .num_parents = 1, 948 .flags = CLK_SET_RATE_PARENT, 949 }, 950 }; 951 952 static struct clk_regmap pwm_b_sel = { 953 .data = &(struct clk_regmap_mux_data){ 954 .offset = PWM_CLK_AB_CTRL, 955 .mask = 0x1, 956 .shift = 25, 957 }, 958 .hw.init = &(struct clk_init_data){ 959 .name = "pwm_b_sel", 960 .ops = &clk_regmap_mux_ops, 961 .parent_data = pwm_abcd_parents, 962 .num_parents = ARRAY_SIZE(pwm_abcd_parents), 963 }, 964 }; 965 966 static struct clk_regmap pwm_b_div = { 967 .data = &(struct clk_regmap_div_data){ 968 .offset = PWM_CLK_AB_CTRL, 969 .shift = 16, 970 .width = 8, 971 }, 972 .hw.init = &(struct clk_init_data){ 973 .name = "pwm_b_div", 974 .ops = &clk_regmap_divider_ops, 975 .parent_hws = (const struct clk_hw *[]) { 976 &pwm_b_sel.hw 977 }, 978 .num_parents = 1, 979 .flags = CLK_SET_RATE_PARENT, 980 }, 981 }; 982 983 static struct clk_regmap pwm_b = { 984 .data = &(struct clk_regmap_gate_data){ 985 .offset = PWM_CLK_AB_CTRL, 986 .bit_idx = 24, 987 }, 988 .hw.init = &(struct clk_init_data) { 989 .name = "pwm_b", 990 .ops = &clk_regmap_gate_ops, 991 .parent_hws = (const struct clk_hw *[]) { 992 &pwm_b_div.hw 993 }, 994 .num_parents = 1, 995 .flags = CLK_SET_RATE_PARENT, 996 }, 997 }; 998 999 static struct clk_regmap pwm_c_sel = { 1000 .data = &(struct clk_regmap_mux_data){ 1001 .offset = PWM_CLK_CD_CTRL, 1002 .mask = 0x1, 1003 .shift = 9, 1004 }, 1005 .hw.init = &(struct clk_init_data){ 1006 .name = "pwm_c_sel", 1007 .ops = &clk_regmap_mux_ops, 1008 .parent_data = pwm_abcd_parents, 1009 .num_parents = ARRAY_SIZE(pwm_abcd_parents), 1010 }, 1011 }; 1012 1013 static struct clk_regmap pwm_c_div = { 1014 .data = &(struct clk_regmap_div_data){ 1015 .offset = PWM_CLK_CD_CTRL, 1016 .shift = 0, 1017 .width = 8, 1018 }, 1019 .hw.init = &(struct clk_init_data){ 1020 .name = "pwm_c_div", 1021 .ops = &clk_regmap_divider_ops, 1022 .parent_hws = (const struct clk_hw *[]) { 1023 &pwm_c_sel.hw 1024 }, 1025 .num_parents = 1, 1026 .flags = CLK_SET_RATE_PARENT, 1027 }, 1028 }; 1029 1030 static struct clk_regmap pwm_c = { 1031 .data = &(struct clk_regmap_gate_data){ 1032 .offset = PWM_CLK_CD_CTRL, 1033 .bit_idx = 8, 1034 }, 1035 .hw.init = &(struct clk_init_data) { 1036 .name = "pwm_c", 1037 .ops = &clk_regmap_gate_ops, 1038 .parent_hws = (const struct clk_hw *[]) { 1039 &pwm_c_div.hw 1040 }, 1041 .num_parents = 1, 1042 .flags = CLK_SET_RATE_PARENT, 1043 }, 1044 }; 1045 1046 static struct clk_regmap pwm_d_sel = { 1047 .data = &(struct clk_regmap_mux_data){ 1048 .offset = PWM_CLK_CD_CTRL, 1049 .mask = 0x1, 1050 .shift = 25, 1051 }, 1052 .hw.init = &(struct clk_init_data){ 1053 .name = "pwm_d_sel", 1054 .ops = &clk_regmap_mux_ops, 1055 .parent_data = pwm_abcd_parents, 1056 .num_parents = ARRAY_SIZE(pwm_abcd_parents), 1057 }, 1058 }; 1059 1060 static struct clk_regmap pwm_d_div = { 1061 .data = &(struct clk_regmap_div_data){ 1062 .offset = PWM_CLK_CD_CTRL, 1063 .shift = 16, 1064 .width = 8, 1065 }, 1066 .hw.init = &(struct clk_init_data){ 1067 .name = "pwm_d_div", 1068 .ops = &clk_regmap_divider_ops, 1069 .parent_hws = (const struct clk_hw *[]) { 1070 &pwm_d_sel.hw 1071 }, 1072 .num_parents = 1, 1073 .flags = CLK_SET_RATE_PARENT, 1074 }, 1075 }; 1076 1077 static struct clk_regmap pwm_d = { 1078 .data = &(struct clk_regmap_gate_data){ 1079 .offset = PWM_CLK_CD_CTRL, 1080 .bit_idx = 24, 1081 }, 1082 .hw.init = &(struct clk_init_data) { 1083 .name = "pwm_d", 1084 .ops = &clk_regmap_gate_ops, 1085 .parent_hws = (const struct clk_hw *[]) { 1086 &pwm_d_div.hw 1087 }, 1088 .num_parents = 1, 1089 .flags = CLK_SET_RATE_PARENT, 1090 }, 1091 }; 1092 1093 static const struct clk_parent_data pwm_ef_parents[] = { 1094 { .fw_name = "xtal", }, 1095 { .hw = &sys.hw }, 1096 { .fw_name = "fclk_div5", }, 1097 { .hw = &rtc.hw }, 1098 }; 1099 1100 static struct clk_regmap pwm_e_sel = { 1101 .data = &(struct clk_regmap_mux_data){ 1102 .offset = PWM_CLK_EF_CTRL, 1103 .mask = 0x3, 1104 .shift = 9, 1105 }, 1106 .hw.init = &(struct clk_init_data){ 1107 .name = "pwm_e_sel", 1108 .ops = &clk_regmap_mux_ops, 1109 .parent_data = pwm_ef_parents, 1110 .num_parents = ARRAY_SIZE(pwm_ef_parents), 1111 }, 1112 }; 1113 1114 static struct clk_regmap pwm_e_div = { 1115 .data = &(struct clk_regmap_div_data){ 1116 .offset = PWM_CLK_EF_CTRL, 1117 .shift = 0, 1118 .width = 8, 1119 }, 1120 .hw.init = &(struct clk_init_data){ 1121 .name = "pwm_e_div", 1122 .ops = &clk_regmap_divider_ops, 1123 .parent_hws = (const struct clk_hw *[]) { 1124 &pwm_e_sel.hw 1125 }, 1126 .num_parents = 1, 1127 .flags = CLK_SET_RATE_PARENT, 1128 }, 1129 }; 1130 1131 static struct clk_regmap pwm_e = { 1132 .data = &(struct clk_regmap_gate_data){ 1133 .offset = PWM_CLK_EF_CTRL, 1134 .bit_idx = 8, 1135 }, 1136 .hw.init = &(struct clk_init_data) { 1137 .name = "pwm_e", 1138 .ops = &clk_regmap_gate_ops, 1139 .parent_hws = (const struct clk_hw *[]) { 1140 &pwm_e_div.hw 1141 }, 1142 .num_parents = 1, 1143 .flags = CLK_SET_RATE_PARENT, 1144 }, 1145 }; 1146 1147 static struct clk_regmap pwm_f_sel = { 1148 .data = &(struct clk_regmap_mux_data){ 1149 .offset = PWM_CLK_EF_CTRL, 1150 .mask = 0x3, 1151 .shift = 25, 1152 }, 1153 .hw.init = &(struct clk_init_data){ 1154 .name = "pwm_f_sel", 1155 .ops = &clk_regmap_mux_ops, 1156 .parent_data = pwm_ef_parents, 1157 .num_parents = ARRAY_SIZE(pwm_ef_parents), 1158 }, 1159 }; 1160 1161 static struct clk_regmap pwm_f_div = { 1162 .data = &(struct clk_regmap_div_data){ 1163 .offset = PWM_CLK_EF_CTRL, 1164 .shift = 16, 1165 .width = 8, 1166 }, 1167 .hw.init = &(struct clk_init_data){ 1168 .name = "pwm_f_div", 1169 .ops = &clk_regmap_divider_ops, 1170 .parent_hws = (const struct clk_hw *[]) { 1171 &pwm_f_sel.hw 1172 }, 1173 .num_parents = 1, 1174 .flags = CLK_SET_RATE_PARENT, 1175 }, 1176 }; 1177 1178 static struct clk_regmap pwm_f = { 1179 .data = &(struct clk_regmap_gate_data){ 1180 .offset = PWM_CLK_EF_CTRL, 1181 .bit_idx = 24, 1182 }, 1183 .hw.init = &(struct clk_init_data) { 1184 .name = "pwm_f", 1185 .ops = &clk_regmap_gate_ops, 1186 .parent_hws = (const struct clk_hw *[]) { 1187 &pwm_f_div.hw 1188 }, 1189 .num_parents = 1, 1190 .flags = CLK_SET_RATE_PARENT, 1191 }, 1192 }; 1193 1194 /* 1195 * spicc clk 1196 * fdiv2 |\ |\ _____ 1197 * ---------| |---DIV--| | | | spicc out 1198 * ---------| | | |-----|GATE |--------- 1199 * ..... |/ | / |_____| 1200 * --------------------|/ 1201 * 24M 1202 */ 1203 static const struct clk_parent_data spicc_spifc_parents[] = { 1204 { .fw_name = "fclk_div2"}, 1205 { .fw_name = "fclk_div3"}, 1206 { .fw_name = "fclk_div5"}, 1207 { .fw_name = "hifi_pll" }, 1208 }; 1209 1210 static struct clk_regmap spicc_sel = { 1211 .data = &(struct clk_regmap_mux_data){ 1212 .offset = SPICC_CLK_CTRL, 1213 .mask = 0x3, 1214 .shift = 9, 1215 }, 1216 .hw.init = &(struct clk_init_data){ 1217 .name = "spicc_sel", 1218 .ops = &clk_regmap_mux_ops, 1219 .parent_data = spicc_spifc_parents, 1220 .num_parents = ARRAY_SIZE(spicc_spifc_parents), 1221 }, 1222 }; 1223 1224 static struct clk_regmap spicc_div = { 1225 .data = &(struct clk_regmap_div_data){ 1226 .offset = SPICC_CLK_CTRL, 1227 .shift = 0, 1228 .width = 8, 1229 }, 1230 .hw.init = &(struct clk_init_data){ 1231 .name = "spicc_div", 1232 .ops = &clk_regmap_divider_ops, 1233 .parent_hws = (const struct clk_hw *[]) { 1234 &spicc_sel.hw 1235 }, 1236 .num_parents = 1, 1237 .flags = CLK_SET_RATE_PARENT, 1238 }, 1239 }; 1240 1241 static struct clk_regmap spicc_sel2 = { 1242 .data = &(struct clk_regmap_mux_data){ 1243 .offset = SPICC_CLK_CTRL, 1244 .mask = 0x1, 1245 .shift = 15, 1246 }, 1247 .hw.init = &(struct clk_init_data){ 1248 .name = "spicc_sel2", 1249 .ops = &clk_regmap_mux_ops, 1250 .parent_data = (const struct clk_parent_data []) { 1251 { .hw = &spicc_div.hw }, 1252 { .fw_name = "xtal", }, 1253 }, 1254 .num_parents = 2, 1255 .flags = CLK_SET_RATE_PARENT, 1256 }, 1257 }; 1258 1259 static struct clk_regmap spicc = { 1260 .data = &(struct clk_regmap_gate_data){ 1261 .offset = SPICC_CLK_CTRL, 1262 .bit_idx = 8, 1263 }, 1264 .hw.init = &(struct clk_init_data) { 1265 .name = "spicc", 1266 .ops = &clk_regmap_gate_ops, 1267 .parent_hws = (const struct clk_hw *[]) { 1268 &spicc_sel2.hw 1269 }, 1270 .num_parents = 1, 1271 .flags = CLK_SET_RATE_PARENT, 1272 }, 1273 }; 1274 1275 static struct clk_regmap ts_div = { 1276 .data = &(struct clk_regmap_div_data){ 1277 .offset = TS_CLK_CTRL, 1278 .shift = 0, 1279 .width = 8, 1280 }, 1281 .hw.init = &(struct clk_init_data){ 1282 .name = "ts_div", 1283 .ops = &clk_regmap_divider_ops, 1284 .parent_data = &(const struct clk_parent_data) { 1285 .fw_name = "xtal", 1286 }, 1287 .num_parents = 1, 1288 }, 1289 }; 1290 1291 static struct clk_regmap ts = { 1292 .data = &(struct clk_regmap_gate_data){ 1293 .offset = TS_CLK_CTRL, 1294 .bit_idx = 8, 1295 }, 1296 .hw.init = &(struct clk_init_data) { 1297 .name = "ts", 1298 .ops = &clk_regmap_gate_ops, 1299 .parent_hws = (const struct clk_hw *[]) { 1300 &ts_div.hw 1301 }, 1302 .num_parents = 1, 1303 .flags = CLK_SET_RATE_PARENT, 1304 }, 1305 }; 1306 1307 static struct clk_regmap spifc_sel = { 1308 .data = &(struct clk_regmap_mux_data){ 1309 .offset = SPIFC_CLK_CTRL, 1310 .mask = 0x3, 1311 .shift = 9, 1312 }, 1313 .hw.init = &(struct clk_init_data){ 1314 .name = "spifc_sel", 1315 .ops = &clk_regmap_mux_ops, 1316 .parent_data = spicc_spifc_parents, 1317 .num_parents = ARRAY_SIZE(spicc_spifc_parents), 1318 }, 1319 }; 1320 1321 static struct clk_regmap spifc_div = { 1322 .data = &(struct clk_regmap_div_data){ 1323 .offset = SPIFC_CLK_CTRL, 1324 .shift = 0, 1325 .width = 8, 1326 }, 1327 .hw.init = &(struct clk_init_data){ 1328 .name = "spifc_div", 1329 .ops = &clk_regmap_divider_ops, 1330 .parent_hws = (const struct clk_hw *[]) { 1331 &spifc_sel.hw 1332 }, 1333 .num_parents = 1, 1334 .flags = CLK_SET_RATE_PARENT, 1335 }, 1336 }; 1337 1338 static struct clk_regmap spifc_sel2 = { 1339 .data = &(struct clk_regmap_mux_data){ 1340 .offset = SPIFC_CLK_CTRL, 1341 .mask = 0x1, 1342 .shift = 15, 1343 }, 1344 .hw.init = &(struct clk_init_data){ 1345 .name = "spifc_sel2", 1346 .ops = &clk_regmap_mux_ops, 1347 .parent_data = (const struct clk_parent_data []) { 1348 { .hw = &spifc_div.hw }, 1349 { .fw_name = "xtal", }, 1350 }, 1351 .num_parents = 2, 1352 .flags = CLK_SET_RATE_PARENT, 1353 }, 1354 }; 1355 1356 static struct clk_regmap spifc = { 1357 .data = &(struct clk_regmap_gate_data){ 1358 .offset = SPIFC_CLK_CTRL, 1359 .bit_idx = 8, 1360 }, 1361 .hw.init = &(struct clk_init_data) { 1362 .name = "spifc", 1363 .ops = &clk_regmap_gate_ops, 1364 .parent_hws = (const struct clk_hw *[]) { 1365 &spifc_sel2.hw 1366 }, 1367 .num_parents = 1, 1368 .flags = CLK_SET_RATE_PARENT, 1369 }, 1370 }; 1371 1372 static const struct clk_parent_data usb_bus_parents[] = { 1373 { .fw_name = "xtal", }, 1374 { .hw = &sys.hw }, 1375 { .fw_name = "fclk_div3", }, 1376 { .fw_name = "fclk_div5", }, 1377 }; 1378 1379 static struct clk_regmap usb_bus_sel = { 1380 .data = &(struct clk_regmap_mux_data){ 1381 .offset = USB_BUSCLK_CTRL, 1382 .mask = 0x3, 1383 .shift = 9, 1384 }, 1385 .hw.init = &(struct clk_init_data){ 1386 .name = "usb_bus_sel", 1387 .ops = &clk_regmap_mux_ops, 1388 .parent_data = usb_bus_parents, 1389 .num_parents = ARRAY_SIZE(usb_bus_parents), 1390 .flags = CLK_SET_RATE_PARENT, 1391 }, 1392 }; 1393 1394 static struct clk_regmap usb_bus_div = { 1395 .data = &(struct clk_regmap_div_data){ 1396 .offset = USB_BUSCLK_CTRL, 1397 .shift = 0, 1398 .width = 8, 1399 }, 1400 .hw.init = &(struct clk_init_data){ 1401 .name = "usb_bus_div", 1402 .ops = &clk_regmap_divider_ops, 1403 .parent_hws = (const struct clk_hw *[]) { 1404 &usb_bus_sel.hw 1405 }, 1406 .num_parents = 1, 1407 .flags = CLK_SET_RATE_PARENT, 1408 }, 1409 }; 1410 1411 static struct clk_regmap usb_bus = { 1412 .data = &(struct clk_regmap_gate_data){ 1413 .offset = USB_BUSCLK_CTRL, 1414 .bit_idx = 8, 1415 }, 1416 .hw.init = &(struct clk_init_data) { 1417 .name = "usb_bus", 1418 .ops = &clk_regmap_gate_ops, 1419 .parent_hws = (const struct clk_hw *[]) { 1420 &usb_bus_div.hw 1421 }, 1422 .num_parents = 1, 1423 .flags = CLK_SET_RATE_PARENT, 1424 }, 1425 }; 1426 1427 static const struct clk_parent_data sd_emmc_psram_dmc_parents[] = { 1428 { .fw_name = "fclk_div2", }, 1429 { .fw_name = "fclk_div3", }, 1430 { .fw_name = "fclk_div5", }, 1431 { .fw_name = "hifi_pll", }, 1432 }; 1433 1434 static struct clk_regmap sd_emmc_sel = { 1435 .data = &(struct clk_regmap_mux_data){ 1436 .offset = SD_EMMC_CLK_CTRL, 1437 .mask = 0x3, 1438 .shift = 9, 1439 }, 1440 .hw.init = &(struct clk_init_data){ 1441 .name = "sd_emmc_sel", 1442 .ops = &clk_regmap_mux_ops, 1443 .parent_data = sd_emmc_psram_dmc_parents, 1444 .num_parents = ARRAY_SIZE(sd_emmc_psram_dmc_parents), 1445 }, 1446 }; 1447 1448 static struct clk_regmap sd_emmc_div = { 1449 .data = &(struct clk_regmap_div_data){ 1450 .offset = SD_EMMC_CLK_CTRL, 1451 .shift = 0, 1452 .width = 8, 1453 }, 1454 .hw.init = &(struct clk_init_data){ 1455 .name = "sd_emmc_div", 1456 .ops = &clk_regmap_divider_ops, 1457 .parent_hws = (const struct clk_hw *[]) { 1458 &sd_emmc_sel.hw 1459 }, 1460 .num_parents = 1, 1461 .flags = CLK_SET_RATE_PARENT, 1462 }, 1463 }; 1464 1465 static struct clk_regmap sd_emmc_sel2 = { 1466 .data = &(struct clk_regmap_mux_data){ 1467 .offset = SD_EMMC_CLK_CTRL, 1468 .mask = 0x1, 1469 .shift = 15, 1470 }, 1471 .hw.init = &(struct clk_init_data){ 1472 .name = "sd_emmc_sel2", 1473 .ops = &clk_regmap_mux_ops, 1474 .parent_data = (const struct clk_parent_data []) { 1475 { .hw = &sd_emmc_div.hw }, 1476 { .fw_name = "xtal", }, 1477 }, 1478 .num_parents = 2, 1479 .flags = CLK_SET_RATE_PARENT, 1480 }, 1481 }; 1482 1483 static struct clk_regmap sd_emmc = { 1484 .data = &(struct clk_regmap_gate_data){ 1485 .offset = SD_EMMC_CLK_CTRL, 1486 .bit_idx = 8, 1487 }, 1488 .hw.init = &(struct clk_init_data) { 1489 .name = "sd_emmc", 1490 .ops = &clk_regmap_gate_ops, 1491 .parent_hws = (const struct clk_hw *[]) { 1492 &sd_emmc_sel2.hw 1493 }, 1494 .num_parents = 1, 1495 .flags = CLK_SET_RATE_PARENT, 1496 }, 1497 }; 1498 1499 static struct clk_regmap psram_sel = { 1500 .data = &(struct clk_regmap_mux_data){ 1501 .offset = PSRAM_CLK_CTRL, 1502 .mask = 0x3, 1503 .shift = 9, 1504 }, 1505 .hw.init = &(struct clk_init_data){ 1506 .name = "psram_sel", 1507 .ops = &clk_regmap_mux_ops, 1508 .parent_data = sd_emmc_psram_dmc_parents, 1509 .num_parents = ARRAY_SIZE(sd_emmc_psram_dmc_parents), 1510 }, 1511 }; 1512 1513 static struct clk_regmap psram_div = { 1514 .data = &(struct clk_regmap_div_data){ 1515 .offset = PSRAM_CLK_CTRL, 1516 .shift = 0, 1517 .width = 8, 1518 }, 1519 .hw.init = &(struct clk_init_data){ 1520 .name = "psram_div", 1521 .ops = &clk_regmap_divider_ops, 1522 .parent_hws = (const struct clk_hw *[]) { 1523 &psram_sel.hw 1524 }, 1525 .num_parents = 1, 1526 .flags = CLK_SET_RATE_PARENT, 1527 }, 1528 }; 1529 1530 static struct clk_regmap psram_sel2 = { 1531 .data = &(struct clk_regmap_mux_data){ 1532 .offset = PSRAM_CLK_CTRL, 1533 .mask = 0x1, 1534 .shift = 15, 1535 }, 1536 .hw.init = &(struct clk_init_data){ 1537 .name = "psram_sel2", 1538 .ops = &clk_regmap_mux_ops, 1539 .parent_data = (const struct clk_parent_data []) { 1540 { .hw = &psram_div.hw }, 1541 { .fw_name = "xtal", }, 1542 }, 1543 .num_parents = 2, 1544 .flags = CLK_SET_RATE_PARENT, 1545 }, 1546 }; 1547 1548 static struct clk_regmap psram = { 1549 .data = &(struct clk_regmap_gate_data){ 1550 .offset = PSRAM_CLK_CTRL, 1551 .bit_idx = 8, 1552 }, 1553 .hw.init = &(struct clk_init_data) { 1554 .name = "psram", 1555 .ops = &clk_regmap_gate_ops, 1556 .parent_hws = (const struct clk_hw *[]) { 1557 &psram_sel2.hw 1558 }, 1559 .num_parents = 1, 1560 .flags = CLK_SET_RATE_PARENT, 1561 }, 1562 }; 1563 1564 static struct clk_regmap dmc_sel = { 1565 .data = &(struct clk_regmap_mux_data){ 1566 .offset = DMC_CLK_CTRL, 1567 .mask = 0x3, 1568 .shift = 9, 1569 }, 1570 .hw.init = &(struct clk_init_data){ 1571 .name = "dmc_sel", 1572 .ops = &clk_regmap_mux_ops, 1573 .parent_data = sd_emmc_psram_dmc_parents, 1574 .num_parents = ARRAY_SIZE(sd_emmc_psram_dmc_parents), 1575 }, 1576 }; 1577 1578 static struct clk_regmap dmc_div = { 1579 .data = &(struct clk_regmap_div_data){ 1580 .offset = DMC_CLK_CTRL, 1581 .shift = 0, 1582 .width = 8, 1583 }, 1584 .hw.init = &(struct clk_init_data){ 1585 .name = "dmc_div", 1586 .ops = &clk_regmap_divider_ops, 1587 .parent_hws = (const struct clk_hw *[]) { 1588 &dmc_sel.hw 1589 }, 1590 .num_parents = 1, 1591 .flags = CLK_SET_RATE_PARENT, 1592 }, 1593 }; 1594 1595 static struct clk_regmap dmc_sel2 = { 1596 .data = &(struct clk_regmap_mux_data){ 1597 .offset = DMC_CLK_CTRL, 1598 .mask = 0x1, 1599 .shift = 15, 1600 }, 1601 .hw.init = &(struct clk_init_data){ 1602 .name = "dmc_sel2", 1603 .ops = &clk_regmap_mux_ops, 1604 .parent_data = (const struct clk_parent_data []) { 1605 { .hw = &dmc_div.hw }, 1606 { .fw_name = "xtal", }, 1607 }, 1608 .num_parents = 2, 1609 .flags = CLK_SET_RATE_PARENT, 1610 }, 1611 }; 1612 1613 static struct clk_regmap dmc = { 1614 .data = &(struct clk_regmap_gate_data){ 1615 .offset = DMC_CLK_CTRL, 1616 .bit_idx = 8, 1617 }, 1618 .hw.init = &(struct clk_init_data) { 1619 .name = "dmc", 1620 .ops = &clk_regmap_gate_ro_ops, 1621 .parent_hws = (const struct clk_hw *[]) { 1622 &dmc_sel2.hw 1623 }, 1624 .num_parents = 1, 1625 .flags = CLK_SET_RATE_PARENT, 1626 }, 1627 }; 1628 1629 static struct clk_regmap ceca_32k_in = { 1630 .data = &(struct clk_regmap_gate_data){ 1631 .offset = CECA_CLK_CTRL0, 1632 .bit_idx = 31, 1633 }, 1634 .hw.init = &(struct clk_init_data) { 1635 .name = "ceca_32k_in", 1636 .ops = &clk_regmap_gate_ops, 1637 .parent_data = &(const struct clk_parent_data) { 1638 .fw_name = "xtal", 1639 }, 1640 .num_parents = 1, 1641 }, 1642 }; 1643 1644 static struct clk_regmap ceca_32k_div = { 1645 .data = &(struct meson_clk_dualdiv_data){ 1646 .n1 = { 1647 .reg_off = CECA_CLK_CTRL0, 1648 .shift = 0, 1649 .width = 12, 1650 }, 1651 .n2 = { 1652 .reg_off = CECA_CLK_CTRL0, 1653 .shift = 12, 1654 .width = 12, 1655 }, 1656 .m1 = { 1657 .reg_off = CECA_CLK_CTRL1, 1658 .shift = 0, 1659 .width = 12, 1660 }, 1661 .m2 = { 1662 .reg_off = CECA_CLK_CTRL1, 1663 .shift = 12, 1664 .width = 12, 1665 }, 1666 .dual = { 1667 .reg_off = CECA_CLK_CTRL0, 1668 .shift = 28, 1669 .width = 1, 1670 }, 1671 .table = clk_32k_div_table, 1672 }, 1673 .hw.init = &(struct clk_init_data){ 1674 .name = "ceca_32k_div", 1675 .ops = &meson_clk_dualdiv_ops, 1676 .parent_hws = (const struct clk_hw *[]) { 1677 &ceca_32k_in.hw 1678 }, 1679 .num_parents = 1, 1680 }, 1681 }; 1682 1683 static struct clk_regmap ceca_32k_sel_pre = { 1684 .data = &(struct clk_regmap_mux_data) { 1685 .offset = CECA_CLK_CTRL1, 1686 .mask = 0x1, 1687 .shift = 24, 1688 .flags = CLK_MUX_ROUND_CLOSEST, 1689 }, 1690 .hw.init = &(struct clk_init_data){ 1691 .name = "ceca_32k_sel_pre", 1692 .ops = &clk_regmap_mux_ops, 1693 .parent_hws = (const struct clk_hw *[]) { 1694 &ceca_32k_div.hw, 1695 &ceca_32k_in.hw, 1696 }, 1697 .num_parents = 2, 1698 .flags = CLK_SET_RATE_PARENT, 1699 }, 1700 }; 1701 1702 static struct clk_regmap ceca_32k_sel = { 1703 .data = &(struct clk_regmap_mux_data) { 1704 .offset = CECA_CLK_CTRL1, 1705 .mask = 0x1, 1706 .shift = 31, 1707 .flags = CLK_MUX_ROUND_CLOSEST, 1708 }, 1709 .hw.init = &(struct clk_init_data){ 1710 .name = "ceca_32k_sel", 1711 .ops = &clk_regmap_mux_ops, 1712 .parent_hws = (const struct clk_hw *[]) { 1713 &ceca_32k_sel_pre.hw, 1714 &rtc.hw, 1715 }, 1716 .num_parents = 2, 1717 }, 1718 }; 1719 1720 static struct clk_regmap ceca_32k_out = { 1721 .data = &(struct clk_regmap_gate_data){ 1722 .offset = CECA_CLK_CTRL0, 1723 .bit_idx = 30, 1724 }, 1725 .hw.init = &(struct clk_init_data){ 1726 .name = "ceca_32k_out", 1727 .ops = &clk_regmap_gate_ops, 1728 .parent_hws = (const struct clk_hw *[]) { 1729 &ceca_32k_sel.hw 1730 }, 1731 .num_parents = 1, 1732 .flags = CLK_SET_RATE_PARENT, 1733 }, 1734 }; 1735 1736 static struct clk_regmap cecb_32k_in = { 1737 .data = &(struct clk_regmap_gate_data){ 1738 .offset = CECB_CLK_CTRL0, 1739 .bit_idx = 31, 1740 }, 1741 .hw.init = &(struct clk_init_data) { 1742 .name = "cecb_32k_in", 1743 .ops = &clk_regmap_gate_ops, 1744 .parent_data = &(const struct clk_parent_data) { 1745 .fw_name = "xtal", 1746 }, 1747 .num_parents = 1, 1748 }, 1749 }; 1750 1751 static struct clk_regmap cecb_32k_div = { 1752 .data = &(struct meson_clk_dualdiv_data){ 1753 .n1 = { 1754 .reg_off = CECB_CLK_CTRL0, 1755 .shift = 0, 1756 .width = 12, 1757 }, 1758 .n2 = { 1759 .reg_off = CECB_CLK_CTRL0, 1760 .shift = 12, 1761 .width = 12, 1762 }, 1763 .m1 = { 1764 .reg_off = CECB_CLK_CTRL1, 1765 .shift = 0, 1766 .width = 12, 1767 }, 1768 .m2 = { 1769 .reg_off = CECB_CLK_CTRL1, 1770 .shift = 12, 1771 .width = 12, 1772 }, 1773 .dual = { 1774 .reg_off = CECB_CLK_CTRL0, 1775 .shift = 28, 1776 .width = 1, 1777 }, 1778 .table = clk_32k_div_table, 1779 }, 1780 .hw.init = &(struct clk_init_data){ 1781 .name = "cecb_32k_div", 1782 .ops = &meson_clk_dualdiv_ops, 1783 .parent_hws = (const struct clk_hw *[]) { 1784 &cecb_32k_in.hw 1785 }, 1786 .num_parents = 1, 1787 }, 1788 }; 1789 1790 static struct clk_regmap cecb_32k_sel_pre = { 1791 .data = &(struct clk_regmap_mux_data) { 1792 .offset = CECB_CLK_CTRL1, 1793 .mask = 0x1, 1794 .shift = 24, 1795 .flags = CLK_MUX_ROUND_CLOSEST, 1796 }, 1797 .hw.init = &(struct clk_init_data){ 1798 .name = "cecb_32k_sel_pre", 1799 .ops = &clk_regmap_mux_ops, 1800 .parent_hws = (const struct clk_hw *[]) { 1801 &cecb_32k_div.hw, 1802 &cecb_32k_in.hw, 1803 }, 1804 .num_parents = 2, 1805 .flags = CLK_SET_RATE_PARENT, 1806 }, 1807 }; 1808 1809 static struct clk_regmap cecb_32k_sel = { 1810 .data = &(struct clk_regmap_mux_data) { 1811 .offset = CECB_CLK_CTRL1, 1812 .mask = 0x1, 1813 .shift = 31, 1814 .flags = CLK_MUX_ROUND_CLOSEST, 1815 }, 1816 .hw.init = &(struct clk_init_data){ 1817 .name = "cecb_32k_sel", 1818 .ops = &clk_regmap_mux_ops, 1819 .parent_hws = (const struct clk_hw *[]) { 1820 &cecb_32k_sel_pre.hw, 1821 &rtc.hw, 1822 }, 1823 .num_parents = 2, 1824 }, 1825 }; 1826 1827 static struct clk_regmap cecb_32k_out = { 1828 .data = &(struct clk_regmap_gate_data){ 1829 .offset = CECB_CLK_CTRL0, 1830 .bit_idx = 30, 1831 }, 1832 .hw.init = &(struct clk_init_data){ 1833 .name = "cecb_32k_out", 1834 .ops = &clk_regmap_gate_ops, 1835 .parent_hws = (const struct clk_hw *[]) { 1836 &cecb_32k_sel.hw 1837 }, 1838 .num_parents = 1, 1839 .flags = CLK_SET_RATE_PARENT, 1840 }, 1841 }; 1842 1843 #define MESON_GATE(_name, _reg, _bit) \ 1844 MESON_PCLK(_name, _reg, _bit, &sys.hw) 1845 1846 static MESON_GATE(clktree, SYS_CLK_EN0, 0); 1847 static MESON_GATE(reset_ctrl, SYS_CLK_EN0, 1); 1848 static MESON_GATE(analog_ctrl, SYS_CLK_EN0, 2); 1849 static MESON_GATE(pwr_ctrl, SYS_CLK_EN0, 3); 1850 static MESON_GATE(pad_ctrl, SYS_CLK_EN0, 4); 1851 static MESON_GATE(sys_ctrl, SYS_CLK_EN0, 5); 1852 static MESON_GATE(temp_sensor, SYS_CLK_EN0, 6); 1853 static MESON_GATE(am2axi_dev, SYS_CLK_EN0, 7); 1854 static MESON_GATE(spicc_b, SYS_CLK_EN0, 8); 1855 static MESON_GATE(spicc_a, SYS_CLK_EN0, 9); 1856 static MESON_GATE(msr, SYS_CLK_EN0, 10); 1857 static MESON_GATE(audio, SYS_CLK_EN0, 11); 1858 static MESON_GATE(jtag_ctrl, SYS_CLK_EN0, 12); 1859 static MESON_GATE(saradc_en, SYS_CLK_EN0, 13); 1860 static MESON_GATE(pwm_ef, SYS_CLK_EN0, 14); 1861 static MESON_GATE(pwm_cd, SYS_CLK_EN0, 15); 1862 static MESON_GATE(pwm_ab, SYS_CLK_EN0, 16); 1863 static MESON_GATE(cec, SYS_CLK_EN0, 17); 1864 static MESON_GATE(i2c_s, SYS_CLK_EN0, 18); 1865 static MESON_GATE(ir_ctrl, SYS_CLK_EN0, 19); 1866 static MESON_GATE(i2c_m_d, SYS_CLK_EN0, 20); 1867 static MESON_GATE(i2c_m_c, SYS_CLK_EN0, 21); 1868 static MESON_GATE(i2c_m_b, SYS_CLK_EN0, 22); 1869 static MESON_GATE(i2c_m_a, SYS_CLK_EN0, 23); 1870 static MESON_GATE(acodec, SYS_CLK_EN0, 24); 1871 static MESON_GATE(otp, SYS_CLK_EN0, 25); 1872 static MESON_GATE(sd_emmc_a, SYS_CLK_EN0, 26); 1873 static MESON_GATE(usb_phy, SYS_CLK_EN0, 27); 1874 static MESON_GATE(usb_ctrl, SYS_CLK_EN0, 28); 1875 static MESON_GATE(sys_dspb, SYS_CLK_EN0, 29); 1876 static MESON_GATE(sys_dspa, SYS_CLK_EN0, 30); 1877 static MESON_GATE(dma, SYS_CLK_EN0, 31); 1878 static MESON_GATE(irq_ctrl, SYS_CLK_EN1, 0); 1879 static MESON_GATE(nic, SYS_CLK_EN1, 1); 1880 static MESON_GATE(gic, SYS_CLK_EN1, 2); 1881 static MESON_GATE(uart_c, SYS_CLK_EN1, 3); 1882 static MESON_GATE(uart_b, SYS_CLK_EN1, 4); 1883 static MESON_GATE(uart_a, SYS_CLK_EN1, 5); 1884 static MESON_GATE(sys_psram, SYS_CLK_EN1, 6); 1885 static MESON_GATE(rsa, SYS_CLK_EN1, 8); 1886 static MESON_GATE(coresight, SYS_CLK_EN1, 9); 1887 static MESON_GATE(am2axi_vad, AXI_CLK_EN, 0); 1888 static MESON_GATE(audio_vad, AXI_CLK_EN, 1); 1889 static MESON_GATE(axi_dmc, AXI_CLK_EN, 3); 1890 static MESON_GATE(axi_psram, AXI_CLK_EN, 4); 1891 static MESON_GATE(ramb, AXI_CLK_EN, 5); 1892 static MESON_GATE(rama, AXI_CLK_EN, 6); 1893 static MESON_GATE(axi_spifc, AXI_CLK_EN, 7); 1894 static MESON_GATE(axi_nic, AXI_CLK_EN, 8); 1895 static MESON_GATE(axi_dma, AXI_CLK_EN, 9); 1896 static MESON_GATE(cpu_ctrl, AXI_CLK_EN, 10); 1897 static MESON_GATE(rom, AXI_CLK_EN, 11); 1898 static MESON_GATE(prod_i2c, AXI_CLK_EN, 12); 1899 1900 /* Array of all clocks registered by this provider */ 1901 static struct clk_hw *a1_periphs_hw_clks[] = { 1902 [CLKID_XTAL_IN] = &xtal_in.hw, 1903 [CLKID_FIXPLL_IN] = &fixpll_in.hw, 1904 [CLKID_USB_PHY_IN] = &usb_phy_in.hw, 1905 [CLKID_USB_CTRL_IN] = &usb_ctrl_in.hw, 1906 [CLKID_HIFIPLL_IN] = &hifipll_in.hw, 1907 [CLKID_SYSPLL_IN] = &syspll_in.hw, 1908 [CLKID_DDS_IN] = &dds_in.hw, 1909 [CLKID_SYS] = &sys.hw, 1910 [CLKID_CLKTREE] = &clktree.hw, 1911 [CLKID_RESET_CTRL] = &reset_ctrl.hw, 1912 [CLKID_ANALOG_CTRL] = &analog_ctrl.hw, 1913 [CLKID_PWR_CTRL] = &pwr_ctrl.hw, 1914 [CLKID_PAD_CTRL] = &pad_ctrl.hw, 1915 [CLKID_SYS_CTRL] = &sys_ctrl.hw, 1916 [CLKID_TEMP_SENSOR] = &temp_sensor.hw, 1917 [CLKID_AM2AXI_DIV] = &am2axi_dev.hw, 1918 [CLKID_SPICC_B] = &spicc_b.hw, 1919 [CLKID_SPICC_A] = &spicc_a.hw, 1920 [CLKID_MSR] = &msr.hw, 1921 [CLKID_AUDIO] = &audio.hw, 1922 [CLKID_JTAG_CTRL] = &jtag_ctrl.hw, 1923 [CLKID_SARADC_EN] = &saradc_en.hw, 1924 [CLKID_PWM_EF] = &pwm_ef.hw, 1925 [CLKID_PWM_CD] = &pwm_cd.hw, 1926 [CLKID_PWM_AB] = &pwm_ab.hw, 1927 [CLKID_CEC] = &cec.hw, 1928 [CLKID_I2C_S] = &i2c_s.hw, 1929 [CLKID_IR_CTRL] = &ir_ctrl.hw, 1930 [CLKID_I2C_M_D] = &i2c_m_d.hw, 1931 [CLKID_I2C_M_C] = &i2c_m_c.hw, 1932 [CLKID_I2C_M_B] = &i2c_m_b.hw, 1933 [CLKID_I2C_M_A] = &i2c_m_a.hw, 1934 [CLKID_ACODEC] = &acodec.hw, 1935 [CLKID_OTP] = &otp.hw, 1936 [CLKID_SD_EMMC_A] = &sd_emmc_a.hw, 1937 [CLKID_USB_PHY] = &usb_phy.hw, 1938 [CLKID_USB_CTRL] = &usb_ctrl.hw, 1939 [CLKID_SYS_DSPB] = &sys_dspb.hw, 1940 [CLKID_SYS_DSPA] = &sys_dspa.hw, 1941 [CLKID_DMA] = &dma.hw, 1942 [CLKID_IRQ_CTRL] = &irq_ctrl.hw, 1943 [CLKID_NIC] = &nic.hw, 1944 [CLKID_GIC] = &gic.hw, 1945 [CLKID_UART_C] = &uart_c.hw, 1946 [CLKID_UART_B] = &uart_b.hw, 1947 [CLKID_UART_A] = &uart_a.hw, 1948 [CLKID_SYS_PSRAM] = &sys_psram.hw, 1949 [CLKID_RSA] = &rsa.hw, 1950 [CLKID_CORESIGHT] = &coresight.hw, 1951 [CLKID_AM2AXI_VAD] = &am2axi_vad.hw, 1952 [CLKID_AUDIO_VAD] = &audio_vad.hw, 1953 [CLKID_AXI_DMC] = &axi_dmc.hw, 1954 [CLKID_AXI_PSRAM] = &axi_psram.hw, 1955 [CLKID_RAMB] = &ramb.hw, 1956 [CLKID_RAMA] = &rama.hw, 1957 [CLKID_AXI_SPIFC] = &axi_spifc.hw, 1958 [CLKID_AXI_NIC] = &axi_nic.hw, 1959 [CLKID_AXI_DMA] = &axi_dma.hw, 1960 [CLKID_CPU_CTRL] = &cpu_ctrl.hw, 1961 [CLKID_ROM] = &rom.hw, 1962 [CLKID_PROC_I2C] = &prod_i2c.hw, 1963 [CLKID_DSPA_SEL] = &dspa_sel.hw, 1964 [CLKID_DSPB_SEL] = &dspb_sel.hw, 1965 [CLKID_DSPA_EN] = &dspa_en.hw, 1966 [CLKID_DSPA_EN_NIC] = &dspa_en_nic.hw, 1967 [CLKID_DSPB_EN] = &dspb_en.hw, 1968 [CLKID_DSPB_EN_NIC] = &dspb_en_nic.hw, 1969 [CLKID_RTC] = &rtc.hw, 1970 [CLKID_CECA_32K] = &ceca_32k_out.hw, 1971 [CLKID_CECB_32K] = &cecb_32k_out.hw, 1972 [CLKID_24M] = &clk_24m.hw, 1973 [CLKID_12M] = &clk_12m.hw, 1974 [CLKID_FCLK_DIV2_DIVN] = &fclk_div2_divn.hw, 1975 [CLKID_GEN] = &gen.hw, 1976 [CLKID_SARADC_SEL] = &saradc_sel.hw, 1977 [CLKID_SARADC] = &saradc.hw, 1978 [CLKID_PWM_A] = &pwm_a.hw, 1979 [CLKID_PWM_B] = &pwm_b.hw, 1980 [CLKID_PWM_C] = &pwm_c.hw, 1981 [CLKID_PWM_D] = &pwm_d.hw, 1982 [CLKID_PWM_E] = &pwm_e.hw, 1983 [CLKID_PWM_F] = &pwm_f.hw, 1984 [CLKID_SPICC] = &spicc.hw, 1985 [CLKID_TS] = &ts.hw, 1986 [CLKID_SPIFC] = &spifc.hw, 1987 [CLKID_USB_BUS] = &usb_bus.hw, 1988 [CLKID_SD_EMMC] = &sd_emmc.hw, 1989 [CLKID_PSRAM] = &psram.hw, 1990 [CLKID_DMC] = &dmc.hw, 1991 [CLKID_SYS_A_SEL] = &sys_a_sel.hw, 1992 [CLKID_SYS_A_DIV] = &sys_a_div.hw, 1993 [CLKID_SYS_A] = &sys_a.hw, 1994 [CLKID_SYS_B_SEL] = &sys_b_sel.hw, 1995 [CLKID_SYS_B_DIV] = &sys_b_div.hw, 1996 [CLKID_SYS_B] = &sys_b.hw, 1997 [CLKID_DSPA_A_SEL] = &dspa_a_sel.hw, 1998 [CLKID_DSPA_A_DIV] = &dspa_a_div.hw, 1999 [CLKID_DSPA_A] = &dspa_a.hw, 2000 [CLKID_DSPA_B_SEL] = &dspa_b_sel.hw, 2001 [CLKID_DSPA_B_DIV] = &dspa_b_div.hw, 2002 [CLKID_DSPA_B] = &dspa_b.hw, 2003 [CLKID_DSPB_A_SEL] = &dspb_a_sel.hw, 2004 [CLKID_DSPB_A_DIV] = &dspb_a_div.hw, 2005 [CLKID_DSPB_A] = &dspb_a.hw, 2006 [CLKID_DSPB_B_SEL] = &dspb_b_sel.hw, 2007 [CLKID_DSPB_B_DIV] = &dspb_b_div.hw, 2008 [CLKID_DSPB_B] = &dspb_b.hw, 2009 [CLKID_RTC_32K_IN] = &rtc_32k_in.hw, 2010 [CLKID_RTC_32K_DIV] = &rtc_32k_div.hw, 2011 [CLKID_RTC_32K_XTAL] = &rtc_32k_xtal.hw, 2012 [CLKID_RTC_32K_SEL] = &rtc_32k_sel.hw, 2013 [CLKID_CECB_32K_IN] = &cecb_32k_in.hw, 2014 [CLKID_CECB_32K_DIV] = &cecb_32k_div.hw, 2015 [CLKID_CECB_32K_SEL_PRE] = &cecb_32k_sel_pre.hw, 2016 [CLKID_CECB_32K_SEL] = &cecb_32k_sel.hw, 2017 [CLKID_CECA_32K_IN] = &ceca_32k_in.hw, 2018 [CLKID_CECA_32K_DIV] = &ceca_32k_div.hw, 2019 [CLKID_CECA_32K_SEL_PRE] = &ceca_32k_sel_pre.hw, 2020 [CLKID_CECA_32K_SEL] = &ceca_32k_sel.hw, 2021 [CLKID_DIV2_PRE] = &fclk_div2_divn_pre.hw, 2022 [CLKID_24M_DIV2] = &clk_24m_div2.hw, 2023 [CLKID_GEN_SEL] = &gen_sel.hw, 2024 [CLKID_GEN_DIV] = &gen_div.hw, 2025 [CLKID_SARADC_DIV] = &saradc_div.hw, 2026 [CLKID_PWM_A_SEL] = &pwm_a_sel.hw, 2027 [CLKID_PWM_A_DIV] = &pwm_a_div.hw, 2028 [CLKID_PWM_B_SEL] = &pwm_b_sel.hw, 2029 [CLKID_PWM_B_DIV] = &pwm_b_div.hw, 2030 [CLKID_PWM_C_SEL] = &pwm_c_sel.hw, 2031 [CLKID_PWM_C_DIV] = &pwm_c_div.hw, 2032 [CLKID_PWM_D_SEL] = &pwm_d_sel.hw, 2033 [CLKID_PWM_D_DIV] = &pwm_d_div.hw, 2034 [CLKID_PWM_E_SEL] = &pwm_e_sel.hw, 2035 [CLKID_PWM_E_DIV] = &pwm_e_div.hw, 2036 [CLKID_PWM_F_SEL] = &pwm_f_sel.hw, 2037 [CLKID_PWM_F_DIV] = &pwm_f_div.hw, 2038 [CLKID_SPICC_SEL] = &spicc_sel.hw, 2039 [CLKID_SPICC_DIV] = &spicc_div.hw, 2040 [CLKID_SPICC_SEL2] = &spicc_sel2.hw, 2041 [CLKID_TS_DIV] = &ts_div.hw, 2042 [CLKID_SPIFC_SEL] = &spifc_sel.hw, 2043 [CLKID_SPIFC_DIV] = &spifc_div.hw, 2044 [CLKID_SPIFC_SEL2] = &spifc_sel2.hw, 2045 [CLKID_USB_BUS_SEL] = &usb_bus_sel.hw, 2046 [CLKID_USB_BUS_DIV] = &usb_bus_div.hw, 2047 [CLKID_SD_EMMC_SEL] = &sd_emmc_sel.hw, 2048 [CLKID_SD_EMMC_DIV] = &sd_emmc_div.hw, 2049 [CLKID_SD_EMMC_SEL2] = &sd_emmc_sel2.hw, 2050 [CLKID_PSRAM_SEL] = &psram_sel.hw, 2051 [CLKID_PSRAM_DIV] = &psram_div.hw, 2052 [CLKID_PSRAM_SEL2] = &psram_sel2.hw, 2053 [CLKID_DMC_SEL] = &dmc_sel.hw, 2054 [CLKID_DMC_DIV] = &dmc_div.hw, 2055 [CLKID_DMC_SEL2] = &dmc_sel2.hw, 2056 }; 2057 2058 static const struct regmap_config a1_periphs_regmap_cfg = { 2059 .reg_bits = 32, 2060 .val_bits = 32, 2061 .reg_stride = 4, 2062 .max_register = DMC_CLK_CTRL, 2063 }; 2064 2065 static struct meson_clk_hw_data a1_periphs_clks = { 2066 .hws = a1_periphs_hw_clks, 2067 .num = ARRAY_SIZE(a1_periphs_hw_clks), 2068 }; 2069 2070 static int meson_a1_periphs_probe(struct platform_device *pdev) 2071 { 2072 struct device *dev = &pdev->dev; 2073 void __iomem *base; 2074 struct regmap *map; 2075 int clkid, err; 2076 2077 base = devm_platform_ioremap_resource(pdev, 0); 2078 if (IS_ERR(base)) 2079 return dev_err_probe(dev, PTR_ERR(base), 2080 "can't ioremap resource\n"); 2081 2082 map = devm_regmap_init_mmio(dev, base, &a1_periphs_regmap_cfg); 2083 if (IS_ERR(map)) 2084 return dev_err_probe(dev, PTR_ERR(map), 2085 "can't init regmap mmio region\n"); 2086 2087 for (clkid = 0; clkid < a1_periphs_clks.num; clkid++) { 2088 err = devm_clk_hw_register(dev, a1_periphs_clks.hws[clkid]); 2089 if (err) 2090 return dev_err_probe(dev, err, 2091 "clock[%d] registration failed\n", 2092 clkid); 2093 } 2094 2095 return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &a1_periphs_clks); 2096 } 2097 2098 static const struct of_device_id a1_periphs_clkc_match_table[] = { 2099 { .compatible = "amlogic,a1-peripherals-clkc", }, 2100 {} 2101 }; 2102 MODULE_DEVICE_TABLE(of, a1_periphs_clkc_match_table); 2103 2104 static struct platform_driver a1_periphs_clkc_driver = { 2105 .probe = meson_a1_periphs_probe, 2106 .driver = { 2107 .name = "a1-peripherals-clkc", 2108 .of_match_table = a1_periphs_clkc_match_table, 2109 }, 2110 }; 2111 module_platform_driver(a1_periphs_clkc_driver); 2112 2113 MODULE_DESCRIPTION("Amlogic A1 Peripherals Clock Controller driver"); 2114 MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>"); 2115 MODULE_AUTHOR("Dmitry Rokosov <ddrokosov@sberdevices.ru>"); 2116 MODULE_LICENSE("GPL"); 2117 MODULE_IMPORT_NS("CLK_MESON"); 2118