1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved. 4 * Author: Jian Hu <jian.hu@amlogic.com> 5 * 6 * Copyright (c) 2023, SberDevices. All Rights Reserved. 7 * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru> 8 */ 9 10 #include <linux/clk-provider.h> 11 #include <linux/platform_device.h> 12 #include "clk-dualdiv.h" 13 #include "clk-regmap.h" 14 #include "meson-clkc-utils.h" 15 16 #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h> 17 18 #define SYS_OSCIN_CTRL 0x0 19 #define RTC_BY_OSCIN_CTRL0 0x4 20 #define RTC_BY_OSCIN_CTRL1 0x8 21 #define RTC_CTRL 0xc 22 #define SYS_CLK_CTRL0 0x10 23 #define SYS_CLK_EN0 0x1c 24 #define SYS_CLK_EN1 0x20 25 #define AXI_CLK_EN 0x24 26 #define DSPA_CLK_EN 0x28 27 #define DSPB_CLK_EN 0x2c 28 #define DSPA_CLK_CTRL0 0x30 29 #define DSPB_CLK_CTRL0 0x34 30 #define CLK12_24_CTRL 0x38 31 #define GEN_CLK_CTRL 0x3c 32 #define SAR_ADC_CLK_CTRL 0xc0 33 #define PWM_CLK_AB_CTRL 0xc4 34 #define PWM_CLK_CD_CTRL 0xc8 35 #define PWM_CLK_EF_CTRL 0xcc 36 #define SPICC_CLK_CTRL 0xd0 37 #define TS_CLK_CTRL 0xd4 38 #define SPIFC_CLK_CTRL 0xd8 39 #define USB_BUSCLK_CTRL 0xdc 40 #define SD_EMMC_CLK_CTRL 0xe0 41 #define CECA_CLK_CTRL0 0xe4 42 #define CECA_CLK_CTRL1 0xe8 43 #define CECB_CLK_CTRL0 0xec 44 #define CECB_CLK_CTRL1 0xf0 45 #define PSRAM_CLK_CTRL 0xf4 46 #define DMC_CLK_CTRL 0xf8 47 48 static struct clk_regmap a1_xtal_in = { 49 .data = &(struct clk_regmap_gate_data){ 50 .offset = SYS_OSCIN_CTRL, 51 .bit_idx = 0, 52 }, 53 .hw.init = &(struct clk_init_data) { 54 .name = "xtal_in", 55 .ops = &clk_regmap_gate_ro_ops, 56 .parent_data = &(const struct clk_parent_data) { 57 .fw_name = "xtal", 58 }, 59 .num_parents = 1, 60 }, 61 }; 62 63 static struct clk_regmap a1_fixpll_in = { 64 .data = &(struct clk_regmap_gate_data){ 65 .offset = SYS_OSCIN_CTRL, 66 .bit_idx = 1, 67 }, 68 .hw.init = &(struct clk_init_data) { 69 .name = "fixpll_in", 70 .ops = &clk_regmap_gate_ro_ops, 71 .parent_data = &(const struct clk_parent_data) { 72 .fw_name = "xtal", 73 }, 74 .num_parents = 1, 75 }, 76 }; 77 78 static struct clk_regmap a1_usb_phy_in = { 79 .data = &(struct clk_regmap_gate_data){ 80 .offset = SYS_OSCIN_CTRL, 81 .bit_idx = 2, 82 }, 83 .hw.init = &(struct clk_init_data) { 84 .name = "usb_phy_in", 85 .ops = &clk_regmap_gate_ops, 86 .parent_data = &(const struct clk_parent_data) { 87 .fw_name = "xtal", 88 }, 89 .num_parents = 1, 90 }, 91 }; 92 93 static struct clk_regmap a1_usb_ctrl_in = { 94 .data = &(struct clk_regmap_gate_data){ 95 .offset = SYS_OSCIN_CTRL, 96 .bit_idx = 3, 97 }, 98 .hw.init = &(struct clk_init_data) { 99 .name = "usb_ctrl_in", 100 .ops = &clk_regmap_gate_ops, 101 .parent_data = &(const struct clk_parent_data) { 102 .fw_name = "xtal", 103 }, 104 .num_parents = 1, 105 }, 106 }; 107 108 static struct clk_regmap a1_hifipll_in = { 109 .data = &(struct clk_regmap_gate_data){ 110 .offset = SYS_OSCIN_CTRL, 111 .bit_idx = 4, 112 }, 113 .hw.init = &(struct clk_init_data) { 114 .name = "hifipll_in", 115 .ops = &clk_regmap_gate_ops, 116 .parent_data = &(const struct clk_parent_data) { 117 .fw_name = "xtal", 118 }, 119 .num_parents = 1, 120 }, 121 }; 122 123 static struct clk_regmap a1_syspll_in = { 124 .data = &(struct clk_regmap_gate_data){ 125 .offset = SYS_OSCIN_CTRL, 126 .bit_idx = 5, 127 }, 128 .hw.init = &(struct clk_init_data) { 129 .name = "syspll_in", 130 .ops = &clk_regmap_gate_ops, 131 .parent_data = &(const struct clk_parent_data) { 132 .fw_name = "xtal", 133 }, 134 .num_parents = 1, 135 }, 136 }; 137 138 static struct clk_regmap a1_dds_in = { 139 .data = &(struct clk_regmap_gate_data){ 140 .offset = SYS_OSCIN_CTRL, 141 .bit_idx = 6, 142 }, 143 .hw.init = &(struct clk_init_data) { 144 .name = "dds_in", 145 .ops = &clk_regmap_gate_ops, 146 .parent_data = &(const struct clk_parent_data) { 147 .fw_name = "xtal", 148 }, 149 .num_parents = 1, 150 }, 151 }; 152 153 static struct clk_regmap a1_rtc_32k_in = { 154 .data = &(struct clk_regmap_gate_data){ 155 .offset = RTC_BY_OSCIN_CTRL0, 156 .bit_idx = 31, 157 }, 158 .hw.init = &(struct clk_init_data) { 159 .name = "rtc_32k_in", 160 .ops = &clk_regmap_gate_ops, 161 .parent_data = &(const struct clk_parent_data) { 162 .fw_name = "xtal", 163 }, 164 .num_parents = 1, 165 }, 166 }; 167 168 static const struct meson_clk_dualdiv_param a1_32k_div_table[] = { 169 { 170 .dual = 1, 171 .n1 = 733, 172 .m1 = 8, 173 .n2 = 732, 174 .m2 = 11, 175 }, 176 {} 177 }; 178 179 static struct clk_regmap a1_rtc_32k_div = { 180 .data = &(struct meson_clk_dualdiv_data){ 181 .n1 = { 182 .reg_off = RTC_BY_OSCIN_CTRL0, 183 .shift = 0, 184 .width = 12, 185 }, 186 .n2 = { 187 .reg_off = RTC_BY_OSCIN_CTRL0, 188 .shift = 12, 189 .width = 12, 190 }, 191 .m1 = { 192 .reg_off = RTC_BY_OSCIN_CTRL1, 193 .shift = 0, 194 .width = 12, 195 }, 196 .m2 = { 197 .reg_off = RTC_BY_OSCIN_CTRL1, 198 .shift = 12, 199 .width = 12, 200 }, 201 .dual = { 202 .reg_off = RTC_BY_OSCIN_CTRL0, 203 .shift = 28, 204 .width = 1, 205 }, 206 .table = a1_32k_div_table, 207 }, 208 .hw.init = &(struct clk_init_data){ 209 .name = "rtc_32k_div", 210 .ops = &meson_clk_dualdiv_ops, 211 .parent_hws = (const struct clk_hw *[]) { 212 &a1_rtc_32k_in.hw 213 }, 214 .num_parents = 1, 215 }, 216 }; 217 218 static struct clk_regmap a1_rtc_32k_xtal = { 219 .data = &(struct clk_regmap_gate_data){ 220 .offset = RTC_BY_OSCIN_CTRL1, 221 .bit_idx = 24, 222 }, 223 .hw.init = &(struct clk_init_data) { 224 .name = "rtc_32k_xtal", 225 .ops = &clk_regmap_gate_ops, 226 .parent_hws = (const struct clk_hw *[]) { 227 &a1_rtc_32k_in.hw 228 }, 229 .num_parents = 1, 230 }, 231 }; 232 233 static struct clk_regmap a1_rtc_32k_sel = { 234 .data = &(struct clk_regmap_mux_data) { 235 .offset = RTC_CTRL, 236 .mask = 0x3, 237 .shift = 0, 238 .flags = CLK_MUX_ROUND_CLOSEST, 239 }, 240 .hw.init = &(struct clk_init_data){ 241 .name = "rtc_32k_sel", 242 .ops = &clk_regmap_mux_ops, 243 .parent_hws = (const struct clk_hw *[]) { 244 &a1_rtc_32k_xtal.hw, 245 &a1_rtc_32k_div.hw, 246 }, 247 .num_parents = 2, 248 .flags = CLK_SET_RATE_PARENT, 249 }, 250 }; 251 252 static struct clk_regmap a1_rtc = { 253 .data = &(struct clk_regmap_gate_data){ 254 .offset = RTC_BY_OSCIN_CTRL0, 255 .bit_idx = 30, 256 }, 257 .hw.init = &(struct clk_init_data){ 258 .name = "rtc", 259 .ops = &clk_regmap_gate_ops, 260 .parent_hws = (const struct clk_hw *[]) { 261 &a1_rtc_32k_sel.hw 262 }, 263 .num_parents = 1, 264 .flags = CLK_SET_RATE_PARENT, 265 }, 266 }; 267 268 static u32 a1_sys_parents_val_table[] = { 0, 1, 2, 3, 7 }; 269 static const struct clk_parent_data a1_sys_parents[] = { 270 { .fw_name = "xtal" }, 271 { .fw_name = "fclk_div2" }, 272 { .fw_name = "fclk_div3" }, 273 { .fw_name = "fclk_div5" }, 274 { .hw = &a1_rtc.hw }, 275 }; 276 277 static struct clk_regmap a1_sys_b_sel = { 278 .data = &(struct clk_regmap_mux_data){ 279 .offset = SYS_CLK_CTRL0, 280 .mask = 0x7, 281 .shift = 26, 282 .table = a1_sys_parents_val_table, 283 }, 284 .hw.init = &(struct clk_init_data){ 285 .name = "sys_b_sel", 286 .ops = &clk_regmap_mux_ro_ops, 287 .parent_data = a1_sys_parents, 288 .num_parents = ARRAY_SIZE(a1_sys_parents), 289 }, 290 }; 291 292 static struct clk_regmap a1_sys_b_div = { 293 .data = &(struct clk_regmap_div_data){ 294 .offset = SYS_CLK_CTRL0, 295 .shift = 16, 296 .width = 10, 297 }, 298 .hw.init = &(struct clk_init_data){ 299 .name = "sys_b_div", 300 .ops = &clk_regmap_divider_ro_ops, 301 .parent_hws = (const struct clk_hw *[]) { 302 &a1_sys_b_sel.hw 303 }, 304 .num_parents = 1, 305 .flags = CLK_SET_RATE_PARENT, 306 }, 307 }; 308 309 static struct clk_regmap a1_sys_b = { 310 .data = &(struct clk_regmap_gate_data){ 311 .offset = SYS_CLK_CTRL0, 312 .bit_idx = 29, 313 }, 314 .hw.init = &(struct clk_init_data) { 315 .name = "sys_b", 316 .ops = &clk_regmap_gate_ro_ops, 317 .parent_hws = (const struct clk_hw *[]) { 318 &a1_sys_b_div.hw 319 }, 320 .num_parents = 1, 321 .flags = CLK_SET_RATE_PARENT, 322 }, 323 }; 324 325 static struct clk_regmap a1_sys_a_sel = { 326 .data = &(struct clk_regmap_mux_data){ 327 .offset = SYS_CLK_CTRL0, 328 .mask = 0x7, 329 .shift = 10, 330 .table = a1_sys_parents_val_table, 331 }, 332 .hw.init = &(struct clk_init_data){ 333 .name = "sys_a_sel", 334 .ops = &clk_regmap_mux_ro_ops, 335 .parent_data = a1_sys_parents, 336 .num_parents = ARRAY_SIZE(a1_sys_parents), 337 }, 338 }; 339 340 static struct clk_regmap a1_sys_a_div = { 341 .data = &(struct clk_regmap_div_data){ 342 .offset = SYS_CLK_CTRL0, 343 .shift = 0, 344 .width = 10, 345 }, 346 .hw.init = &(struct clk_init_data){ 347 .name = "sys_a_div", 348 .ops = &clk_regmap_divider_ro_ops, 349 .parent_hws = (const struct clk_hw *[]) { 350 &a1_sys_a_sel.hw 351 }, 352 .num_parents = 1, 353 .flags = CLK_SET_RATE_PARENT, 354 }, 355 }; 356 357 static struct clk_regmap a1_sys_a = { 358 .data = &(struct clk_regmap_gate_data){ 359 .offset = SYS_CLK_CTRL0, 360 .bit_idx = 13, 361 }, 362 .hw.init = &(struct clk_init_data) { 363 .name = "sys_a", 364 .ops = &clk_regmap_gate_ro_ops, 365 .parent_hws = (const struct clk_hw *[]) { 366 &a1_sys_a_div.hw 367 }, 368 .num_parents = 1, 369 .flags = CLK_SET_RATE_PARENT, 370 }, 371 }; 372 373 static struct clk_regmap a1_sys = { 374 .data = &(struct clk_regmap_mux_data){ 375 .offset = SYS_CLK_CTRL0, 376 .mask = 0x1, 377 .shift = 31, 378 }, 379 .hw.init = &(struct clk_init_data){ 380 .name = "sys", 381 .ops = &clk_regmap_mux_ro_ops, 382 .parent_hws = (const struct clk_hw *[]) { 383 &a1_sys_a.hw, 384 &a1_sys_b.hw, 385 }, 386 .num_parents = 2, 387 /* 388 * This clock is used by APB bus which is set in boot ROM code 389 * and is required by the platform to operate correctly. 390 * Until the following condition are met, we need this clock to 391 * be marked as critical: 392 * a) Mark the clock used by a firmware resource, if possible 393 * b) CCF has a clock hand-off mechanism to make the sure the 394 * clock stays on until the proper driver comes along 395 */ 396 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 397 }, 398 }; 399 400 static u32 a1_dsp_parents_val_table[] = { 0, 1, 2, 3, 4, 7 }; 401 static const struct clk_parent_data a1_dsp_parents[] = { 402 { .fw_name = "xtal", }, 403 { .fw_name = "fclk_div2", }, 404 { .fw_name = "fclk_div3", }, 405 { .fw_name = "fclk_div5", }, 406 { .fw_name = "hifi_pll", }, 407 { .hw = &a1_rtc.hw }, 408 }; 409 410 static struct clk_regmap a1_dspa_a_sel = { 411 .data = &(struct clk_regmap_mux_data){ 412 .offset = DSPA_CLK_CTRL0, 413 .mask = 0x7, 414 .shift = 10, 415 .table = a1_dsp_parents_val_table, 416 }, 417 .hw.init = &(struct clk_init_data){ 418 .name = "dspa_a_sel", 419 .ops = &clk_regmap_mux_ops, 420 .parent_data = a1_dsp_parents, 421 .num_parents = ARRAY_SIZE(a1_dsp_parents), 422 }, 423 }; 424 425 static struct clk_regmap a1_dspa_a_div = { 426 .data = &(struct clk_regmap_div_data){ 427 .offset = DSPA_CLK_CTRL0, 428 .shift = 0, 429 .width = 10, 430 }, 431 .hw.init = &(struct clk_init_data){ 432 .name = "dspa_a_div", 433 .ops = &clk_regmap_divider_ops, 434 .parent_hws = (const struct clk_hw *[]) { 435 &a1_dspa_a_sel.hw 436 }, 437 .num_parents = 1, 438 .flags = CLK_SET_RATE_PARENT, 439 }, 440 }; 441 442 static struct clk_regmap a1_dspa_a = { 443 .data = &(struct clk_regmap_gate_data){ 444 .offset = DSPA_CLK_CTRL0, 445 .bit_idx = 13, 446 }, 447 .hw.init = &(struct clk_init_data) { 448 .name = "dspa_a", 449 .ops = &clk_regmap_gate_ops, 450 .parent_hws = (const struct clk_hw *[]) { 451 &a1_dspa_a_div.hw 452 }, 453 .num_parents = 1, 454 .flags = CLK_SET_RATE_PARENT, 455 }, 456 }; 457 458 static struct clk_regmap a1_dspa_b_sel = { 459 .data = &(struct clk_regmap_mux_data){ 460 .offset = DSPA_CLK_CTRL0, 461 .mask = 0x7, 462 .shift = 26, 463 .table = a1_dsp_parents_val_table, 464 }, 465 .hw.init = &(struct clk_init_data){ 466 .name = "dspa_b_sel", 467 .ops = &clk_regmap_mux_ops, 468 .parent_data = a1_dsp_parents, 469 .num_parents = ARRAY_SIZE(a1_dsp_parents), 470 }, 471 }; 472 473 static struct clk_regmap a1_dspa_b_div = { 474 .data = &(struct clk_regmap_div_data){ 475 .offset = DSPA_CLK_CTRL0, 476 .shift = 16, 477 .width = 10, 478 }, 479 .hw.init = &(struct clk_init_data){ 480 .name = "dspa_b_div", 481 .ops = &clk_regmap_divider_ops, 482 .parent_hws = (const struct clk_hw *[]) { 483 &a1_dspa_b_sel.hw 484 }, 485 .num_parents = 1, 486 .flags = CLK_SET_RATE_PARENT, 487 }, 488 }; 489 490 static struct clk_regmap a1_dspa_b = { 491 .data = &(struct clk_regmap_gate_data){ 492 .offset = DSPA_CLK_CTRL0, 493 .bit_idx = 29, 494 }, 495 .hw.init = &(struct clk_init_data) { 496 .name = "dspa_b", 497 .ops = &clk_regmap_gate_ops, 498 .parent_hws = (const struct clk_hw *[]) { 499 &a1_dspa_b_div.hw 500 }, 501 .num_parents = 1, 502 .flags = CLK_SET_RATE_PARENT, 503 }, 504 }; 505 506 static struct clk_regmap a1_dspa_sel = { 507 .data = &(struct clk_regmap_mux_data){ 508 .offset = DSPA_CLK_CTRL0, 509 .mask = 0x1, 510 .shift = 15, 511 }, 512 .hw.init = &(struct clk_init_data){ 513 .name = "dspa_sel", 514 .ops = &clk_regmap_mux_ops, 515 .parent_hws = (const struct clk_hw *[]) { 516 &a1_dspa_a.hw, 517 &a1_dspa_b.hw, 518 }, 519 .num_parents = 2, 520 .flags = CLK_SET_RATE_PARENT, 521 }, 522 }; 523 524 static struct clk_regmap a1_dspa_en = { 525 .data = &(struct clk_regmap_gate_data){ 526 .offset = DSPA_CLK_EN, 527 .bit_idx = 1, 528 }, 529 .hw.init = &(struct clk_init_data) { 530 .name = "dspa_en", 531 .ops = &clk_regmap_gate_ops, 532 .parent_hws = (const struct clk_hw *[]) { 533 &a1_dspa_sel.hw 534 }, 535 .num_parents = 1, 536 .flags = CLK_SET_RATE_PARENT, 537 }, 538 }; 539 540 static struct clk_regmap a1_dspa_en_nic = { 541 .data = &(struct clk_regmap_gate_data){ 542 .offset = DSPA_CLK_EN, 543 .bit_idx = 0, 544 }, 545 .hw.init = &(struct clk_init_data) { 546 .name = "dspa_en_nic", 547 .ops = &clk_regmap_gate_ops, 548 .parent_hws = (const struct clk_hw *[]) { 549 &a1_dspa_sel.hw 550 }, 551 .num_parents = 1, 552 .flags = CLK_SET_RATE_PARENT, 553 }, 554 }; 555 556 static struct clk_regmap a1_dspb_a_sel = { 557 .data = &(struct clk_regmap_mux_data){ 558 .offset = DSPB_CLK_CTRL0, 559 .mask = 0x7, 560 .shift = 10, 561 .table = a1_dsp_parents_val_table, 562 }, 563 .hw.init = &(struct clk_init_data){ 564 .name = "dspb_a_sel", 565 .ops = &clk_regmap_mux_ops, 566 .parent_data = a1_dsp_parents, 567 .num_parents = ARRAY_SIZE(a1_dsp_parents), 568 }, 569 }; 570 571 static struct clk_regmap a1_dspb_a_div = { 572 .data = &(struct clk_regmap_div_data){ 573 .offset = DSPB_CLK_CTRL0, 574 .shift = 0, 575 .width = 10, 576 }, 577 .hw.init = &(struct clk_init_data){ 578 .name = "dspb_a_div", 579 .ops = &clk_regmap_divider_ops, 580 .parent_hws = (const struct clk_hw *[]) { 581 &a1_dspb_a_sel.hw 582 }, 583 .num_parents = 1, 584 .flags = CLK_SET_RATE_PARENT, 585 }, 586 }; 587 588 static struct clk_regmap a1_dspb_a = { 589 .data = &(struct clk_regmap_gate_data){ 590 .offset = DSPB_CLK_CTRL0, 591 .bit_idx = 13, 592 }, 593 .hw.init = &(struct clk_init_data) { 594 .name = "dspb_a", 595 .ops = &clk_regmap_gate_ops, 596 .parent_hws = (const struct clk_hw *[]) { 597 &a1_dspb_a_div.hw 598 }, 599 .num_parents = 1, 600 .flags = CLK_SET_RATE_PARENT, 601 }, 602 }; 603 604 static struct clk_regmap a1_dspb_b_sel = { 605 .data = &(struct clk_regmap_mux_data){ 606 .offset = DSPB_CLK_CTRL0, 607 .mask = 0x7, 608 .shift = 26, 609 .table = a1_dsp_parents_val_table, 610 }, 611 .hw.init = &(struct clk_init_data){ 612 .name = "dspb_b_sel", 613 .ops = &clk_regmap_mux_ops, 614 .parent_data = a1_dsp_parents, 615 .num_parents = ARRAY_SIZE(a1_dsp_parents), 616 }, 617 }; 618 619 static struct clk_regmap a1_dspb_b_div = { 620 .data = &(struct clk_regmap_div_data){ 621 .offset = DSPB_CLK_CTRL0, 622 .shift = 16, 623 .width = 10, 624 }, 625 .hw.init = &(struct clk_init_data){ 626 .name = "dspb_b_div", 627 .ops = &clk_regmap_divider_ops, 628 .parent_hws = (const struct clk_hw *[]) { 629 &a1_dspb_b_sel.hw 630 }, 631 .num_parents = 1, 632 .flags = CLK_SET_RATE_PARENT, 633 }, 634 }; 635 636 static struct clk_regmap a1_dspb_b = { 637 .data = &(struct clk_regmap_gate_data){ 638 .offset = DSPB_CLK_CTRL0, 639 .bit_idx = 29, 640 }, 641 .hw.init = &(struct clk_init_data) { 642 .name = "dspb_b", 643 .ops = &clk_regmap_gate_ops, 644 .parent_hws = (const struct clk_hw *[]) { 645 &a1_dspb_b_div.hw 646 }, 647 .num_parents = 1, 648 .flags = CLK_SET_RATE_PARENT, 649 }, 650 }; 651 652 static struct clk_regmap a1_dspb_sel = { 653 .data = &(struct clk_regmap_mux_data){ 654 .offset = DSPB_CLK_CTRL0, 655 .mask = 0x1, 656 .shift = 15, 657 }, 658 .hw.init = &(struct clk_init_data){ 659 .name = "dspb_sel", 660 .ops = &clk_regmap_mux_ops, 661 .parent_hws = (const struct clk_hw *[]) { 662 &a1_dspb_a.hw, 663 &a1_dspb_b.hw, 664 }, 665 .num_parents = 2, 666 .flags = CLK_SET_RATE_PARENT, 667 }, 668 }; 669 670 static struct clk_regmap a1_dspb_en = { 671 .data = &(struct clk_regmap_gate_data){ 672 .offset = DSPB_CLK_EN, 673 .bit_idx = 1, 674 }, 675 .hw.init = &(struct clk_init_data) { 676 .name = "dspb_en", 677 .ops = &clk_regmap_gate_ops, 678 .parent_hws = (const struct clk_hw *[]) { 679 &a1_dspb_sel.hw 680 }, 681 .num_parents = 1, 682 .flags = CLK_SET_RATE_PARENT, 683 }, 684 }; 685 686 static struct clk_regmap a1_dspb_en_nic = { 687 .data = &(struct clk_regmap_gate_data){ 688 .offset = DSPB_CLK_EN, 689 .bit_idx = 0, 690 }, 691 .hw.init = &(struct clk_init_data) { 692 .name = "dspb_en_nic", 693 .ops = &clk_regmap_gate_ops, 694 .parent_hws = (const struct clk_hw *[]) { 695 &a1_dspb_sel.hw 696 }, 697 .num_parents = 1, 698 .flags = CLK_SET_RATE_PARENT, 699 }, 700 }; 701 702 static struct clk_regmap a1_24m = { 703 .data = &(struct clk_regmap_gate_data){ 704 .offset = CLK12_24_CTRL, 705 .bit_idx = 11, 706 }, 707 .hw.init = &(struct clk_init_data) { 708 .name = "24m", 709 .ops = &clk_regmap_gate_ops, 710 .parent_data = &(const struct clk_parent_data) { 711 .fw_name = "xtal", 712 }, 713 .num_parents = 1, 714 }, 715 }; 716 717 static struct clk_fixed_factor a1_24m_div2 = { 718 .mult = 1, 719 .div = 2, 720 .hw.init = &(struct clk_init_data){ 721 .name = "24m_div2", 722 .ops = &clk_fixed_factor_ops, 723 .parent_hws = (const struct clk_hw *[]) { 724 &a1_24m.hw 725 }, 726 .num_parents = 1, 727 }, 728 }; 729 730 static struct clk_regmap a1_12m = { 731 .data = &(struct clk_regmap_gate_data){ 732 .offset = CLK12_24_CTRL, 733 .bit_idx = 10, 734 }, 735 .hw.init = &(struct clk_init_data) { 736 .name = "12m", 737 .ops = &clk_regmap_gate_ops, 738 .parent_hws = (const struct clk_hw *[]) { 739 &a1_24m_div2.hw 740 }, 741 .num_parents = 1, 742 }, 743 }; 744 745 static struct clk_regmap a1_fclk_div2_divn_pre = { 746 .data = &(struct clk_regmap_div_data){ 747 .offset = CLK12_24_CTRL, 748 .shift = 0, 749 .width = 8, 750 }, 751 .hw.init = &(struct clk_init_data){ 752 .name = "fclk_div2_divn_pre", 753 .ops = &clk_regmap_divider_ops, 754 .parent_data = &(const struct clk_parent_data) { 755 .fw_name = "fclk_div2", 756 }, 757 .num_parents = 1, 758 }, 759 }; 760 761 static struct clk_regmap a1_fclk_div2_divn = { 762 .data = &(struct clk_regmap_gate_data){ 763 .offset = CLK12_24_CTRL, 764 .bit_idx = 12, 765 }, 766 .hw.init = &(struct clk_init_data){ 767 .name = "fclk_div2_divn", 768 .ops = &clk_regmap_gate_ops, 769 .parent_hws = (const struct clk_hw *[]) { 770 &a1_fclk_div2_divn_pre.hw 771 }, 772 .num_parents = 1, 773 .flags = CLK_SET_RATE_PARENT, 774 }, 775 }; 776 777 /* 778 * the index 2 is sys_pll_div16, it will be implemented in the CPU clock driver, 779 * the index 4 is the clock measurement source, it's not supported yet 780 */ 781 static u32 a1_gen_parents_val_table[] = { 0, 1, 3, 5, 6, 7, 8 }; 782 static const struct clk_parent_data a1_gen_parents[] = { 783 { .fw_name = "xtal", }, 784 { .hw = &a1_rtc.hw }, 785 { .fw_name = "hifi_pll", }, 786 { .fw_name = "fclk_div2", }, 787 { .fw_name = "fclk_div3", }, 788 { .fw_name = "fclk_div5", }, 789 { .fw_name = "fclk_div7", }, 790 }; 791 792 static struct clk_regmap a1_gen_sel = { 793 .data = &(struct clk_regmap_mux_data){ 794 .offset = GEN_CLK_CTRL, 795 .mask = 0xf, 796 .shift = 12, 797 .table = a1_gen_parents_val_table, 798 }, 799 .hw.init = &(struct clk_init_data){ 800 .name = "gen_sel", 801 .ops = &clk_regmap_mux_ops, 802 .parent_data = a1_gen_parents, 803 .num_parents = ARRAY_SIZE(a1_gen_parents), 804 /* 805 * The GEN clock can be connected to an external pad, so it 806 * may be set up directly from the device tree. Additionally, 807 * the GEN clock can be inherited from a more accurate RTC 808 * clock, so in certain situations, it may be necessary 809 * to freeze its parent. 810 */ 811 .flags = CLK_SET_RATE_NO_REPARENT, 812 }, 813 }; 814 815 static struct clk_regmap a1_gen_div = { 816 .data = &(struct clk_regmap_div_data){ 817 .offset = GEN_CLK_CTRL, 818 .shift = 0, 819 .width = 11, 820 }, 821 .hw.init = &(struct clk_init_data){ 822 .name = "gen_div", 823 .ops = &clk_regmap_divider_ops, 824 .parent_hws = (const struct clk_hw *[]) { 825 &a1_gen_sel.hw 826 }, 827 .num_parents = 1, 828 .flags = CLK_SET_RATE_PARENT, 829 }, 830 }; 831 832 static struct clk_regmap a1_gen = { 833 .data = &(struct clk_regmap_gate_data){ 834 .offset = GEN_CLK_CTRL, 835 .bit_idx = 11, 836 }, 837 .hw.init = &(struct clk_init_data) { 838 .name = "gen", 839 .ops = &clk_regmap_gate_ops, 840 .parent_hws = (const struct clk_hw *[]) { 841 &a1_gen_div.hw 842 }, 843 .num_parents = 1, 844 .flags = CLK_SET_RATE_PARENT, 845 }, 846 }; 847 848 static struct clk_regmap a1_saradc_sel = { 849 .data = &(struct clk_regmap_mux_data){ 850 .offset = SAR_ADC_CLK_CTRL, 851 .mask = 0x1, 852 .shift = 9, 853 }, 854 .hw.init = &(struct clk_init_data){ 855 .name = "saradc_sel", 856 .ops = &clk_regmap_mux_ops, 857 .parent_data = (const struct clk_parent_data []) { 858 { .fw_name = "xtal", }, 859 { .hw = &a1_sys.hw, }, 860 }, 861 .num_parents = 2, 862 }, 863 }; 864 865 static struct clk_regmap a1_saradc_div = { 866 .data = &(struct clk_regmap_div_data){ 867 .offset = SAR_ADC_CLK_CTRL, 868 .shift = 0, 869 .width = 8, 870 }, 871 .hw.init = &(struct clk_init_data){ 872 .name = "saradc_div", 873 .ops = &clk_regmap_divider_ops, 874 .parent_hws = (const struct clk_hw *[]) { 875 &a1_saradc_sel.hw 876 }, 877 .num_parents = 1, 878 .flags = CLK_SET_RATE_PARENT, 879 }, 880 }; 881 882 static struct clk_regmap a1_saradc = { 883 .data = &(struct clk_regmap_gate_data){ 884 .offset = SAR_ADC_CLK_CTRL, 885 .bit_idx = 8, 886 }, 887 .hw.init = &(struct clk_init_data) { 888 .name = "saradc", 889 .ops = &clk_regmap_gate_ops, 890 .parent_hws = (const struct clk_hw *[]) { 891 &a1_saradc_div.hw 892 }, 893 .num_parents = 1, 894 .flags = CLK_SET_RATE_PARENT, 895 }, 896 }; 897 898 static const struct clk_parent_data a1_pwm_abcd_parents[] = { 899 { .fw_name = "xtal", }, 900 { .hw = &a1_sys.hw }, 901 { .hw = &a1_rtc.hw }, 902 }; 903 904 static struct clk_regmap a1_pwm_a_sel = { 905 .data = &(struct clk_regmap_mux_data){ 906 .offset = PWM_CLK_AB_CTRL, 907 .mask = 0x1, 908 .shift = 9, 909 }, 910 .hw.init = &(struct clk_init_data){ 911 .name = "pwm_a_sel", 912 .ops = &clk_regmap_mux_ops, 913 .parent_data = a1_pwm_abcd_parents, 914 .num_parents = ARRAY_SIZE(a1_pwm_abcd_parents), 915 }, 916 }; 917 918 static struct clk_regmap a1_pwm_a_div = { 919 .data = &(struct clk_regmap_div_data){ 920 .offset = PWM_CLK_AB_CTRL, 921 .shift = 0, 922 .width = 8, 923 }, 924 .hw.init = &(struct clk_init_data){ 925 .name = "pwm_a_div", 926 .ops = &clk_regmap_divider_ops, 927 .parent_hws = (const struct clk_hw *[]) { 928 &a1_pwm_a_sel.hw 929 }, 930 .num_parents = 1, 931 .flags = CLK_SET_RATE_PARENT, 932 }, 933 }; 934 935 static struct clk_regmap a1_pwm_a = { 936 .data = &(struct clk_regmap_gate_data){ 937 .offset = PWM_CLK_AB_CTRL, 938 .bit_idx = 8, 939 }, 940 .hw.init = &(struct clk_init_data) { 941 .name = "pwm_a", 942 .ops = &clk_regmap_gate_ops, 943 .parent_hws = (const struct clk_hw *[]) { 944 &a1_pwm_a_div.hw 945 }, 946 .num_parents = 1, 947 .flags = CLK_SET_RATE_PARENT, 948 }, 949 }; 950 951 static struct clk_regmap a1_pwm_b_sel = { 952 .data = &(struct clk_regmap_mux_data){ 953 .offset = PWM_CLK_AB_CTRL, 954 .mask = 0x1, 955 .shift = 25, 956 }, 957 .hw.init = &(struct clk_init_data){ 958 .name = "pwm_b_sel", 959 .ops = &clk_regmap_mux_ops, 960 .parent_data = a1_pwm_abcd_parents, 961 .num_parents = ARRAY_SIZE(a1_pwm_abcd_parents), 962 }, 963 }; 964 965 static struct clk_regmap a1_pwm_b_div = { 966 .data = &(struct clk_regmap_div_data){ 967 .offset = PWM_CLK_AB_CTRL, 968 .shift = 16, 969 .width = 8, 970 }, 971 .hw.init = &(struct clk_init_data){ 972 .name = "pwm_b_div", 973 .ops = &clk_regmap_divider_ops, 974 .parent_hws = (const struct clk_hw *[]) { 975 &a1_pwm_b_sel.hw 976 }, 977 .num_parents = 1, 978 .flags = CLK_SET_RATE_PARENT, 979 }, 980 }; 981 982 static struct clk_regmap a1_pwm_b = { 983 .data = &(struct clk_regmap_gate_data){ 984 .offset = PWM_CLK_AB_CTRL, 985 .bit_idx = 24, 986 }, 987 .hw.init = &(struct clk_init_data) { 988 .name = "pwm_b", 989 .ops = &clk_regmap_gate_ops, 990 .parent_hws = (const struct clk_hw *[]) { 991 &a1_pwm_b_div.hw 992 }, 993 .num_parents = 1, 994 .flags = CLK_SET_RATE_PARENT, 995 }, 996 }; 997 998 static struct clk_regmap a1_pwm_c_sel = { 999 .data = &(struct clk_regmap_mux_data){ 1000 .offset = PWM_CLK_CD_CTRL, 1001 .mask = 0x1, 1002 .shift = 9, 1003 }, 1004 .hw.init = &(struct clk_init_data){ 1005 .name = "pwm_c_sel", 1006 .ops = &clk_regmap_mux_ops, 1007 .parent_data = a1_pwm_abcd_parents, 1008 .num_parents = ARRAY_SIZE(a1_pwm_abcd_parents), 1009 }, 1010 }; 1011 1012 static struct clk_regmap a1_pwm_c_div = { 1013 .data = &(struct clk_regmap_div_data){ 1014 .offset = PWM_CLK_CD_CTRL, 1015 .shift = 0, 1016 .width = 8, 1017 }, 1018 .hw.init = &(struct clk_init_data){ 1019 .name = "pwm_c_div", 1020 .ops = &clk_regmap_divider_ops, 1021 .parent_hws = (const struct clk_hw *[]) { 1022 &a1_pwm_c_sel.hw 1023 }, 1024 .num_parents = 1, 1025 .flags = CLK_SET_RATE_PARENT, 1026 }, 1027 }; 1028 1029 static struct clk_regmap a1_pwm_c = { 1030 .data = &(struct clk_regmap_gate_data){ 1031 .offset = PWM_CLK_CD_CTRL, 1032 .bit_idx = 8, 1033 }, 1034 .hw.init = &(struct clk_init_data) { 1035 .name = "pwm_c", 1036 .ops = &clk_regmap_gate_ops, 1037 .parent_hws = (const struct clk_hw *[]) { 1038 &a1_pwm_c_div.hw 1039 }, 1040 .num_parents = 1, 1041 .flags = CLK_SET_RATE_PARENT, 1042 }, 1043 }; 1044 1045 static struct clk_regmap a1_pwm_d_sel = { 1046 .data = &(struct clk_regmap_mux_data){ 1047 .offset = PWM_CLK_CD_CTRL, 1048 .mask = 0x1, 1049 .shift = 25, 1050 }, 1051 .hw.init = &(struct clk_init_data){ 1052 .name = "pwm_d_sel", 1053 .ops = &clk_regmap_mux_ops, 1054 .parent_data = a1_pwm_abcd_parents, 1055 .num_parents = ARRAY_SIZE(a1_pwm_abcd_parents), 1056 }, 1057 }; 1058 1059 static struct clk_regmap a1_pwm_d_div = { 1060 .data = &(struct clk_regmap_div_data){ 1061 .offset = PWM_CLK_CD_CTRL, 1062 .shift = 16, 1063 .width = 8, 1064 }, 1065 .hw.init = &(struct clk_init_data){ 1066 .name = "pwm_d_div", 1067 .ops = &clk_regmap_divider_ops, 1068 .parent_hws = (const struct clk_hw *[]) { 1069 &a1_pwm_d_sel.hw 1070 }, 1071 .num_parents = 1, 1072 .flags = CLK_SET_RATE_PARENT, 1073 }, 1074 }; 1075 1076 static struct clk_regmap a1_pwm_d = { 1077 .data = &(struct clk_regmap_gate_data){ 1078 .offset = PWM_CLK_CD_CTRL, 1079 .bit_idx = 24, 1080 }, 1081 .hw.init = &(struct clk_init_data) { 1082 .name = "pwm_d", 1083 .ops = &clk_regmap_gate_ops, 1084 .parent_hws = (const struct clk_hw *[]) { 1085 &a1_pwm_d_div.hw 1086 }, 1087 .num_parents = 1, 1088 .flags = CLK_SET_RATE_PARENT, 1089 }, 1090 }; 1091 1092 static const struct clk_parent_data a1_pwm_ef_parents[] = { 1093 { .fw_name = "xtal", }, 1094 { .hw = &a1_sys.hw }, 1095 { .fw_name = "fclk_div5", }, 1096 { .hw = &a1_rtc.hw }, 1097 }; 1098 1099 static struct clk_regmap a1_pwm_e_sel = { 1100 .data = &(struct clk_regmap_mux_data){ 1101 .offset = PWM_CLK_EF_CTRL, 1102 .mask = 0x3, 1103 .shift = 9, 1104 }, 1105 .hw.init = &(struct clk_init_data){ 1106 .name = "pwm_e_sel", 1107 .ops = &clk_regmap_mux_ops, 1108 .parent_data = a1_pwm_ef_parents, 1109 .num_parents = ARRAY_SIZE(a1_pwm_ef_parents), 1110 }, 1111 }; 1112 1113 static struct clk_regmap a1_pwm_e_div = { 1114 .data = &(struct clk_regmap_div_data){ 1115 .offset = PWM_CLK_EF_CTRL, 1116 .shift = 0, 1117 .width = 8, 1118 }, 1119 .hw.init = &(struct clk_init_data){ 1120 .name = "pwm_e_div", 1121 .ops = &clk_regmap_divider_ops, 1122 .parent_hws = (const struct clk_hw *[]) { 1123 &a1_pwm_e_sel.hw 1124 }, 1125 .num_parents = 1, 1126 .flags = CLK_SET_RATE_PARENT, 1127 }, 1128 }; 1129 1130 static struct clk_regmap a1_pwm_e = { 1131 .data = &(struct clk_regmap_gate_data){ 1132 .offset = PWM_CLK_EF_CTRL, 1133 .bit_idx = 8, 1134 }, 1135 .hw.init = &(struct clk_init_data) { 1136 .name = "pwm_e", 1137 .ops = &clk_regmap_gate_ops, 1138 .parent_hws = (const struct clk_hw *[]) { 1139 &a1_pwm_e_div.hw 1140 }, 1141 .num_parents = 1, 1142 .flags = CLK_SET_RATE_PARENT, 1143 }, 1144 }; 1145 1146 static struct clk_regmap a1_pwm_f_sel = { 1147 .data = &(struct clk_regmap_mux_data){ 1148 .offset = PWM_CLK_EF_CTRL, 1149 .mask = 0x3, 1150 .shift = 25, 1151 }, 1152 .hw.init = &(struct clk_init_data){ 1153 .name = "pwm_f_sel", 1154 .ops = &clk_regmap_mux_ops, 1155 .parent_data = a1_pwm_ef_parents, 1156 .num_parents = ARRAY_SIZE(a1_pwm_ef_parents), 1157 }, 1158 }; 1159 1160 static struct clk_regmap a1_pwm_f_div = { 1161 .data = &(struct clk_regmap_div_data){ 1162 .offset = PWM_CLK_EF_CTRL, 1163 .shift = 16, 1164 .width = 8, 1165 }, 1166 .hw.init = &(struct clk_init_data){ 1167 .name = "pwm_f_div", 1168 .ops = &clk_regmap_divider_ops, 1169 .parent_hws = (const struct clk_hw *[]) { 1170 &a1_pwm_f_sel.hw 1171 }, 1172 .num_parents = 1, 1173 .flags = CLK_SET_RATE_PARENT, 1174 }, 1175 }; 1176 1177 static struct clk_regmap a1_pwm_f = { 1178 .data = &(struct clk_regmap_gate_data){ 1179 .offset = PWM_CLK_EF_CTRL, 1180 .bit_idx = 24, 1181 }, 1182 .hw.init = &(struct clk_init_data) { 1183 .name = "pwm_f", 1184 .ops = &clk_regmap_gate_ops, 1185 .parent_hws = (const struct clk_hw *[]) { 1186 &a1_pwm_f_div.hw 1187 }, 1188 .num_parents = 1, 1189 .flags = CLK_SET_RATE_PARENT, 1190 }, 1191 }; 1192 1193 /* 1194 * spicc clk 1195 * fdiv2 |\ |\ _____ 1196 * ---------| |---DIV--| | | | spicc out 1197 * ---------| | | |-----|GATE |--------- 1198 * ..... |/ | / |_____| 1199 * --------------------|/ 1200 * 24M 1201 */ 1202 static const struct clk_parent_data a1_spi_parents[] = { 1203 { .fw_name = "fclk_div2"}, 1204 { .fw_name = "fclk_div3"}, 1205 { .fw_name = "fclk_div5"}, 1206 { .fw_name = "hifi_pll" }, 1207 }; 1208 1209 static struct clk_regmap a1_spicc_sel = { 1210 .data = &(struct clk_regmap_mux_data){ 1211 .offset = SPICC_CLK_CTRL, 1212 .mask = 0x3, 1213 .shift = 9, 1214 }, 1215 .hw.init = &(struct clk_init_data){ 1216 .name = "spicc_sel", 1217 .ops = &clk_regmap_mux_ops, 1218 .parent_data = a1_spi_parents, 1219 .num_parents = ARRAY_SIZE(a1_spi_parents), 1220 }, 1221 }; 1222 1223 static struct clk_regmap a1_spicc_div = { 1224 .data = &(struct clk_regmap_div_data){ 1225 .offset = SPICC_CLK_CTRL, 1226 .shift = 0, 1227 .width = 8, 1228 }, 1229 .hw.init = &(struct clk_init_data){ 1230 .name = "spicc_div", 1231 .ops = &clk_regmap_divider_ops, 1232 .parent_hws = (const struct clk_hw *[]) { 1233 &a1_spicc_sel.hw 1234 }, 1235 .num_parents = 1, 1236 .flags = CLK_SET_RATE_PARENT, 1237 }, 1238 }; 1239 1240 static struct clk_regmap a1_spicc_sel2 = { 1241 .data = &(struct clk_regmap_mux_data){ 1242 .offset = SPICC_CLK_CTRL, 1243 .mask = 0x1, 1244 .shift = 15, 1245 }, 1246 .hw.init = &(struct clk_init_data){ 1247 .name = "spicc_sel2", 1248 .ops = &clk_regmap_mux_ops, 1249 .parent_data = (const struct clk_parent_data []) { 1250 { .hw = &a1_spicc_div.hw }, 1251 { .fw_name = "xtal", }, 1252 }, 1253 .num_parents = 2, 1254 .flags = CLK_SET_RATE_PARENT, 1255 }, 1256 }; 1257 1258 static struct clk_regmap a1_spicc = { 1259 .data = &(struct clk_regmap_gate_data){ 1260 .offset = SPICC_CLK_CTRL, 1261 .bit_idx = 8, 1262 }, 1263 .hw.init = &(struct clk_init_data) { 1264 .name = "spicc", 1265 .ops = &clk_regmap_gate_ops, 1266 .parent_hws = (const struct clk_hw *[]) { 1267 &a1_spicc_sel2.hw 1268 }, 1269 .num_parents = 1, 1270 .flags = CLK_SET_RATE_PARENT, 1271 }, 1272 }; 1273 1274 static struct clk_regmap a1_ts_div = { 1275 .data = &(struct clk_regmap_div_data){ 1276 .offset = TS_CLK_CTRL, 1277 .shift = 0, 1278 .width = 8, 1279 }, 1280 .hw.init = &(struct clk_init_data){ 1281 .name = "ts_div", 1282 .ops = &clk_regmap_divider_ops, 1283 .parent_data = &(const struct clk_parent_data) { 1284 .fw_name = "xtal", 1285 }, 1286 .num_parents = 1, 1287 }, 1288 }; 1289 1290 static struct clk_regmap a1_ts = { 1291 .data = &(struct clk_regmap_gate_data){ 1292 .offset = TS_CLK_CTRL, 1293 .bit_idx = 8, 1294 }, 1295 .hw.init = &(struct clk_init_data) { 1296 .name = "ts", 1297 .ops = &clk_regmap_gate_ops, 1298 .parent_hws = (const struct clk_hw *[]) { 1299 &a1_ts_div.hw 1300 }, 1301 .num_parents = 1, 1302 .flags = CLK_SET_RATE_PARENT, 1303 }, 1304 }; 1305 1306 static struct clk_regmap a1_spifc_sel = { 1307 .data = &(struct clk_regmap_mux_data){ 1308 .offset = SPIFC_CLK_CTRL, 1309 .mask = 0x3, 1310 .shift = 9, 1311 }, 1312 .hw.init = &(struct clk_init_data){ 1313 .name = "spifc_sel", 1314 .ops = &clk_regmap_mux_ops, 1315 .parent_data = a1_spi_parents, 1316 .num_parents = ARRAY_SIZE(a1_spi_parents), 1317 }, 1318 }; 1319 1320 static struct clk_regmap a1_spifc_div = { 1321 .data = &(struct clk_regmap_div_data){ 1322 .offset = SPIFC_CLK_CTRL, 1323 .shift = 0, 1324 .width = 8, 1325 }, 1326 .hw.init = &(struct clk_init_data){ 1327 .name = "spifc_div", 1328 .ops = &clk_regmap_divider_ops, 1329 .parent_hws = (const struct clk_hw *[]) { 1330 &a1_spifc_sel.hw 1331 }, 1332 .num_parents = 1, 1333 .flags = CLK_SET_RATE_PARENT, 1334 }, 1335 }; 1336 1337 static struct clk_regmap a1_spifc_sel2 = { 1338 .data = &(struct clk_regmap_mux_data){ 1339 .offset = SPIFC_CLK_CTRL, 1340 .mask = 0x1, 1341 .shift = 15, 1342 }, 1343 .hw.init = &(struct clk_init_data){ 1344 .name = "spifc_sel2", 1345 .ops = &clk_regmap_mux_ops, 1346 .parent_data = (const struct clk_parent_data []) { 1347 { .hw = &a1_spifc_div.hw }, 1348 { .fw_name = "xtal", }, 1349 }, 1350 .num_parents = 2, 1351 .flags = CLK_SET_RATE_PARENT, 1352 }, 1353 }; 1354 1355 static struct clk_regmap a1_spifc = { 1356 .data = &(struct clk_regmap_gate_data){ 1357 .offset = SPIFC_CLK_CTRL, 1358 .bit_idx = 8, 1359 }, 1360 .hw.init = &(struct clk_init_data) { 1361 .name = "spifc", 1362 .ops = &clk_regmap_gate_ops, 1363 .parent_hws = (const struct clk_hw *[]) { 1364 &a1_spifc_sel2.hw 1365 }, 1366 .num_parents = 1, 1367 .flags = CLK_SET_RATE_PARENT, 1368 }, 1369 }; 1370 1371 static const struct clk_parent_data a1_usb_bus_parents[] = { 1372 { .fw_name = "xtal", }, 1373 { .hw = &a1_sys.hw }, 1374 { .fw_name = "fclk_div3", }, 1375 { .fw_name = "fclk_div5", }, 1376 }; 1377 1378 static struct clk_regmap a1_usb_bus_sel = { 1379 .data = &(struct clk_regmap_mux_data){ 1380 .offset = USB_BUSCLK_CTRL, 1381 .mask = 0x3, 1382 .shift = 9, 1383 }, 1384 .hw.init = &(struct clk_init_data){ 1385 .name = "usb_bus_sel", 1386 .ops = &clk_regmap_mux_ops, 1387 .parent_data = a1_usb_bus_parents, 1388 .num_parents = ARRAY_SIZE(a1_usb_bus_parents), 1389 .flags = CLK_SET_RATE_PARENT, 1390 }, 1391 }; 1392 1393 static struct clk_regmap a1_usb_bus_div = { 1394 .data = &(struct clk_regmap_div_data){ 1395 .offset = USB_BUSCLK_CTRL, 1396 .shift = 0, 1397 .width = 8, 1398 }, 1399 .hw.init = &(struct clk_init_data){ 1400 .name = "usb_bus_div", 1401 .ops = &clk_regmap_divider_ops, 1402 .parent_hws = (const struct clk_hw *[]) { 1403 &a1_usb_bus_sel.hw 1404 }, 1405 .num_parents = 1, 1406 .flags = CLK_SET_RATE_PARENT, 1407 }, 1408 }; 1409 1410 static struct clk_regmap a1_usb_bus = { 1411 .data = &(struct clk_regmap_gate_data){ 1412 .offset = USB_BUSCLK_CTRL, 1413 .bit_idx = 8, 1414 }, 1415 .hw.init = &(struct clk_init_data) { 1416 .name = "usb_bus", 1417 .ops = &clk_regmap_gate_ops, 1418 .parent_hws = (const struct clk_hw *[]) { 1419 &a1_usb_bus_div.hw 1420 }, 1421 .num_parents = 1, 1422 .flags = CLK_SET_RATE_PARENT, 1423 }, 1424 }; 1425 1426 static const struct clk_parent_data a1_sd_emmc_parents[] = { 1427 { .fw_name = "fclk_div2", }, 1428 { .fw_name = "fclk_div3", }, 1429 { .fw_name = "fclk_div5", }, 1430 { .fw_name = "hifi_pll", }, 1431 }; 1432 1433 static struct clk_regmap a1_sd_emmc_sel = { 1434 .data = &(struct clk_regmap_mux_data){ 1435 .offset = SD_EMMC_CLK_CTRL, 1436 .mask = 0x3, 1437 .shift = 9, 1438 }, 1439 .hw.init = &(struct clk_init_data){ 1440 .name = "sd_emmc_sel", 1441 .ops = &clk_regmap_mux_ops, 1442 .parent_data = a1_sd_emmc_parents, 1443 .num_parents = ARRAY_SIZE(a1_sd_emmc_parents), 1444 }, 1445 }; 1446 1447 static struct clk_regmap a1_sd_emmc_div = { 1448 .data = &(struct clk_regmap_div_data){ 1449 .offset = SD_EMMC_CLK_CTRL, 1450 .shift = 0, 1451 .width = 8, 1452 }, 1453 .hw.init = &(struct clk_init_data){ 1454 .name = "sd_emmc_div", 1455 .ops = &clk_regmap_divider_ops, 1456 .parent_hws = (const struct clk_hw *[]) { 1457 &a1_sd_emmc_sel.hw 1458 }, 1459 .num_parents = 1, 1460 .flags = CLK_SET_RATE_PARENT, 1461 }, 1462 }; 1463 1464 static struct clk_regmap a1_sd_emmc_sel2 = { 1465 .data = &(struct clk_regmap_mux_data){ 1466 .offset = SD_EMMC_CLK_CTRL, 1467 .mask = 0x1, 1468 .shift = 15, 1469 }, 1470 .hw.init = &(struct clk_init_data){ 1471 .name = "sd_emmc_sel2", 1472 .ops = &clk_regmap_mux_ops, 1473 .parent_data = (const struct clk_parent_data []) { 1474 { .hw = &a1_sd_emmc_div.hw }, 1475 { .fw_name = "xtal", }, 1476 }, 1477 .num_parents = 2, 1478 .flags = CLK_SET_RATE_PARENT, 1479 }, 1480 }; 1481 1482 static struct clk_regmap a1_sd_emmc = { 1483 .data = &(struct clk_regmap_gate_data){ 1484 .offset = SD_EMMC_CLK_CTRL, 1485 .bit_idx = 8, 1486 }, 1487 .hw.init = &(struct clk_init_data) { 1488 .name = "sd_emmc", 1489 .ops = &clk_regmap_gate_ops, 1490 .parent_hws = (const struct clk_hw *[]) { 1491 &a1_sd_emmc_sel2.hw 1492 }, 1493 .num_parents = 1, 1494 .flags = CLK_SET_RATE_PARENT, 1495 }, 1496 }; 1497 1498 static struct clk_regmap a1_psram_sel = { 1499 .data = &(struct clk_regmap_mux_data){ 1500 .offset = PSRAM_CLK_CTRL, 1501 .mask = 0x3, 1502 .shift = 9, 1503 }, 1504 .hw.init = &(struct clk_init_data){ 1505 .name = "psram_sel", 1506 .ops = &clk_regmap_mux_ops, 1507 .parent_data = a1_sd_emmc_parents, 1508 .num_parents = ARRAY_SIZE(a1_sd_emmc_parents), 1509 }, 1510 }; 1511 1512 static struct clk_regmap a1_psram_div = { 1513 .data = &(struct clk_regmap_div_data){ 1514 .offset = PSRAM_CLK_CTRL, 1515 .shift = 0, 1516 .width = 8, 1517 }, 1518 .hw.init = &(struct clk_init_data){ 1519 .name = "psram_div", 1520 .ops = &clk_regmap_divider_ops, 1521 .parent_hws = (const struct clk_hw *[]) { 1522 &a1_psram_sel.hw 1523 }, 1524 .num_parents = 1, 1525 .flags = CLK_SET_RATE_PARENT, 1526 }, 1527 }; 1528 1529 static struct clk_regmap a1_psram_sel2 = { 1530 .data = &(struct clk_regmap_mux_data){ 1531 .offset = PSRAM_CLK_CTRL, 1532 .mask = 0x1, 1533 .shift = 15, 1534 }, 1535 .hw.init = &(struct clk_init_data){ 1536 .name = "psram_sel2", 1537 .ops = &clk_regmap_mux_ops, 1538 .parent_data = (const struct clk_parent_data []) { 1539 { .hw = &a1_psram_div.hw }, 1540 { .fw_name = "xtal", }, 1541 }, 1542 .num_parents = 2, 1543 .flags = CLK_SET_RATE_PARENT, 1544 }, 1545 }; 1546 1547 static struct clk_regmap a1_psram = { 1548 .data = &(struct clk_regmap_gate_data){ 1549 .offset = PSRAM_CLK_CTRL, 1550 .bit_idx = 8, 1551 }, 1552 .hw.init = &(struct clk_init_data) { 1553 .name = "psram", 1554 .ops = &clk_regmap_gate_ops, 1555 .parent_hws = (const struct clk_hw *[]) { 1556 &a1_psram_sel2.hw 1557 }, 1558 .num_parents = 1, 1559 .flags = CLK_SET_RATE_PARENT, 1560 }, 1561 }; 1562 1563 static struct clk_regmap a1_dmc_sel = { 1564 .data = &(struct clk_regmap_mux_data){ 1565 .offset = DMC_CLK_CTRL, 1566 .mask = 0x3, 1567 .shift = 9, 1568 }, 1569 .hw.init = &(struct clk_init_data){ 1570 .name = "dmc_sel", 1571 .ops = &clk_regmap_mux_ops, 1572 .parent_data = a1_sd_emmc_parents, 1573 .num_parents = ARRAY_SIZE(a1_sd_emmc_parents), 1574 }, 1575 }; 1576 1577 static struct clk_regmap a1_dmc_div = { 1578 .data = &(struct clk_regmap_div_data){ 1579 .offset = DMC_CLK_CTRL, 1580 .shift = 0, 1581 .width = 8, 1582 }, 1583 .hw.init = &(struct clk_init_data){ 1584 .name = "dmc_div", 1585 .ops = &clk_regmap_divider_ops, 1586 .parent_hws = (const struct clk_hw *[]) { 1587 &a1_dmc_sel.hw 1588 }, 1589 .num_parents = 1, 1590 .flags = CLK_SET_RATE_PARENT, 1591 }, 1592 }; 1593 1594 static struct clk_regmap a1_dmc_sel2 = { 1595 .data = &(struct clk_regmap_mux_data){ 1596 .offset = DMC_CLK_CTRL, 1597 .mask = 0x1, 1598 .shift = 15, 1599 }, 1600 .hw.init = &(struct clk_init_data){ 1601 .name = "dmc_sel2", 1602 .ops = &clk_regmap_mux_ops, 1603 .parent_data = (const struct clk_parent_data []) { 1604 { .hw = &a1_dmc_div.hw }, 1605 { .fw_name = "xtal", }, 1606 }, 1607 .num_parents = 2, 1608 .flags = CLK_SET_RATE_PARENT, 1609 }, 1610 }; 1611 1612 static struct clk_regmap a1_dmc = { 1613 .data = &(struct clk_regmap_gate_data){ 1614 .offset = DMC_CLK_CTRL, 1615 .bit_idx = 8, 1616 }, 1617 .hw.init = &(struct clk_init_data) { 1618 .name = "dmc", 1619 .ops = &clk_regmap_gate_ro_ops, 1620 .parent_hws = (const struct clk_hw *[]) { 1621 &a1_dmc_sel2.hw 1622 }, 1623 .num_parents = 1, 1624 .flags = CLK_SET_RATE_PARENT, 1625 }, 1626 }; 1627 1628 static struct clk_regmap a1_ceca_32k_in = { 1629 .data = &(struct clk_regmap_gate_data){ 1630 .offset = CECA_CLK_CTRL0, 1631 .bit_idx = 31, 1632 }, 1633 .hw.init = &(struct clk_init_data) { 1634 .name = "ceca_32k_in", 1635 .ops = &clk_regmap_gate_ops, 1636 .parent_data = &(const struct clk_parent_data) { 1637 .fw_name = "xtal", 1638 }, 1639 .num_parents = 1, 1640 }, 1641 }; 1642 1643 static struct clk_regmap a1_ceca_32k_div = { 1644 .data = &(struct meson_clk_dualdiv_data){ 1645 .n1 = { 1646 .reg_off = CECA_CLK_CTRL0, 1647 .shift = 0, 1648 .width = 12, 1649 }, 1650 .n2 = { 1651 .reg_off = CECA_CLK_CTRL0, 1652 .shift = 12, 1653 .width = 12, 1654 }, 1655 .m1 = { 1656 .reg_off = CECA_CLK_CTRL1, 1657 .shift = 0, 1658 .width = 12, 1659 }, 1660 .m2 = { 1661 .reg_off = CECA_CLK_CTRL1, 1662 .shift = 12, 1663 .width = 12, 1664 }, 1665 .dual = { 1666 .reg_off = CECA_CLK_CTRL0, 1667 .shift = 28, 1668 .width = 1, 1669 }, 1670 .table = a1_32k_div_table, 1671 }, 1672 .hw.init = &(struct clk_init_data){ 1673 .name = "ceca_32k_div", 1674 .ops = &meson_clk_dualdiv_ops, 1675 .parent_hws = (const struct clk_hw *[]) { 1676 &a1_ceca_32k_in.hw 1677 }, 1678 .num_parents = 1, 1679 }, 1680 }; 1681 1682 static struct clk_regmap a1_ceca_32k_sel_pre = { 1683 .data = &(struct clk_regmap_mux_data) { 1684 .offset = CECA_CLK_CTRL1, 1685 .mask = 0x1, 1686 .shift = 24, 1687 .flags = CLK_MUX_ROUND_CLOSEST, 1688 }, 1689 .hw.init = &(struct clk_init_data){ 1690 .name = "ceca_32k_sel_pre", 1691 .ops = &clk_regmap_mux_ops, 1692 .parent_hws = (const struct clk_hw *[]) { 1693 &a1_ceca_32k_div.hw, 1694 &a1_ceca_32k_in.hw, 1695 }, 1696 .num_parents = 2, 1697 .flags = CLK_SET_RATE_PARENT, 1698 }, 1699 }; 1700 1701 static struct clk_regmap a1_ceca_32k_sel = { 1702 .data = &(struct clk_regmap_mux_data) { 1703 .offset = CECA_CLK_CTRL1, 1704 .mask = 0x1, 1705 .shift = 31, 1706 .flags = CLK_MUX_ROUND_CLOSEST, 1707 }, 1708 .hw.init = &(struct clk_init_data){ 1709 .name = "ceca_32k_sel", 1710 .ops = &clk_regmap_mux_ops, 1711 .parent_hws = (const struct clk_hw *[]) { 1712 &a1_ceca_32k_sel_pre.hw, 1713 &a1_rtc.hw, 1714 }, 1715 .num_parents = 2, 1716 }, 1717 }; 1718 1719 static struct clk_regmap a1_ceca_32k_out = { 1720 .data = &(struct clk_regmap_gate_data){ 1721 .offset = CECA_CLK_CTRL0, 1722 .bit_idx = 30, 1723 }, 1724 .hw.init = &(struct clk_init_data){ 1725 .name = "ceca_32k_out", 1726 .ops = &clk_regmap_gate_ops, 1727 .parent_hws = (const struct clk_hw *[]) { 1728 &a1_ceca_32k_sel.hw 1729 }, 1730 .num_parents = 1, 1731 .flags = CLK_SET_RATE_PARENT, 1732 }, 1733 }; 1734 1735 static struct clk_regmap a1_cecb_32k_in = { 1736 .data = &(struct clk_regmap_gate_data){ 1737 .offset = CECB_CLK_CTRL0, 1738 .bit_idx = 31, 1739 }, 1740 .hw.init = &(struct clk_init_data) { 1741 .name = "cecb_32k_in", 1742 .ops = &clk_regmap_gate_ops, 1743 .parent_data = &(const struct clk_parent_data) { 1744 .fw_name = "xtal", 1745 }, 1746 .num_parents = 1, 1747 }, 1748 }; 1749 1750 static struct clk_regmap a1_cecb_32k_div = { 1751 .data = &(struct meson_clk_dualdiv_data){ 1752 .n1 = { 1753 .reg_off = CECB_CLK_CTRL0, 1754 .shift = 0, 1755 .width = 12, 1756 }, 1757 .n2 = { 1758 .reg_off = CECB_CLK_CTRL0, 1759 .shift = 12, 1760 .width = 12, 1761 }, 1762 .m1 = { 1763 .reg_off = CECB_CLK_CTRL1, 1764 .shift = 0, 1765 .width = 12, 1766 }, 1767 .m2 = { 1768 .reg_off = CECB_CLK_CTRL1, 1769 .shift = 12, 1770 .width = 12, 1771 }, 1772 .dual = { 1773 .reg_off = CECB_CLK_CTRL0, 1774 .shift = 28, 1775 .width = 1, 1776 }, 1777 .table = a1_32k_div_table, 1778 }, 1779 .hw.init = &(struct clk_init_data){ 1780 .name = "cecb_32k_div", 1781 .ops = &meson_clk_dualdiv_ops, 1782 .parent_hws = (const struct clk_hw *[]) { 1783 &a1_cecb_32k_in.hw 1784 }, 1785 .num_parents = 1, 1786 }, 1787 }; 1788 1789 static struct clk_regmap a1_cecb_32k_sel_pre = { 1790 .data = &(struct clk_regmap_mux_data) { 1791 .offset = CECB_CLK_CTRL1, 1792 .mask = 0x1, 1793 .shift = 24, 1794 .flags = CLK_MUX_ROUND_CLOSEST, 1795 }, 1796 .hw.init = &(struct clk_init_data){ 1797 .name = "cecb_32k_sel_pre", 1798 .ops = &clk_regmap_mux_ops, 1799 .parent_hws = (const struct clk_hw *[]) { 1800 &a1_cecb_32k_div.hw, 1801 &a1_cecb_32k_in.hw, 1802 }, 1803 .num_parents = 2, 1804 .flags = CLK_SET_RATE_PARENT, 1805 }, 1806 }; 1807 1808 static struct clk_regmap a1_cecb_32k_sel = { 1809 .data = &(struct clk_regmap_mux_data) { 1810 .offset = CECB_CLK_CTRL1, 1811 .mask = 0x1, 1812 .shift = 31, 1813 .flags = CLK_MUX_ROUND_CLOSEST, 1814 }, 1815 .hw.init = &(struct clk_init_data){ 1816 .name = "cecb_32k_sel", 1817 .ops = &clk_regmap_mux_ops, 1818 .parent_hws = (const struct clk_hw *[]) { 1819 &a1_cecb_32k_sel_pre.hw, 1820 &a1_rtc.hw, 1821 }, 1822 .num_parents = 2, 1823 }, 1824 }; 1825 1826 static struct clk_regmap a1_cecb_32k_out = { 1827 .data = &(struct clk_regmap_gate_data){ 1828 .offset = CECB_CLK_CTRL0, 1829 .bit_idx = 30, 1830 }, 1831 .hw.init = &(struct clk_init_data){ 1832 .name = "cecb_32k_out", 1833 .ops = &clk_regmap_gate_ops, 1834 .parent_hws = (const struct clk_hw *[]) { 1835 &a1_cecb_32k_sel.hw 1836 }, 1837 .num_parents = 1, 1838 .flags = CLK_SET_RATE_PARENT, 1839 }, 1840 }; 1841 1842 static const struct clk_parent_data a1_pclk_parents = { .hw = &a1_sys.hw }; 1843 1844 #define A1_PCLK(_name, _reg, _bit, _flags) \ 1845 MESON_PCLK(a1_##_name, _reg, _bit, &a1_pclk_parents, _flags) 1846 1847 /* 1848 * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons 1849 * Users are encouraged to test without it and submit changes to: 1850 * - remove the flag if not necessary 1851 * - replace the flag with something more adequate, such as CLK_IS_CRITICAL, 1852 * if appropriate. 1853 * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirable 1854 * for a particular clock. 1855 */ 1856 static A1_PCLK(clktree, SYS_CLK_EN0, 0, CLK_IGNORE_UNUSED); 1857 static A1_PCLK(reset_ctrl, SYS_CLK_EN0, 1, CLK_IGNORE_UNUSED); 1858 static A1_PCLK(analog_ctrl, SYS_CLK_EN0, 2, CLK_IGNORE_UNUSED); 1859 static A1_PCLK(pwr_ctrl, SYS_CLK_EN0, 3, CLK_IGNORE_UNUSED); 1860 static A1_PCLK(pad_ctrl, SYS_CLK_EN0, 4, CLK_IGNORE_UNUSED); 1861 static A1_PCLK(sys_ctrl, SYS_CLK_EN0, 5, CLK_IGNORE_UNUSED); 1862 static A1_PCLK(temp_sensor, SYS_CLK_EN0, 6, CLK_IGNORE_UNUSED); 1863 static A1_PCLK(am2axi_dev, SYS_CLK_EN0, 7, CLK_IGNORE_UNUSED); 1864 static A1_PCLK(spicc_b, SYS_CLK_EN0, 8, CLK_IGNORE_UNUSED); 1865 static A1_PCLK(spicc_a, SYS_CLK_EN0, 9, CLK_IGNORE_UNUSED); 1866 static A1_PCLK(msr, SYS_CLK_EN0, 10, CLK_IGNORE_UNUSED); 1867 static A1_PCLK(audio, SYS_CLK_EN0, 11, CLK_IGNORE_UNUSED); 1868 static A1_PCLK(jtag_ctrl, SYS_CLK_EN0, 12, CLK_IGNORE_UNUSED); 1869 static A1_PCLK(saradc_en, SYS_CLK_EN0, 13, CLK_IGNORE_UNUSED); 1870 static A1_PCLK(pwm_ef, SYS_CLK_EN0, 14, CLK_IGNORE_UNUSED); 1871 static A1_PCLK(pwm_cd, SYS_CLK_EN0, 15, CLK_IGNORE_UNUSED); 1872 static A1_PCLK(pwm_ab, SYS_CLK_EN0, 16, CLK_IGNORE_UNUSED); 1873 static A1_PCLK(cec, SYS_CLK_EN0, 17, CLK_IGNORE_UNUSED); 1874 static A1_PCLK(i2c_s, SYS_CLK_EN0, 18, CLK_IGNORE_UNUSED); 1875 static A1_PCLK(ir_ctrl, SYS_CLK_EN0, 19, CLK_IGNORE_UNUSED); 1876 static A1_PCLK(i2c_m_d, SYS_CLK_EN0, 20, CLK_IGNORE_UNUSED); 1877 static A1_PCLK(i2c_m_c, SYS_CLK_EN0, 21, CLK_IGNORE_UNUSED); 1878 static A1_PCLK(i2c_m_b, SYS_CLK_EN0, 22, CLK_IGNORE_UNUSED); 1879 static A1_PCLK(i2c_m_a, SYS_CLK_EN0, 23, CLK_IGNORE_UNUSED); 1880 static A1_PCLK(acodec, SYS_CLK_EN0, 24, CLK_IGNORE_UNUSED); 1881 static A1_PCLK(otp, SYS_CLK_EN0, 25, CLK_IGNORE_UNUSED); 1882 static A1_PCLK(sd_emmc_a, SYS_CLK_EN0, 26, CLK_IGNORE_UNUSED); 1883 static A1_PCLK(usb_phy, SYS_CLK_EN0, 27, CLK_IGNORE_UNUSED); 1884 static A1_PCLK(usb_ctrl, SYS_CLK_EN0, 28, CLK_IGNORE_UNUSED); 1885 static A1_PCLK(sys_dspb, SYS_CLK_EN0, 29, CLK_IGNORE_UNUSED); 1886 static A1_PCLK(sys_dspa, SYS_CLK_EN0, 30, CLK_IGNORE_UNUSED); 1887 static A1_PCLK(dma, SYS_CLK_EN0, 31, CLK_IGNORE_UNUSED); 1888 1889 static A1_PCLK(irq_ctrl, SYS_CLK_EN1, 0, CLK_IGNORE_UNUSED); 1890 static A1_PCLK(nic, SYS_CLK_EN1, 1, CLK_IGNORE_UNUSED); 1891 static A1_PCLK(gic, SYS_CLK_EN1, 2, CLK_IGNORE_UNUSED); 1892 static A1_PCLK(uart_c, SYS_CLK_EN1, 3, CLK_IGNORE_UNUSED); 1893 static A1_PCLK(uart_b, SYS_CLK_EN1, 4, CLK_IGNORE_UNUSED); 1894 static A1_PCLK(uart_a, SYS_CLK_EN1, 5, CLK_IGNORE_UNUSED); 1895 static A1_PCLK(sys_psram, SYS_CLK_EN1, 6, CLK_IGNORE_UNUSED); 1896 static A1_PCLK(rsa, SYS_CLK_EN1, 8, CLK_IGNORE_UNUSED); 1897 static A1_PCLK(coresight, SYS_CLK_EN1, 9, CLK_IGNORE_UNUSED); 1898 1899 static A1_PCLK(am2axi_vad, AXI_CLK_EN, 0, CLK_IGNORE_UNUSED); 1900 static A1_PCLK(audio_vad, AXI_CLK_EN, 1, CLK_IGNORE_UNUSED); 1901 static A1_PCLK(axi_dmc, AXI_CLK_EN, 3, CLK_IGNORE_UNUSED); 1902 static A1_PCLK(axi_psram, AXI_CLK_EN, 4, CLK_IGNORE_UNUSED); 1903 static A1_PCLK(ramb, AXI_CLK_EN, 5, CLK_IGNORE_UNUSED); 1904 static A1_PCLK(rama, AXI_CLK_EN, 6, CLK_IGNORE_UNUSED); 1905 static A1_PCLK(axi_spifc, AXI_CLK_EN, 7, CLK_IGNORE_UNUSED); 1906 static A1_PCLK(axi_nic, AXI_CLK_EN, 8, CLK_IGNORE_UNUSED); 1907 static A1_PCLK(axi_dma, AXI_CLK_EN, 9, CLK_IGNORE_UNUSED); 1908 static A1_PCLK(cpu_ctrl, AXI_CLK_EN, 10, CLK_IGNORE_UNUSED); 1909 static A1_PCLK(rom, AXI_CLK_EN, 11, CLK_IGNORE_UNUSED); 1910 static A1_PCLK(prod_i2c, AXI_CLK_EN, 12, CLK_IGNORE_UNUSED); 1911 1912 /* Array of all clocks registered by this provider */ 1913 static struct clk_hw *a1_peripherals_hw_clks[] = { 1914 [CLKID_XTAL_IN] = &a1_xtal_in.hw, 1915 [CLKID_FIXPLL_IN] = &a1_fixpll_in.hw, 1916 [CLKID_USB_PHY_IN] = &a1_usb_phy_in.hw, 1917 [CLKID_USB_CTRL_IN] = &a1_usb_ctrl_in.hw, 1918 [CLKID_HIFIPLL_IN] = &a1_hifipll_in.hw, 1919 [CLKID_SYSPLL_IN] = &a1_syspll_in.hw, 1920 [CLKID_DDS_IN] = &a1_dds_in.hw, 1921 [CLKID_SYS] = &a1_sys.hw, 1922 [CLKID_CLKTREE] = &a1_clktree.hw, 1923 [CLKID_RESET_CTRL] = &a1_reset_ctrl.hw, 1924 [CLKID_ANALOG_CTRL] = &a1_analog_ctrl.hw, 1925 [CLKID_PWR_CTRL] = &a1_pwr_ctrl.hw, 1926 [CLKID_PAD_CTRL] = &a1_pad_ctrl.hw, 1927 [CLKID_SYS_CTRL] = &a1_sys_ctrl.hw, 1928 [CLKID_TEMP_SENSOR] = &a1_temp_sensor.hw, 1929 [CLKID_AM2AXI_DIV] = &a1_am2axi_dev.hw, 1930 [CLKID_SPICC_B] = &a1_spicc_b.hw, 1931 [CLKID_SPICC_A] = &a1_spicc_a.hw, 1932 [CLKID_MSR] = &a1_msr.hw, 1933 [CLKID_AUDIO] = &a1_audio.hw, 1934 [CLKID_JTAG_CTRL] = &a1_jtag_ctrl.hw, 1935 [CLKID_SARADC_EN] = &a1_saradc_en.hw, 1936 [CLKID_PWM_EF] = &a1_pwm_ef.hw, 1937 [CLKID_PWM_CD] = &a1_pwm_cd.hw, 1938 [CLKID_PWM_AB] = &a1_pwm_ab.hw, 1939 [CLKID_CEC] = &a1_cec.hw, 1940 [CLKID_I2C_S] = &a1_i2c_s.hw, 1941 [CLKID_IR_CTRL] = &a1_ir_ctrl.hw, 1942 [CLKID_I2C_M_D] = &a1_i2c_m_d.hw, 1943 [CLKID_I2C_M_C] = &a1_i2c_m_c.hw, 1944 [CLKID_I2C_M_B] = &a1_i2c_m_b.hw, 1945 [CLKID_I2C_M_A] = &a1_i2c_m_a.hw, 1946 [CLKID_ACODEC] = &a1_acodec.hw, 1947 [CLKID_OTP] = &a1_otp.hw, 1948 [CLKID_SD_EMMC_A] = &a1_sd_emmc_a.hw, 1949 [CLKID_USB_PHY] = &a1_usb_phy.hw, 1950 [CLKID_USB_CTRL] = &a1_usb_ctrl.hw, 1951 [CLKID_SYS_DSPB] = &a1_sys_dspb.hw, 1952 [CLKID_SYS_DSPA] = &a1_sys_dspa.hw, 1953 [CLKID_DMA] = &a1_dma.hw, 1954 [CLKID_IRQ_CTRL] = &a1_irq_ctrl.hw, 1955 [CLKID_NIC] = &a1_nic.hw, 1956 [CLKID_GIC] = &a1_gic.hw, 1957 [CLKID_UART_C] = &a1_uart_c.hw, 1958 [CLKID_UART_B] = &a1_uart_b.hw, 1959 [CLKID_UART_A] = &a1_uart_a.hw, 1960 [CLKID_SYS_PSRAM] = &a1_sys_psram.hw, 1961 [CLKID_RSA] = &a1_rsa.hw, 1962 [CLKID_CORESIGHT] = &a1_coresight.hw, 1963 [CLKID_AM2AXI_VAD] = &a1_am2axi_vad.hw, 1964 [CLKID_AUDIO_VAD] = &a1_audio_vad.hw, 1965 [CLKID_AXI_DMC] = &a1_axi_dmc.hw, 1966 [CLKID_AXI_PSRAM] = &a1_axi_psram.hw, 1967 [CLKID_RAMB] = &a1_ramb.hw, 1968 [CLKID_RAMA] = &a1_rama.hw, 1969 [CLKID_AXI_SPIFC] = &a1_axi_spifc.hw, 1970 [CLKID_AXI_NIC] = &a1_axi_nic.hw, 1971 [CLKID_AXI_DMA] = &a1_axi_dma.hw, 1972 [CLKID_CPU_CTRL] = &a1_cpu_ctrl.hw, 1973 [CLKID_ROM] = &a1_rom.hw, 1974 [CLKID_PROC_I2C] = &a1_prod_i2c.hw, 1975 [CLKID_DSPA_SEL] = &a1_dspa_sel.hw, 1976 [CLKID_DSPB_SEL] = &a1_dspb_sel.hw, 1977 [CLKID_DSPA_EN] = &a1_dspa_en.hw, 1978 [CLKID_DSPA_EN_NIC] = &a1_dspa_en_nic.hw, 1979 [CLKID_DSPB_EN] = &a1_dspb_en.hw, 1980 [CLKID_DSPB_EN_NIC] = &a1_dspb_en_nic.hw, 1981 [CLKID_RTC] = &a1_rtc.hw, 1982 [CLKID_CECA_32K] = &a1_ceca_32k_out.hw, 1983 [CLKID_CECB_32K] = &a1_cecb_32k_out.hw, 1984 [CLKID_24M] = &a1_24m.hw, 1985 [CLKID_12M] = &a1_12m.hw, 1986 [CLKID_FCLK_DIV2_DIVN] = &a1_fclk_div2_divn.hw, 1987 [CLKID_GEN] = &a1_gen.hw, 1988 [CLKID_SARADC_SEL] = &a1_saradc_sel.hw, 1989 [CLKID_SARADC] = &a1_saradc.hw, 1990 [CLKID_PWM_A] = &a1_pwm_a.hw, 1991 [CLKID_PWM_B] = &a1_pwm_b.hw, 1992 [CLKID_PWM_C] = &a1_pwm_c.hw, 1993 [CLKID_PWM_D] = &a1_pwm_d.hw, 1994 [CLKID_PWM_E] = &a1_pwm_e.hw, 1995 [CLKID_PWM_F] = &a1_pwm_f.hw, 1996 [CLKID_SPICC] = &a1_spicc.hw, 1997 [CLKID_TS] = &a1_ts.hw, 1998 [CLKID_SPIFC] = &a1_spifc.hw, 1999 [CLKID_USB_BUS] = &a1_usb_bus.hw, 2000 [CLKID_SD_EMMC] = &a1_sd_emmc.hw, 2001 [CLKID_PSRAM] = &a1_psram.hw, 2002 [CLKID_DMC] = &a1_dmc.hw, 2003 [CLKID_SYS_A_SEL] = &a1_sys_a_sel.hw, 2004 [CLKID_SYS_A_DIV] = &a1_sys_a_div.hw, 2005 [CLKID_SYS_A] = &a1_sys_a.hw, 2006 [CLKID_SYS_B_SEL] = &a1_sys_b_sel.hw, 2007 [CLKID_SYS_B_DIV] = &a1_sys_b_div.hw, 2008 [CLKID_SYS_B] = &a1_sys_b.hw, 2009 [CLKID_DSPA_A_SEL] = &a1_dspa_a_sel.hw, 2010 [CLKID_DSPA_A_DIV] = &a1_dspa_a_div.hw, 2011 [CLKID_DSPA_A] = &a1_dspa_a.hw, 2012 [CLKID_DSPA_B_SEL] = &a1_dspa_b_sel.hw, 2013 [CLKID_DSPA_B_DIV] = &a1_dspa_b_div.hw, 2014 [CLKID_DSPA_B] = &a1_dspa_b.hw, 2015 [CLKID_DSPB_A_SEL] = &a1_dspb_a_sel.hw, 2016 [CLKID_DSPB_A_DIV] = &a1_dspb_a_div.hw, 2017 [CLKID_DSPB_A] = &a1_dspb_a.hw, 2018 [CLKID_DSPB_B_SEL] = &a1_dspb_b_sel.hw, 2019 [CLKID_DSPB_B_DIV] = &a1_dspb_b_div.hw, 2020 [CLKID_DSPB_B] = &a1_dspb_b.hw, 2021 [CLKID_RTC_32K_IN] = &a1_rtc_32k_in.hw, 2022 [CLKID_RTC_32K_DIV] = &a1_rtc_32k_div.hw, 2023 [CLKID_RTC_32K_XTAL] = &a1_rtc_32k_xtal.hw, 2024 [CLKID_RTC_32K_SEL] = &a1_rtc_32k_sel.hw, 2025 [CLKID_CECB_32K_IN] = &a1_cecb_32k_in.hw, 2026 [CLKID_CECB_32K_DIV] = &a1_cecb_32k_div.hw, 2027 [CLKID_CECB_32K_SEL_PRE] = &a1_cecb_32k_sel_pre.hw, 2028 [CLKID_CECB_32K_SEL] = &a1_cecb_32k_sel.hw, 2029 [CLKID_CECA_32K_IN] = &a1_ceca_32k_in.hw, 2030 [CLKID_CECA_32K_DIV] = &a1_ceca_32k_div.hw, 2031 [CLKID_CECA_32K_SEL_PRE] = &a1_ceca_32k_sel_pre.hw, 2032 [CLKID_CECA_32K_SEL] = &a1_ceca_32k_sel.hw, 2033 [CLKID_DIV2_PRE] = &a1_fclk_div2_divn_pre.hw, 2034 [CLKID_24M_DIV2] = &a1_24m_div2.hw, 2035 [CLKID_GEN_SEL] = &a1_gen_sel.hw, 2036 [CLKID_GEN_DIV] = &a1_gen_div.hw, 2037 [CLKID_SARADC_DIV] = &a1_saradc_div.hw, 2038 [CLKID_PWM_A_SEL] = &a1_pwm_a_sel.hw, 2039 [CLKID_PWM_A_DIV] = &a1_pwm_a_div.hw, 2040 [CLKID_PWM_B_SEL] = &a1_pwm_b_sel.hw, 2041 [CLKID_PWM_B_DIV] = &a1_pwm_b_div.hw, 2042 [CLKID_PWM_C_SEL] = &a1_pwm_c_sel.hw, 2043 [CLKID_PWM_C_DIV] = &a1_pwm_c_div.hw, 2044 [CLKID_PWM_D_SEL] = &a1_pwm_d_sel.hw, 2045 [CLKID_PWM_D_DIV] = &a1_pwm_d_div.hw, 2046 [CLKID_PWM_E_SEL] = &a1_pwm_e_sel.hw, 2047 [CLKID_PWM_E_DIV] = &a1_pwm_e_div.hw, 2048 [CLKID_PWM_F_SEL] = &a1_pwm_f_sel.hw, 2049 [CLKID_PWM_F_DIV] = &a1_pwm_f_div.hw, 2050 [CLKID_SPICC_SEL] = &a1_spicc_sel.hw, 2051 [CLKID_SPICC_DIV] = &a1_spicc_div.hw, 2052 [CLKID_SPICC_SEL2] = &a1_spicc_sel2.hw, 2053 [CLKID_TS_DIV] = &a1_ts_div.hw, 2054 [CLKID_SPIFC_SEL] = &a1_spifc_sel.hw, 2055 [CLKID_SPIFC_DIV] = &a1_spifc_div.hw, 2056 [CLKID_SPIFC_SEL2] = &a1_spifc_sel2.hw, 2057 [CLKID_USB_BUS_SEL] = &a1_usb_bus_sel.hw, 2058 [CLKID_USB_BUS_DIV] = &a1_usb_bus_div.hw, 2059 [CLKID_SD_EMMC_SEL] = &a1_sd_emmc_sel.hw, 2060 [CLKID_SD_EMMC_DIV] = &a1_sd_emmc_div.hw, 2061 [CLKID_SD_EMMC_SEL2] = &a1_sd_emmc_sel2.hw, 2062 [CLKID_PSRAM_SEL] = &a1_psram_sel.hw, 2063 [CLKID_PSRAM_DIV] = &a1_psram_div.hw, 2064 [CLKID_PSRAM_SEL2] = &a1_psram_sel2.hw, 2065 [CLKID_DMC_SEL] = &a1_dmc_sel.hw, 2066 [CLKID_DMC_DIV] = &a1_dmc_div.hw, 2067 [CLKID_DMC_SEL2] = &a1_dmc_sel2.hw, 2068 }; 2069 2070 static const struct meson_clkc_data a1_peripherals_clkc_data = { 2071 .hw_clks = { 2072 .hws = a1_peripherals_hw_clks, 2073 .num = ARRAY_SIZE(a1_peripherals_hw_clks), 2074 }, 2075 }; 2076 2077 static const struct of_device_id a1_peripherals_clkc_match_table[] = { 2078 { 2079 .compatible = "amlogic,a1-peripherals-clkc", 2080 .data = &a1_peripherals_clkc_data, 2081 }, 2082 {} 2083 }; 2084 MODULE_DEVICE_TABLE(of, a1_peripherals_clkc_match_table); 2085 2086 static struct platform_driver a1_peripherals_clkc_driver = { 2087 .probe = meson_clkc_mmio_probe, 2088 .driver = { 2089 .name = "a1-peripherals-clkc", 2090 .of_match_table = a1_peripherals_clkc_match_table, 2091 }, 2092 }; 2093 module_platform_driver(a1_peripherals_clkc_driver); 2094 2095 MODULE_DESCRIPTION("Amlogic A1 Peripherals Clock Controller driver"); 2096 MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>"); 2097 MODULE_AUTHOR("Dmitry Rokosov <ddrokosov@sberdevices.ru>"); 2098 MODULE_LICENSE("GPL"); 2099 MODULE_IMPORT_NS("CLK_MESON"); 2100