1*889c2b7eSJerome Brunetconfig COMMON_CLK_MESON_INPUT 2*889c2b7eSJerome Brunet tristate 3cb7c47d7SMichael Turquette 4*889c2b7eSJerome Brunetconfig COMMON_CLK_MESON_REGMAP 5*889c2b7eSJerome Brunet tristate 6ea11dda9SJerome Brunet select REGMAP 7ea11dda9SJerome Brunet 8*889c2b7eSJerome Brunetconfig COMMON_CLK_MESON_DUALDIV 9*889c2b7eSJerome Brunet tristate 10*889c2b7eSJerome Brunet select COMMON_CLK_MESON_REGMAP 11*889c2b7eSJerome Brunet 12*889c2b7eSJerome Brunetconfig COMMON_CLK_MESON_MPLL 13*889c2b7eSJerome Brunet tristate 14*889c2b7eSJerome Brunet select COMMON_CLK_MESON_REGMAP 15*889c2b7eSJerome Brunet 16*889c2b7eSJerome Brunetconfig COMMON_CLK_MESON_PHASE 17*889c2b7eSJerome Brunet tristate 18*889c2b7eSJerome Brunet select COMMON_CLK_MESON_REGMAP 19*889c2b7eSJerome Brunet 20*889c2b7eSJerome Brunetconfig COMMON_CLK_MESON_PLL 21*889c2b7eSJerome Brunet tristate 22*889c2b7eSJerome Brunet select COMMON_CLK_MESON_REGMAP 23*889c2b7eSJerome Brunet 24*889c2b7eSJerome Brunetconfig COMMON_CLK_MESON_SCLK_DIV 25*889c2b7eSJerome Brunet tristate 26*889c2b7eSJerome Brunet select COMMON_CLK_MESON_REGMAP 27*889c2b7eSJerome Brunet 28*889c2b7eSJerome Brunetconfig COMMON_CLK_MESON_VID_PLL_DIV 29*889c2b7eSJerome Brunet tristate 30*889c2b7eSJerome Brunet select COMMON_CLK_MESON_REGMAP 31*889c2b7eSJerome Brunet 32*889c2b7eSJerome Brunetconfig COMMON_CLK_MESON_AO_CLKC 33*889c2b7eSJerome Brunet tristate 34*889c2b7eSJerome Brunet select COMMON_CLK_MESON_REGMAP 35*889c2b7eSJerome Brunet select COMMON_CLK_MESON_INPUT 36*889c2b7eSJerome Brunet select RESET_CONTROLLER 37*889c2b7eSJerome Brunet 38cb7c47d7SMichael Turquetteconfig COMMON_CLK_MESON8B 39cb7c47d7SMichael Turquette bool 40*889c2b7eSJerome Brunet depends on ARCH_MESON 41*889c2b7eSJerome Brunet select COMMON_CLK_MESON_REGMAP 42*889c2b7eSJerome Brunet select COMMON_CLK_MESON_MPLL 43*889c2b7eSJerome Brunet select COMMON_CLK_MESON_PLL 44*889c2b7eSJerome Brunet select MFD_SYSCON 4518962172SMartin Blumenstingl select RESET_CONTROLLER 46cb7c47d7SMichael Turquette help 47855f06a1SMartin Blumenstingl Support for the clock controller on AmLogic S802 (Meson8), 48855f06a1SMartin Blumenstingl S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you 49855f06a1SMartin Blumenstingl want peripherals and CPU frequency scaling to work. 50738f66d3SMichael Turquette 51738f66d3SMichael Turquetteconfig COMMON_CLK_GXBB 52738f66d3SMichael Turquette bool 53*889c2b7eSJerome Brunet depends on ARCH_MESON 54*889c2b7eSJerome Brunet select COMMON_CLK_MESON_INPUT 55*889c2b7eSJerome Brunet select COMMON_CLK_MESON_REGMAP 56*889c2b7eSJerome Brunet select COMMON_CLK_MESON_DUALDIV 57*889c2b7eSJerome Brunet select COMMON_CLK_MESON_VID_PLL_DIV 58*889c2b7eSJerome Brunet select COMMON_CLK_MESON_MPLL 59*889c2b7eSJerome Brunet select COMMON_CLK_MESON_PLL 60*889c2b7eSJerome Brunet select COMMON_CLK_MESON_AO_CLKC 614162dd5bSJerome Brunet select MFD_SYSCON 62738f66d3SMichael Turquette help 63738f66d3SMichael Turquette Support for the clock controller on AmLogic S905 devices, aka gxbb. 64738f66d3SMichael Turquette Say Y if you want peripherals and CPU frequency scaling to work. 6578b4af31SQiufang Dai 6678b4af31SQiufang Daiconfig COMMON_CLK_AXG 6778b4af31SQiufang Dai bool 68*889c2b7eSJerome Brunet depends on ARCH_MESON 69*889c2b7eSJerome Brunet select COMMON_CLK_MESON_INPUT 70*889c2b7eSJerome Brunet select COMMON_CLK_MESON_REGMAP 71*889c2b7eSJerome Brunet select COMMON_CLK_MESON_DUALDIV 72*889c2b7eSJerome Brunet select COMMON_CLK_MESON_MPLL 73*889c2b7eSJerome Brunet select COMMON_CLK_MESON_PLL 74*889c2b7eSJerome Brunet select COMMON_CLK_MESON_AO_CLKC 754162dd5bSJerome Brunet select MFD_SYSCON 7678b4af31SQiufang Dai help 7778b4af31SQiufang Dai Support for the clock controller on AmLogic A113D devices, aka axg. 7878b4af31SQiufang Dai Say Y if you want peripherals and CPU frequency scaling to work. 791cd50181SJerome Brunet 801cd50181SJerome Brunetconfig COMMON_CLK_AXG_AUDIO 811cd50181SJerome Brunet tristate "Meson AXG Audio Clock Controller Driver" 82*889c2b7eSJerome Brunet depends on ARCH_MESON 83*889c2b7eSJerome Brunet select COMMON_CLK_MESON_INPUT 84*889c2b7eSJerome Brunet select COMMON_CLK_MESON_REGMAP 85*889c2b7eSJerome Brunet select COMMON_CLK_MESON_PHASE 86*889c2b7eSJerome Brunet select COMMON_CLK_MESON_SCLK_DIV 87cb78ba76SJerome Brunet select REGMAP_MMIO 881cd50181SJerome Brunet help 891cd50181SJerome Brunet Support for the audio clock controller on AmLogic A113D devices, 901cd50181SJerome Brunet aka axg, Say Y if you want audio subsystem to work. 91