xref: /linux/drivers/clk/mediatek/reset.h (revision 2d2a2900588cabe2ff3abd552d1683e5f1ce398b)

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2022 MediaTek Inc.
 */

#ifndef __DRV_CLK_MTK_RESET_H
#define __DRV_CLK_MTK_RESET_H

#include <linux/reset-controller.h>
#include <linux/types.h>

/**
 * enum mtk_reset_version - Version of MediaTek clock reset controller.
 * @MTK_RST_SIMPLE: Use the same registers for bit set and clear.
 * @MTK_RST_SET_CLR: Use separate registers for bit set and clear.
 * @MTK_RST_MAX: Total quantity of version for MediaTek clock reset controller.
 */
enum mtk_reset_version {
	MTK_RST_SIMPLE = 0,
	MTK_RST_SET_CLR,
	MTK_RST_MAX,
};

/**
 * struct mtk_clk_rst_desc - Description of MediaTek clock reset.
 * @version: Reset version which is defined in enum mtk_reset_version.
 * @reg_ofs: Base offset of the reset register.
 * @rst_bank_nr: Quantity of reset bank.
 */
struct mtk_clk_rst_desc {
	enum mtk_reset_version version;
	u16 reg_ofs;
	u32 rst_bank_nr;
};

/**
 * struct mtk_clk_rst_data - Data of MediaTek clock reset controller.
 * @regmap: Pointer to base address of reset register address.
 * @rcdev: Reset controller device.
 * @desc: Pointer to description of the reset controller.
 */
struct mtk_clk_rst_data {
	struct regmap *regmap;
	struct reset_controller_dev rcdev;
	const struct mtk_clk_rst_desc *desc;
};

/**
 * mtk_register_reset_controller - Register MediaTek clock reset controller
 * @np: Pointer to device node.
 * @desc: Constant pointer to description of clock reset.
 */
void mtk_register_reset_controller(struct device_node *np,
				   const struct mtk_clk_rst_desc *desc);

#endif /* __DRV_CLK_MTK_RESET_H */