1b348c26cSRex-BC Chen /* SPDX-License-Identifier: GPL-2.0-only */ 2b348c26cSRex-BC Chen /* 3b348c26cSRex-BC Chen * Copyright (c) 2022 MediaTek Inc. 4b348c26cSRex-BC Chen */ 5b348c26cSRex-BC Chen 6b348c26cSRex-BC Chen #ifndef __DRV_CLK_MTK_RESET_H 7b348c26cSRex-BC Chen #define __DRV_CLK_MTK_RESET_H 8b348c26cSRex-BC Chen 9b348c26cSRex-BC Chen #include <linux/reset-controller.h> 10b348c26cSRex-BC Chen #include <linux/types.h> 11b348c26cSRex-BC Chen 12723e3671SRex-BC Chen #define RST_NR_PER_BANK 32 13723e3671SRex-BC Chen 14*a0bc8ae5SRex-BC Chen /* Infra global controller reset set register */ 15*a0bc8ae5SRex-BC Chen #define INFRA_RST0_SET_OFFSET 0x120 16*a0bc8ae5SRex-BC Chen #define INFRA_RST1_SET_OFFSET 0x130 17*a0bc8ae5SRex-BC Chen #define INFRA_RST2_SET_OFFSET 0x140 18*a0bc8ae5SRex-BC Chen #define INFRA_RST3_SET_OFFSET 0x150 19*a0bc8ae5SRex-BC Chen #define INFRA_RST4_SET_OFFSET 0x730 20*a0bc8ae5SRex-BC Chen 21370bf628SRex-BC Chen /** 22370bf628SRex-BC Chen * enum mtk_reset_version - Version of MediaTek clock reset controller. 23370bf628SRex-BC Chen * @MTK_RST_SIMPLE: Use the same registers for bit set and clear. 24370bf628SRex-BC Chen * @MTK_RST_SET_CLR: Use separate registers for bit set and clear. 25370bf628SRex-BC Chen * @MTK_RST_MAX: Total quantity of version for MediaTek clock reset controller. 26370bf628SRex-BC Chen */ 27370bf628SRex-BC Chen enum mtk_reset_version { 28370bf628SRex-BC Chen MTK_RST_SIMPLE = 0, 29370bf628SRex-BC Chen MTK_RST_SET_CLR, 30370bf628SRex-BC Chen MTK_RST_MAX, 31370bf628SRex-BC Chen }; 32370bf628SRex-BC Chen 332d2a2900SRex-BC Chen /** 342d2a2900SRex-BC Chen * struct mtk_clk_rst_desc - Description of MediaTek clock reset. 352d2a2900SRex-BC Chen * @version: Reset version which is defined in enum mtk_reset_version. 36723e3671SRex-BC Chen * @rst_bank_ofs: Pointer to an array containing base offsets of the reset register. 372d2a2900SRex-BC Chen * @rst_bank_nr: Quantity of reset bank. 38322989ddSRex-BC Chen * @rst_idx_map:Pointer to an array containing ids if input argument is index. 39322989ddSRex-BC Chen * This array is not necessary if our input argument does not mean index. 40322989ddSRex-BC Chen * @rst_idx_map_nr: Quantity of reset index map. 412d2a2900SRex-BC Chen */ 422d2a2900SRex-BC Chen struct mtk_clk_rst_desc { 432d2a2900SRex-BC Chen enum mtk_reset_version version; 44723e3671SRex-BC Chen u16 *rst_bank_ofs; 452d2a2900SRex-BC Chen u32 rst_bank_nr; 46322989ddSRex-BC Chen u16 *rst_idx_map; 47322989ddSRex-BC Chen u32 rst_idx_map_nr; 482d2a2900SRex-BC Chen }; 492d2a2900SRex-BC Chen 502d2a2900SRex-BC Chen /** 512d2a2900SRex-BC Chen * struct mtk_clk_rst_data - Data of MediaTek clock reset controller. 522d2a2900SRex-BC Chen * @regmap: Pointer to base address of reset register address. 532d2a2900SRex-BC Chen * @rcdev: Reset controller device. 542d2a2900SRex-BC Chen * @desc: Pointer to description of the reset controller. 552d2a2900SRex-BC Chen */ 562d2a2900SRex-BC Chen struct mtk_clk_rst_data { 57b348c26cSRex-BC Chen struct regmap *regmap; 58b348c26cSRex-BC Chen struct reset_controller_dev rcdev; 592d2a2900SRex-BC Chen const struct mtk_clk_rst_desc *desc; 60b348c26cSRex-BC Chen }; 61b348c26cSRex-BC Chen 62370bf628SRex-BC Chen /** 63761bc640SRex-BC Chen * mtk_register_reset_controller - Register mediatek clock reset controller with device 64761bc640SRex-BC Chen * @np: Pointer to device. 65761bc640SRex-BC Chen * @desc: Constant pointer to description of clock reset. 66761bc640SRex-BC Chen * 67761bc640SRex-BC Chen * Return: 0 on success and errorno otherwise. 68761bc640SRex-BC Chen */ 69761bc640SRex-BC Chen int mtk_register_reset_controller_with_dev(struct device *dev, 70761bc640SRex-BC Chen const struct mtk_clk_rst_desc *desc); 71761bc640SRex-BC Chen 72b348c26cSRex-BC Chen #endif /* __DRV_CLK_MTK_RESET_H */ 73